arm: am33xx: Add CPSW MII mac select support
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / devices.c
1 /*
2  * linux/arch/arm/mach-omap2/devices.c
3  *
4  * OMAP2 platform device setup/initialization
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  */
11 #include <linux/gpio.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/io.h>
16 #include <linux/clk.h>
17 #include <linux/err.h>
18 #include <linux/slab.h>
19 #include <linux/of.h>
20 #include <linux/davinci_emac.h>
21 #include <linux/cpsw.h>
22 #include <linux/etherdevice.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/can/platform/d_can.h>
25 #include <linux/platform_data/uio_pruss.h>
27 #include <mach/hardware.h>
28 #include <mach/irqs.h>
29 #include <mach/board-am335xevm.h>
30 #include <asm/mach-types.h>
31 #include <asm/mach/map.h>
32 #include <asm/pmu.h>
34 #ifdef  CONFIG_OMAP3_EDMA
35 #include <mach/edma.h>
36 #endif
38 #include <asm/hardware/asp.h>
40 #include <plat/tc.h>
41 #include <plat/board.h>
42 #include <plat/mcbsp.h>
43 #include <plat/mmc.h>
44 #include <plat/dma.h>
45 #include <plat/omap_hwmod.h>
46 #include <plat/omap_device.h>
47 #include <plat/omap4-keypad.h>
49 /* LCD controller similar DA8xx */
50 #include <video/da8xx-fb.h>
52 #include "mux.h"
53 #include "control.h"
54 #include "devices.h"
56 #define L3_MODULES_MAX_LEN 12
57 #define L3_MODULES 3
59 static int __init omap3_l3_init(void)
60 {
61         int l;
62         struct omap_hwmod *oh;
63         struct platform_device *pdev;
64         char oh_name[L3_MODULES_MAX_LEN];
66         /*
67          * To avoid code running on other OMAPs in
68          * multi-omap builds
69          */
70         if (!(cpu_is_omap34xx()) || (cpu_is_am33xx()))
71                 return -ENODEV;
73         l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
75         oh = omap_hwmod_lookup(oh_name);
77         if (!oh)
78                 pr_err("could not look up %s\n", oh_name);
80         pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
81                                                            NULL, 0, 0);
83         WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
85         return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
86 }
87 postcore_initcall(omap3_l3_init);
89 static int __init omap4_l3_init(void)
90 {
91         int l, i;
92         struct omap_hwmod *oh[3];
93         struct platform_device *pdev;
94         char oh_name[L3_MODULES_MAX_LEN];
96         /* If dtb is there, the devices will be created dynamically */
97         if (of_have_populated_dt())
98                 return -ENODEV;
100         /*
101          * To avoid code running on other OMAPs in
102          * multi-omap builds
103          */
104         if (!(cpu_is_omap44xx()))
105                 return -ENODEV;
107         for (i = 0; i < L3_MODULES; i++) {
108                 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
110                 oh[i] = omap_hwmod_lookup(oh_name);
111                 if (!(oh[i]))
112                         pr_err("could not look up %s\n", oh_name);
113         }
115         pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
116                                                      0, NULL, 0, 0);
118         WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
120         return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
122 postcore_initcall(omap4_l3_init);
124 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
126 static struct resource omap2cam_resources[] = {
127         {
128                 .start          = OMAP24XX_CAMERA_BASE,
129                 .end            = OMAP24XX_CAMERA_BASE + 0xfff,
130                 .flags          = IORESOURCE_MEM,
131         },
132         {
133                 .start          = INT_24XX_CAM_IRQ,
134                 .flags          = IORESOURCE_IRQ,
135         }
136 };
138 static struct platform_device omap2cam_device = {
139         .name           = "omap24xxcam",
140         .id             = -1,
141         .num_resources  = ARRAY_SIZE(omap2cam_resources),
142         .resource       = omap2cam_resources,
143 };
144 #endif
145 #define L4_PER_LCDC_PHYS        0x4830E000
147 static struct resource am33xx_lcdc_resources[] = {
148         [0] = { /* registers */
149                 .start  = L4_PER_LCDC_PHYS,
150                 .end    = L4_PER_LCDC_PHYS + SZ_4K - 1,
151                 .flags  = IORESOURCE_MEM,
152         },
153         [1] = { /* interrupt */
154                 .start  = AM33XX_IRQ_LCD,
155                 .end    = AM33XX_IRQ_LCD,
156                 .flags  = IORESOURCE_IRQ,
157         },
158 };
160 static struct platform_device am33xx_lcdc_device = {
161         .name           = "da8xx_lcdc",
162         .id             = 0,
163         .num_resources  = ARRAY_SIZE(am33xx_lcdc_resources),
164         .resource       = am33xx_lcdc_resources,
165 };
167 void __init am33xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
169         int ret;
171         am33xx_lcdc_device.dev.platform_data = pdata;
173         ret = platform_device_register(&am33xx_lcdc_device);
174         if (ret)
175                 pr_warning("am33xx_register_lcdc: lcdc registration failed: %d\n",
176                                 ret);
180 #if defined(CONFIG_SND_AM335X_SOC_EVM) || \
181                                 defined(CONFIG_SND_AM335X_SOC_EVM_MODULE)
182 static struct resource am335x_mcasp1_resource[] = {
183         {
184                 .name = "mcasp1",
185                 .start = AM33XX_ASP1_BASE,
186                 .end = AM33XX_ASP1_BASE + (SZ_1K * 12) - 1,
187                 .flags = IORESOURCE_MEM,
188         },
189         /* TX event */
190         {
191                 .start = AM33XX_DMA_MCASP1_X,
192                 .end = AM33XX_DMA_MCASP1_X,
193                 .flags = IORESOURCE_DMA,
194         },
195         /* RX event */
196         {
197                 .start = AM33XX_DMA_MCASP1_R,
198                 .end = AM33XX_DMA_MCASP1_R,
199                 .flags = IORESOURCE_DMA,
200         },
201 };
203 static struct platform_device am335x_mcasp1_device = {
204         .name = "davinci-mcasp",
205         .id = 1,
206         .num_resources = ARRAY_SIZE(am335x_mcasp1_resource),
207         .resource = am335x_mcasp1_resource,
208 };
210 void __init am335x_register_mcasp1(struct snd_platform_data *pdata)
212         am335x_mcasp1_device.dev.platform_data = pdata;
213         platform_device_register(&am335x_mcasp1_device);
216 #else
217 void __init am335x_register_mcasp1(struct snd_platform_data *pdata) {}
218 #endif
220 #if (defined(CONFIG_SND_AM33XX_SOC) || (defined(CONFIG_SND_AM33XX_SOC_MODULE)))
221 struct platform_device am33xx_pcm_device = {
222         .name           = "davinci-pcm-audio",
223         .id             = -1,
224 };
226 static void am33xx_init_pcm(void)
228         platform_device_register(&am33xx_pcm_device);
231 #else
232 static inline void am33xx_init_pcm(void) {}
233 #endif
235 static struct resource omap3isp_resources[] = {
236         {
237                 .start          = OMAP3430_ISP_BASE,
238                 .end            = OMAP3430_ISP_END,
239                 .flags          = IORESOURCE_MEM,
240         },
241         {
242                 .start          = OMAP3430_ISP_CCP2_BASE,
243                 .end            = OMAP3430_ISP_CCP2_END,
244                 .flags          = IORESOURCE_MEM,
245         },
246         {
247                 .start          = OMAP3430_ISP_CCDC_BASE,
248                 .end            = OMAP3430_ISP_CCDC_END,
249                 .flags          = IORESOURCE_MEM,
250         },
251         {
252                 .start          = OMAP3430_ISP_HIST_BASE,
253                 .end            = OMAP3430_ISP_HIST_END,
254                 .flags          = IORESOURCE_MEM,
255         },
256         {
257                 .start          = OMAP3430_ISP_H3A_BASE,
258                 .end            = OMAP3430_ISP_H3A_END,
259                 .flags          = IORESOURCE_MEM,
260         },
261         {
262                 .start          = OMAP3430_ISP_PREV_BASE,
263                 .end            = OMAP3430_ISP_PREV_END,
264                 .flags          = IORESOURCE_MEM,
265         },
266         {
267                 .start          = OMAP3430_ISP_RESZ_BASE,
268                 .end            = OMAP3430_ISP_RESZ_END,
269                 .flags          = IORESOURCE_MEM,
270         },
271         {
272                 .start          = OMAP3430_ISP_SBL_BASE,
273                 .end            = OMAP3430_ISP_SBL_END,
274                 .flags          = IORESOURCE_MEM,
275         },
276         {
277                 .start          = OMAP3430_ISP_CSI2A_REGS1_BASE,
278                 .end            = OMAP3430_ISP_CSI2A_REGS1_END,
279                 .flags          = IORESOURCE_MEM,
280         },
281         {
282                 .start          = OMAP3430_ISP_CSIPHY2_BASE,
283                 .end            = OMAP3430_ISP_CSIPHY2_END,
284                 .flags          = IORESOURCE_MEM,
285         },
286         {
287                 .start          = OMAP3630_ISP_CSI2A_REGS2_BASE,
288                 .end            = OMAP3630_ISP_CSI2A_REGS2_END,
289                 .flags          = IORESOURCE_MEM,
290         },
291         {
292                 .start          = OMAP3630_ISP_CSI2C_REGS1_BASE,
293                 .end            = OMAP3630_ISP_CSI2C_REGS1_END,
294                 .flags          = IORESOURCE_MEM,
295         },
296         {
297                 .start          = OMAP3630_ISP_CSIPHY1_BASE,
298                 .end            = OMAP3630_ISP_CSIPHY1_END,
299                 .flags          = IORESOURCE_MEM,
300         },
301         {
302                 .start          = OMAP3630_ISP_CSI2C_REGS2_BASE,
303                 .end            = OMAP3630_ISP_CSI2C_REGS2_END,
304                 .flags          = IORESOURCE_MEM,
305         },
306         {
307                 .start          = INT_34XX_CAM_IRQ,
308                 .flags          = IORESOURCE_IRQ,
309         }
310 };
312 static struct platform_device omap3isp_device = {
313         .name           = "omap3isp",
314         .id             = -1,
315         .num_resources  = ARRAY_SIZE(omap3isp_resources),
316         .resource       = omap3isp_resources,
317 };
319 int omap3_init_camera(struct isp_platform_data *pdata)
321         omap3isp_device.dev.platform_data = pdata;
322         return platform_device_register(&omap3isp_device);
325 static inline void omap_init_camera(void)
327 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
328         if (cpu_is_omap24xx())
329                 platform_device_register(&omap2cam_device);
330 #endif
333 int __init omap4_keyboard_init(struct omap4_keypad_platform_data
334                         *sdp4430_keypad_data, struct omap_board_data *bdata)
336         struct platform_device *pdev;
337         struct omap_hwmod *oh;
338         struct omap4_keypad_platform_data *keypad_data;
339         unsigned int id = -1;
340         char *oh_name = "kbd";
341         char *name = "omap4-keypad";
343         oh = omap_hwmod_lookup(oh_name);
344         if (!oh) {
345                 pr_err("Could not look up %s\n", oh_name);
346                 return -ENODEV;
347         }
349         keypad_data = sdp4430_keypad_data;
351         pdev = omap_device_build(name, id, oh, keypad_data,
352                         sizeof(struct omap4_keypad_platform_data), NULL, 0, 0);
354         if (IS_ERR(pdev)) {
355                 WARN(1, "Can't build omap_device for %s:%s.\n",
356                                                 name, oh->name);
357                 return PTR_ERR(pdev);
358         }
359         oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
361         return 0;
364 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
365 static inline void omap_init_mbox(void)
367         struct omap_hwmod *oh;
368         struct platform_device *pdev;
370         oh = omap_hwmod_lookup("mailbox");
371         if (!oh) {
372                 pr_err("%s: unable to find hwmod\n", __func__);
373                 return;
374         }
376         pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0);
377         WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
378                                                 __func__, PTR_ERR(pdev));
380 #else
381 static inline void omap_init_mbox(void) { }
382 #endif /* CONFIG_OMAP_MBOX_FWK */
384 static inline void omap_init_sti(void) {}
386 #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
388 static struct platform_device omap_pcm = {
389         .name   = "omap-pcm-audio",
390         .id     = -1,
391 };
393 /*
394  * OMAP2420 has 2 McBSP ports
395  * OMAP2430 has 5 McBSP ports
396  * OMAP3 has 5 McBSP ports
397  * OMAP4 has 4 McBSP ports
398  */
399 OMAP_MCBSP_PLATFORM_DEVICE(1);
400 OMAP_MCBSP_PLATFORM_DEVICE(2);
401 OMAP_MCBSP_PLATFORM_DEVICE(3);
402 OMAP_MCBSP_PLATFORM_DEVICE(4);
403 OMAP_MCBSP_PLATFORM_DEVICE(5);
405 static void omap_init_audio(void)
407         if (cpu_is_am33xx())
408                 return;
410         platform_device_register(&omap_mcbsp1);
411         platform_device_register(&omap_mcbsp2);
412         if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
413                 platform_device_register(&omap_mcbsp3);
414                 platform_device_register(&omap_mcbsp4);
415         }
416         if (cpu_is_omap243x() || cpu_is_omap34xx())
417                 platform_device_register(&omap_mcbsp5);
419         platform_device_register(&omap_pcm);
422 #else
423 static inline void omap_init_audio(void) {}
424 #endif
426 #if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
427                 defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
429 static void omap_init_mcpdm(void)
431         struct omap_hwmod *oh;
432         struct platform_device *pdev;
434         oh = omap_hwmod_lookup("mcpdm");
435         if (!oh) {
436                 printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
437                 return;
438         }
440         pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0, NULL, 0, 0);
441         WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n");
443 #else
444 static inline void omap_init_mcpdm(void) {}
445 #endif
447 #if defined(CONFIG_SND_OMAP_SOC_DMIC) || \
448                 defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE)
450 static void omap_init_dmic(void)
452         struct omap_hwmod *oh;
453         struct platform_device *pdev;
455         oh = omap_hwmod_lookup("dmic");
456         if (!oh) {
457                 printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
458                 return;
459         }
461         pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0, NULL, 0, 0);
462         WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
464 #else
465 static inline void omap_init_dmic(void) {}
466 #endif
468 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
470 #include <plat/mcspi.h>
472 static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
474         struct platform_device *pdev;
475         char *name = "omap2_mcspi";
476         struct omap2_mcspi_platform_config *pdata;
477         static int spi_num;
478         struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr;
480         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
481         if (!pdata) {
482                 pr_err("Memory allocation for McSPI device failed\n");
483                 return -ENOMEM;
484         }
486         pdata->num_cs = mcspi_attrib->num_chipselect;
487         switch (oh->class->rev) {
488         case OMAP2_MCSPI_REV:
489         case OMAP3_MCSPI_REV:
490                         pdata->regs_offset = 0;
491                         break;
492         case OMAP4_MCSPI_REV:
493                         pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET;
494                         break;
495         default:
496                         pr_err("Invalid McSPI Revision value\n");
497                         return -EINVAL;
498         }
500         spi_num++;
501         pdev = omap_device_build(name, spi_num, oh, pdata,
502                                 sizeof(*pdata), NULL, 0, 0);
503         WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n",
504                                 name, oh->name);
505         kfree(pdata);
506         return 0;
509 static void omap_init_mcspi(void)
511         omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
514 #else
515 static inline void omap_init_mcspi(void) {}
516 #endif
518 #ifdef CONFIG_SOC_OMAPAM33XX
520 static int omap_elm_init(struct omap_hwmod *oh, void *unused)
522         struct platform_device *pdev;
523         char *name = "omap2_elm";
524         static int elm_num;
527         elm_num++;
528         pdev = omap_device_build(name, elm_num, oh, NULL,
529                                 0,      NULL,
530                                 0, 0);
531         return 0;
534 static void omap_init_elm(void)
537         omap_hwmod_for_each_by_class("elm", omap_elm_init, NULL);
540 #else
541 static void omap_init_elm(void) {}
542 #endif
545 static struct resource omap2_pmu_resource = {
546         .start  = 3,
547         .end    = 3,
548         .flags  = IORESOURCE_IRQ,
549 };
551 static struct resource omap3_pmu_resource = {
552         .start  = INT_34XX_BENCH_MPU_EMUL,
553         .end    = INT_34XX_BENCH_MPU_EMUL,
554         .flags  = IORESOURCE_IRQ,
555 };
557 static struct platform_device omap_pmu_device = {
558         .name           = "arm-pmu",
559         .id             = ARM_PMU_DEVICE_CPU,
560         .num_resources  = 1,
561 };
563 static void omap_init_pmu(void)
565         if (cpu_is_omap24xx())
566                 omap_pmu_device.resource = &omap2_pmu_resource;
567         else if (cpu_is_omap34xx() && !cpu_is_am33xx())
568                 omap_pmu_device.resource = &omap3_pmu_resource;
569         else
570                 return;
572         platform_device_register(&omap_pmu_device);
576 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
578 #ifdef CONFIG_ARCH_OMAP2
579 static struct resource omap2_sham_resources[] = {
580         {
581                 .start  = OMAP24XX_SEC_SHA1MD5_BASE,
582                 .end    = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
583                 .flags  = IORESOURCE_MEM,
584         },
585         {
586                 .start  = INT_24XX_SHA1MD5,
587                 .flags  = IORESOURCE_IRQ,
588         }
589 };
590 static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
591 #else
592 #define omap2_sham_resources            NULL
593 #define omap2_sham_resources_sz         0
594 #endif
596 #ifdef CONFIG_ARCH_OMAP3
597 static struct resource omap3_sham_resources[] = {
598         {
599                 .start  = OMAP34XX_SEC_SHA1MD5_BASE,
600                 .end    = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
601                 .flags  = IORESOURCE_MEM,
602         },
603         {
604                 .start  = INT_34XX_SHA1MD52_IRQ,
605                 .flags  = IORESOURCE_IRQ,
606         },
607         {
608                 .start  = OMAP34XX_DMA_SHA1MD5_RX,
609                 .flags  = IORESOURCE_DMA,
610         }
611 };
612 static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
613 #else
614 #define omap3_sham_resources            NULL
615 #define omap3_sham_resources_sz         0
616 #endif
618 static struct platform_device sham_device = {
619         .name           = "omap-sham",
620         .id             = -1,
621 };
623 static void omap_init_sham(void)
625         if (cpu_is_omap24xx()) {
626                 sham_device.resource = omap2_sham_resources;
627                 sham_device.num_resources = omap2_sham_resources_sz;
628         } else if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
629                 sham_device.resource = omap3_sham_resources;
630                 sham_device.num_resources = omap3_sham_resources_sz;
631         } else {
632                 pr_err("%s: platform not supported\n", __func__);
633                 return;
634         }
635         platform_device_register(&sham_device);
637 #else
638 static inline void omap_init_sham(void) { }
639 #endif
641 #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
643 #ifdef CONFIG_ARCH_OMAP2
644 static struct resource omap2_aes_resources[] = {
645         {
646                 .start  = OMAP24XX_SEC_AES_BASE,
647                 .end    = OMAP24XX_SEC_AES_BASE + 0x4C,
648                 .flags  = IORESOURCE_MEM,
649         },
650         {
651                 .start  = OMAP24XX_DMA_AES_TX,
652                 .flags  = IORESOURCE_DMA,
653         },
654         {
655                 .start  = OMAP24XX_DMA_AES_RX,
656                 .flags  = IORESOURCE_DMA,
657         }
658 };
659 static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
660 #else
661 #define omap2_aes_resources             NULL
662 #define omap2_aes_resources_sz          0
663 #endif
665 #ifdef CONFIG_ARCH_OMAP3
666 static struct resource omap3_aes_resources[] = {
667         {
668                 .start  = OMAP34XX_SEC_AES_BASE,
669                 .end    = OMAP34XX_SEC_AES_BASE + 0x4C,
670                 .flags  = IORESOURCE_MEM,
671         },
672         {
673                 .start  = OMAP34XX_DMA_AES2_TX,
674                 .flags  = IORESOURCE_DMA,
675         },
676         {
677                 .start  = OMAP34XX_DMA_AES2_RX,
678                 .flags  = IORESOURCE_DMA,
679         }
680 };
681 static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
682 #else
683 #define omap3_aes_resources             NULL
684 #define omap3_aes_resources_sz          0
685 #endif
687 static struct platform_device aes_device = {
688         .name           = "omap-aes",
689         .id             = -1,
690 };
692 static void omap_init_aes(void)
694         if (cpu_is_omap24xx()) {
695                 aes_device.resource = omap2_aes_resources;
696                 aes_device.num_resources = omap2_aes_resources_sz;
697         } else if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
698                 aes_device.resource = omap3_aes_resources;
699                 aes_device.num_resources = omap3_aes_resources_sz;
700         } else {
701                 pr_err("%s: platform not supported\n", __func__);
702                 return;
703         }
704         platform_device_register(&aes_device);
707 #else
708 static inline void omap_init_aes(void) { }
709 #endif
711 /*-------------------------------------------------------------------------*/
713 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
715 static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
716                                                         *mmc_controller)
718         if ((mmc_controller->slots[0].switch_pin > 0) && \
719                 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
720                 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
721                                         OMAP_PIN_INPUT_PULLUP);
722         if ((mmc_controller->slots[0].gpio_wp > 0) && \
723                 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
724                 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
725                                         OMAP_PIN_INPUT_PULLUP);
727         omap_mux_init_signal("sdmmc_cmd", 0);
728         omap_mux_init_signal("sdmmc_clki", 0);
729         omap_mux_init_signal("sdmmc_clko", 0);
730         omap_mux_init_signal("sdmmc_dat0", 0);
731         omap_mux_init_signal("sdmmc_dat_dir0", 0);
732         omap_mux_init_signal("sdmmc_cmd_dir", 0);
733         if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
734                 omap_mux_init_signal("sdmmc_dat1", 0);
735                 omap_mux_init_signal("sdmmc_dat2", 0);
736                 omap_mux_init_signal("sdmmc_dat3", 0);
737                 omap_mux_init_signal("sdmmc_dat_dir1", 0);
738                 omap_mux_init_signal("sdmmc_dat_dir2", 0);
739                 omap_mux_init_signal("sdmmc_dat_dir3", 0);
740         }
742         /*
743          * Use internal loop-back in MMC/SDIO Module Input Clock
744          * selection
745          */
746         if (mmc_controller->slots[0].internal_clock) {
747                 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
748                 v |= (1 << 24);
749                 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
750         }
753 void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
755         char *name = "mmci-omap";
757         if (!mmc_data[0]) {
758                 pr_err("%s fails: Incomplete platform data\n", __func__);
759                 return;
760         }
762         omap242x_mmc_mux(mmc_data[0]);
763         omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE,
764                                         INT_24XX_MMC_IRQ, mmc_data[0]);
767 #endif
769 /*-------------------------------------------------------------------------*/
771 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
772 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
773 #define OMAP_HDQ_BASE   0x480B2000
774 #endif
775 static struct resource omap_hdq_resources[] = {
776         {
777                 .start          = OMAP_HDQ_BASE,
778                 .end            = OMAP_HDQ_BASE + 0x1C,
779                 .flags          = IORESOURCE_MEM,
780         },
781         {
782                 .start          = INT_24XX_HDQ_IRQ,
783                 .flags          = IORESOURCE_IRQ,
784         },
785 };
786 static struct platform_device omap_hdq_dev = {
787         .name = "omap_hdq",
788         .id = 0,
789         .dev = {
790                 .platform_data = NULL,
791         },
792         .num_resources  = ARRAY_SIZE(omap_hdq_resources),
793         .resource       = omap_hdq_resources,
794 };
795 static inline void omap_hdq_init(void)
797         (void) platform_device_register(&omap_hdq_dev);
799 #else
800 static inline void omap_hdq_init(void) {}
801 #endif
803 /*---------------------------------------------------------------------------*/
805 #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
806         defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
807 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
808 static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
809 };
810 #else
811 static struct resource omap_vout_resource[2] = {
812 };
813 #endif
815 static struct platform_device omap_vout_device = {
816         .name           = "omap_vout",
817         .num_resources  = ARRAY_SIZE(omap_vout_resource),
818         .resource       = &omap_vout_resource[0],
819         .id             = -1,
820 };
821 static void omap_init_vout(void)
823         if (platform_device_register(&omap_vout_device) < 0)
824                 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
826 #else
827 static inline void omap_init_vout(void) {}
828 #endif
830 #if defined(CONFIG_SOC_OMAPAM33XX) && defined(CONFIG_OMAP3_EDMA)
832 #define AM33XX_TPCC_BASE                0x49000000
833 #define AM33XX_TPTC0_BASE               0x49800000
834 #define AM33XX_TPTC1_BASE               0x49900000
835 #define AM33XX_TPTC2_BASE               0x49a00000
837 #define AM33XX_SCM_BASE_EDMA            0x00000f90
839 static struct resource am33xx_edma_resources[] = {
840         {
841                 .name   = "edma_cc0",
842                 .start  = AM33XX_TPCC_BASE,
843                 .end    = AM33XX_TPCC_BASE + SZ_32K - 1,
844                 .flags  = IORESOURCE_MEM,
845         },
846         {
847                 .name   = "edma_tc0",
848                 .start  = AM33XX_TPTC0_BASE,
849                 .end    = AM33XX_TPTC0_BASE + SZ_1K - 1,
850                 .flags  = IORESOURCE_MEM,
851         },
852         {
853                 .name   = "edma_tc1",
854                 .start  = AM33XX_TPTC1_BASE,
855                 .end    = AM33XX_TPTC1_BASE + SZ_1K - 1,
856                 .flags  = IORESOURCE_MEM,
857         },
858         {
859                 .name   = "edma_tc2",
860                 .start  = AM33XX_TPTC2_BASE,
861                 .end    = AM33XX_TPTC2_BASE + SZ_1K - 1,
862                 .flags  = IORESOURCE_MEM,
863         },
864         {
865                 .name   = "edma0",
866                 .start  = AM33XX_IRQ_TPCC0_INT_PO0,
867                 .flags  = IORESOURCE_IRQ,
868         },
869         {
870                 .name   = "edma0_err",
871                 .start  = AM33XX_IRQ_TPCC0_ERRINT_PO,
872                 .flags  = IORESOURCE_IRQ,
873         },
874 };
876 static const s16 am33xx_dma_rsv_chans[][2] = {
877         /* (offset, number) */
878         {0, 2},
879         {14, 2},
880         {26, 6},
881         {48, 4},
882         {56, 8},
883         {-1, -1}
884 };
886 static const s16 am33xx_dma_rsv_slots[][2] = {
887         /* (offset, number) */
888         {0, 2},
889         {14, 2},
890         {26, 6},
891         {48, 4},
892         {56, 8},
893         {64, 127},
894         {-1, -1}
895 };
897 /* Three Transfer Controllers on AM33XX */
898 static const s8 am33xx_queue_tc_mapping[][2] = {
899         /* {event queue no, TC no} */
900         {0, 0},
901         {1, 1},
902         {2, 2},
903         {-1, -1}
904 };
906 static const s8 am33xx_queue_priority_mapping[][2] = {
907         /* {event queue no, Priority} */
908         {0, 0},
909         {1, 1},
910         {2, 2},
911         {-1, -1}
912 };
914 static struct event_to_channel_map am33xx_xbar_event_mapping[] = {
915         /* {xbar event no, Channel} */
916         {1, 12},        /* SDTXEVT1 -> MMCHS2 */
917         {2, 13},        /* SDRXEVT1 -> MMCHS2 */
918         {3, -1},
919         {4, -1},
920         {5, -1},
921         {6, -1},
922         {7, -1},
923         {8, -1},
924         {9, -1},
925         {10, -1},
926         {11, -1},
927         {12, -1},
928         {13, -1},
929         {14, -1},
930         {15, -1},
931         {16, -1},
932         {17, -1},
933         {18, -1},
934         {19, -1},
935         {20, -1},
936         {21, -1},
937         {22, -1},
938         {23, -1},
939         {24, -1},
940         {25, -1},
941         {26, -1},
942         {27, -1},
943         {28, -1},
944         {29, -1},
945         {30, -1},
946         {31, -1},
947         {-1, -1}
948 };
950 /**
951  * map_xbar_event_to_channel - maps a crossbar event to a DMA channel
952  * according to the configuration provided
953  * @event: the event number for which mapping is required
954  * @channel: channel being activated
955  * @xbar_event_mapping: array that has the event to channel map
956  *
957  * Events that are routed by default are not mapped. Only events that
958  * are crossbar mapped are routed to available channels according to
959  * the configuration provided
960  *
961  * Returns zero on success, else negative errno.
962  */
963 int map_xbar_event_to_channel(unsigned int event, unsigned int *channel,
964                         struct event_to_channel_map *xbar_event_mapping)
966         unsigned int ctrl = 0;
967         unsigned int xbar_evt_no = 0;
968         unsigned int val = 0;
969         unsigned int offset = 0;
970         unsigned int mask = 0;
972         ctrl = EDMA_CTLR(event);
973         xbar_evt_no = event - (edma_info[ctrl]->num_channels);
975         if (event < edma_info[ctrl]->num_channels) {
976                 *channel = event;
977         } else if (event < edma_info[ctrl]->num_events) {
978                 *channel = xbar_event_mapping[xbar_evt_no].channel_no;
979                 /* confirm the range */
980                 if (*channel < EDMA_MAX_DMACH)
981                         clear_bit(*channel, edma_info[ctrl]->edma_unused);
982                 mask = (*channel)%4;
983                 offset = (*channel)/4;
984                 offset *= 4;
985                 offset += mask;
986                 val = (unsigned int)__raw_readl(AM33XX_CTRL_REGADDR(
987                                         AM33XX_SCM_BASE_EDMA + offset));
988                 val = val & (~(0xFF));
989                 val = val | (xbar_event_mapping[xbar_evt_no].xbar_event_no);
990                 __raw_writel(val,
991                         AM33XX_CTRL_REGADDR(AM33XX_SCM_BASE_EDMA + offset));
992                 return 0;
993         } else {
994                 return -EINVAL;
995         }
997         return 0;
1000 static struct edma_soc_info am33xx_edma_info[] = {
1001         {
1002                 .n_channel              = 64,
1003                 .n_region               = 4,
1004                 .n_slot                 = 256,
1005                 .n_tc                   = 3,
1006                 .n_cc                   = 1,
1007                 .rsv_chans              = am33xx_dma_rsv_chans,
1008                 .rsv_slots              = am33xx_dma_rsv_slots,
1009                 .queue_tc_mapping       = am33xx_queue_tc_mapping,
1010                 .queue_priority_mapping = am33xx_queue_priority_mapping,
1011                 .is_xbar                = 1,
1012                 .n_events               = 95,
1013                 .xbar_event_mapping     = am33xx_xbar_event_mapping,
1014                 .map_xbar_channel       = map_xbar_event_to_channel,
1015         },
1016 };
1018 static struct platform_device am33xx_edma_device = {
1019         .name           = "edma",
1020         .id             = -1,
1021         .dev = {
1022                 .platform_data = am33xx_edma_info,
1023         },
1024         .num_resources  = ARRAY_SIZE(am33xx_edma_resources),
1025         .resource       = am33xx_edma_resources,
1026 };
1028 int __init am33xx_register_edma(void)
1030         struct platform_device *pdev;
1031         static struct clk *edma_clk;
1033         if (cpu_is_am33xx())
1034                 pdev = &am33xx_edma_device;
1035         else {
1036                 pr_err("%s: platform not supported\n", __func__);
1037                 return -ENODEV;
1038         }
1040         edma_clk = clk_get(NULL, "tpcc_ick");
1041         if (IS_ERR(edma_clk)) {
1042                 printk(KERN_ERR "EDMA: Failed to get clock\n");
1043                 return -EBUSY;
1044         }
1045         clk_enable(edma_clk);
1046         edma_clk = clk_get(NULL, "tptc0_ick");
1047         if (IS_ERR(edma_clk)) {
1048                 printk(KERN_ERR "EDMA: Failed to get clock\n");
1049                 return -EBUSY;
1050         }
1051         clk_enable(edma_clk);
1052         edma_clk = clk_get(NULL, "tptc1_ick");
1053         if (IS_ERR(edma_clk)) {
1054                 printk(KERN_ERR "EDMA: Failed to get clock\n");
1055                 return -EBUSY;
1056         }
1057         clk_enable(edma_clk);
1058         edma_clk = clk_get(NULL, "tptc2_ick");
1059         if (IS_ERR(edma_clk)) {
1060                 printk(KERN_ERR "EDMA: Failed to get clock\n");
1061                 return -EBUSY;
1062         }
1063         clk_enable(edma_clk);
1065         return platform_device_register(pdev);
1068 #else
1069 static inline void am33xx_register_edma(void) {}
1070 #endif
1072 #if defined (CONFIG_SOC_OMAPAM33XX)
1073 struct uio_pruss_pdata am335x_pruss_uio_pdata = {
1074         .pintc_base     = 0x20000,
1075 };
1077 static struct resource am335x_pruss_resources[] = {
1078         {
1079                 .start  = AM33XX_ICSS_BASE,
1080                 .end    = AM33XX_ICSS_BASE + AM33XX_ICSS_LEN,
1081                 .flags  = IORESOURCE_MEM,
1082         },
1083         {
1084                 .start  = AM33XX_IRQ_ICSS0_0,
1085                 .end    = AM33XX_IRQ_ICSS0_0,
1086                 .flags  = IORESOURCE_IRQ,
1087         },
1088         {
1089                 .start  = AM33XX_IRQ_ICSS0_1,
1090                 .end    = AM33XX_IRQ_ICSS0_1,
1091                 .flags  = IORESOURCE_IRQ,
1092         },
1093         {
1094                 .start  = AM33XX_IRQ_ICSS0_2,
1095                 .end    = AM33XX_IRQ_ICSS0_2,
1096                 .flags  = IORESOURCE_IRQ,
1097         },
1098         {
1099                 .start  = AM33XX_IRQ_ICSS0_3,
1100                 .end    = AM33XX_IRQ_ICSS0_3,
1101                 .flags  = IORESOURCE_IRQ,
1102         },
1103         {
1104                 .start  = AM33XX_IRQ_ICSS0_4,
1105                 .end    = AM33XX_IRQ_ICSS0_4,
1106                 .flags  = IORESOURCE_IRQ,
1107         },
1108         {
1109                 .start  = AM33XX_IRQ_ICSS0_5,
1110                 .end    = AM33XX_IRQ_ICSS0_5,
1111                 .flags  = IORESOURCE_IRQ,
1112         },
1113         {
1114                 .start  = AM33XX_IRQ_ICSS0_6,
1115                 .end    = AM33XX_IRQ_ICSS0_6,
1116                 .flags  = IORESOURCE_IRQ,
1117         },
1118         {
1119                 .start  = AM33XX_IRQ_ICSS0_7,
1120                 .end    = AM33XX_IRQ_ICSS0_7,
1121                 .flags  = IORESOURCE_IRQ,
1122         },
1123 };
1125 static struct platform_device am335x_pruss_uio_dev = {
1126         .name           = "pruss_uio",
1127         .id             = -1,
1128         .num_resources  = ARRAY_SIZE(am335x_pruss_resources),
1129         .resource       = am335x_pruss_resources,
1130         .dev     =      {
1131                 .coherent_dma_mask = 0xffffffff,
1132         }
1133 };
1135 int __init am335x_register_pruss_uio(struct uio_pruss_pdata *config)
1137         am335x_pruss_uio_dev.dev.platform_data = config;
1138         return platform_device_register(&am335x_pruss_uio_dev);
1140 #endif
1142 /*-------------------------------------------------------------------------*/
1144 static int __init omap2_init_devices(void)
1146         /*
1147          * please keep these calls, and their implementations above,
1148          * in alphabetical order so they're easier to sort through.
1149          */
1150         omap_init_audio();
1151         omap_init_mcpdm();
1152         omap_init_dmic();
1153         omap_init_camera();
1154         omap_init_mbox();
1155         omap_init_mcspi();
1156         omap_init_elm();
1157         omap_init_pmu();
1158         omap_hdq_init();
1159         omap_init_sti();
1160         omap_init_sham();
1161         omap_init_aes();
1162         omap_init_vout();
1163         am33xx_register_edma();
1164         am33xx_init_pcm();
1165 #if defined (CONFIG_SOC_OMAPAM33XX)
1166         am335x_register_pruss_uio(&am335x_pruss_uio_pdata);
1167 #endif
1168         return 0;
1170 arch_initcall(omap2_init_devices);
1172 #define AM33XX_EMAC_MDIO_FREQ           (1000000)
1174 static u64 am33xx_cpsw_dmamask = DMA_BIT_MASK(32);
1175 /* TODO : Verify the offsets */
1176 static struct cpsw_slave_data am33xx_cpsw_slaves[] = {
1177         {
1178                 .slave_reg_ofs  = 0x208,
1179                 .sliver_reg_ofs = 0xd80,
1180                 .phy_id         = "0:00",
1181         },
1182         {
1183                 .slave_reg_ofs  = 0x308,
1184                 .sliver_reg_ofs = 0xdc0,
1185                 .phy_id         = "0:01",
1186         },
1187 };
1189 static struct cpsw_platform_data am33xx_cpsw_pdata = {
1190         .ss_reg_ofs             = 0x1200,
1191         .channels               = 8,
1192         .cpdma_reg_ofs          = 0x800,
1193         .slaves                 = 2,
1194         .slave_data             = am33xx_cpsw_slaves,
1195         .ale_reg_ofs            = 0xd00,
1196         .ale_entries            = 1024,
1197         .host_port_reg_ofs      = 0x108,
1198         .hw_stats_reg_ofs       = 0x900,
1199         .bd_ram_ofs             = 0x2000,
1200         .bd_ram_size            = SZ_8K,
1201         .rx_descs               = 64,
1202         .mac_control            = BIT(5), /* MIIEN */
1203         .gigabit_en             = 1,
1204         .host_port_num          = 0,
1205         .no_bd_ram              = false,
1206         .version                = CPSW_VERSION_2,
1207 };
1209 static struct mdio_platform_data am33xx_cpsw_mdiopdata = {
1210         .bus_freq       = AM33XX_EMAC_MDIO_FREQ,
1211 };
1213 static struct resource am33xx_cpsw_mdioresources[] = {
1214         {
1215                 .start  = AM33XX_CPSW_MDIO_BASE,
1216                 .end    = AM33XX_CPSW_MDIO_BASE + SZ_256 - 1,
1217                 .flags  = IORESOURCE_MEM,
1218         },
1219 };
1221 static struct platform_device am33xx_cpsw_mdiodevice = {
1222         .name           = "davinci_mdio",
1223         .id             = 0,
1224         .num_resources  = ARRAY_SIZE(am33xx_cpsw_mdioresources),
1225         .resource       = am33xx_cpsw_mdioresources,
1226         .dev.platform_data = &am33xx_cpsw_mdiopdata,
1227 };
1229 static struct resource am33xx_cpsw_resources[] = {
1230         {
1231                 .start  = AM33XX_CPSW_BASE,
1232                 .end    = AM33XX_CPSW_BASE + SZ_2K - 1,
1233                 .flags  = IORESOURCE_MEM,
1234         },
1235         {
1236                 .start  = AM33XX_CPSW_SS_BASE,
1237                 .end    = AM33XX_CPSW_SS_BASE + SZ_256 - 1,
1238                 .flags  = IORESOURCE_MEM,
1239         },
1240         {
1241                 .start  = AM33XX_IRQ_CPSW_C0_RX,
1242                 .end    = AM33XX_IRQ_CPSW_C0_RX,
1243                 .flags  = IORESOURCE_IRQ,
1244         },
1245         {
1246                 .start  = AM33XX_IRQ_DMTIMER5,
1247                 .end    = AM33XX_IRQ_DMTIMER5,
1248                 .flags  = IORESOURCE_IRQ,
1249         },
1250         {
1251                 .start  = AM33XX_IRQ_DMTIMER6,
1252                 .end    = AM33XX_IRQ_DMTIMER6,
1253                 .flags  = IORESOURCE_IRQ,
1254         },
1255         {
1256                 .start  = AM33XX_IRQ_CPSW_C0,
1257                 .end    = AM33XX_IRQ_CPSW_C0,
1258                 .flags  = IORESOURCE_IRQ,
1259         },
1260 };
1262 static struct platform_device am33xx_cpsw_device = {
1263         .name           =       "cpsw",
1264         .id             =       0,
1265         .num_resources  =       ARRAY_SIZE(am33xx_cpsw_resources),
1266         .resource       =       am33xx_cpsw_resources,
1267         .dev            =       {
1268                                         .platform_data  = &am33xx_cpsw_pdata,
1269                                         .dma_mask       = &am33xx_cpsw_dmamask,
1270                                         .coherent_dma_mask = DMA_BIT_MASK(32),
1271                                 },
1272 };
1274 static unsigned char  am33xx_macid0[ETH_ALEN];
1275 static unsigned char  am33xx_macid1[ETH_ALEN];
1276 static unsigned int   am33xx_evmid;
1278 /*
1279 * am33xx_evmid_fillup - set up board evmid
1280 * @evmid - evm id which needs to be configured
1282 * This function is called to configure board evm id.
1283 * IA Motor Control EVM needs special setting of MAC PHY Id.
1284 * This function is called when IA Motor Control EVM is detected
1285 * during boot-up.
1286 */
1287 void am33xx_evmid_fillup(unsigned int evmid)
1289         am33xx_evmid = evmid;
1290         return;
1293 /*
1294 * am33xx_cpsw_macidfillup - setup mac adrresses
1295 * @eeprommacid0 - mac id 0 which needs to be configured
1296 * @eeprommacid1 - mac id 1 which needs to be configured
1298 * This function is called to configure mac addresses.
1299 * Mac addresses are read from eeprom and this function is called
1300 * to store those mac adresses in am33xx_macid0 and am33xx_macid1.
1301 * In case, mac address read from eFuse are invalid, mac addresses
1302 * stored in these variable are used.
1303 */
1304 void am33xx_cpsw_macidfillup(char *eeprommacid0, char *eeprommacid1)
1306         u32 i;
1308         /* Fillup these mac addresses with the mac adresses from eeprom */
1309         for (i = 0; i < ETH_ALEN; i++) {
1310                 am33xx_macid0[i] = eeprommacid0[i];
1311                 am33xx_macid1[i] = eeprommacid1[i];
1312         }
1314         return;
1317 #define MII_MODE_ENABLE         0x0
1318 #define RMII_MODE_ENABLE        0x5
1319 #define RGMII_MODE_ENABLE       0xA
1320 #define MAC_MII_SEL             0x650
1322 void am33xx_cpsw_init(unsigned int gigen)
1324         u32 mac_lo, mac_hi;
1325         u32 i;
1327         mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_LO);
1328         mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_HI);
1329         am33xx_cpsw_slaves[0].mac_addr[0] = mac_hi & 0xFF;
1330         am33xx_cpsw_slaves[0].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1331         am33xx_cpsw_slaves[0].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
1332         am33xx_cpsw_slaves[0].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
1333         am33xx_cpsw_slaves[0].mac_addr[4] = mac_lo & 0xFF;
1334         am33xx_cpsw_slaves[0].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
1336         /* Read MACID0 from eeprom if eFuse MACID is invalid */
1337         if (!is_valid_ether_addr(am33xx_cpsw_slaves[0].mac_addr)) {
1338                 for (i = 0; i < ETH_ALEN; i++)
1339                         am33xx_cpsw_slaves[0].mac_addr[i] = am33xx_macid0[i];
1340         }
1342         mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_LO);
1343         mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_HI);
1344         am33xx_cpsw_slaves[1].mac_addr[0] = mac_hi & 0xFF;
1345         am33xx_cpsw_slaves[1].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1346         am33xx_cpsw_slaves[1].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
1347         am33xx_cpsw_slaves[1].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
1348         am33xx_cpsw_slaves[1].mac_addr[4] = mac_lo & 0xFF;
1349         am33xx_cpsw_slaves[1].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
1351         /* Read MACID1 from eeprom if eFuse MACID is invalid */
1352         if (!is_valid_ether_addr(am33xx_cpsw_slaves[1].mac_addr)) {
1353                 for (i = 0; i < ETH_ALEN; i++)
1354                         am33xx_cpsw_slaves[1].mac_addr[i] = am33xx_macid1[i];
1355         }
1357         if (am33xx_evmid == BEAGLE_BONE_OLD) {
1358                 __raw_writel(RMII_MODE_ENABLE,
1359                                 AM33XX_CTRL_REGADDR(MAC_MII_SEL));
1360         } else if (am33xx_evmid == BEAGLE_BONE_A3) {
1361                 __raw_writel(MII_MODE_ENABLE,
1362                                 AM33XX_CTRL_REGADDR(MAC_MII_SEL));
1363         } else if (am33xx_evmid == IND_AUT_MTR_EVM) {
1364                 am33xx_cpsw_slaves[0].phy_id = "0:1e";
1365                 am33xx_cpsw_slaves[1].phy_id = "0:00";
1366         } else {
1367                 __raw_writel(RGMII_MODE_ENABLE,
1368                                 AM33XX_CTRL_REGADDR(MAC_MII_SEL));
1369         }
1371         am33xx_cpsw_pdata.gigabit_en = gigen;
1373         memcpy(am33xx_cpsw_pdata.mac_addr,
1374                         am33xx_cpsw_slaves[0].mac_addr, ETH_ALEN);
1375         platform_device_register(&am33xx_cpsw_mdiodevice);
1376         platform_device_register(&am33xx_cpsw_device);
1377         clk_add_alias(NULL, dev_name(&am33xx_cpsw_mdiodevice.dev),
1378                         NULL, &am33xx_cpsw_device.dev);
1381 #define AM33XX_D_CAN_RAM_BASE                   0x1000
1382 #define AM33XX_D_CAN_NUM_MSG_OBJS               64
1383 #define AM33XX_CTL_DCAN_RAMINIT_OFFSET          0x644
1384 #define AM33XX_D_CAN_RAMINIT_START(n)           (0x1 << n)
1386 static void d_can_hw_raminit(unsigned int instance)
1388         u32 val;
1390         /* Read the value */
1391         val = __raw_readl(AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET));
1393         /* Modify by setting "0" */
1394         val &= ~AM33XX_D_CAN_RAMINIT_START(instance);
1395         __raw_writel(val, AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET));
1397         /* Reset to one */
1398         val |= AM33XX_D_CAN_RAMINIT_START(instance);
1399         __raw_writel(val, AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET));
1401         /* Give some time delay for transition from 0 -> 1 */
1402         udelay(1);
1405 static struct d_can_platform_data am33xx_evm_d_can0_pdata = {
1406         .d_can_offset           = 0,
1407         .d_can_ram_offset       = AM33XX_D_CAN_RAM_BASE,
1408         .num_of_msg_objs        = AM33XX_D_CAN_NUM_MSG_OBJS,
1409         .dma_support            = false,
1410         .parity_check           = false,
1411         .fck_name               = "dcan0_fck",
1412         .ick_name               = "dcan0_ick",
1413 };
1415 static struct resource am33xx_d_can0_resources[] = {
1416         {
1417                 .start  = AM33XX_D_CAN0_BASE,
1418                 .end    = AM33XX_D_CAN0_BASE + 0x3FFF,
1419                 .flags  = IORESOURCE_MEM,
1420         },
1421         {
1422                 .name   = "int0",
1423                 .start  = AM33XX_IRQ_DCAN0_0,
1424                 .end    = AM33XX_IRQ_DCAN0_0,
1425                 .flags  = IORESOURCE_IRQ,
1426         },
1427         {
1428                 .name   = "int1",
1429                 .start  = AM33XX_IRQ_DCAN0_1,
1430                 .end    = AM33XX_IRQ_DCAN0_1,
1431                 .flags  = IORESOURCE_IRQ,
1432         },
1433 };
1435 static struct platform_device am33xx_d_can0_device = {
1436         .dev            = {
1437                 .platform_data = &am33xx_evm_d_can0_pdata,
1438         },
1439         .name           = "d_can",
1440         .id             = -1,
1441         .num_resources  = ARRAY_SIZE(am33xx_d_can0_resources),
1442         .resource       = am33xx_d_can0_resources,
1443 };
1445 static struct resource am33xx_d_can1_resources[] = {
1446         {
1447                 .start  = AM33XX_D_CAN1_BASE,
1448                 .end    = AM33XX_D_CAN1_BASE + 0x3FFF,
1449                 .flags  = IORESOURCE_MEM,
1450         },
1451         {
1452                 .name   = "int0",
1453                 .start  = AM33XX_IRQ_DCAN1_0,
1454                 .end    = AM33XX_IRQ_DCAN1_0,
1455                 .flags  = IORESOURCE_IRQ,
1456         },
1457         {
1458                 .name   = "int1",
1459                 .start  = AM33XX_IRQ_DCAN1_1,
1460                 .end    = AM33XX_IRQ_DCAN1_1,
1461                 .flags  = IORESOURCE_IRQ,
1462         },
1463 };
1465 static struct d_can_platform_data am33xx_evm_d_can1_pdata = {
1466         .d_can_offset           = 0,
1467         .d_can_ram_offset       = AM33XX_D_CAN_RAM_BASE,
1468         .num_of_msg_objs        = AM33XX_D_CAN_NUM_MSG_OBJS,
1469         .dma_support            = false,
1470         .parity_check           = false,
1471         .fck_name               = "dcan1_fck",
1472         .ick_name               = "dcan1_ick",
1473 };
1475 static struct platform_device am33xx_d_can1_device = {
1476         .dev            = {
1477                 .platform_data = &am33xx_evm_d_can1_pdata,
1478         },
1479         .name           = "d_can",
1480         .id             = -1,
1481         .num_resources  = ARRAY_SIZE(am33xx_d_can1_resources),
1482         .resource       = am33xx_d_can1_resources,
1483 };
1485 void am33xx_d_can_init(unsigned int instance)
1487         switch (instance) {
1488         case 0:
1489                 d_can_hw_raminit(instance);
1490                 platform_device_register(&am33xx_d_can0_device);
1491                 break;
1492         case 1:
1493                 d_can_hw_raminit(instance);
1494                 platform_device_register(&am33xx_d_can1_device);
1495                 break;
1496         default:
1497                 break;
1498         }
1501 #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
1502 static int __init omap_init_wdt(void)
1504         int id = -1;
1505         struct platform_device *pdev;
1506         struct omap_hwmod *oh;
1507         char *oh_name = "wd_timer2";
1508         char *dev_name = "omap_wdt";
1510         if (!cpu_class_is_omap2())
1511                 return 0;
1513         oh = omap_hwmod_lookup(oh_name);
1514         if (!oh) {
1515                 pr_err("Could not look up wd_timer%d hwmod\n", id);
1516                 return -EINVAL;
1517         }
1519         pdev = omap_device_build(dev_name, id, oh, NULL, 0, NULL, 0, 0);
1520         WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
1521                                 dev_name, oh->name);
1522         return 0;
1524 subsys_initcall(omap_init_wdt);
1525 #endif