1 /*
2 * linux/arch/arm/mach-omap2/devices.c
3 *
4 * OMAP2 platform device setup/initialization
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11 #include <linux/gpio.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/io.h>
16 #include <linux/clk.h>
17 #include <linux/err.h>
18 #include <linux/slab.h>
19 #include <linux/of.h>
20 #include <linux/davinci_emac.h>
21 #include <linux/cpsw.h>
22 #include <linux/etherdevice.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/can/platform/d_can.h>
26 #include <mach/hardware.h>
27 #include <mach/irqs.h>
28 #include <mach/board-am335xevm.h>
29 #include <asm/mach-types.h>
30 #include <asm/mach/map.h>
31 #include <asm/pmu.h>
33 #ifdef CONFIG_OMAP3_EDMA
34 #include <mach/edma.h>
35 #endif
37 #include <asm/hardware/asp.h>
39 #include <plat/tc.h>
40 #include <plat/board.h>
41 #include <plat/mcbsp.h>
42 #include <plat/mmc.h>
43 #include <plat/dma.h>
44 #include <plat/omap_hwmod.h>
45 #include <plat/omap_device.h>
46 #include <plat/omap4-keypad.h>
48 /* LCD controller similar DA8xx */
49 #include <video/da8xx-fb.h>
51 #include "mux.h"
52 #include "control.h"
53 #include "devices.h"
55 #define L3_MODULES_MAX_LEN 12
56 #define L3_MODULES 3
58 static int __init omap3_l3_init(void)
59 {
60 int l;
61 struct omap_hwmod *oh;
62 struct platform_device *pdev;
63 char oh_name[L3_MODULES_MAX_LEN];
65 /*
66 * To avoid code running on other OMAPs in
67 * multi-omap builds
68 */
69 if (!(cpu_is_omap34xx()))
70 return -ENODEV;
72 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
74 oh = omap_hwmod_lookup(oh_name);
76 if (!oh)
77 pr_err("could not look up %s\n", oh_name);
79 pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
80 NULL, 0, 0);
82 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
84 return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
85 }
86 postcore_initcall(omap3_l3_init);
88 static int __init omap4_l3_init(void)
89 {
90 int l, i;
91 struct omap_hwmod *oh[3];
92 struct platform_device *pdev;
93 char oh_name[L3_MODULES_MAX_LEN];
95 /* If dtb is there, the devices will be created dynamically */
96 if (of_have_populated_dt())
97 return -ENODEV;
99 /*
100 * To avoid code running on other OMAPs in
101 * multi-omap builds
102 */
103 if (!(cpu_is_omap44xx()))
104 return -ENODEV;
106 for (i = 0; i < L3_MODULES; i++) {
107 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
109 oh[i] = omap_hwmod_lookup(oh_name);
110 if (!(oh[i]))
111 pr_err("could not look up %s\n", oh_name);
112 }
114 pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
115 0, NULL, 0, 0);
117 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
119 return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
120 }
121 postcore_initcall(omap4_l3_init);
123 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
125 static struct resource omap2cam_resources[] = {
126 {
127 .start = OMAP24XX_CAMERA_BASE,
128 .end = OMAP24XX_CAMERA_BASE + 0xfff,
129 .flags = IORESOURCE_MEM,
130 },
131 {
132 .start = INT_24XX_CAM_IRQ,
133 .flags = IORESOURCE_IRQ,
134 }
135 };
137 static struct platform_device omap2cam_device = {
138 .name = "omap24xxcam",
139 .id = -1,
140 .num_resources = ARRAY_SIZE(omap2cam_resources),
141 .resource = omap2cam_resources,
142 };
143 #endif
144 #define L4_PER_LCDC_PHYS 0x4830E000
146 static struct resource am33xx_lcdc_resources[] = {
147 [0] = { /* registers */
148 .start = L4_PER_LCDC_PHYS,
149 .end = L4_PER_LCDC_PHYS + SZ_4K - 1,
150 .flags = IORESOURCE_MEM,
151 },
152 [1] = { /* interrupt */
153 .start = AM33XX_IRQ_LCD,
154 .end = AM33XX_IRQ_LCD,
155 .flags = IORESOURCE_IRQ,
156 },
157 };
159 static struct platform_device am33xx_lcdc_device = {
160 .name = "da8xx_lcdc",
161 .id = 0,
162 .num_resources = ARRAY_SIZE(am33xx_lcdc_resources),
163 .resource = am33xx_lcdc_resources,
164 };
166 void __init am33xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
167 {
168 int ret;
170 am33xx_lcdc_device.dev.platform_data = pdata;
172 ret = platform_device_register(&am33xx_lcdc_device);
173 if (ret)
174 pr_warning("am33xx_register_lcdc: lcdc registration failed: %d\n",
175 ret);
177 }
179 #if defined(CONFIG_SND_AM335X_SOC_EVM) || \
180 defined(CONFIG_SND_AM335X_SOC_EVM_MODULE)
181 static struct resource am335x_mcasp1_resource[] = {
182 {
183 .name = "mcasp1",
184 .start = AM33XX_ASP1_BASE,
185 .end = AM33XX_ASP1_BASE + (SZ_1K * 12) - 1,
186 .flags = IORESOURCE_MEM,
187 },
188 /* TX event */
189 {
190 .start = AM33XX_DMA_MCASP1_X,
191 .end = AM33XX_DMA_MCASP1_X,
192 .flags = IORESOURCE_DMA,
193 },
194 /* RX event */
195 {
196 .start = AM33XX_DMA_MCASP1_R,
197 .end = AM33XX_DMA_MCASP1_R,
198 .flags = IORESOURCE_DMA,
199 },
200 };
202 static struct platform_device am335x_mcasp1_device = {
203 .name = "davinci-mcasp",
204 .id = 1,
205 .num_resources = ARRAY_SIZE(am335x_mcasp1_resource),
206 .resource = am335x_mcasp1_resource,
207 };
209 void __init am335x_register_mcasp1(struct snd_platform_data *pdata)
210 {
211 am335x_mcasp1_device.dev.platform_data = pdata;
212 platform_device_register(&am335x_mcasp1_device);
213 }
215 #else
216 void __init am335x_register_mcasp1(struct snd_platform_data *pdata) {}
217 #endif
219 #if (defined(CONFIG_SND_AM33XX_SOC) || (defined(CONFIG_SND_AM33XX_SOC_MODULE)))
220 struct platform_device am33xx_pcm_device = {
221 .name = "davinci-pcm-audio",
222 .id = -1,
223 };
225 static void am33xx_init_pcm(void)
226 {
227 platform_device_register(&am33xx_pcm_device);
228 }
230 #else
231 static inline void am33xx_init_pcm(void) {}
232 #endif
234 static struct resource omap3isp_resources[] = {
235 {
236 .start = OMAP3430_ISP_BASE,
237 .end = OMAP3430_ISP_END,
238 .flags = IORESOURCE_MEM,
239 },
240 {
241 .start = OMAP3430_ISP_CCP2_BASE,
242 .end = OMAP3430_ISP_CCP2_END,
243 .flags = IORESOURCE_MEM,
244 },
245 {
246 .start = OMAP3430_ISP_CCDC_BASE,
247 .end = OMAP3430_ISP_CCDC_END,
248 .flags = IORESOURCE_MEM,
249 },
250 {
251 .start = OMAP3430_ISP_HIST_BASE,
252 .end = OMAP3430_ISP_HIST_END,
253 .flags = IORESOURCE_MEM,
254 },
255 {
256 .start = OMAP3430_ISP_H3A_BASE,
257 .end = OMAP3430_ISP_H3A_END,
258 .flags = IORESOURCE_MEM,
259 },
260 {
261 .start = OMAP3430_ISP_PREV_BASE,
262 .end = OMAP3430_ISP_PREV_END,
263 .flags = IORESOURCE_MEM,
264 },
265 {
266 .start = OMAP3430_ISP_RESZ_BASE,
267 .end = OMAP3430_ISP_RESZ_END,
268 .flags = IORESOURCE_MEM,
269 },
270 {
271 .start = OMAP3430_ISP_SBL_BASE,
272 .end = OMAP3430_ISP_SBL_END,
273 .flags = IORESOURCE_MEM,
274 },
275 {
276 .start = OMAP3430_ISP_CSI2A_REGS1_BASE,
277 .end = OMAP3430_ISP_CSI2A_REGS1_END,
278 .flags = IORESOURCE_MEM,
279 },
280 {
281 .start = OMAP3430_ISP_CSIPHY2_BASE,
282 .end = OMAP3430_ISP_CSIPHY2_END,
283 .flags = IORESOURCE_MEM,
284 },
285 {
286 .start = OMAP3630_ISP_CSI2A_REGS2_BASE,
287 .end = OMAP3630_ISP_CSI2A_REGS2_END,
288 .flags = IORESOURCE_MEM,
289 },
290 {
291 .start = OMAP3630_ISP_CSI2C_REGS1_BASE,
292 .end = OMAP3630_ISP_CSI2C_REGS1_END,
293 .flags = IORESOURCE_MEM,
294 },
295 {
296 .start = OMAP3630_ISP_CSIPHY1_BASE,
297 .end = OMAP3630_ISP_CSIPHY1_END,
298 .flags = IORESOURCE_MEM,
299 },
300 {
301 .start = OMAP3630_ISP_CSI2C_REGS2_BASE,
302 .end = OMAP3630_ISP_CSI2C_REGS2_END,
303 .flags = IORESOURCE_MEM,
304 },
305 {
306 .start = INT_34XX_CAM_IRQ,
307 .flags = IORESOURCE_IRQ,
308 }
309 };
311 static struct platform_device omap3isp_device = {
312 .name = "omap3isp",
313 .id = -1,
314 .num_resources = ARRAY_SIZE(omap3isp_resources),
315 .resource = omap3isp_resources,
316 };
318 int omap3_init_camera(struct isp_platform_data *pdata)
319 {
320 omap3isp_device.dev.platform_data = pdata;
321 return platform_device_register(&omap3isp_device);
322 }
324 static inline void omap_init_camera(void)
325 {
326 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
327 if (cpu_is_omap24xx())
328 platform_device_register(&omap2cam_device);
329 #endif
330 }
332 int __init omap4_keyboard_init(struct omap4_keypad_platform_data
333 *sdp4430_keypad_data, struct omap_board_data *bdata)
334 {
335 struct platform_device *pdev;
336 struct omap_hwmod *oh;
337 struct omap4_keypad_platform_data *keypad_data;
338 unsigned int id = -1;
339 char *oh_name = "kbd";
340 char *name = "omap4-keypad";
342 oh = omap_hwmod_lookup(oh_name);
343 if (!oh) {
344 pr_err("Could not look up %s\n", oh_name);
345 return -ENODEV;
346 }
348 keypad_data = sdp4430_keypad_data;
350 pdev = omap_device_build(name, id, oh, keypad_data,
351 sizeof(struct omap4_keypad_platform_data), NULL, 0, 0);
353 if (IS_ERR(pdev)) {
354 WARN(1, "Can't build omap_device for %s:%s.\n",
355 name, oh->name);
356 return PTR_ERR(pdev);
357 }
358 oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
360 return 0;
361 }
363 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
364 static inline void omap_init_mbox(void)
365 {
366 struct omap_hwmod *oh;
367 struct platform_device *pdev;
369 oh = omap_hwmod_lookup("mailbox");
370 if (!oh) {
371 pr_err("%s: unable to find hwmod\n", __func__);
372 return;
373 }
375 pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0);
376 WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
377 __func__, PTR_ERR(pdev));
378 }
379 #else
380 static inline void omap_init_mbox(void) { }
381 #endif /* CONFIG_OMAP_MBOX_FWK */
383 static inline void omap_init_sti(void) {}
385 #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
387 static struct platform_device omap_pcm = {
388 .name = "omap-pcm-audio",
389 .id = -1,
390 };
392 /*
393 * OMAP2420 has 2 McBSP ports
394 * OMAP2430 has 5 McBSP ports
395 * OMAP3 has 5 McBSP ports
396 * OMAP4 has 4 McBSP ports
397 */
398 OMAP_MCBSP_PLATFORM_DEVICE(1);
399 OMAP_MCBSP_PLATFORM_DEVICE(2);
400 OMAP_MCBSP_PLATFORM_DEVICE(3);
401 OMAP_MCBSP_PLATFORM_DEVICE(4);
402 OMAP_MCBSP_PLATFORM_DEVICE(5);
404 static void omap_init_audio(void)
405 {
406 platform_device_register(&omap_mcbsp1);
407 platform_device_register(&omap_mcbsp2);
408 if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
409 platform_device_register(&omap_mcbsp3);
410 platform_device_register(&omap_mcbsp4);
411 }
412 if (cpu_is_omap243x() || cpu_is_omap34xx())
413 platform_device_register(&omap_mcbsp5);
415 platform_device_register(&omap_pcm);
416 }
418 #else
419 static inline void omap_init_audio(void) {}
420 #endif
422 #if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
423 defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
425 static void omap_init_mcpdm(void)
426 {
427 struct omap_hwmod *oh;
428 struct platform_device *pdev;
430 oh = omap_hwmod_lookup("mcpdm");
431 if (!oh) {
432 printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
433 return;
434 }
436 pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0, NULL, 0, 0);
437 WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n");
438 }
439 #else
440 static inline void omap_init_mcpdm(void) {}
441 #endif
443 #if defined(CONFIG_SND_OMAP_SOC_DMIC) || \
444 defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE)
446 static void omap_init_dmic(void)
447 {
448 struct omap_hwmod *oh;
449 struct platform_device *pdev;
451 oh = omap_hwmod_lookup("dmic");
452 if (!oh) {
453 printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
454 return;
455 }
457 pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0, NULL, 0, 0);
458 WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
459 }
460 #else
461 static inline void omap_init_dmic(void) {}
462 #endif
464 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
466 #include <plat/mcspi.h>
468 static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
469 {
470 struct platform_device *pdev;
471 char *name = "omap2_mcspi";
472 struct omap2_mcspi_platform_config *pdata;
473 static int spi_num;
474 struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr;
476 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
477 if (!pdata) {
478 pr_err("Memory allocation for McSPI device failed\n");
479 return -ENOMEM;
480 }
482 pdata->num_cs = mcspi_attrib->num_chipselect;
483 switch (oh->class->rev) {
484 case OMAP2_MCSPI_REV:
485 case OMAP3_MCSPI_REV:
486 pdata->regs_offset = 0;
487 break;
488 case OMAP4_MCSPI_REV:
489 pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET;
490 break;
491 default:
492 pr_err("Invalid McSPI Revision value\n");
493 return -EINVAL;
494 }
496 spi_num++;
497 pdev = omap_device_build(name, spi_num, oh, pdata,
498 sizeof(*pdata), NULL, 0, 0);
499 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n",
500 name, oh->name);
501 kfree(pdata);
502 return 0;
503 }
505 static void omap_init_mcspi(void)
506 {
507 omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
508 }
510 #else
511 static inline void omap_init_mcspi(void) {}
512 #endif
514 #ifdef CONFIG_SOC_OMAPAM33XX
516 static int omap_elm_init(struct omap_hwmod *oh, void *unused)
517 {
518 struct platform_device *pdev;
519 char *name = "omap2_elm";
520 static int elm_num;
523 elm_num++;
524 pdev = omap_device_build(name, elm_num, oh, NULL,
525 0, NULL,
526 0, 0);
527 return 0;
528 }
530 static void omap_init_elm(void)
531 {
533 omap_hwmod_for_each_by_class("elm", omap_elm_init, NULL);
534 }
536 #else
537 static void omap_init_elm(void) {}
538 #endif
541 static struct resource omap2_pmu_resource = {
542 .start = 3,
543 .end = 3,
544 .flags = IORESOURCE_IRQ,
545 };
547 static struct resource omap3_pmu_resource = {
548 .start = INT_34XX_BENCH_MPU_EMUL,
549 .end = INT_34XX_BENCH_MPU_EMUL,
550 .flags = IORESOURCE_IRQ,
551 };
553 static struct platform_device omap_pmu_device = {
554 .name = "arm-pmu",
555 .id = ARM_PMU_DEVICE_CPU,
556 .num_resources = 1,
557 };
559 static void omap_init_pmu(void)
560 {
561 if (cpu_is_omap24xx())
562 omap_pmu_device.resource = &omap2_pmu_resource;
563 else if (cpu_is_omap34xx())
564 omap_pmu_device.resource = &omap3_pmu_resource;
565 else
566 return;
568 platform_device_register(&omap_pmu_device);
569 }
572 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
574 #ifdef CONFIG_ARCH_OMAP2
575 static struct resource omap2_sham_resources[] = {
576 {
577 .start = OMAP24XX_SEC_SHA1MD5_BASE,
578 .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
579 .flags = IORESOURCE_MEM,
580 },
581 {
582 .start = INT_24XX_SHA1MD5,
583 .flags = IORESOURCE_IRQ,
584 }
585 };
586 static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
587 #else
588 #define omap2_sham_resources NULL
589 #define omap2_sham_resources_sz 0
590 #endif
592 #ifdef CONFIG_ARCH_OMAP3
593 static struct resource omap3_sham_resources[] = {
594 {
595 .start = OMAP34XX_SEC_SHA1MD5_BASE,
596 .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
597 .flags = IORESOURCE_MEM,
598 },
599 {
600 .start = INT_34XX_SHA1MD52_IRQ,
601 .flags = IORESOURCE_IRQ,
602 },
603 {
604 .start = OMAP34XX_DMA_SHA1MD5_RX,
605 .flags = IORESOURCE_DMA,
606 }
607 };
608 static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
609 #else
610 #define omap3_sham_resources NULL
611 #define omap3_sham_resources_sz 0
612 #endif
614 static struct platform_device sham_device = {
615 .name = "omap-sham",
616 .id = -1,
617 };
619 static void omap_init_sham(void)
620 {
621 if (cpu_is_omap24xx()) {
622 sham_device.resource = omap2_sham_resources;
623 sham_device.num_resources = omap2_sham_resources_sz;
624 } else if (cpu_is_omap34xx()) {
625 sham_device.resource = omap3_sham_resources;
626 sham_device.num_resources = omap3_sham_resources_sz;
627 } else {
628 pr_err("%s: platform not supported\n", __func__);
629 return;
630 }
631 platform_device_register(&sham_device);
632 }
633 #else
634 static inline void omap_init_sham(void) { }
635 #endif
637 #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
639 #ifdef CONFIG_ARCH_OMAP2
640 static struct resource omap2_aes_resources[] = {
641 {
642 .start = OMAP24XX_SEC_AES_BASE,
643 .end = OMAP24XX_SEC_AES_BASE + 0x4C,
644 .flags = IORESOURCE_MEM,
645 },
646 {
647 .start = OMAP24XX_DMA_AES_TX,
648 .flags = IORESOURCE_DMA,
649 },
650 {
651 .start = OMAP24XX_DMA_AES_RX,
652 .flags = IORESOURCE_DMA,
653 }
654 };
655 static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
656 #else
657 #define omap2_aes_resources NULL
658 #define omap2_aes_resources_sz 0
659 #endif
661 #ifdef CONFIG_ARCH_OMAP3
662 static struct resource omap3_aes_resources[] = {
663 {
664 .start = OMAP34XX_SEC_AES_BASE,
665 .end = OMAP34XX_SEC_AES_BASE + 0x4C,
666 .flags = IORESOURCE_MEM,
667 },
668 {
669 .start = OMAP34XX_DMA_AES2_TX,
670 .flags = IORESOURCE_DMA,
671 },
672 {
673 .start = OMAP34XX_DMA_AES2_RX,
674 .flags = IORESOURCE_DMA,
675 }
676 };
677 static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
678 #else
679 #define omap3_aes_resources NULL
680 #define omap3_aes_resources_sz 0
681 #endif
683 static struct platform_device aes_device = {
684 .name = "omap-aes",
685 .id = -1,
686 };
688 static void omap_init_aes(void)
689 {
690 if (cpu_is_omap24xx()) {
691 aes_device.resource = omap2_aes_resources;
692 aes_device.num_resources = omap2_aes_resources_sz;
693 } else if (cpu_is_omap34xx()) {
694 aes_device.resource = omap3_aes_resources;
695 aes_device.num_resources = omap3_aes_resources_sz;
696 } else {
697 pr_err("%s: platform not supported\n", __func__);
698 return;
699 }
700 platform_device_register(&aes_device);
701 }
703 #else
704 static inline void omap_init_aes(void) { }
705 #endif
707 /*-------------------------------------------------------------------------*/
709 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
711 static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
712 *mmc_controller)
713 {
714 if ((mmc_controller->slots[0].switch_pin > 0) && \
715 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
716 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
717 OMAP_PIN_INPUT_PULLUP);
718 if ((mmc_controller->slots[0].gpio_wp > 0) && \
719 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
720 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
721 OMAP_PIN_INPUT_PULLUP);
723 omap_mux_init_signal("sdmmc_cmd", 0);
724 omap_mux_init_signal("sdmmc_clki", 0);
725 omap_mux_init_signal("sdmmc_clko", 0);
726 omap_mux_init_signal("sdmmc_dat0", 0);
727 omap_mux_init_signal("sdmmc_dat_dir0", 0);
728 omap_mux_init_signal("sdmmc_cmd_dir", 0);
729 if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
730 omap_mux_init_signal("sdmmc_dat1", 0);
731 omap_mux_init_signal("sdmmc_dat2", 0);
732 omap_mux_init_signal("sdmmc_dat3", 0);
733 omap_mux_init_signal("sdmmc_dat_dir1", 0);
734 omap_mux_init_signal("sdmmc_dat_dir2", 0);
735 omap_mux_init_signal("sdmmc_dat_dir3", 0);
736 }
738 /*
739 * Use internal loop-back in MMC/SDIO Module Input Clock
740 * selection
741 */
742 if (mmc_controller->slots[0].internal_clock) {
743 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
744 v |= (1 << 24);
745 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
746 }
747 }
749 void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
750 {
751 char *name = "mmci-omap";
753 if (!mmc_data[0]) {
754 pr_err("%s fails: Incomplete platform data\n", __func__);
755 return;
756 }
758 omap242x_mmc_mux(mmc_data[0]);
759 omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE,
760 INT_24XX_MMC_IRQ, mmc_data[0]);
761 }
763 #endif
765 /*-------------------------------------------------------------------------*/
767 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
768 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
769 #define OMAP_HDQ_BASE 0x480B2000
770 #endif
771 static struct resource omap_hdq_resources[] = {
772 {
773 .start = OMAP_HDQ_BASE,
774 .end = OMAP_HDQ_BASE + 0x1C,
775 .flags = IORESOURCE_MEM,
776 },
777 {
778 .start = INT_24XX_HDQ_IRQ,
779 .flags = IORESOURCE_IRQ,
780 },
781 };
782 static struct platform_device omap_hdq_dev = {
783 .name = "omap_hdq",
784 .id = 0,
785 .dev = {
786 .platform_data = NULL,
787 },
788 .num_resources = ARRAY_SIZE(omap_hdq_resources),
789 .resource = omap_hdq_resources,
790 };
791 static inline void omap_hdq_init(void)
792 {
793 (void) platform_device_register(&omap_hdq_dev);
794 }
795 #else
796 static inline void omap_hdq_init(void) {}
797 #endif
799 /*---------------------------------------------------------------------------*/
801 #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
802 defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
803 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
804 static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
805 };
806 #else
807 static struct resource omap_vout_resource[2] = {
808 };
809 #endif
811 static struct platform_device omap_vout_device = {
812 .name = "omap_vout",
813 .num_resources = ARRAY_SIZE(omap_vout_resource),
814 .resource = &omap_vout_resource[0],
815 .id = -1,
816 };
817 static void omap_init_vout(void)
818 {
819 if (platform_device_register(&omap_vout_device) < 0)
820 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
821 }
822 #else
823 static inline void omap_init_vout(void) {}
824 #endif
826 #if defined(CONFIG_SOC_OMAPAM33XX) && defined(CONFIG_OMAP3_EDMA)
828 #define AM33XX_TPCC_BASE 0x49000000
829 #define AM33XX_TPTC0_BASE 0x49800000
830 #define AM33XX_TPTC1_BASE 0x49900000
831 #define AM33XX_TPTC2_BASE 0x49a00000
833 #define AM33XX_SCM_BASE_EDMA 0x00000f90
835 static struct resource am33xx_edma_resources[] = {
836 {
837 .name = "edma_cc0",
838 .start = AM33XX_TPCC_BASE,
839 .end = AM33XX_TPCC_BASE + SZ_32K - 1,
840 .flags = IORESOURCE_MEM,
841 },
842 {
843 .name = "edma_tc0",
844 .start = AM33XX_TPTC0_BASE,
845 .end = AM33XX_TPTC0_BASE + SZ_1K - 1,
846 .flags = IORESOURCE_MEM,
847 },
848 {
849 .name = "edma_tc1",
850 .start = AM33XX_TPTC1_BASE,
851 .end = AM33XX_TPTC1_BASE + SZ_1K - 1,
852 .flags = IORESOURCE_MEM,
853 },
854 {
855 .name = "edma_tc2",
856 .start = AM33XX_TPTC2_BASE,
857 .end = AM33XX_TPTC2_BASE + SZ_1K - 1,
858 .flags = IORESOURCE_MEM,
859 },
860 {
861 .name = "edma0",
862 .start = AM33XX_IRQ_TPCC0_INT_PO0,
863 .flags = IORESOURCE_IRQ,
864 },
865 {
866 .name = "edma0_err",
867 .start = AM33XX_IRQ_TPCC0_ERRINT_PO,
868 .flags = IORESOURCE_IRQ,
869 },
870 };
872 static const s16 am33xx_dma_rsv_chans[][2] = {
873 /* (offset, number) */
874 {0, 2},
875 {14, 2},
876 {26, 6},
877 {48, 4},
878 {56, 8},
879 {-1, -1}
880 };
882 static const s16 am33xx_dma_rsv_slots[][2] = {
883 /* (offset, number) */
884 {0, 2},
885 {14, 2},
886 {26, 6},
887 {48, 4},
888 {56, 8},
889 {64, 127},
890 {-1, -1}
891 };
893 /* Three Transfer Controllers on AM33XX */
894 static const s8 am33xx_queue_tc_mapping[][2] = {
895 /* {event queue no, TC no} */
896 {0, 0},
897 {1, 1},
898 {2, 2},
899 {-1, -1}
900 };
902 static const s8 am33xx_queue_priority_mapping[][2] = {
903 /* {event queue no, Priority} */
904 {0, 0},
905 {1, 1},
906 {2, 2},
907 {-1, -1}
908 };
910 static struct event_to_channel_map am33xx_xbar_event_mapping[] = {
911 /* {xbar event no, Channel} */
912 {1, 12}, /* SDTXEVT1 -> MMCHS2 */
913 {2, 13}, /* SDRXEVT1 -> MMCHS2 */
914 {3, -1},
915 {4, -1},
916 {5, -1},
917 {6, -1},
918 {7, -1},
919 {8, -1},
920 {9, -1},
921 {10, -1},
922 {11, -1},
923 {12, -1},
924 {13, -1},
925 {14, -1},
926 {15, -1},
927 {16, -1},
928 {17, -1},
929 {18, -1},
930 {19, -1},
931 {20, -1},
932 {21, -1},
933 {22, -1},
934 {23, -1},
935 {24, -1},
936 {25, -1},
937 {26, -1},
938 {27, -1},
939 {28, -1},
940 {29, -1},
941 {30, -1},
942 {31, -1},
943 {-1, -1}
944 };
946 /**
947 * map_xbar_event_to_channel - maps a crossbar event to a DMA channel
948 * according to the configuration provided
949 * @event: the event number for which mapping is required
950 * @channel: channel being activated
951 * @xbar_event_mapping: array that has the event to channel map
952 *
953 * Events that are routed by default are not mapped. Only events that
954 * are crossbar mapped are routed to available channels according to
955 * the configuration provided
956 *
957 * Returns zero on success, else negative errno.
958 */
959 int map_xbar_event_to_channel(unsigned int event, unsigned int *channel,
960 struct event_to_channel_map *xbar_event_mapping)
961 {
962 unsigned int ctrl = 0;
963 unsigned int xbar_evt_no = 0;
964 unsigned int val = 0;
965 unsigned int offset = 0;
966 unsigned int mask = 0;
968 ctrl = EDMA_CTLR(event);
969 xbar_evt_no = event - (edma_info[ctrl]->num_channels);
971 if (event < edma_info[ctrl]->num_channels) {
972 *channel = event;
973 } else if (event < edma_info[ctrl]->num_events) {
974 *channel = xbar_event_mapping[xbar_evt_no].channel_no;
975 /* confirm the range */
976 if (*channel < EDMA_MAX_DMACH)
977 clear_bit(*channel, edma_info[ctrl]->edma_unused);
978 mask = (*channel)%4;
979 offset = (*channel)/4;
980 offset *= 4;
981 offset += mask;
982 val = (unsigned int)__raw_readl(AM33XX_CTRL_REGADDR(
983 AM33XX_SCM_BASE_EDMA + offset));
984 val = val & (~(0xFF));
985 val = val | (xbar_event_mapping[xbar_evt_no].xbar_event_no);
986 __raw_writel(val,
987 AM33XX_CTRL_REGADDR(AM33XX_SCM_BASE_EDMA + offset));
988 return 0;
989 } else {
990 return -EINVAL;
991 }
993 return 0;
994 }
996 static struct edma_soc_info am33xx_edma_info[] = {
997 {
998 .n_channel = 64,
999 .n_region = 4,
1000 .n_slot = 256,
1001 .n_tc = 3,
1002 .n_cc = 1,
1003 .rsv_chans = am33xx_dma_rsv_chans,
1004 .rsv_slots = am33xx_dma_rsv_slots,
1005 .queue_tc_mapping = am33xx_queue_tc_mapping,
1006 .queue_priority_mapping = am33xx_queue_priority_mapping,
1007 .is_xbar = 1,
1008 .n_events = 95,
1009 .xbar_event_mapping = am33xx_xbar_event_mapping,
1010 .map_xbar_channel = map_xbar_event_to_channel,
1011 },
1012 };
1014 static struct platform_device am33xx_edma_device = {
1015 .name = "edma",
1016 .id = -1,
1017 .dev = {
1018 .platform_data = am33xx_edma_info,
1019 },
1020 .num_resources = ARRAY_SIZE(am33xx_edma_resources),
1021 .resource = am33xx_edma_resources,
1022 };
1024 int __init am33xx_register_edma(void)
1025 {
1026 struct platform_device *pdev;
1027 static struct clk *edma_clk;
1029 if (cpu_is_am33xx())
1030 pdev = &am33xx_edma_device;
1031 else {
1032 pr_err("%s: platform not supported\n", __func__);
1033 return -ENODEV;
1034 }
1036 edma_clk = clk_get(NULL, "tpcc_ick");
1037 if (IS_ERR(edma_clk)) {
1038 printk(KERN_ERR "EDMA: Failed to get clock\n");
1039 return -EBUSY;
1040 }
1041 clk_enable(edma_clk);
1042 edma_clk = clk_get(NULL, "tptc0_ick");
1043 if (IS_ERR(edma_clk)) {
1044 printk(KERN_ERR "EDMA: Failed to get clock\n");
1045 return -EBUSY;
1046 }
1047 clk_enable(edma_clk);
1048 edma_clk = clk_get(NULL, "tptc1_ick");
1049 if (IS_ERR(edma_clk)) {
1050 printk(KERN_ERR "EDMA: Failed to get clock\n");
1051 return -EBUSY;
1052 }
1053 clk_enable(edma_clk);
1054 edma_clk = clk_get(NULL, "tptc2_ick");
1055 if (IS_ERR(edma_clk)) {
1056 printk(KERN_ERR "EDMA: Failed to get clock\n");
1057 return -EBUSY;
1058 }
1059 clk_enable(edma_clk);
1061 return platform_device_register(pdev);
1062 }
1064 #else
1065 static inline void am33xx_register_edma(void) {}
1066 #endif
1068 /*-------------------------------------------------------------------------*/
1070 static int __init omap2_init_devices(void)
1071 {
1072 /*
1073 * please keep these calls, and their implementations above,
1074 * in alphabetical order so they're easier to sort through.
1075 */
1076 omap_init_audio();
1077 omap_init_mcpdm();
1078 omap_init_dmic();
1079 omap_init_camera();
1080 omap_init_mbox();
1081 omap_init_mcspi();
1082 omap_init_elm();
1083 omap_init_pmu();
1084 omap_hdq_init();
1085 omap_init_sti();
1086 omap_init_sham();
1087 omap_init_aes();
1088 omap_init_vout();
1089 am33xx_register_edma();
1090 am33xx_init_pcm();
1092 return 0;
1093 }
1094 arch_initcall(omap2_init_devices);
1096 #define AM33XX_CPSW_BASE (0x4A100000)
1097 #define AM33XX_CPSW_MDIO_BASE (0x4A101000)
1098 #define AM33XX_CPSW_SS_BASE (0x4A101200)
1099 #define AM33XX_EMAC_MDIO_FREQ (1000000)
1101 static u64 am33xx_cpsw_dmamask = DMA_BIT_MASK(32);
1102 /* TODO : Verify the offsets */
1103 static struct cpsw_slave_data am33xx_cpsw_slaves[] = {
1104 {
1105 .slave_reg_ofs = 0x208,
1106 .sliver_reg_ofs = 0xd80,
1107 .phy_id = "0:00",
1108 },
1109 {
1110 .slave_reg_ofs = 0x308,
1111 .sliver_reg_ofs = 0xdc0,
1112 .phy_id = "0:01",
1113 },
1114 };
1116 static struct cpsw_platform_data am33xx_cpsw_pdata = {
1117 .ss_reg_ofs = 0x1200,
1118 .channels = 8,
1119 .cpdma_reg_ofs = 0x800,
1120 .slaves = 2,
1121 .slave_data = am33xx_cpsw_slaves,
1122 .ale_reg_ofs = 0xd00,
1123 .ale_entries = 1024,
1124 .host_port_reg_ofs = 0x108,
1125 .hw_stats_reg_ofs = 0x900,
1126 .bd_ram_ofs = 0x2000,
1127 .bd_ram_size = SZ_8K,
1128 .rx_descs = 64,
1129 .mac_control = BIT(5), /* MIIEN */
1130 .gigabit_en = 1,
1131 .host_port_num = 0,
1132 .no_bd_ram = false,
1133 .version = CPSW_VERSION_2,
1134 };
1136 static struct mdio_platform_data am33xx_cpsw_mdiopdata = {
1137 .bus_freq = AM33XX_EMAC_MDIO_FREQ,
1138 };
1140 static struct resource am33xx_cpsw_mdioresources[] = {
1141 {
1142 .start = AM33XX_CPSW_MDIO_BASE,
1143 .end = AM33XX_CPSW_MDIO_BASE + SZ_256 - 1,
1144 .flags = IORESOURCE_MEM,
1145 },
1146 };
1148 static struct platform_device am33xx_cpsw_mdiodevice = {
1149 .name = "davinci_mdio",
1150 .id = 0,
1151 .num_resources = ARRAY_SIZE(am33xx_cpsw_mdioresources),
1152 .resource = am33xx_cpsw_mdioresources,
1153 .dev.platform_data = &am33xx_cpsw_mdiopdata,
1154 };
1156 static struct resource am33xx_cpsw_resources[] = {
1157 {
1158 .start = AM33XX_CPSW_BASE,
1159 .end = AM33XX_CPSW_BASE + SZ_2K - 1,
1160 .flags = IORESOURCE_MEM,
1161 },
1162 {
1163 .start = AM33XX_CPSW_SS_BASE,
1164 .end = AM33XX_CPSW_SS_BASE + SZ_256 - 1,
1165 .flags = IORESOURCE_MEM,
1166 },
1167 {
1168 .start = AM33XX_IRQ_CPSW_C0_RX,
1169 .end = AM33XX_IRQ_CPSW_C0_RX,
1170 .flags = IORESOURCE_IRQ,
1171 },
1172 {
1173 .start = AM33XX_IRQ_CPSW_RX,
1174 .end = AM33XX_IRQ_CPSW_RX,
1175 .flags = IORESOURCE_IRQ,
1176 },
1177 {
1178 .start = AM33XX_IRQ_CPSW_TX,
1179 .end = AM33XX_IRQ_CPSW_TX,
1180 .flags = IORESOURCE_IRQ,
1181 },
1182 {
1183 .start = AM33XX_IRQ_CPSW_C0,
1184 .end = AM33XX_IRQ_CPSW_C0,
1185 .flags = IORESOURCE_IRQ,
1186 },
1187 };
1189 static struct platform_device am33xx_cpsw_device = {
1190 .name = "cpsw",
1191 .id = 0,
1192 .num_resources = ARRAY_SIZE(am33xx_cpsw_resources),
1193 .resource = am33xx_cpsw_resources,
1194 .dev = {
1195 .platform_data = &am33xx_cpsw_pdata,
1196 .dma_mask = &am33xx_cpsw_dmamask,
1197 .coherent_dma_mask = DMA_BIT_MASK(32),
1198 },
1199 };
1201 static unsigned char am33xx_macid0[ETH_ALEN];
1202 static unsigned char am33xx_macid1[ETH_ALEN];
1203 static unsigned int am33xx_evmid;
1205 /*
1206 * am33xx_evmid_fillup - set up board evmid
1207 * @evmid - evm id which needs to be configured
1208 *
1209 * This function is called to configure board evm id.
1210 * IA Motor Control EVM needs special setting of MAC PHY Id.
1211 * This function is called when IA Motor Control EVM is detected
1212 * during boot-up.
1213 */
1214 void am33xx_evmid_fillup(unsigned int evmid)
1215 {
1216 am33xx_evmid = evmid;
1217 return;
1218 }
1220 /*
1221 * am33xx_cpsw_macidfillup - setup mac adrresses
1222 * @eeprommacid0 - mac id 0 which needs to be configured
1223 * @eeprommacid1 - mac id 1 which needs to be configured
1224 *
1225 * This function is called to configure mac addresses.
1226 * Mac addresses are read from eeprom and this function is called
1227 * to store those mac adresses in am33xx_macid0 and am33xx_macid1.
1228 * In case, mac address read from eFuse are invalid, mac addresses
1229 * stored in these variable are used.
1230 */
1231 void am33xx_cpsw_macidfillup(char *eeprommacid0, char *eeprommacid1)
1232 {
1233 u32 i;
1235 /* Fillup these mac addresses with the mac adresses from eeprom */
1236 for (i = 0; i < ETH_ALEN; i++) {
1237 am33xx_macid0[i] = eeprommacid0[i];
1238 am33xx_macid1[i] = eeprommacid1[i];
1239 }
1241 return;
1242 }
1244 void am33xx_cpsw_init(unsigned int gigen)
1245 {
1246 u32 mac_lo, mac_hi;
1247 u32 i;
1249 mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_LO);
1250 mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_HI);
1251 am33xx_cpsw_slaves[0].mac_addr[0] = mac_hi & 0xFF;
1252 am33xx_cpsw_slaves[0].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1253 am33xx_cpsw_slaves[0].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
1254 am33xx_cpsw_slaves[0].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
1255 am33xx_cpsw_slaves[0].mac_addr[4] = mac_lo & 0xFF;
1256 am33xx_cpsw_slaves[0].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
1258 /* Read MACID0 from eeprom if eFuse MACID is invalid */
1259 if (!is_valid_ether_addr(am33xx_cpsw_slaves[0].mac_addr)) {
1260 for (i = 0; i < ETH_ALEN; i++)
1261 am33xx_cpsw_slaves[0].mac_addr[i] = am33xx_macid0[i];
1262 }
1264 mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_LO);
1265 mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_HI);
1266 am33xx_cpsw_slaves[1].mac_addr[0] = mac_hi & 0xFF;
1267 am33xx_cpsw_slaves[1].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
1268 am33xx_cpsw_slaves[1].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
1269 am33xx_cpsw_slaves[1].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
1270 am33xx_cpsw_slaves[1].mac_addr[4] = mac_lo & 0xFF;
1271 am33xx_cpsw_slaves[1].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
1273 /* Read MACID1 from eeprom if eFuse MACID is invalid */
1274 if (!is_valid_ether_addr(am33xx_cpsw_slaves[1].mac_addr)) {
1275 for (i = 0; i < ETH_ALEN; i++)
1276 am33xx_cpsw_slaves[1].mac_addr[i] = am33xx_macid1[i];
1277 }
1279 if (am33xx_evmid == IND_AUT_MTR_EVM) {
1280 am33xx_cpsw_slaves[0].phy_id = "0:1e";
1281 am33xx_cpsw_slaves[1].phy_id = "0:00";
1282 }
1284 am33xx_cpsw_pdata.gigabit_en = gigen;
1286 memcpy(am33xx_cpsw_pdata.mac_addr,
1287 am33xx_cpsw_slaves[0].mac_addr, ETH_ALEN);
1288 platform_device_register(&am33xx_cpsw_mdiodevice);
1289 platform_device_register(&am33xx_cpsw_device);
1290 clk_add_alias(NULL, dev_name(&am33xx_cpsw_mdiodevice.dev),
1291 NULL, &am33xx_cpsw_device.dev);
1292 }
1294 #define AM33XX_D_CAN_RAM_BASE 0x1000
1295 #define AM33XX_D_CAN_NUM_MSG_OBJS 64
1296 #define AM33XX_CTL_DCAN_RAMINIT_OFFSET 0x644
1297 #define AM33XX_D_CAN_RAMINIT_START(n) (0x1 << n)
1299 static void d_can_hw_raminit(unsigned int instance)
1300 {
1301 u32 val;
1303 /* Read the value */
1304 val = __raw_readl(AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET));
1306 /* Modify by setting "0" */
1307 val &= ~AM33XX_D_CAN_RAMINIT_START(instance);
1308 __raw_writel(val, AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET));
1310 /* Reset to one */
1311 val |= AM33XX_D_CAN_RAMINIT_START(instance);
1312 __raw_writel(val, AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET));
1314 /* Give some time delay for transition from 0 -> 1 */
1315 udelay(1);
1316 }
1318 static struct d_can_platform_data am33xx_evm_d_can0_pdata = {
1319 .d_can_offset = 0,
1320 .d_can_ram_offset = AM33XX_D_CAN_RAM_BASE,
1321 .num_of_msg_objs = AM33XX_D_CAN_NUM_MSG_OBJS,
1322 .dma_support = false,
1323 .parity_check = false,
1324 .fck_name = "dcan0_fck",
1325 .ick_name = "dcan0_ick",
1326 };
1328 static struct resource am33xx_d_can0_resources[] = {
1329 {
1330 .start = AM33XX_D_CAN0_BASE,
1331 .end = AM33XX_D_CAN0_BASE + 0x3FFF,
1332 .flags = IORESOURCE_MEM,
1333 },
1334 {
1335 .name = "int0",
1336 .start = AM33XX_IRQ_DCAN0_0,
1337 .end = AM33XX_IRQ_DCAN0_0,
1338 .flags = IORESOURCE_IRQ,
1339 },
1340 {
1341 .name = "int1",
1342 .start = AM33XX_IRQ_DCAN0_1,
1343 .end = AM33XX_IRQ_DCAN0_1,
1344 .flags = IORESOURCE_IRQ,
1345 },
1346 };
1348 static struct platform_device am33xx_d_can0_device = {
1349 .dev = {
1350 .platform_data = &am33xx_evm_d_can0_pdata,
1351 },
1352 .name = "d_can",
1353 .id = -1,
1354 .num_resources = ARRAY_SIZE(am33xx_d_can0_resources),
1355 .resource = am33xx_d_can0_resources,
1356 };
1358 static struct resource am33xx_d_can1_resources[] = {
1359 {
1360 .start = AM33XX_D_CAN1_BASE,
1361 .end = AM33XX_D_CAN1_BASE + 0x3FFF,
1362 .flags = IORESOURCE_MEM,
1363 },
1364 {
1365 .name = "int0",
1366 .start = AM33XX_IRQ_DCAN1_0,
1367 .end = AM33XX_IRQ_DCAN1_0,
1368 .flags = IORESOURCE_IRQ,
1369 },
1370 {
1371 .name = "int1",
1372 .start = AM33XX_IRQ_DCAN1_1,
1373 .end = AM33XX_IRQ_DCAN1_1,
1374 .flags = IORESOURCE_IRQ,
1375 },
1376 };
1378 static struct d_can_platform_data am33xx_evm_d_can1_pdata = {
1379 .d_can_offset = 0,
1380 .d_can_ram_offset = AM33XX_D_CAN_RAM_BASE,
1381 .num_of_msg_objs = AM33XX_D_CAN_NUM_MSG_OBJS,
1382 .dma_support = false,
1383 .parity_check = false,
1384 .fck_name = "dcan1_fck",
1385 .ick_name = "dcan1_ick",
1386 };
1388 static struct platform_device am33xx_d_can1_device = {
1389 .dev = {
1390 .platform_data = &am33xx_evm_d_can1_pdata,
1391 },
1392 .name = "d_can",
1393 .id = -1,
1394 .num_resources = ARRAY_SIZE(am33xx_d_can1_resources),
1395 .resource = am33xx_d_can1_resources,
1396 };
1398 void am33xx_d_can_init(unsigned int instance)
1399 {
1400 switch (instance) {
1401 case 0:
1402 d_can_hw_raminit(instance);
1403 platform_device_register(&am33xx_d_can0_device);
1404 break;
1405 case 1:
1406 d_can_hw_raminit(instance);
1407 platform_device_register(&am33xx_d_can1_device);
1408 break;
1409 default:
1410 break;
1411 }
1412 }
1414 #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
1415 static int __init omap_init_wdt(void)
1416 {
1417 int id = -1;
1418 struct platform_device *pdev;
1419 struct omap_hwmod *oh;
1420 char *oh_name = "wd_timer2";
1421 char *dev_name = "omap_wdt";
1423 if (!cpu_class_is_omap2())
1424 return 0;
1426 oh = omap_hwmod_lookup(oh_name);
1427 if (!oh) {
1428 pr_err("Could not look up wd_timer%d hwmod\n", id);
1429 return -EINVAL;
1430 }
1432 pdev = omap_device_build(dev_name, id, oh, NULL, 0, NULL, 0, 0);
1433 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
1434 dev_name, oh->name);
1435 return 0;
1436 }
1437 subsys_initcall(omap_init_wdt);
1438 #endif