arch/arm/mach-omap2/display.c

   1 /*
   2  * OMAP2plus display device setup / initialization.
   3  *
   4  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   5  *      Senthilvadivu Guruswamy
   6  *      Sumit Semwal
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13  * kind, whether express or implied; without even the implied warranty
  14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/string.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/io.h>
  23 #include <linux/clk.h>
  24 #include <linux/err.h>
  25 #include <linux/delay.h>
  26
  27 #include <video/omapdss.h>
  28 #include <plat/omap_hwmod.h>
  29 #include <plat/omap_device.h>
  30 #include <plat/omap-pm.h>
  31 #include "common.h"
  32
  33 #include "control.h"
  34 #include "display.h"
  35
  36 #define DISPC_CONTROL           0x0040
  37 #define DISPC_CONTROL2          0x0238
  38 #define DISPC_IRQSTATUS         0x0018
  39
  40 #define DSS_SYSCONFIG           0x10
  41 #define DSS_SYSSTATUS           0x14
  42 #define DSS_CONTROL             0x40
  43 #define DSS_SDI_CONTROL         0x44
  44 #define DSS_PLL_CONTROL         0x48
  45
  46 #define LCD_EN_MASK             (0x1 << 0)
  47 #define DIGIT_EN_MASK           (0x1 << 1)
  48
  49 #define FRAMEDONE_IRQ_SHIFT     0
  50 #define EVSYNC_EVEN_IRQ_SHIFT   2
  51 #define EVSYNC_ODD_IRQ_SHIFT    3
  52 #define FRAMEDONE2_IRQ_SHIFT    22
  53 #define FRAMEDONETV_IRQ_SHIFT   24
  54
  55 /*
  56  * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
  57  *     reset before deciding that something has gone wrong
  58  */
  59 #define FRAMEDONE_IRQ_TIMEOUT           100
  60
  61 static struct platform_device omap_display_device = {
  62         .name          = "omapdss",
  63         .id            = -1,
  64         .dev            = {
  65                 .platform_data = NULL,
  66         },
  67 };
  68
  69 struct omap_dss_hwmod_data {
  70         const char *oh_name;
  71         const char *dev_name;
  72         const int id;
  73 };
  74
  75 static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
  76         { "dss_core", "omapdss_dss", -1 },
  77         { "dss_dispc", "omapdss_dispc", -1 },
  78         { "dss_rfbi", "omapdss_rfbi", -1 },
  79         { "dss_venc", "omapdss_venc", -1 },
  80 };
  81
  82 static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
  83         { "dss_core", "omapdss_dss", -1 },
  84         { "dss_dispc", "omapdss_dispc", -1 },
  85         { "dss_rfbi", "omapdss_rfbi", -1 },
  86         { "dss_venc", "omapdss_venc", -1 },
  87         { "dss_dsi1", "omapdss_dsi", 0 },
  88 };
  89
  90 static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
  91         { "dss_core", "omapdss_dss", -1 },
  92         { "dss_dispc", "omapdss_dispc", -1 },
  93         { "dss_rfbi", "omapdss_rfbi", -1 },
  94         { "dss_venc", "omapdss_venc", -1 },
  95         { "dss_dsi1", "omapdss_dsi", 0 },
  96         { "dss_dsi2", "omapdss_dsi", 1 },
  97         { "dss_hdmi", "omapdss_hdmi", -1 },
  98 };
  99
 100 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
 101 {
 102         u32 enable_mask, enable_shift;
 103         u32 pipd_mask, pipd_shift;
 104         u32 reg;
 105
 106         if (dsi_id == 0) {
 107                 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
 108                 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
 109                 pipd_mask = OMAP4_DSI1_PIPD_MASK;
 110                 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
 111         } else if (dsi_id == 1) {
 112                 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
 113                 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
 114                 pipd_mask = OMAP4_DSI2_PIPD_MASK;
 115                 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
 116         } else {
 117                 return -ENODEV;
 118         }
 119
 120         reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
 121
 122         reg &= ~enable_mask;
 123         reg &= ~pipd_mask;
 124
 125         reg |= (lanes << enable_shift) & enable_mask;
 126         reg |= (lanes << pipd_shift) & pipd_mask;
 127
 128         omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
 129
 130         return 0;
 131 }
 132
 133 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
 134 {
 135         if (cpu_is_omap44xx())
 136                 return omap4_dsi_mux_pads(dsi_id, lane_mask);
 137
 138         return 0;
 139 }
 140
 141 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
 142 {
 143         if (cpu_is_omap44xx())
 144                 omap4_dsi_mux_pads(dsi_id, 0);
 145 }
 146
 147 int __init omap_display_init(struct omap_dss_board_info *board_data)
 148 {
 149         int r = 0;
 150         struct omap_hwmod *oh;
 151         struct platform_device *pdev;
 152         int i, oh_count;
 153         struct omap_display_platform_data pdata;
 154         const struct omap_dss_hwmod_data *curr_dss_hwmod;
 155
 156         memset(&pdata, 0, sizeof(pdata));
 157
 158         if (cpu_is_omap24xx()) {
 159                 curr_dss_hwmod = omap2_dss_hwmod_data;
 160                 oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
 161         } else if (cpu_is_omap34xx()) {
 162                 curr_dss_hwmod = omap3_dss_hwmod_data;
 163                 oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
 164         } else {
 165                 curr_dss_hwmod = omap4_dss_hwmod_data;
 166                 oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
 167         }
 168
 169         if (board_data->dsi_enable_pads == NULL)
 170                 board_data->dsi_enable_pads = omap_dsi_enable_pads;
 171         if (board_data->dsi_disable_pads == NULL)
 172                 board_data->dsi_disable_pads = omap_dsi_disable_pads;
 173
 174         pdata.board_data = board_data;
 175         pdata.board_data->get_context_loss_count =
 176                 omap_pm_get_dev_context_loss_count;
 177
 178         for (i = 0; i < oh_count; i++) {
 179                 oh = omap_hwmod_lookup(curr_dss_hwmod[i].oh_name);
 180                 if (!oh) {
 181                         pr_err("Could not look up %s\n",
 182                                 curr_dss_hwmod[i].oh_name);
 183                         return -ENODEV;
 184                 }
 185
 186                 pdev = omap_device_build(curr_dss_hwmod[i].dev_name,
 187                                 curr_dss_hwmod[i].id, oh, &pdata,
 188                                 sizeof(struct omap_display_platform_data),
 189                                 NULL, 0, 0);
 190
 191                 if (WARN((IS_ERR(pdev)), "Could not build omap_device for %s\n",
 192                                 curr_dss_hwmod[i].oh_name))
 193                         return -ENODEV;
 194         }
 195         omap_display_device.dev.platform_data = board_data;
 196
 197         r = platform_device_register(&omap_display_device);
 198         if (r < 0)
 199                 printk(KERN_ERR "Unable to register OMAP-Display device\n");
 200
 201         return r;
 202 }
 203
 204 static void dispc_disable_outputs(void)
 205 {
 206         u32 v, irq_mask = 0;
 207         bool lcd_en, digit_en, lcd2_en = false;
 208         int i;
 209         struct omap_dss_dispc_dev_attr *da;
 210         struct omap_hwmod *oh;
 211
 212         oh = omap_hwmod_lookup("dss_dispc");
 213         if (!oh) {
 214                 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
 215                 return;
 216         }
 217
 218         if (!oh->dev_attr) {
 219                 pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
 220                 return;
 221         }
 222
 223         da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
 224
 225         /* store value of LCDENABLE and DIGITENABLE bits */
 226         v = omap_hwmod_read(oh, DISPC_CONTROL);
 227         lcd_en = v & LCD_EN_MASK;
 228         digit_en = v & DIGIT_EN_MASK;
 229
 230         /* store value of LCDENABLE for LCD2 */
 231         if (da->manager_count > 2) {
 232                 v = omap_hwmod_read(oh, DISPC_CONTROL2);
 233                 lcd2_en = v & LCD_EN_MASK;
 234         }
 235
 236         if (!(lcd_en | digit_en | lcd2_en))
 237                 return; /* no managers currently enabled */
 238
 239         /*
 240          * If any manager was enabled, we need to disable it before
 241          * DSS clocks are disabled or DISPC module is reset
 242          */
 243         if (lcd_en)
 244                 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
 245
 246         if (digit_en) {
 247                 if (da->has_framedonetv_irq) {
 248                         irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
 249                 } else {
 250                         irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
 251                                 1 << EVSYNC_ODD_IRQ_SHIFT;
 252                 }
 253         }
 254
 255         if (lcd2_en)
 256                 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
 257
 258         /*
 259          * clear any previous FRAMEDONE, FRAMEDONETV,
 260          * EVSYNC_EVEN/ODD or FRAMEDONE2 interrupts
 261          */
 262         omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
 263
 264         /* disable LCD and TV managers */
 265         v = omap_hwmod_read(oh, DISPC_CONTROL);
 266         v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
 267         omap_hwmod_write(v, oh, DISPC_CONTROL);
 268
 269         /* disable LCD2 manager */
 270         if (da->manager_count > 2) {
 271                 v = omap_hwmod_read(oh, DISPC_CONTROL2);
 272                 v &= ~LCD_EN_MASK;
 273                 omap_hwmod_write(v, oh, DISPC_CONTROL2);
 274         }
 275
 276         i = 0;
 277         while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
 278                irq_mask) {
 279                 i++;
 280                 if (i > FRAMEDONE_IRQ_TIMEOUT) {
 281                         pr_err("didn't get FRAMEDONE1/2 or TV interrupt\n");
 282                         break;
 283                 }
 284                 mdelay(1);
 285         }
 286 }
 287
 288 #define MAX_MODULE_SOFTRESET_WAIT       10000
 289 int omap_dss_reset(struct omap_hwmod *oh)
 290 {
 291         struct omap_hwmod_opt_clk *oc;
 292         int c = 0;
 293         int i, r;
 294
 295         if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
 296                 pr_err("dss_core: hwmod data doesn't contain reset data\n");
 297                 return -EINVAL;
 298         }
 299
 300         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
 301                 if (oc->_clk)
 302                         clk_enable(oc->_clk);
 303
 304         dispc_disable_outputs();
 305
 306         /* clear SDI registers */
 307         if (cpu_is_omap3430()) {
 308                 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
 309                 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
 310         }
 311
 312         /*
 313          * clear DSS_CONTROL register to switch DSS clock sources to
 314          * PRCM clock, if any
 315          */
 316         omap_hwmod_write(0x0, oh, DSS_CONTROL);
 317
 318         omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
 319                                 & SYSS_RESETDONE_MASK),
 320                         MAX_MODULE_SOFTRESET_WAIT, c);
 321
 322         if (c == MAX_MODULE_SOFTRESET_WAIT)
 323                 pr_warning("dss_core: waiting for reset to finish failed\n");
 324         else
 325                 pr_debug("dss_core: softreset done\n");
 326
 327         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
 328                 if (oc->_clk)
 329                         clk_disable(oc->_clk);
 330
 331         r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
 332
 333         return r;
 334 }