arm:omap:am33xx: Register HSMMC Platform on AM335x EVM
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / hsmmc.c
1 /*
2  * linux/arch/arm/mach-omap2/hsmmc.c
3  *
4  * Copyright (C) 2007-2008 Texas Instruments
5  * Copyright (C) 2008 Nokia Corporation
6  * Author: Texas Instruments
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/string.h>
15 #include <linux/delay.h>
16 #include <linux/gpio.h>
17 #include <mach/hardware.h>
18 #include <plat/mmc.h>
19 #include <plat/omap-pm.h>
20 #include <plat/mux.h>
21 #include <plat/omap_device.h>
23 #include "mux.h"
24 #include "hsmmc.h"
25 #include "control.h"
27 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
29 static u16 control_pbias_offset;
30 static u16 control_devconf1_offset;
31 static u16 control_mmc1;
33 #define HSMMC_NAME_LEN  9
35 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
37 static int hsmmc_get_context_loss(struct device *dev)
38 {
39         return omap_pm_get_dev_context_loss_count(dev);
40 }
42 #else
43 #define hsmmc_get_context_loss NULL
44 #endif
46 static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
47                                   int power_on, int vdd)
48 {
49         u32 reg, prog_io;
50         struct omap_mmc_platform_data *mmc = dev->platform_data;
52         if (mmc->slots[0].remux)
53                 mmc->slots[0].remux(dev, slot, power_on);
55         /*
56          * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
57          * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
58          * 1.8V and 3.0V modes, controlled by the PBIAS register.
59          *
60          * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
61          * is most naturally TWL VSIM; those pins also use PBIAS.
62          *
63          * FIXME handle VMMC1A as needed ...
64          */
65         if (power_on) {
66                 if (cpu_is_omap2430()) {
67                         reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
68                         if ((1 << vdd) >= MMC_VDD_30_31)
69                                 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
70                         else
71                                 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
72                         omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
73                 }
75                 if (mmc->slots[0].internal_clock) {
76                         reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
77                         reg |= OMAP2_MMCSDIO1ADPCLKISEL;
78                         omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
79                 }
81                 reg = omap_ctrl_readl(control_pbias_offset);
82                 if (cpu_is_omap3630()) {
83                         /* Set MMC I/O to 52Mhz */
84                         prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
85                         prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
86                         omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
87                 } else {
88                         reg |= OMAP2_PBIASSPEEDCTRL0;
89                 }
90                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
91                 omap_ctrl_writel(reg, control_pbias_offset);
92         } else {
93                 reg = omap_ctrl_readl(control_pbias_offset);
94                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
95                 omap_ctrl_writel(reg, control_pbias_offset);
96         }
97 }
99 static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
100                                  int power_on, int vdd)
102         u32 reg;
104         /* 100ms delay required for PBIAS configuration */
105         msleep(100);
107         if (power_on) {
108                 reg = omap_ctrl_readl(control_pbias_offset);
109                 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
110                 if ((1 << vdd) <= MMC_VDD_165_195)
111                         reg &= ~OMAP2_PBIASLITEVMODE0;
112                 else
113                         reg |= OMAP2_PBIASLITEVMODE0;
114                 omap_ctrl_writel(reg, control_pbias_offset);
115         } else {
116                 reg = omap_ctrl_readl(control_pbias_offset);
117                 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
118                         OMAP2_PBIASLITEVMODE0);
119                 omap_ctrl_writel(reg, control_pbias_offset);
120         }
123 static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
124                                   int power_on, int vdd)
126         u32 reg;
128         /*
129          * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
130          * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
131          * 1.8V and 3.0V modes, controlled by the PBIAS register.
132          */
133         reg = omap4_ctrl_pad_readl(control_pbias_offset);
134         reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
135                 OMAP4_MMC1_PWRDNZ_MASK |
136                 OMAP4_MMC1_PBIASLITE_VMODE_MASK);
137         omap4_ctrl_pad_writel(reg, control_pbias_offset);
140 static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
141                                  int power_on, int vdd)
143         u32 reg;
144         unsigned long timeout;
146         if (power_on) {
147                 reg = omap4_ctrl_pad_readl(control_pbias_offset);
148                 reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
149                 if ((1 << vdd) <= MMC_VDD_165_195)
150                         reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
151                 else
152                         reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
153                 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
154                         OMAP4_MMC1_PWRDNZ_MASK);
155                 omap4_ctrl_pad_writel(reg, control_pbias_offset);
157                 timeout = jiffies + msecs_to_jiffies(5);
158                 do {
159                         reg = omap4_ctrl_pad_readl(control_pbias_offset);
160                         if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK))
161                                 break;
162                         usleep_range(100, 200);
163                 } while (!time_after(jiffies, timeout));
165                 if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
166                         pr_err("Pbias Voltage is not same as LDO\n");
167                         /* Caution : On VMODE_ERROR Power Down MMC IO */
168                         reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
169                         omap4_ctrl_pad_writel(reg, control_pbias_offset);
170                 }
171         }
174 static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
176         u32 reg;
178         if (mmc->slots[0].internal_clock) {
179                 reg = omap_ctrl_readl(control_devconf1_offset);
180                 reg |= OMAP2_MMCSDIO2ADPCLKISEL;
181                 omap_ctrl_writel(reg, control_devconf1_offset);
182         }
185 static void hsmmc23_before_set_reg(struct device *dev, int slot,
186                                    int power_on, int vdd)
188         struct omap_mmc_platform_data *mmc = dev->platform_data;
190         if (mmc->slots[0].remux)
191                 mmc->slots[0].remux(dev, slot, power_on);
193         if (power_on)
194                 hsmmc2_select_input_clk_src(mmc);
197 static int am35x_hsmmc2_set_power(struct device *dev, int slot,
198                                   int power_on, int vdd)
200         struct omap_mmc_platform_data *mmc = dev->platform_data;
202         if (power_on)
203                 hsmmc2_select_input_clk_src(mmc);
205         return 0;
208 static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
209                                                         int vdd)
211         return 0;
214 static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
215                         int controller_nr)
217         if (gpio_is_valid(mmc_controller->slots[0].switch_pin) &&
218                 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
219                 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
220                                         OMAP_PIN_INPUT_PULLUP);
221         if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) &&
222                 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
223                 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
224                                         OMAP_PIN_INPUT_PULLUP);
225         if (cpu_is_omap34xx()) {
226                 if (controller_nr == 0) {
227                         omap_mux_init_signal("sdmmc1_clk",
228                                 OMAP_PIN_INPUT_PULLUP);
229                         omap_mux_init_signal("sdmmc1_cmd",
230                                 OMAP_PIN_INPUT_PULLUP);
231                         omap_mux_init_signal("sdmmc1_dat0",
232                                 OMAP_PIN_INPUT_PULLUP);
233                         if (mmc_controller->slots[0].caps &
234                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
235                                 omap_mux_init_signal("sdmmc1_dat1",
236                                         OMAP_PIN_INPUT_PULLUP);
237                                 omap_mux_init_signal("sdmmc1_dat2",
238                                         OMAP_PIN_INPUT_PULLUP);
239                                 omap_mux_init_signal("sdmmc1_dat3",
240                                         OMAP_PIN_INPUT_PULLUP);
241                         }
242                         if (mmc_controller->slots[0].caps &
243                                                 MMC_CAP_8_BIT_DATA) {
244                                 omap_mux_init_signal("sdmmc1_dat4",
245                                         OMAP_PIN_INPUT_PULLUP);
246                                 omap_mux_init_signal("sdmmc1_dat5",
247                                         OMAP_PIN_INPUT_PULLUP);
248                                 omap_mux_init_signal("sdmmc1_dat6",
249                                         OMAP_PIN_INPUT_PULLUP);
250                                 omap_mux_init_signal("sdmmc1_dat7",
251                                         OMAP_PIN_INPUT_PULLUP);
252                         }
253                 }
254                 if (controller_nr == 1) {
255                         /* MMC2 */
256                         omap_mux_init_signal("sdmmc2_clk",
257                                 OMAP_PIN_INPUT_PULLUP);
258                         omap_mux_init_signal("sdmmc2_cmd",
259                                 OMAP_PIN_INPUT_PULLUP);
260                         omap_mux_init_signal("sdmmc2_dat0",
261                                 OMAP_PIN_INPUT_PULLUP);
263                         /*
264                          * For 8 wire configurations, Lines DAT4, 5, 6 and 7
265                          * need to be muxed in the board-*.c files
266                          */
267                         if (mmc_controller->slots[0].caps &
268                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
269                                 omap_mux_init_signal("sdmmc2_dat1",
270                                         OMAP_PIN_INPUT_PULLUP);
271                                 omap_mux_init_signal("sdmmc2_dat2",
272                                         OMAP_PIN_INPUT_PULLUP);
273                                 omap_mux_init_signal("sdmmc2_dat3",
274                                         OMAP_PIN_INPUT_PULLUP);
275                         }
276                         if (mmc_controller->slots[0].caps &
277                                                         MMC_CAP_8_BIT_DATA) {
278                                 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
279                                         OMAP_PIN_INPUT_PULLUP);
280                                 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
281                                         OMAP_PIN_INPUT_PULLUP);
282                                 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
283                                         OMAP_PIN_INPUT_PULLUP);
284                                 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
285                                         OMAP_PIN_INPUT_PULLUP);
286                         }
287                 }
289                 /*
290                  * For MMC3 the pins need to be muxed in the board-*.c files
291                  */
292         }
295 static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
296                                         struct omap_mmc_platform_data *mmc)
298         char *hc_name;
300         hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
301         if (!hc_name) {
302                 pr_err("Cannot allocate memory for controller slot name\n");
303                 kfree(hc_name);
304                 return -ENOMEM;
305         }
307         if (cpu_is_am33xx())
308                 mmc->version = MMC_CTRL_VERSION_2;
310         if (c->name)
311                 strncpy(hc_name, c->name, HSMMC_NAME_LEN);
312         else
313                 snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
314                                                                 c->mmc, 1);
315         mmc->slots[0].name = hc_name;
316         mmc->nr_slots = 1;
317         mmc->slots[0].caps = c->caps;
318         mmc->slots[0].pm_caps = c->pm_caps;
319         mmc->slots[0].internal_clock = !c->ext_clock;
320         mmc->dma_mask = 0xffffffff;
321         if (cpu_is_omap44xx())
322                 mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
323         else
324                 mmc->reg_offset = 0;
326         mmc->get_context_loss_count = hsmmc_get_context_loss;
328         mmc->slots[0].switch_pin = c->gpio_cd;
329         mmc->slots[0].gpio_wp = c->gpio_wp;
331         mmc->slots[0].remux = c->remux;
332         mmc->slots[0].init_card = c->init_card;
334         if (c->cover_only)
335                 mmc->slots[0].cover = 1;
337         if (c->nonremovable)
338                 mmc->slots[0].nonremovable = 1;
340         if (c->power_saving)
341                 mmc->slots[0].power_saving = 1;
343         if (c->no_off)
344                 mmc->slots[0].no_off = 1;
346         if (c->no_off_init)
347                 mmc->slots[0].no_regulator_off_init = c->no_off_init;
349         if (c->vcc_aux_disable_is_sleep)
350                 mmc->slots[0].vcc_aux_disable_is_sleep = 1;
352         /*
353          * NOTE:  MMC slots should have a Vcc regulator set up.
354          * This may be from a TWL4030-family chip, another
355          * controllable regulator, or a fixed supply.
356          *
357          * temporary HACK: ocr_mask instead of fixed supply
358          */
359         if (cpu_is_omap3505() || cpu_is_omap3517())
360                 mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
361                                          MMC_VDD_26_27 |
362                                          MMC_VDD_27_28 |
363                                          MMC_VDD_29_30 |
364                                          MMC_VDD_30_31 |
365                                          MMC_VDD_31_32;
366         else
367                 mmc->slots[0].ocr_mask = c->ocr_mask;
369         if (!cpu_is_omap3517() && !cpu_is_omap3505() && !cpu_is_am33xx())
370                 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
372         if ((cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) ||
373                                                                 cpu_is_am33xx())
374                 mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
376         switch (c->mmc) {
377         case 1:
378                 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
379                         /* on-chip level shifting via PBIAS0/PBIAS1 */
380                         if (cpu_is_omap44xx()) {
381                                 mmc->slots[0].before_set_reg =
382                                                 omap4_hsmmc1_before_set_reg;
383                                 mmc->slots[0].after_set_reg =
384                                                 omap4_hsmmc1_after_set_reg;
385                         } else {
386                                 mmc->slots[0].before_set_reg =
387                                                 omap_hsmmc1_before_set_reg;
388                                 mmc->slots[0].after_set_reg =
389                                                 omap_hsmmc1_after_set_reg;
390                         }
391                 }
393                 if (cpu_is_omap3517() || cpu_is_omap3505() || cpu_is_am33xx())
394                         mmc->slots[0].set_power = nop_mmc_set_power;
396                 /* OMAP3630 HSMMC1 supports only 4-bit */
397                 if (cpu_is_omap3630() &&
398                                 (c->caps & MMC_CAP_8_BIT_DATA)) {
399                         c->caps &= ~MMC_CAP_8_BIT_DATA;
400                         c->caps |= MMC_CAP_4_BIT_DATA;
401                         mmc->slots[0].caps = c->caps;
402                 }
403                 break;
404         case 2:
405                 if (cpu_is_omap3517() || cpu_is_omap3505())
406                         mmc->slots[0].set_power = am35x_hsmmc2_set_power;
408                 if (c->ext_clock)
409                         c->transceiver = 1;
410                 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
411                         c->caps &= ~MMC_CAP_8_BIT_DATA;
412                         c->caps |= MMC_CAP_4_BIT_DATA;
413                 }
414                 /* FALLTHROUGH */
415         case 3:
416                 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
417                         /* off-chip level shifting, or none */
418                         mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
419                         mmc->slots[0].after_set_reg = NULL;
420                 }
421                 break;
422         case 4:
423         case 5:
424                 mmc->slots[0].before_set_reg = NULL;
425                 mmc->slots[0].after_set_reg = NULL;
426                 break;
427         default:
428                 pr_err("MMC%d configuration not supported!\n", c->mmc);
429                 kfree(hc_name);
430                 return -ENODEV;
431         }
432         return 0;
435 #define MAX_OMAP_MMC_HWMOD_NAME_LEN             16
437 void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
439         struct omap_hwmod *oh;
440         struct platform_device *pdev;
441         char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
442         struct omap_mmc_platform_data *mmc_data;
443         struct omap_mmc_dev_attr *mmc_dev_attr;
444         char *name;
445         int l;
447         mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
448         if (!mmc_data) {
449                 pr_err("Cannot allocate memory for mmc device!\n");
450                 goto done;
451         }
453         if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
454                 pr_err("%s fails!\n", __func__);
455                 goto done;
456         }
458         if (!cpu_is_am33xx())
459                 omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
461         name = "omap_hsmmc";
463         l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
464                      "mmc%d", ctrl_nr);
465         WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
466              "String buffer overflow in MMC%d device setup\n", ctrl_nr);
467         oh = omap_hwmod_lookup(oh_name);
468         if (!oh) {
469                 pr_err("Could not look up %s\n", oh_name);
470                 kfree(mmc_data->slots[0].name);
471                 goto done;
472         }
474         if (oh->dev_attr != NULL) {
475                 mmc_dev_attr = oh->dev_attr;
476                 mmc_data->controller_flags = mmc_dev_attr->flags;
477         }
479         pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
480                 sizeof(struct omap_mmc_platform_data), NULL, 0, false);
481         if (IS_ERR(pdev)) {
482                 WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
483                 kfree(mmc_data->slots[0].name);
484                 goto done;
485         }
486         /*
487          * return device handle to board setup code
488          * required to populate for regulator framework structure
489          */
490         hsmmcinfo->dev = &pdev->dev;
492 done:
493         kfree(mmc_data);
496 void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
498         u32 reg;
500         if (!cpu_is_omap44xx()) {
501                 if (cpu_is_omap2430()) {
502                         control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
503                         control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
504                 } else {
505                         control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
506                         control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
507                 }
508         } else {
509                 control_pbias_offset =
510                         OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
511                 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
512                 reg = omap4_ctrl_pad_readl(control_mmc1);
513                 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
514                         OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
515                 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
516                         OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
517                 reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
518                         OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
519                         OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
520                 omap4_ctrl_pad_writel(reg, control_mmc1);
521         }
523         for (; controllers->mmc; controllers++)
524                 omap_init_hsmmc(controllers, controllers->mmc);
528 #endif