1 /*
2 * Mailbox reservation modules for OMAP2/3
3 *
4 * Copyright (C) 2006-2009 Nokia Corporation
5 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
6 * and Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
13 #include <linux/module.h>
14 #include <linux/clk.h>
15 #include <linux/err.h>
16 #include <linux/platform_device.h>
17 #include <linux/io.h>
18 #include <linux/pm_runtime.h>
19 #include <plat/mailbox.h>
20 #include <mach/irqs.h>
22 #define MAILBOX_REVISION 0x000
23 #define MAILBOX_MESSAGE(m) (0x040 + 0x4 * (m))
24 #define MAILBOX_FIFOSTATUS(m) (0x080 + 0x4 * (m))
25 #define MAILBOX_MSGSTATUS(m) (0x0c0 + 0x4 * (m))
26 #define MAILBOX_IRQSTATUS(u) (0x100 + 0x8 * (u))
27 #define MAILBOX_IRQENABLE(u) (0x104 + 0x8 * (u))
29 #define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u))
30 #define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u))
31 #define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u))
33 #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
34 #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
36 /* TODO: This can and should be based on #users and #sub-modules */
37 #define MBOX_REG_SIZE 0x120
39 #define OMAP4_MBOX_REG_SIZE 0x130
41 #define AM33XX_MBOX_REG_SIZE 0x140
43 #define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
44 #define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
45 #define AM33XX_MBOX_NR_REGS (AM33XX_MBOX_REG_SIZE / sizeof(u32))
47 static void __iomem *mbox_base;
49 struct omap_mbox2_fifo {
50 unsigned long msg;
51 unsigned long fifo_stat;
52 unsigned long msg_stat;
53 };
55 struct omap_mbox2_priv {
56 struct omap_mbox2_fifo tx_fifo;
57 struct omap_mbox2_fifo rx_fifo;
58 unsigned long irqenable;
59 unsigned long irqstatus;
60 u32 newmsg_bit;
61 u32 notfull_bit;
62 u32 ctx[OMAP4_MBOX_NR_REGS];
63 unsigned long irqdisable;
64 };
66 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
67 omap_mbox_type_t irq);
69 static inline unsigned int mbox_read_reg(size_t ofs)
70 {
71 return __raw_readl(mbox_base + ofs);
72 }
74 static inline void mbox_write_reg(u32 val, size_t ofs)
75 {
76 __raw_writel(val, mbox_base + ofs);
77 }
79 /* Mailbox H/W preparations */
80 static int omap2_mbox_startup(struct omap_mbox *mbox)
81 {
82 u32 l;
84 pm_runtime_enable(mbox->dev->parent);
85 pm_runtime_get_sync(mbox->dev->parent);
87 l = mbox_read_reg(MAILBOX_REVISION);
88 pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
90 omap2_mbox_enable_irq(mbox, IRQ_RX);
92 return 0;
93 }
95 static void omap2_mbox_shutdown(struct omap_mbox *mbox)
96 {
97 pm_runtime_put_sync(mbox->dev->parent);
98 pm_runtime_disable(mbox->dev->parent);
99 }
101 /* Mailbox FIFO handle functions */
102 static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
103 {
104 struct omap_mbox2_fifo *fifo =
105 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
106 return (mbox_msg_t) mbox_read_reg(fifo->msg);
107 }
109 static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
110 {
111 struct omap_mbox2_fifo *fifo =
112 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
113 mbox_write_reg(msg, fifo->msg);
114 }
116 static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
117 {
118 struct omap_mbox2_fifo *fifo =
119 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
120 return (mbox_read_reg(fifo->msg_stat) == 0);
121 }
123 static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
124 {
125 struct omap_mbox2_fifo *fifo =
126 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
127 return mbox_read_reg(fifo->fifo_stat);
128 }
130 static int omap2_mbox_fifo_needs_flush(struct omap_mbox *mbox)
131 {
132 struct omap_mbox2_fifo *fifo =
133 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
134 return (mbox_read_reg(fifo->msg_stat) == 0);
135 }
137 static mbox_msg_t omap2_mbox_fifo_readback(struct omap_mbox *mbox)
138 {
139 struct omap_mbox2_fifo *fifo =
140 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
141 return (mbox_msg_t) mbox_read_reg(fifo->msg);
142 }
144 /* Mailbox IRQ handle functions */
145 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
146 omap_mbox_type_t irq)
147 {
148 struct omap_mbox2_priv *p = mbox->priv;
149 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
151 l = mbox_read_reg(p->irqenable);
152 l |= bit;
153 mbox_write_reg(l, p->irqenable);
154 }
156 static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
157 omap_mbox_type_t irq)
158 {
159 struct omap_mbox2_priv *p = mbox->priv;
160 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
162 if (!cpu_is_omap44xx() && !cpu_is_am33xx())
163 bit = mbox_read_reg(p->irqdisable) & ~bit;
165 mbox_write_reg(bit, p->irqdisable);
166 }
168 static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
169 omap_mbox_type_t irq)
170 {
171 struct omap_mbox2_priv *p = mbox->priv;
172 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
174 mbox_write_reg(bit, p->irqstatus);
176 /* Flush posted write for irq status to avoid spurious interrupts */
177 mbox_read_reg(p->irqstatus);
178 }
180 static int omap2_mbox_is_irq(struct omap_mbox *mbox,
181 omap_mbox_type_t irq)
182 {
183 struct omap_mbox2_priv *p = mbox->priv;
184 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
185 u32 enable = mbox_read_reg(p->irqenable);
186 u32 status = mbox_read_reg(p->irqstatus);
188 return (int)(enable & status & bit);
189 }
191 static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
192 {
193 int i;
194 struct omap_mbox2_priv *p = mbox->priv;
195 int nr_regs;
196 if (cpu_is_omap44xx())
197 nr_regs = OMAP4_MBOX_NR_REGS;
198 else
199 nr_regs = MBOX_NR_REGS;
200 for (i = 0; i < nr_regs; i++) {
201 p->ctx[i] = mbox_read_reg(i * sizeof(u32));
203 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
204 i, p->ctx[i]);
205 }
206 }
208 static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
209 {
210 int i;
211 struct omap_mbox2_priv *p = mbox->priv;
212 int nr_regs;
213 if (cpu_is_omap44xx())
214 nr_regs = OMAP4_MBOX_NR_REGS;
215 else
216 nr_regs = MBOX_NR_REGS;
217 for (i = 0; i < nr_regs; i++) {
218 mbox_write_reg(p->ctx[i], i * sizeof(u32));
220 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
221 i, p->ctx[i]);
222 }
223 }
225 static struct omap_mbox_ops omap2_mbox_ops = {
226 .type = OMAP_MBOX_TYPE2,
227 .startup = omap2_mbox_startup,
228 .shutdown = omap2_mbox_shutdown,
229 .fifo_read = omap2_mbox_fifo_read,
230 .fifo_write = omap2_mbox_fifo_write,
231 .fifo_empty = omap2_mbox_fifo_empty,
232 .fifo_full = omap2_mbox_fifo_full,
233 .fifo_needs_flush = omap2_mbox_fifo_needs_flush,
234 .fifo_readback = omap2_mbox_fifo_readback,
235 .enable_irq = omap2_mbox_enable_irq,
236 .disable_irq = omap2_mbox_disable_irq,
237 .ack_irq = omap2_mbox_ack_irq,
238 .is_irq = omap2_mbox_is_irq,
239 .save_ctx = omap2_mbox_save_ctx,
240 .restore_ctx = omap2_mbox_restore_ctx,
241 };
243 /*
244 * MAILBOX 0: ARM -> DSP,
245 * MAILBOX 1: ARM <- DSP.
246 * MAILBOX 2: ARM -> IVA,
247 * MAILBOX 3: ARM <- IVA.
248 */
250 /* FIXME: the following structs should be filled automatically by the user id */
252 /* DSP */
253 static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
254 .tx_fifo = {
255 .msg = MAILBOX_MESSAGE(0),
256 .fifo_stat = MAILBOX_FIFOSTATUS(0),
257 },
258 .rx_fifo = {
259 .msg = MAILBOX_MESSAGE(1),
260 .msg_stat = MAILBOX_MSGSTATUS(1),
261 },
262 .irqenable = MAILBOX_IRQENABLE(0),
263 .irqstatus = MAILBOX_IRQSTATUS(0),
264 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
265 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
266 .irqdisable = MAILBOX_IRQENABLE(0),
267 };
269 struct omap_mbox mbox_dsp_info = {
270 .name = "dsp",
271 .ops = &omap2_mbox_ops,
272 .priv = &omap2_mbox_dsp_priv,
273 };
275 struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
277 /* IVA */
278 static struct omap_mbox2_priv omap2_mbox_iva_priv = {
279 .tx_fifo = {
280 .msg = MAILBOX_MESSAGE(2),
281 .fifo_stat = MAILBOX_FIFOSTATUS(2),
282 },
283 .rx_fifo = {
284 .msg = MAILBOX_MESSAGE(3),
285 .msg_stat = MAILBOX_MSGSTATUS(3),
286 },
287 .irqenable = MAILBOX_IRQENABLE(3),
288 .irqstatus = MAILBOX_IRQSTATUS(3),
289 .notfull_bit = MAILBOX_IRQ_NOTFULL(2),
290 .newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
291 .irqdisable = MAILBOX_IRQENABLE(3),
292 };
294 static struct omap_mbox mbox_iva_info = {
295 .name = "iva",
296 .ops = &omap2_mbox_ops,
297 .priv = &omap2_mbox_iva_priv,
298 };
300 struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL };
302 /* A8 -> Wakeup-M3 */
303 static struct omap_mbox2_priv omap2_mbox_m3_priv = {
304 .tx_fifo = {
305 .msg = MAILBOX_MESSAGE(0),
306 .fifo_stat = MAILBOX_FIFOSTATUS(0),
307 .msg_stat = MAILBOX_MSGSTATUS(0),
308 },
309 /* TODO: No M3->A8 so this needs to be removed */
310 .rx_fifo = {
311 .msg = MAILBOX_MESSAGE(1),
312 .msg_stat = MAILBOX_MSGSTATUS(1),
313 },
314 .irqenable = OMAP4_MAILBOX_IRQENABLE(3),
315 .irqstatus = OMAP4_MAILBOX_IRQSTATUS(3),
316 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
317 .newmsg_bit = MAILBOX_IRQ_NEWMSG(0),
318 .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(3),
319 };
321 struct omap_mbox wkup_m3_info = {
322 .name = "wkup_m3",
323 .ops = &omap2_mbox_ops,
324 .priv = &omap2_mbox_m3_priv,
325 };
327 struct omap_mbox *am33xx_mboxes[] = { &wkup_m3_info, NULL };
329 /* OMAP4 */
330 static struct omap_mbox2_priv omap2_mbox_1_priv = {
331 .tx_fifo = {
332 .msg = MAILBOX_MESSAGE(0),
333 .fifo_stat = MAILBOX_FIFOSTATUS(0),
334 },
335 .rx_fifo = {
336 .msg = MAILBOX_MESSAGE(1),
337 .msg_stat = MAILBOX_MSGSTATUS(1),
338 },
339 .irqenable = OMAP4_MAILBOX_IRQENABLE(0),
340 .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
341 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
342 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
343 .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
344 };
346 struct omap_mbox mbox_1_info = {
347 .name = "mailbox-1",
348 .ops = &omap2_mbox_ops,
349 .priv = &omap2_mbox_1_priv,
350 };
352 static struct omap_mbox2_priv omap2_mbox_2_priv = {
353 .tx_fifo = {
354 .msg = MAILBOX_MESSAGE(3),
355 .fifo_stat = MAILBOX_FIFOSTATUS(3),
356 },
357 .rx_fifo = {
358 .msg = MAILBOX_MESSAGE(2),
359 .msg_stat = MAILBOX_MSGSTATUS(2),
360 },
361 .irqenable = OMAP4_MAILBOX_IRQENABLE(0),
362 .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
363 .notfull_bit = MAILBOX_IRQ_NOTFULL(3),
364 .newmsg_bit = MAILBOX_IRQ_NEWMSG(2),
365 .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
366 };
368 struct omap_mbox mbox_2_info = {
369 .name = "mailbox-2",
370 .ops = &omap2_mbox_ops,
371 .priv = &omap2_mbox_2_priv,
372 };
374 struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
376 static int __devinit omap2_mbox_probe(struct platform_device *pdev)
377 {
378 struct resource *mem;
379 int ret;
380 struct omap_mbox **list;
382 if (false)
383 ;
384 else if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
385 list = omap3_mboxes;
387 list[0]->irq = platform_get_irq(pdev, 0);
388 } else if (cpu_is_am33xx()) {
389 list = am33xx_mboxes;
391 list[0]->irq = platform_get_irq(pdev, 0);
392 }
393 else if (cpu_is_omap2430()) {
394 list = omap2_mboxes;
396 list[0]->irq = platform_get_irq(pdev, 0);
397 } else if (cpu_is_omap2420()) {
398 list = omap2_mboxes;
400 list[0]->irq = platform_get_irq_byname(pdev, "dsp");
401 list[1]->irq = platform_get_irq_byname(pdev, "iva");
402 }
403 else if (cpu_is_omap44xx()) {
404 list = omap4_mboxes;
406 list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
407 }
408 else {
409 pr_err("%s: platform not supported\n", __func__);
410 return -ENODEV;
411 }
413 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
414 mbox_base = ioremap(mem->start, resource_size(mem));
415 if (!mbox_base)
416 return -ENOMEM;
418 ret = omap_mbox_register(&pdev->dev, list);
419 if (ret) {
420 iounmap(mbox_base);
421 return ret;
422 }
424 return 0;
425 }
427 static int __devexit omap2_mbox_remove(struct platform_device *pdev)
428 {
429 omap_mbox_unregister();
430 iounmap(mbox_base);
431 return 0;
432 }
434 static struct platform_driver omap2_mbox_driver = {
435 .probe = omap2_mbox_probe,
436 .remove = __devexit_p(omap2_mbox_remove),
437 .driver = {
438 .name = "omap-mailbox",
439 },
440 };
442 static int __init omap2_mbox_init(void)
443 {
444 return platform_driver_register(&omap2_mbox_driver);
445 }
447 static void __exit omap2_mbox_exit(void)
448 {
449 platform_driver_unregister(&omap2_mbox_driver);
450 }
452 device_initcall(omap2_mbox_init);
453 module_exit(omap2_mbox_exit);
455 MODULE_LICENSE("GPL v2");
456 MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
457 MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
458 MODULE_AUTHOR("Paul Mundt");
459 MODULE_ALIAS("platform:omap2-mailbox");