1 /*
2 * AM33XX mux data
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-omap2/mux34xx.c Original copyright follows:
7 *
8 * Copyright (C) 2009 Nokia
9 * Copyright (C) 2009 Texas Instruments
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
16 #include <linux/module.h>
17 #include <linux/init.h>
19 #include "mux.h"
21 #ifdef CONFIG_OMAP_MUX
23 #define _AM33XX_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
24 { \
25 .reg_offset = (AM33XX_CONTROL_PADCONF_##M0##_OFFSET), \
26 .gpio = (g), \
27 .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
28 }
30 /* AM33XX pin mux super set */
31 static struct omap_mux __initdata am33xx_muxmodes[] = {
32 _AM33XX_MUXENTRY(GPMC_AD0, 0,
33 "gpmc_ad0", "mmc1_dat0", NULL, NULL,
34 NULL, NULL, NULL, NULL),
35 _AM33XX_MUXENTRY(GPMC_AD1, 0,
36 "gpmc_ad1", "mmc1_dat1", NULL, NULL,
37 NULL, NULL, NULL, NULL),
38 _AM33XX_MUXENTRY(GPMC_AD2, 0,
39 "gpmc_ad2", "mmc1_dat2", NULL, NULL,
40 NULL, NULL, NULL, NULL),
41 _AM33XX_MUXENTRY(GPMC_AD3, 0,
42 "gpmc_ad3", "mmc1_dat3", NULL, NULL,
43 NULL, NULL, NULL, NULL),
44 _AM33XX_MUXENTRY(GPMC_AD4, 0,
45 "gpmc_ad4", "mmc1_dat4", NULL, NULL,
46 NULL, NULL, NULL, NULL),
47 _AM33XX_MUXENTRY(GPMC_AD5, 0,
48 "gpmc_ad5", "mmc1_dat5", NULL, NULL,
49 NULL, NULL, NULL, NULL),
50 _AM33XX_MUXENTRY(GPMC_AD6, 0,
51 "gpmc_ad6", "mmc1_dat6", NULL, NULL,
52 NULL, NULL, NULL, NULL),
53 _AM33XX_MUXENTRY(GPMC_AD7, 0,
54 "gpmc_ad7", "mmc1_dat7", NULL, NULL,
55 NULL, NULL, NULL, NULL),
56 _AM33XX_MUXENTRY(GPMC_AD8, 0,
57 "gpmc_ad8", "lcd_data16", "mmc1_dat0", "mmc2_dat4",
58 NULL, NULL, NULL, NULL),
59 _AM33XX_MUXENTRY(GPMC_AD9, 0,
60 "gpmc_ad9", "lcd_data17", "mmc1_dat1", "mmc2_dat5",
61 NULL, NULL, NULL, NULL),
62 _AM33XX_MUXENTRY(GPMC_AD10, 0,
63 "gpmc_ad10", "lcd_data18", "mmc1_dat2", "mmc2_dat6",
64 NULL, NULL, NULL, NULL),
65 _AM33XX_MUXENTRY(GPMC_AD11, 0,
66 "gpmc_ad11", "lcd_data19", "mmc1_dat3", "mmc2_dat7",
67 NULL, NULL, NULL, NULL),
68 _AM33XX_MUXENTRY(GPMC_AD12, 0,
69 "gpmc_ad12", "lcd_data20", "mmc1_dat4", "mmc2_dat0",
70 NULL, NULL, NULL, NULL),
71 _AM33XX_MUXENTRY(GPMC_AD13, 0,
72 "gpmc_ad13", "lcd_data21", "mmc1_dat5", "mmc2_dat1",
73 NULL, NULL, NULL, NULL),
74 _AM33XX_MUXENTRY(GPMC_AD14, 0,
75 "gpmc_ad14", "lcd_data22", "mmc1_dat6", "mmc2_dat2",
76 NULL, NULL, NULL, NULL),
77 _AM33XX_MUXENTRY(GPMC_AD15, 0,
78 "gpmc_ad15", "lcd_data23", "mmc1_dat7", "mmc2_dat3",
79 NULL, NULL, NULL, NULL),
80 _AM33XX_MUXENTRY(GPMC_A0, 0,
81 "gpmc_a0", "mii2_txen", "rgmii2_tctl", "rmii2_txen",
82 NULL, NULL, NULL, NULL),
83 _AM33XX_MUXENTRY(GPMC_A1, 0,
84 "gpmc_a1", "mii2_rxdv", "rgmii2_rctl", "mmc2_dat0",
85 NULL, NULL, NULL, NULL),
86 _AM33XX_MUXENTRY(GPMC_A2, 0,
87 "gpmc_a2", "mii2_txd3", "rgmii2_td3", "mmc2_dat1",
88 NULL, NULL, NULL, NULL),
89 _AM33XX_MUXENTRY(GPMC_A3, 0,
90 "gpmc_a3", "mii2_txd2", "rgmii2_td2", "mmc2_dat2",
91 NULL, NULL, NULL, NULL),
92 _AM33XX_MUXENTRY(GPMC_A4, 0,
93 "gpmc_a4", "mii2_txd1", "rgmii2_td1", "rmii2_txd1",
94 "gpmc_a20", NULL, NULL, NULL),
95 _AM33XX_MUXENTRY(GPMC_A5, 0,
96 "gpmc_a5", "mii2_txd0", "rgmii2_td0", "rmii2_txd0",
97 "gpmc_a21", NULL, NULL, NULL),
98 _AM33XX_MUXENTRY(GPMC_A6, 0,
99 "gpmc_a6", "mii2_txclk", "rgmii2_tclk", "mmc2_dat4",
100 "gpmc_a22", NULL, NULL, NULL),
101 _AM33XX_MUXENTRY(GPMC_A7, 0,
102 "gpmc_a7", "mii2_rxclk", "rgmii2_rclk", "mmc2_dat5",
103 NULL, NULL, NULL, NULL),
104 _AM33XX_MUXENTRY(GPMC_A8, 0,
105 "gpmc_a8", "mii2_rxd3", "rgmii2_rd3", "mmc2_dat6",
106 NULL, NULL, "mcasp0_aclkx", NULL),
107 _AM33XX_MUXENTRY(GPMC_A9, 0,
108 "gpmc_a9", "mii2_rxd2", "rgmii2_rd2", "mmc2_dat7",
109 NULL, NULL, "mcasp0_fsx", NULL),
110 _AM33XX_MUXENTRY(GPMC_A10, 0,
111 "gpmc_a10", "mii2_rxd1", "rgmii2_rd1", "rmii2_rxd1",
112 NULL, NULL, "mcasp0_axr0", NULL),
113 _AM33XX_MUXENTRY(GPMC_A11, 0,
114 "gpmc_a11", "mii2_rxd0", "rgmii2_rd0", "rmii2_rxd0",
115 NULL, NULL, "mcasp0_axr1", NULL),
116 _AM33XX_MUXENTRY(GPMC_WAIT0, 0,
117 "gpmc_wait0", "mii2_crs", NULL, "rmii2_crs_dv",
118 "mmc1_sdcd", NULL, NULL, NULL),
119 _AM33XX_MUXENTRY(GPMC_WPN, 0,
120 "gpmc_wpn", "mii2_rxerr", NULL, "rmii2_rxerr",
121 "mmc2_sdcd", NULL, NULL, NULL),
122 _AM33XX_MUXENTRY(GPMC_BEN1, 0,
123 "gpmc_ben1", "mii2_col", NULL, "mmc2_dat3",
124 NULL, NULL, "mcasp0_aclkr", NULL),
125 _AM33XX_MUXENTRY(GPMC_CSN0, 0,
126 "gpmc_csn0", NULL, NULL, NULL,
127 NULL, NULL, NULL, "mmc1_sdwp"),
128 _AM33XX_MUXENTRY(GPMC_CSN1, 0,
129 "gpmc_csn1", NULL, "mmc1_clk", NULL,
130 NULL, NULL, NULL, "gpio1_30"),
131 _AM33XX_MUXENTRY(GPMC_CSN2, 0,
132 "gpmc_csn2", NULL, "mmc1_cmd", NULL,
133 NULL, NULL, NULL, "gpio1_31"),
134 _AM33XX_MUXENTRY(GPMC_CSN3, 0,
135 "gpmc_csn3", NULL, NULL, "mmc2_cmd",
136 NULL, NULL, NULL, NULL),
137 _AM33XX_MUXENTRY(GPMC_CLK, 0,
138 "gpmc_clk", NULL, NULL, "mmc2_clk",
139 NULL, NULL, "mcasp0_fsr", NULL),
140 _AM33XX_MUXENTRY(GPMC_ADVN_ALE, 0,
141 "gpmc_advn_ale", NULL, NULL, NULL,
142 NULL, NULL, NULL, "mmc1_sdcd"),
143 _AM33XX_MUXENTRY(GPMC_OEN_REN, 0,
144 "gpmc_oen_ren", NULL, NULL, NULL,
145 NULL, NULL, NULL, NULL),
146 _AM33XX_MUXENTRY(GPMC_WEN, 0,
147 "gpmc_wen", NULL, NULL, NULL,
148 NULL, NULL, NULL, NULL),
149 _AM33XX_MUXENTRY(GPMC_BEN0_CLE, 0,
150 "gpmc_ben0_cle", NULL, NULL, NULL,
151 NULL, NULL, NULL, NULL),
152 _AM33XX_MUXENTRY(LCD_DATA0, 0,
153 "lcd_data0", "gpmc_a0", NULL, NULL,
154 NULL, NULL, NULL, NULL),
155 _AM33XX_MUXENTRY(LCD_DATA1, 0,
156 "lcd_data1", "gpmc_a1", NULL, NULL,
157 NULL, NULL, NULL, NULL),
158 _AM33XX_MUXENTRY(LCD_DATA2, 0,
159 "lcd_data2", "gpmc_a2", NULL, NULL,
160 NULL, NULL, NULL, NULL),
161 _AM33XX_MUXENTRY(LCD_DATA3, 0,
162 "lcd_data3", "gpmc_a3", NULL, NULL,
163 NULL, NULL, NULL, NULL),
164 _AM33XX_MUXENTRY(LCD_DATA4, 0,
165 "lcd_data4", "gpmc_a4", NULL, NULL,
166 NULL, NULL, NULL, NULL),
167 _AM33XX_MUXENTRY(LCD_DATA5, 0,
168 "lcd_data5", "gpmc_a5", NULL, NULL,
169 NULL, NULL, NULL, NULL),
170 _AM33XX_MUXENTRY(LCD_DATA6, 0,
171 "lcd_data6", "gpmc_a6", NULL, NULL,
172 NULL, NULL, NULL, NULL),
173 _AM33XX_MUXENTRY(LCD_DATA7, 0,
174 "lcd_data7", "gpmc_a7", NULL, NULL,
175 NULL, NULL, NULL, NULL),
176 _AM33XX_MUXENTRY(LCD_DATA8, 0,
177 "lcd_data8", "gpmc_a12", NULL, "mcasp0_aclkx",
178 NULL, NULL, NULL, NULL),
179 _AM33XX_MUXENTRY(LCD_DATA9, 0,
180 "lcd_data9", "gpmc_a13", NULL, "mcasp0_fsx",
181 NULL, NULL, NULL, NULL),
182 _AM33XX_MUXENTRY(LCD_DATA10, 0,
183 "lcd_data10", "gpmc_a14", NULL, "mcasp0_axr0",
184 NULL, NULL, NULL, NULL),
185 _AM33XX_MUXENTRY(LCD_DATA11, 0,
186 "lcd_data11", "gpmc_a15", NULL, "mcasp0_ahclkr",
187 "mcasp0_axr2", NULL, NULL, NULL),
188 _AM33XX_MUXENTRY(LCD_DATA12, 0,
189 "lcd_data12", "gpmc_a16", NULL, "mcasp0_aclkr",
190 "mcasp0_axr2", NULL, NULL, NULL),
191 _AM33XX_MUXENTRY(LCD_DATA13, 0,
192 "lcd_data13", "gpmc_a17", NULL, "mcasp0_fsr",
193 "mcasp0_axr3", NULL, NULL, NULL),
194 _AM33XX_MUXENTRY(LCD_DATA14, 0,
195 "lcd_data14", "gpmc_a18", NULL, "mcasp0_axr1",
196 NULL, NULL, NULL, NULL),
197 _AM33XX_MUXENTRY(LCD_DATA15, 0,
198 "lcd_data15", "gpmc_a19", NULL, "mcasp0_ahclkx",
199 "mcasp0_axr3", NULL, NULL, NULL),
200 _AM33XX_MUXENTRY(LCD_VSYNC, 0,
201 "lcd_vsync", NULL, NULL, NULL,
202 NULL, NULL, NULL, NULL),
203 _AM33XX_MUXENTRY(LCD_HSYNC, 0,
204 "lcd_hsync", NULL, NULL, NULL,
205 NULL, NULL, NULL, NULL),
206 _AM33XX_MUXENTRY(LCD_PCLK, 0,
207 "lcd_pclk", NULL, NULL, NULL,
208 NULL, NULL, NULL, NULL),
209 _AM33XX_MUXENTRY(LCD_AC_BIAS_EN, 0,
210 "lcd_ac_bias_en", NULL, NULL, NULL,
211 NULL, NULL, NULL, "gpio2_25"),
212 _AM33XX_MUXENTRY(GPMC_CLK, 0,
213 "gpmc_clk", "lcd_memory_clk_mux", NULL, NULL,
214 NULL, NULL, NULL, NULL),
215 _AM33XX_MUXENTRY(MMC0_DAT3, 0,
216 "mmc0_dat3", NULL, NULL, NULL,
217 NULL, NULL, NULL, NULL),
218 _AM33XX_MUXENTRY(MMC0_DAT2, 0,
219 "mmc0_dat2", NULL, NULL, NULL,
220 NULL, NULL, NULL, NULL),
221 _AM33XX_MUXENTRY(MMC0_DAT1, 0,
222 "mmc0_dat1", NULL, NULL, NULL,
223 NULL, NULL, NULL, NULL),
224 _AM33XX_MUXENTRY(MMC0_DAT0, 0,
225 "mmc0_dat0", NULL, NULL, NULL,
226 NULL, NULL, NULL, NULL),
227 _AM33XX_MUXENTRY(MMC0_CLK, 0,
228 "mmc0_clk", NULL, NULL, NULL,
229 NULL, NULL, NULL, NULL),
230 _AM33XX_MUXENTRY(MMC0_CMD, 0,
231 "mmc0_cmd", NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL),
233 _AM33XX_MUXENTRY(MII1_COL, 0,
234 "mii1_col", "rmii2_refclk", "spi1_sclk", NULL,
235 "mcasp1_axr2", "mmc2_dat3", "mcasp0_axr2", NULL),
236 _AM33XX_MUXENTRY(MII1_CRS, 0,
237 "mii1_crs", "rmii1_crs_dv", "spi1_d0", NULL,
238 "mcasp1_aclkx", NULL, NULL, NULL),
239 _AM33XX_MUXENTRY(MII1_RXERR, 0,
240 "mii1_rxerr", "rmii1_rxerr", "spi1_d1", NULL,
241 "mcasp1_fsx", NULL, NULL, NULL),
242 _AM33XX_MUXENTRY(MII1_TXEN, 0,
243 "mii1_txen", "rmii1_txen", "rgmii1_tctl", NULL,
244 "mcasp1_axr0", NULL, "mmc2_cmd", NULL),
245 _AM33XX_MUXENTRY(MII1_RXDV, 0,
246 "mii1_rxdv", NULL, "rgmii1_rctl", NULL,
247 "mcasp1_aclx", "mmc2_dat0", "mcasp0_aclkr", NULL),
248 _AM33XX_MUXENTRY(MII1_TXD3, 0,
249 "mii1_txd3", NULL, "rgmii1_td3", NULL,
250 "mcasp1_fsx", "mmc2_dat1", "mcasp0_fsr", NULL),
251 _AM33XX_MUXENTRY(MII1_TXD2, 0,
252 "mii1_txd2", NULL, "rgmii1_td2", NULL,
253 "mcasp1_axr0", "mmc2_dat2", "mcasp0_ahclkx", NULL),
254 _AM33XX_MUXENTRY(MII1_TXD1, 0,
255 "mii1_txd1", "rmii1_txd1", "rgmii1_td1", "mcasp1_fsr",
256 "mcasp1_axr1", NULL, "mmc1_cmd", NULL),
257 _AM33XX_MUXENTRY(MII1_TXD0, 0,
258 "mii1_txd0", "rmii1_txd0", "rgmii1_td0", "mcasp1_axr2",
259 "mcasp1_aclkr", NULL, "mmc1_clk", NULL),
260 _AM33XX_MUXENTRY(MII1_TXCLK, 0,
261 "mii1_txclk", NULL, "rgmii1_tclk", "mmc0_dat7",
262 "mmc1_dat0", NULL, "mcasp0_aclkx", NULL),
263 _AM33XX_MUXENTRY(MII1_RXCLK, 0,
264 "mii1_rxclk", NULL, "rgmii1_rclk", "mmc0_dat6",
265 "mmc1_dat1", NULL, "mcasp0_fsx", NULL),
266 _AM33XX_MUXENTRY(MII1_RXD3, 0,
267 "mii1_rxd3", NULL, "rgmii1_rd3", "mmc0_dat5",
268 "mmc1_dat2", NULL, "mcasp0_axr0", NULL),
269 _AM33XX_MUXENTRY(MII1_RXD2, 0,
270 "mii1_rxd2", NULL, "rgmii1_rd2", "mmc0_dat4",
271 "mmc1_dat3", NULL, "mcasp0_axr1", NULL),
272 _AM33XX_MUXENTRY(MII1_RXD1, 0,
273 "mii1_rxd1", "rmii1_rxd1", "rgmii1_rd1", "mcasp1_axr3",
274 "mcasp1_fsr", NULL, "mmc2_clk", NULL),
275 _AM33XX_MUXENTRY(MII1_RXD0, 0,
276 "mii1_rxd0", "rmii1_rxd0", "rgmii1_rd0", "mcasp1_ahclkx",
277 "mcasp1_ahclkr", "mcasp1_aclkr", "mcasp0_axr3", NULL),
278 _AM33XX_MUXENTRY(MII1_REFCLK, 0,
279 "rmii1_refclk", NULL, "spi1_cs0", NULL,
280 "mcasp1_axr3", "mmc0_pow", "mcasp1_ahclkx", NULL),
281 _AM33XX_MUXENTRY(MDIO_DATA, 0,
282 "mdio_data", NULL, NULL, NULL,
283 "mmc0_sdcd", "mmc1_cmd", "mmc2_cmd", NULL),
284 _AM33XX_MUXENTRY(MDIO_CLK, 0,
285 "mdio_clk", NULL, NULL, NULL,
286 "mmc0_sdwp", "mmc1_clk", "mmc2_clk", NULL),
287 _AM33XX_MUXENTRY(SPI0_SCLK, 0,
288 "spi0_sclk", NULL, NULL, NULL,
289 NULL, NULL, NULL, NULL),
290 _AM33XX_MUXENTRY(SPI0_D0, 0,
291 "spi0_d0", NULL, NULL, NULL,
292 NULL, NULL, NULL, NULL),
293 _AM33XX_MUXENTRY(SPI0_D1, 0,
294 "spi0_d1", "mmc1_sdwp", "i2c1_sda", NULL,
295 NULL, NULL, NULL, NULL),
296 _AM33XX_MUXENTRY(SPI0_CS0, 0,
297 "spi0_cs0", "mmc2_sdwp", "i2c1_scl", NULL,
298 NULL, NULL, NULL, NULL),
299 _AM33XX_MUXENTRY(SPI0_CS1, 0,
300 "spi0_cs1", "uart3_rxd", NULL, "mmc0_pow",
301 NULL, "mmc0_sdcd", NULL, NULL),
302 _AM33XX_MUXENTRY(ECAP0_IN_PWM0_OUT, 0,
303 "ecap0_in_pwm0_out", "uart3_txd", "spi1_cs1", NULL,
304 "spi1_sclk", "mmc0_sdwp", NULL, "gpio0_7"),
305 _AM33XX_MUXENTRY(UART0_CTSN, 0,
306 "uatr0_ctsn", NULL, NULL, NULL,
307 "spi1_d0", NULL, NULL, NULL),
308 _AM33XX_MUXENTRY(UART0_RTSN, 0,
309 "uart0_rtsn", NULL, NULL, NULL,
310 "spi1_d1", "spi1_cs0", NULL, NULL),
311 _AM33XX_MUXENTRY(UART0_RXD, 0,
312 "uart0_rxd", "spi1_cs0", NULL, NULL,
313 NULL, NULL, NULL, NULL),
314 _AM33XX_MUXENTRY(UART0_TXD, 0,
315 "uart0_txd", "spi1_cs1", NULL, NULL,
316 NULL, NULL, NULL, NULL),
317 _AM33XX_MUXENTRY(UART1_CTSN, 0,
318 "uart1_ctsn", NULL, NULL, NULL,
319 "spi1_cs0", NULL, NULL, NULL),
320 _AM33XX_MUXENTRY(UART1_RTSN, 0,
321 "uart1_rtsn", NULL, NULL, NULL,
322 "spi1_cs1", NULL, NULL, NULL),
323 _AM33XX_MUXENTRY(UART1_RXD, 0,
324 "uart1_rxd", "mmc1_sdwp", NULL, NULL,
325 NULL, NULL, NULL, NULL),
326 _AM33XX_MUXENTRY(UART1_TXD, 0,
327 "uart1_txd", "mmc2_sdwp", NULL, NULL,
328 NULL, NULL, NULL, NULL),
329 _AM33XX_MUXENTRY(I2C0_SDA, 0,
330 "i2c0_sda", NULL, NULL, NULL,
331 NULL, NULL, NULL, NULL),
332 _AM33XX_MUXENTRY(I2C0_SCL, 0,
333 "i2c0_scl", NULL, NULL, NULL,
334 NULL, NULL, NULL, NULL),
335 _AM33XX_MUXENTRY(MCASP0_ACLKX, 0,
336 "mcasp0_aclkx", NULL, NULL, "spi1_sclk",
337 "mmc0_sdcd", NULL, NULL, NULL),
338 _AM33XX_MUXENTRY(MCASP0_FSX, 0,
339 "mcasp0_fsx", NULL, NULL, "spi1_d0",
340 "mmc1_sdcd", NULL, NULL, NULL),
341 _AM33XX_MUXENTRY(MCASP0_AXR0, 0,
342 "mcasp0_axr0", NULL, NULL, "spi1_d1",
343 "mmc2_sdcd", NULL, NULL, NULL),
344 _AM33XX_MUXENTRY(MCASP0_AHCLKR, 0,
345 "mcasp0_ahclkr", NULL, "mcasp0_axr2", "spi1_cs0",
346 NULL, NULL, NULL, "gpio3_17"),
347 _AM33XX_MUXENTRY(MCASP0_ACLKR, 0,
348 "mcasp0_aclkr", NULL, "mcasp0_axr2", "mcasp1_aclkx",
349 "mmc0_sdwp", NULL, NULL, NULL),
350 _AM33XX_MUXENTRY(MCASP0_FSR, 0,
351 "mcasp0_fsr", NULL, "mcasp0_axr3", "mcasp1_fsx",
352 NULL, NULL, NULL, NULL),
353 _AM33XX_MUXENTRY(MCASP0_AXR1, 0,
354 "mcasp0_axr1", NULL, NULL, "mcasp1_axr0",
355 NULL, NULL, NULL, NULL),
356 _AM33XX_MUXENTRY(MCASP0_AHCLKX, 0,
357 "mcasp0_ahclkx", "mcasp0_axr3", NULL, "mcasp1_axr1",
358 NULL, NULL, NULL, NULL),
359 _AM33XX_MUXENTRY(XDMA_EVENT_INTR0, 0,
360 "xdma_event_intr0", NULL, NULL, NULL,
361 "spi1_cs1", NULL, NULL, NULL),
362 _AM33XX_MUXENTRY(XDMA_EVENT_INTR1, 0,
363 "xdma_event_intr1", NULL, NULL, "clkout2",
364 NULL, NULL, NULL, NULL),
365 _AM33XX_MUXENTRY(WARMRSTN, 0,
366 NULL, NULL, NULL, NULL,
367 NULL, NULL, NULL, NULL),
368 _AM33XX_MUXENTRY(PWRONRSTN, 0,
369 NULL, NULL, NULL, NULL,
370 NULL, NULL, NULL, NULL),
371 _AM33XX_MUXENTRY(NMIN, 0,
372 NULL, NULL, NULL, NULL,
373 NULL, NULL, NULL, NULL),
374 _AM33XX_MUXENTRY(XTALIN, 0,
375 NULL, NULL, NULL, NULL,
376 NULL, NULL, NULL, NULL),
377 _AM33XX_MUXENTRY(XTALOUT, 0,
378 NULL, NULL, NULL, NULL,
379 NULL, NULL, NULL, NULL),
380 _AM33XX_MUXENTRY(TMS, 0,
381 NULL, NULL, NULL, NULL,
382 NULL, NULL, NULL, NULL),
383 _AM33XX_MUXENTRY(TDI, 0,
384 NULL, NULL, NULL, NULL,
385 NULL, NULL, NULL, NULL),
386 _AM33XX_MUXENTRY(TDO, 0,
387 NULL, NULL, NULL, NULL,
388 NULL, NULL, NULL, NULL),
389 _AM33XX_MUXENTRY(TCK, 0,
390 NULL, NULL, NULL, NULL,
391 NULL, NULL, NULL, NULL),
392 _AM33XX_MUXENTRY(TRSTN, 0,
393 NULL, NULL, NULL, NULL,
394 NULL, NULL, NULL, NULL),
395 _AM33XX_MUXENTRY(EMU0, 0,
396 NULL, NULL, NULL, NULL,
397 NULL, NULL, NULL, NULL),
398 _AM33XX_MUXENTRY(EMU1, 0,
399 NULL, NULL, NULL, NULL,
400 NULL, NULL, NULL, NULL),
401 _AM33XX_MUXENTRY(RTC_XTALIN, 0,
402 NULL, NULL, NULL, NULL,
403 NULL, NULL, NULL, NULL),
404 _AM33XX_MUXENTRY(RTC_XTALOUT, 0,
405 NULL, NULL, NULL, NULL,
406 NULL, NULL, NULL, NULL),
407 _AM33XX_MUXENTRY(RTC_PWRONRSTN, 0,
408 NULL, NULL, NULL, NULL,
409 NULL, NULL, NULL, NULL),
410 _AM33XX_MUXENTRY(PMIC_POWER_EN, 0,
411 NULL, NULL, NULL, NULL,
412 NULL, NULL, NULL, NULL),
413 _AM33XX_MUXENTRY(EXT_WAKEUP, 0,
414 NULL, NULL, NULL, NULL,
415 NULL, NULL, NULL, NULL),
416 _AM33XX_MUXENTRY(USB0_DRVVBUS, 0,
417 "usb0_drvvbus", NULL, NULL, NULL,
418 NULL, NULL, NULL, NULL),
419 _AM33XX_MUXENTRY(USB1_DRVVBUS, 0,
420 "usb1_drvvbus", NULL, NULL, NULL,
421 NULL, NULL, NULL, NULL),
422 _AM33XX_MUXENTRY(DDR_RESETN, 0,
423 NULL, NULL, NULL, NULL,
424 NULL, NULL, NULL, NULL),
425 _AM33XX_MUXENTRY(DDR_CSN0, 0,
426 NULL, NULL, NULL, NULL,
427 NULL, NULL, NULL, NULL),
428 _AM33XX_MUXENTRY(DDR_CKE, 0,
429 NULL, NULL, NULL, NULL,
430 NULL, NULL, NULL, NULL),
431 _AM33XX_MUXENTRY(DDR_CK, 0,
432 NULL, NULL, NULL, NULL,
433 NULL, NULL, NULL, NULL),
434 _AM33XX_MUXENTRY(DDR_CKN, 0,
435 NULL, NULL, NULL, NULL,
436 NULL, NULL, NULL, NULL),
437 _AM33XX_MUXENTRY(DDR_CASN, 0,
438 NULL, NULL, NULL, NULL,
439 NULL, NULL, NULL, NULL),
440 _AM33XX_MUXENTRY(DDR_RASN, 0,
441 NULL, NULL, NULL, NULL,
442 NULL, NULL, NULL, NULL),
443 _AM33XX_MUXENTRY(DDR_WEN, 0,
444 NULL, NULL, NULL, NULL,
445 NULL, NULL, NULL, NULL),
446 _AM33XX_MUXENTRY(DDR_BA0, 0,
447 NULL, NULL, NULL, NULL,
448 NULL, NULL, NULL, NULL),
449 _AM33XX_MUXENTRY(DDR_BA1, 0,
450 NULL, NULL, NULL, NULL,
451 NULL, NULL, NULL, NULL),
452 _AM33XX_MUXENTRY(DDR_BA2, 0,
453 NULL, NULL, NULL, NULL,
454 NULL, NULL, NULL, NULL),
455 _AM33XX_MUXENTRY(DDR_A0, 0,
456 NULL, NULL, NULL, NULL,
457 NULL, NULL, NULL, NULL),
458 _AM33XX_MUXENTRY(DDR_A1, 0,
459 NULL, NULL, NULL, NULL,
460 NULL, NULL, NULL, NULL),
461 _AM33XX_MUXENTRY(DDR_A2, 0,
462 NULL, NULL, NULL, NULL,
463 NULL, NULL, NULL, NULL),
464 _AM33XX_MUXENTRY(DDR_A3, 0,
465 NULL, NULL, NULL, NULL,
466 NULL, NULL, NULL, NULL),
467 _AM33XX_MUXENTRY(DDR_A4, 0,
468 NULL, NULL, NULL, NULL,
469 NULL, NULL, NULL, NULL),
470 _AM33XX_MUXENTRY(DDR_A5, 0,
471 NULL, NULL, NULL, NULL,
472 NULL, NULL, NULL, NULL),
473 _AM33XX_MUXENTRY(DDR_A6, 0,
474 NULL, NULL, NULL, NULL,
475 NULL, NULL, NULL, NULL),
476 _AM33XX_MUXENTRY(DDR_A7, 0,
477 NULL, NULL, NULL, NULL,
478 NULL, NULL, NULL, NULL),
479 _AM33XX_MUXENTRY(DDR_A8, 0,
480 NULL, NULL, NULL, NULL,
481 NULL, NULL, NULL, NULL),
482 _AM33XX_MUXENTRY(DDR_A9, 0,
483 NULL, NULL, NULL, NULL,
484 NULL, NULL, NULL, NULL),
485 _AM33XX_MUXENTRY(DDR_A10, 0,
486 NULL, NULL, NULL, NULL,
487 NULL, NULL, NULL, NULL),
488 _AM33XX_MUXENTRY(DDR_A11, 0,
489 NULL, NULL, NULL, NULL,
490 NULL, NULL, NULL, NULL),
491 _AM33XX_MUXENTRY(DDR_A12, 0,
492 NULL, NULL, NULL, NULL,
493 NULL, NULL, NULL, NULL),
494 _AM33XX_MUXENTRY(DDR_A13, 0,
495 NULL, NULL, NULL, NULL,
496 NULL, NULL, NULL, NULL),
497 _AM33XX_MUXENTRY(DDR_A14, 0,
498 NULL, NULL, NULL, NULL,
499 NULL, NULL, NULL, NULL),
500 _AM33XX_MUXENTRY(DDR_A15, 0,
501 NULL, NULL, NULL, NULL,
502 NULL, NULL, NULL, NULL),
503 _AM33XX_MUXENTRY(DDR_ODT, 0,
504 NULL, NULL, NULL, NULL,
505 NULL, NULL, NULL, NULL),
506 _AM33XX_MUXENTRY(DDR_D0, 0,
507 NULL, NULL, NULL, NULL,
508 NULL, NULL, NULL, NULL),
509 _AM33XX_MUXENTRY(DDR_D1, 0,
510 NULL, NULL, NULL, NULL,
511 NULL, NULL, NULL, NULL),
512 _AM33XX_MUXENTRY(DDR_D2, 0,
513 NULL, NULL, NULL, NULL,
514 NULL, NULL, NULL, NULL),
515 _AM33XX_MUXENTRY(DDR_D3, 0,
516 NULL, NULL, NULL, NULL,
517 NULL, NULL, NULL, NULL),
518 _AM33XX_MUXENTRY(DDR_D4, 0,
519 NULL, NULL, NULL, NULL,
520 NULL, NULL, NULL, NULL),
521 _AM33XX_MUXENTRY(DDR_D5, 0,
522 NULL, NULL, NULL, NULL,
523 NULL, NULL, NULL, NULL),
524 _AM33XX_MUXENTRY(DDR_D6, 0,
525 NULL, NULL, NULL, NULL,
526 NULL, NULL, NULL, NULL),
527 _AM33XX_MUXENTRY(DDR_D7, 0,
528 NULL, NULL, NULL, NULL,
529 NULL, NULL, NULL, NULL),
530 _AM33XX_MUXENTRY(DDR_D8, 0,
531 NULL, NULL, NULL, NULL,
532 NULL, NULL, NULL, NULL),
533 _AM33XX_MUXENTRY(DDR_D9, 0,
534 NULL, NULL, NULL, NULL,
535 NULL, NULL, NULL, NULL),
536 _AM33XX_MUXENTRY(DDR_D10, 0,
537 NULL, NULL, NULL, NULL,
538 NULL, NULL, NULL, NULL),
539 _AM33XX_MUXENTRY(DDR_D11, 0,
540 NULL, NULL, NULL, NULL,
541 NULL, NULL, NULL, NULL),
542 _AM33XX_MUXENTRY(DDR_D12, 0,
543 NULL, NULL, NULL, NULL,
544 NULL, NULL, NULL, NULL),
545 _AM33XX_MUXENTRY(DDR_D13, 0,
546 NULL, NULL, NULL, NULL,
547 NULL, NULL, NULL, NULL),
548 _AM33XX_MUXENTRY(DDR_D14, 0,
549 NULL, NULL, NULL, NULL,
550 NULL, NULL, NULL, NULL),
551 _AM33XX_MUXENTRY(DDR_D15, 0,
552 NULL, NULL, NULL, NULL,
553 NULL, NULL, NULL, NULL),
554 _AM33XX_MUXENTRY(DDR_DQM0, 0,
555 NULL, NULL, NULL, NULL,
556 NULL, NULL, NULL, NULL),
557 _AM33XX_MUXENTRY(DDR_DQM1, 0,
558 NULL, NULL, NULL, NULL,
559 NULL, NULL, NULL, NULL),
560 _AM33XX_MUXENTRY(DDR_DQS0, 0,
561 NULL, NULL, NULL, NULL,
562 NULL, NULL, NULL, NULL),
563 _AM33XX_MUXENTRY(DDR_DQSN0, 0,
564 NULL, NULL, NULL, NULL,
565 NULL, NULL, NULL, NULL),
566 _AM33XX_MUXENTRY(DDR_DQS1, 0,
567 NULL, NULL, NULL, NULL,
568 NULL, NULL, NULL, NULL),
569 _AM33XX_MUXENTRY(DDR_DQSN1, 0,
570 NULL, NULL, NULL, NULL,
571 NULL, NULL, NULL, NULL),
572 _AM33XX_MUXENTRY(DDR_VREF, 0,
573 NULL, NULL, NULL, NULL,
574 NULL, NULL, NULL, NULL),
575 _AM33XX_MUXENTRY(DDR_VTP, 0,
576 NULL, NULL, NULL, NULL,
577 NULL, NULL, NULL, NULL),
578 _AM33XX_MUXENTRY(AIN0, 0,
579 "ain0", NULL, NULL, NULL,
580 NULL, NULL, NULL, NULL),
581 _AM33XX_MUXENTRY(AIN1, 0,
582 "ain1", NULL, NULL, NULL,
583 NULL, NULL, NULL, NULL),
584 _AM33XX_MUXENTRY(AIN2, 0,
585 "ain2", NULL, NULL, NULL,
586 NULL, NULL, NULL, NULL),
587 _AM33XX_MUXENTRY(AIN3, 0,
588 "ain3", NULL, NULL, NULL,
589 NULL, NULL, NULL, NULL),
590 _AM33XX_MUXENTRY(VREFP, 0,
591 "vrefp", NULL, NULL, NULL,
592 NULL, NULL, NULL, NULL),
593 _AM33XX_MUXENTRY(VREFN, 0,
594 "vrefn", NULL, NULL, NULL,
595 NULL, NULL, NULL, NULL),
596 { .reg_offset = OMAP_MUX_TERMINATOR },
597 };
599 int __init am33xx_mux_init(struct omap_board_mux *board_subset)
600 {
601 return omap_mux_init("core", 0, AM33XX_CONTROL_PADCONF_MUX_PBASE,
602 AM33XX_CONTROL_PADCONF_MUX_SIZE, am33xx_muxmodes,
603 NULL, board_subset, NULL);
604 }
605 #else
606 int __init am33xx_mux_init(struct omap_board_mux *board_subset)
607 {
608 return 0;
609 }
610 #endif