1 /*
2 * AM33XX pad control register macros.
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
16 #ifndef __ARCH_ARM_MACH_OMAP2_MUX335X_H
17 #define __ARCH_ARM_MACH_OMAP2_MUX335X_H
19 #define AM33XX_CONTROL_PADCONF_MUX_PBASE 0x44E10000LU
21 /* If pin is not defined as input, pull would get disabled.
22 * If defined as input, flags supplied will determine pull on/off.
23 */
24 #define AM33XX_MUX(mode0, mux_value) \
25 { \
26 .reg_offset = (AM33XX_CONTROL_PADCONF_##mode0##_OFFSET), \
27 .value = (((mux_value) & AM33XX_INPUT_EN) ? (mux_value)\
28 : ((mux_value) | AM33XX_PULL_DISA)), \
29 }
31 /*
32 * AM33XX CONTROL_PADCONF* register offsets for pin-muxing
33 *
34 * Add AM33XX_CONTROL_PADCONF_MUX_PBASE to these values to get the
35 * absolute addresses. The macro names below are mode-0 names of
36 * corresponding pins.
37 */
39 #define AM33XX_CONTROL_PADCONF_GPMC_AD0_OFFSET 0x0800
40 #define AM33XX_CONTROL_PADCONF_GPMC_AD1_OFFSET 0x0804
41 #define AM33XX_CONTROL_PADCONF_GPMC_AD2_OFFSET 0x0808
42 #define AM33XX_CONTROL_PADCONF_GPMC_AD3_OFFSET 0x080C
43 #define AM33XX_CONTROL_PADCONF_GPMC_AD4_OFFSET 0x0810
44 #define AM33XX_CONTROL_PADCONF_GPMC_AD5_OFFSET 0x0814
45 #define AM33XX_CONTROL_PADCONF_GPMC_AD6_OFFSET 0x0818
46 #define AM33XX_CONTROL_PADCONF_GPMC_AD7_OFFSET 0x081C
47 #define AM33XX_CONTROL_PADCONF_GPMC_AD8_OFFSET 0x0820
48 #define AM33XX_CONTROL_PADCONF_GPMC_AD9_OFFSET 0x0824
49 #define AM33XX_CONTROL_PADCONF_GPMC_AD10_OFFSET 0x0828
50 #define AM33XX_CONTROL_PADCONF_GPMC_AD11_OFFSET 0x082C
51 #define AM33XX_CONTROL_PADCONF_GPMC_AD12_OFFSET 0x0830
52 #define AM33XX_CONTROL_PADCONF_GPMC_AD13_OFFSET 0x0834
53 #define AM33XX_CONTROL_PADCONF_GPMC_AD14_OFFSET 0x0838
54 #define AM33XX_CONTROL_PADCONF_GPMC_AD15_OFFSET 0x083C
55 #define AM33XX_CONTROL_PADCONF_GPMC_A0_OFFSET 0x0840
56 #define AM33XX_CONTROL_PADCONF_GPMC_A1_OFFSET 0x0844
57 #define AM33XX_CONTROL_PADCONF_GPMC_A2_OFFSET 0x0848
58 #define AM33XX_CONTROL_PADCONF_GPMC_A3_OFFSET 0x084C
59 #define AM33XX_CONTROL_PADCONF_GPMC_A4_OFFSET 0x0850
60 #define AM33XX_CONTROL_PADCONF_GPMC_A5_OFFSET 0x0854
61 #define AM33XX_CONTROL_PADCONF_GPMC_A6_OFFSET 0x0858
62 #define AM33XX_CONTROL_PADCONF_GPMC_A7_OFFSET 0x085C
63 #define AM33XX_CONTROL_PADCONF_GPMC_A8_OFFSET 0x0860
64 #define AM33XX_CONTROL_PADCONF_GPMC_A9_OFFSET 0x0864
65 #define AM33XX_CONTROL_PADCONF_GPMC_A10_OFFSET 0x0868
66 #define AM33XX_CONTROL_PADCONF_GPMC_A11_OFFSET 0x086C
67 #define AM33XX_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x0870
68 #define AM33XX_CONTROL_PADCONF_GPMC_WPN_OFFSET 0x0874
69 #define AM33XX_CONTROL_PADCONF_GPMC_BEN1_OFFSET 0x0878
70 #define AM33XX_CONTROL_PADCONF_GPMC_CSN0_OFFSET 0x087C
71 #define AM33XX_CONTROL_PADCONF_GPMC_CSN1_OFFSET 0x0880
72 #define AM33XX_CONTROL_PADCONF_GPMC_CSN2_OFFSET 0x0884
73 #define AM33XX_CONTROL_PADCONF_GPMC_CSN3_OFFSET 0x0888
74 #define AM33XX_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x088C
75 #define AM33XX_CONTROL_PADCONF_GPMC_ADVN_ALE_OFFSET 0x0890
76 #define AM33XX_CONTROL_PADCONF_GPMC_OEN_REN_OFFSET 0x0894
77 #define AM33XX_CONTROL_PADCONF_GPMC_WEN_OFFSET 0x0898
78 #define AM33XX_CONTROL_PADCONF_GPMC_BEN0_CLE_OFFSET 0x089C
79 #define AM33XX_CONTROL_PADCONF_LCD_DATA0_OFFSET 0x08A0
80 #define AM33XX_CONTROL_PADCONF_LCD_DATA1_OFFSET 0x08A4
81 #define AM33XX_CONTROL_PADCONF_LCD_DATA2_OFFSET 0x08A8
82 #define AM33XX_CONTROL_PADCONF_LCD_DATA3_OFFSET 0x08AC
83 #define AM33XX_CONTROL_PADCONF_LCD_DATA4_OFFSET 0x08B0
84 #define AM33XX_CONTROL_PADCONF_LCD_DATA5_OFFSET 0x08B4
85 #define AM33XX_CONTROL_PADCONF_LCD_DATA6_OFFSET 0x08B8
86 #define AM33XX_CONTROL_PADCONF_LCD_DATA7_OFFSET 0x08BC
87 #define AM33XX_CONTROL_PADCONF_LCD_DATA8_OFFSET 0x08C0
88 #define AM33XX_CONTROL_PADCONF_LCD_DATA9_OFFSET 0x08C4
89 #define AM33XX_CONTROL_PADCONF_LCD_DATA10_OFFSET 0x08C8
90 #define AM33XX_CONTROL_PADCONF_LCD_DATA11_OFFSET 0x08CC
91 #define AM33XX_CONTROL_PADCONF_LCD_DATA12_OFFSET 0x08D0
92 #define AM33XX_CONTROL_PADCONF_LCD_DATA13_OFFSET 0x08D4
93 #define AM33XX_CONTROL_PADCONF_LCD_DATA14_OFFSET 0x08D8
94 #define AM33XX_CONTROL_PADCONF_LCD_DATA15_OFFSET 0x08DC
95 #define AM33XX_CONTROL_PADCONF_LCD_VSYNC_OFFSET 0x08E0
96 #define AM33XX_CONTROL_PADCONF_LCD_HSYNC_OFFSET 0x08E4
97 #define AM33XX_CONTROL_PADCONF_LCD_PCLK_OFFSET 0x08E8
98 #define AM33XX_CONTROL_PADCONF_LCD_AC_BIAS_EN_OFFSET 0x08EC
99 #define AM33XX_CONTROL_PADCONF_MMC0_DAT3_OFFSET 0x08F0
100 #define AM33XX_CONTROL_PADCONF_MMC0_DAT2_OFFSET 0x08F4
101 #define AM33XX_CONTROL_PADCONF_MMC0_DAT1_OFFSET 0x08F8
102 #define AM33XX_CONTROL_PADCONF_MMC0_DAT0_OFFSET 0x08FC
103 #define AM33XX_CONTROL_PADCONF_MMC0_CLK_OFFSET 0x0900
104 #define AM33XX_CONTROL_PADCONF_MMC0_CMD_OFFSET 0x0904
105 #define AM33XX_CONTROL_PADCONF_MII1_COL_OFFSET 0x0908
106 #define AM33XX_CONTROL_PADCONF_MII1_CRS_OFFSET 0x090C
107 #define AM33XX_CONTROL_PADCONF_MII1_RXERR_OFFSET 0x0910
108 #define AM33XX_CONTROL_PADCONF_MII1_TXEN_OFFSET 0x0914
109 #define AM33XX_CONTROL_PADCONF_MII1_RXDV_OFFSET 0x0918
110 #define AM33XX_CONTROL_PADCONF_MII1_TXD3_OFFSET 0x091C
111 #define AM33XX_CONTROL_PADCONF_MII1_TXD2_OFFSET 0x0920
112 #define AM33XX_CONTROL_PADCONF_MII1_TXD1_OFFSET 0x0924
113 #define AM33XX_CONTROL_PADCONF_MII1_TXD0_OFFSET 0x0928
114 #define AM33XX_CONTROL_PADCONF_MII1_TXCLK_OFFSET 0x092C
115 #define AM33XX_CONTROL_PADCONF_MII1_RXCLK_OFFSET 0x0930
116 #define AM33XX_CONTROL_PADCONF_MII1_RXD3_OFFSET 0x0934
117 #define AM33XX_CONTROL_PADCONF_MII1_RXD2_OFFSET 0x0938
118 #define AM33XX_CONTROL_PADCONF_MII1_RXD1_OFFSET 0x093C
119 #define AM33XX_CONTROL_PADCONF_MII1_RXD0_OFFSET 0x0940
120 #define AM33XX_CONTROL_PADCONF_MII1_REFCLK_OFFSET 0x0944
121 #define AM33XX_CONTROL_PADCONF_MDIO_DATA_OFFSET 0x0948
122 #define AM33XX_CONTROL_PADCONF_MDIO_CLK_OFFSET 0x094C
123 #define AM33XX_CONTROL_PADCONF_SPI0_SCLK_OFFSET 0x0950
124 #define AM33XX_CONTROL_PADCONF_SPI0_D0_OFFSET 0x0954
125 #define AM33XX_CONTROL_PADCONF_SPI0_D1_OFFSET 0x0958
126 #define AM33XX_CONTROL_PADCONF_SPI0_CS0_OFFSET 0x095C
127 #define AM33XX_CONTROL_PADCONF_SPI0_CS1_OFFSET 0x0960
128 #define AM33XX_CONTROL_PADCONF_ECAP0_IN_PWM0_OUT_OFFSET 0x0964
129 #define AM33XX_CONTROL_PADCONF_UART0_CTSN_OFFSET 0x0968
130 #define AM33XX_CONTROL_PADCONF_UART0_RTSN_OFFSET 0x096C
131 #define AM33XX_CONTROL_PADCONF_UART0_RXD_OFFSET 0x0970
132 #define AM33XX_CONTROL_PADCONF_UART0_TXD_OFFSET 0x0974
133 #define AM33XX_CONTROL_PADCONF_UART1_CTSN_OFFSET 0x0978
134 #define AM33XX_CONTROL_PADCONF_UART1_RTSN_OFFSET 0x097C
135 #define AM33XX_CONTROL_PADCONF_UART1_RXD_OFFSET 0x0980
136 #define AM33XX_CONTROL_PADCONF_UART1_TXD_OFFSET 0x0984
137 #define AM33XX_CONTROL_PADCONF_I2C0_SDA_OFFSET 0x0988
138 #define AM33XX_CONTROL_PADCONF_I2C0_SCL_OFFSET 0x098C
139 #define AM33XX_CONTROL_PADCONF_MCASP0_ACLKX_OFFSET 0x0990
140 #define AM33XX_CONTROL_PADCONF_MCASP0_FSX_OFFSET 0x0994
141 #define AM33XX_CONTROL_PADCONF_MCASP0_AXR0_OFFSET 0x0998
142 #define AM33XX_CONTROL_PADCONF_MCASP0_AHCLKR_OFFSET 0x099C
143 #define AM33XX_CONTROL_PADCONF_MCASP0_ACLKR_OFFSET 0x09A0
144 #define AM33XX_CONTROL_PADCONF_MCASP0_FSR_OFFSET 0x09A4
145 #define AM33XX_CONTROL_PADCONF_MCASP0_AXR1_OFFSET 0x09A8
146 #define AM33XX_CONTROL_PADCONF_MCASP0_AHCLKX_OFFSET 0x09AC
147 #define AM33XX_CONTROL_PADCONF_XDMA_EVENT_INTR0_OFFSET 0x09B0
148 #define AM33XX_CONTROL_PADCONF_XDMA_EVENT_INTR1_OFFSET 0x09B4
149 #define AM33XX_CONTROL_PADCONF_WARMRSTN_OFFSET 0x09B8
150 #define AM33XX_CONTROL_PADCONF_PWRONRSTN_OFFSET 0x09BC
151 #define AM33XX_CONTROL_PADCONF_NMIN_OFFSET 0x09C0
152 #define AM33XX_CONTROL_PADCONF_XTALIN_OFFSET 0x09C4
153 #define AM33XX_CONTROL_PADCONF_XTALOUT_OFFSET 0x09C8
154 #define AM33XX_CONTROL_PADCONF_TMS_OFFSET 0x09D0
155 #define AM33XX_CONTROL_PADCONF_TDI_OFFSET 0x09D4
156 #define AM33XX_CONTROL_PADCONF_TDO_OFFSET 0x09D8
157 #define AM33XX_CONTROL_PADCONF_TCK_OFFSET 0x09DC
158 #define AM33XX_CONTROL_PADCONF_TRSTN_OFFSET 0x09E0
159 #define AM33XX_CONTROL_PADCONF_EMU0_OFFSET 0x09E4
160 #define AM33XX_CONTROL_PADCONF_EMU1_OFFSET 0x09E8
161 #define AM33XX_CONTROL_PADCONF_RTC_XTALIN_OFFSET 0x09EC
162 #define AM33XX_CONTROL_PADCONF_RTC_XTALOUT_OFFSET 0x09F0
163 #define AM33XX_CONTROL_PADCONF_RTC_PWRONRSTN_OFFSET 0x09F8
164 #define AM33XX_CONTROL_PADCONF_EXT_WAKEUP_OFFSET 0x0A00
165 #define AM33XX_CONTROL_PADCONF_PMIC_POWER_EN_OFFSET 0x09F4
166 #define AM33XX_CONTROL_PADCONF_RTC_KALDO_ENN_OFFSET 0x0A04
167 #define AM33XX_CONTROL_PADCONF_USB0_DM_OFFSET 0x0A08
168 #define AM33XX_CONTROL_PADCONF_USB0_DP_OFFSET 0x0A0C
169 #define AM33XX_CONTROL_PADCONF_USB0_CE_OFFSET 0x0A10
170 #define AM33XX_CONTROL_PADCONF_USB0_ID_OFFSET 0x0A14
171 #define AM33XX_CONTROL_PADCONF_USB0_VBUS_OFFSET 0x0A18
172 #define AM33XX_CONTROL_PADCONF_USB0_DRVVBUS_OFFSET 0x0A1C
173 #define AM33XX_CONTROL_PADCONF_USB1_DM_OFFSET 0x0A20
174 #define AM33XX_CONTROL_PADCONF_USB1_DP_OFFSET 0x0A24
175 #define AM33XX_CONTROL_PADCONF_USB1_CE_OFFSET 0x0A28
176 #define AM33XX_CONTROL_PADCONF_USB1_ID_OFFSET 0x0A2C
177 #define AM33XX_CONTROL_PADCONF_USB1_VBUS_OFFSET 0x0A30
178 #define AM33XX_CONTROL_PADCONF_USB1_DRVVBUS_OFFSET 0x0A34
179 #define AM33XX_CONTROL_PADCONF_DDR_RESETN_OFFSET 0x0A38
180 #define AM33XX_CONTROL_PADCONF_DDR_CSN0_OFFSET 0x0A3C
181 #define AM33XX_CONTROL_PADCONF_DDR_CKE_OFFSET 0x0A40
182 #define AM33XX_CONTROL_PADCONF_DDR_CK_OFFSET 0x0A44
183 #define AM33XX_CONTROL_PADCONF_DDR_CKN_OFFSET 0x0A48
184 #define AM33XX_CONTROL_PADCONF_DDR_CASN_OFFSET 0x0A4C
185 #define AM33XX_CONTROL_PADCONF_DDR_RASN_OFFSET 0x0A50
186 #define AM33XX_CONTROL_PADCONF_DDR_WEN_OFFSET 0x0A54
187 #define AM33XX_CONTROL_PADCONF_DDR_BA0_OFFSET 0x0A58
188 #define AM33XX_CONTROL_PADCONF_DDR_BA1_OFFSET 0x0A5C
189 #define AM33XX_CONTROL_PADCONF_DDR_BA2_OFFSET 0x0A60
190 #define AM33XX_CONTROL_PADCONF_DDR_A0_OFFSET 0x0A64
191 #define AM33XX_CONTROL_PADCONF_DDR_A1_OFFSET 0x0A68
192 #define AM33XX_CONTROL_PADCONF_DDR_A2_OFFSET 0x0A6C
193 #define AM33XX_CONTROL_PADCONF_DDR_A3_OFFSET 0x0A70
194 #define AM33XX_CONTROL_PADCONF_DDR_A4_OFFSET 0x0A74
195 #define AM33XX_CONTROL_PADCONF_DDR_A5_OFFSET 0x0A78
196 #define AM33XX_CONTROL_PADCONF_DDR_A6_OFFSET 0x0A7C
197 #define AM33XX_CONTROL_PADCONF_DDR_A7_OFFSET 0x0A80
198 #define AM33XX_CONTROL_PADCONF_DDR_A8_OFFSET 0x0A84
199 #define AM33XX_CONTROL_PADCONF_DDR_A9_OFFSET 0x0A88
200 #define AM33XX_CONTROL_PADCONF_DDR_A10_OFFSET 0x0A8C
201 #define AM33XX_CONTROL_PADCONF_DDR_A11_OFFSET 0x0A90
202 #define AM33XX_CONTROL_PADCONF_DDR_A12_OFFSET 0x0A94
203 #define AM33XX_CONTROL_PADCONF_DDR_A13_OFFSET 0x0A98
204 #define AM33XX_CONTROL_PADCONF_DDR_A14_OFFSET 0x0A9C
205 #define AM33XX_CONTROL_PADCONF_DDR_A15_OFFSET 0x0AA0
206 #define AM33XX_CONTROL_PADCONF_DDR_ODT_OFFSET 0x0AA4
207 #define AM33XX_CONTROL_PADCONF_DDR_D0_OFFSET 0x0AA8
208 #define AM33XX_CONTROL_PADCONF_DDR_D1_OFFSET 0x0AAC
209 #define AM33XX_CONTROL_PADCONF_DDR_D2_OFFSET 0x0AB0
210 #define AM33XX_CONTROL_PADCONF_DDR_D3_OFFSET 0x0AB4
211 #define AM33XX_CONTROL_PADCONF_DDR_D4_OFFSET 0x0AB8
212 #define AM33XX_CONTROL_PADCONF_DDR_D5_OFFSET 0x0ABC
213 #define AM33XX_CONTROL_PADCONF_DDR_D6_OFFSET 0x0AC0
214 #define AM33XX_CONTROL_PADCONF_DDR_D7_OFFSET 0x0AC4
215 #define AM33XX_CONTROL_PADCONF_DDR_D8_OFFSET 0x0AC8
216 #define AM33XX_CONTROL_PADCONF_DDR_D9_OFFSET 0x0ACC
217 #define AM33XX_CONTROL_PADCONF_DDR_D10_OFFSET 0x0AD0
218 #define AM33XX_CONTROL_PADCONF_DDR_D11_OFFSET 0x0AD4
219 #define AM33XX_CONTROL_PADCONF_DDR_D12_OFFSET 0x0AD8
220 #define AM33XX_CONTROL_PADCONF_DDR_D13_OFFSET 0x0ADC
221 #define AM33XX_CONTROL_PADCONF_DDR_D14_OFFSET 0x0AE0
222 #define AM33XX_CONTROL_PADCONF_DDR_D15_OFFSET 0x0AE4
223 #define AM33XX_CONTROL_PADCONF_DDR_DQM0_OFFSET 0x0AE8
224 #define AM33XX_CONTROL_PADCONF_DDR_DQM1_OFFSET 0x0AEC
225 #define AM33XX_CONTROL_PADCONF_DDR_DQS0_OFFSET 0x0AF0
226 #define AM33XX_CONTROL_PADCONF_DDR_DQSN0_OFFSET 0x0AF4
227 #define AM33XX_CONTROL_PADCONF_DDR_DQS1_OFFSET 0x0AF8
228 #define AM33XX_CONTROL_PADCONF_DDR_DQSN1_OFFSET 0x0AFC
229 #define AM33XX_CONTROL_PADCONF_DDR_VREF_OFFSET 0x0B00
230 #define AM33XX_CONTROL_PADCONF_DDR_VTP_OFFSET 0x0B04
231 #define AM33XX_CONTROL_PADCONF_AIN3_OFFSET 0x0B20
232 #define AM33XX_CONTROL_PADCONF_AIN2_OFFSET 0x0B24
233 #define AM33XX_CONTROL_PADCONF_AIN1_OFFSET 0x0B28
234 #define AM33XX_CONTROL_PADCONF_AIN0_OFFSET 0x0B2C
235 #define AM33XX_CONTROL_PADCONF_VREFP_OFFSET 0x0B30
236 #define AM33XX_CONTROL_PADCONF_VREFN_OFFSET 0x0B34
238 #define AM33XX_CONTROL_PADCONF_MUX_SIZE \
239 (AM33XX_CONTROL_PADCONF_VREFN_OFFSET + 0x4)
241 #endif