1 /*
2 * OMAP4 specific common source file.
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc.
5 * Author:
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 *
8 *
9 * This program is free software,you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/io.h>
17 #include <linux/platform_device.h>
18 #include <linux/memblock.h>
20 #include <asm/hardware/gic.h>
21 #include <asm/hardware/cache-l2x0.h>
22 #include <asm/mach/map.h>
24 #include <plat/irqs.h>
25 #include <plat/sram.h>
27 #include <mach/hardware.h>
28 #include <mach/omap-wakeupgen.h>
30 #include "common.h"
31 #include "omap4-sar-layout.h"
33 #ifdef CONFIG_CACHE_L2X0
34 static void __iomem *l2cache_base;
35 #endif
37 static void __iomem *sar_ram_base;
39 #ifdef CONFIG_OMAP4_ERRATA_I688
40 /* Used to implement memory barrier on DRAM path */
41 #define OMAP4_DRAM_BARRIER_VA 0xfe600000
43 void __iomem *dram_sync, *sram_sync;
45 void omap_bus_sync(void)
46 {
47 if (dram_sync && sram_sync) {
48 writel_relaxed(readl_relaxed(dram_sync), dram_sync);
49 writel_relaxed(readl_relaxed(sram_sync), sram_sync);
50 isb();
51 }
52 }
54 static int __init omap_barriers_init(void)
55 {
56 struct map_desc dram_io_desc[1];
57 phys_addr_t paddr;
58 u32 size;
60 if (!cpu_is_omap44xx())
61 return -ENODEV;
63 size = ALIGN(PAGE_SIZE, SZ_1M);
64 paddr = memblock_alloc(size, SZ_1M);
65 if (!paddr) {
66 pr_err("%s: failed to reserve 4 Kbytes\n", __func__);
67 return -ENOMEM;
68 }
69 memblock_free(paddr, size);
70 memblock_remove(paddr, size);
71 dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
72 dram_io_desc[0].pfn = __phys_to_pfn(paddr);
73 dram_io_desc[0].length = size;
74 dram_io_desc[0].type = MT_MEMORY_SO;
75 iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
76 dram_sync = (void __iomem *) dram_io_desc[0].virtual;
77 sram_sync = (void __iomem *) OMAP4_SRAM_VA;
79 pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
80 (long long) paddr, dram_io_desc[0].virtual);
82 return 0;
83 }
84 core_initcall(omap_barriers_init);
85 #endif
87 void __init gic_init_irq(void)
88 {
89 void __iomem *omap_irq_base;
90 void __iomem *gic_dist_base_addr;
92 /* Static mapping, never released */
93 gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
94 BUG_ON(!gic_dist_base_addr);
96 /* Static mapping, never released */
97 omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
98 BUG_ON(!omap_irq_base);
100 omap_wakeupgen_init();
102 gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
103 }
105 #ifdef CONFIG_CACHE_L2X0
107 void __iomem *omap4_get_l2cache_base(void)
108 {
109 return l2cache_base;
110 }
112 static void omap4_l2x0_disable(void)
113 {
114 /* Disable PL310 L2 Cache controller */
115 omap_smc1(0x102, 0x0);
116 }
118 static void omap4_l2x0_set_debug(unsigned long val)
119 {
120 /* Program PL310 L2 Cache controller debug register */
121 omap_smc1(0x100, val);
122 }
124 static int __init omap_l2_cache_init(void)
125 {
126 u32 aux_ctrl = 0;
128 /*
129 * To avoid code running on other OMAPs in
130 * multi-omap builds
131 */
132 if (!cpu_is_omap44xx())
133 return -ENODEV;
135 /* Static mapping, never released */
136 l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
137 if (WARN_ON(!l2cache_base))
138 return -ENOMEM;
140 /*
141 * 16-way associativity, parity disabled
142 * Way size - 32KB (es1.0)
143 * Way size - 64KB (es2.0 +)
144 */
145 aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
146 (0x1 << 25) |
147 (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
148 (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
150 if (omap_rev() == OMAP4430_REV_ES1_0) {
151 aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
152 } else {
153 aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
154 (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
155 (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
156 (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
157 (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
158 }
159 if (omap_rev() != OMAP4430_REV_ES1_0)
160 omap_smc1(0x109, aux_ctrl);
162 /* Enable PL310 L2 Cache controller */
163 omap_smc1(0x102, 0x1);
165 l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
167 /*
168 * Override default outer_cache.disable with a OMAP4
169 * specific one
170 */
171 outer_cache.disable = omap4_l2x0_disable;
172 outer_cache.set_debug = omap4_l2x0_set_debug;
174 return 0;
175 }
176 early_initcall(omap_l2_cache_init);
177 #endif
179 void __iomem *omap4_get_sar_ram_base(void)
180 {
181 return sar_ram_base;
182 }
184 /*
185 * SAR RAM used to save and restore the HW
186 * context in low power modes
187 */
188 static int __init omap4_sar_ram_init(void)
189 {
190 /*
191 * To avoid code running on other OMAPs in
192 * multi-omap builds
193 */
194 if (!cpu_is_omap44xx())
195 return -ENOMEM;
197 /* Static mapping, never released */
198 sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
199 if (WARN_ON(!sar_ram_base))
200 return -ENOMEM;
202 return 0;
203 }
204 early_initcall(omap4_sar_ram_init);