2f9982cc32ca3aab51308cc5bca492e617198741
1 /*
2 * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
3 *
4 * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <linux/err.h>
20 #include <linux/errno.h>
22 #include <plat/omap_hwmod.h>
23 #include <plat/cpu.h>
24 #include <plat/gpio.h>
25 #include <plat/dma.h>
26 #include <plat/mmc.h>
27 #include <plat/mcspi.h>
28 #include <plat/i2c.h>
29 #include <plat/clock.h>
30 #include <plat/prcm.h>
32 #include "omap_hwmod_common_data.h"
33 #include "control.h"
34 #include "cm33xx.h"
35 #include "prm33xx.h"
36 #include "common.h"
38 /* Backward references (IPs with Bus Master capability) */
39 static struct omap_hwmod am33xx_mpu_hwmod;
40 static struct omap_hwmod am33xx_l3_main_hwmod;
41 static struct omap_hwmod am33xx_l3slow_hwmod;
42 static struct omap_hwmod am33xx_l4wkup_hwmod;
43 static struct omap_hwmod am33xx_l4per_hwmod;
44 static struct omap_hwmod am33xx_uart1_hwmod;
45 static struct omap_hwmod am33xx_uart2_hwmod;
46 static struct omap_hwmod am33xx_uart3_hwmod;
47 static struct omap_hwmod am33xx_uart4_hwmod;
48 static struct omap_hwmod am33xx_uart5_hwmod;
49 static struct omap_hwmod am33xx_uart6_hwmod;
50 static struct omap_hwmod am33xx_timer0_hwmod;
51 static struct omap_hwmod am33xx_timer1_hwmod;
52 static struct omap_hwmod am33xx_timer2_hwmod;
53 static struct omap_hwmod am33xx_timer3_hwmod;
54 static struct omap_hwmod am33xx_timer4_hwmod;
55 static struct omap_hwmod am33xx_timer5_hwmod;
56 static struct omap_hwmod am33xx_timer6_hwmod;
57 static struct omap_hwmod am33xx_timer7_hwmod;
58 static struct omap_hwmod am33xx_wd_timer1_hwmod;
59 static struct omap_hwmod am33xx_tpcc_hwmod;
60 static struct omap_hwmod am33xx_tptc0_hwmod;
61 static struct omap_hwmod am33xx_tptc1_hwmod;
62 static struct omap_hwmod am33xx_tptc2_hwmod;
63 static struct omap_hwmod am33xx_dcan0_hwmod;
64 static struct omap_hwmod am33xx_dcan1_hwmod;
65 static struct omap_hwmod am33xx_gpio0_hwmod;
66 static struct omap_hwmod am33xx_gpio1_hwmod;
67 static struct omap_hwmod am33xx_gpio2_hwmod;
68 static struct omap_hwmod am33xx_gpio3_hwmod;
69 static struct omap_hwmod am33xx_i2c1_hwmod;
70 static struct omap_hwmod am33xx_i2c2_hwmod;
71 static struct omap_hwmod am33xx_i2c3_hwmod;
72 static struct omap_hwmod am33xx_usbss_hwmod;
73 static struct omap_hwmod am33xx_mmc0_hwmod;
74 static struct omap_hwmod am33xx_mmc1_hwmod;
75 static struct omap_hwmod am33xx_mmc2_hwmod;
76 static struct omap_hwmod am33xx_spi0_hwmod;
77 static struct omap_hwmod am33xx_spi1_hwmod;
78 static struct omap_hwmod am33xx_elm_hwmod;
79 static struct omap_hwmod am33xx_adc_tsc_hwmod;
80 static struct omap_hwmod am33xx_mcasp0_hwmod;
81 static struct omap_hwmod am33xx_mcasp1_hwmod;
82 static struct omap_hwmod am33xx_ehrpwm0_hwmod;
83 static struct omap_hwmod am33xx_ehrpwm1_hwmod;
84 static struct omap_hwmod am33xx_ehrpwm2_hwmod;
85 static struct omap_hwmod am33xx_ecap0_hwmod;
86 static struct omap_hwmod am33xx_ecap1_hwmod;
87 static struct omap_hwmod am33xx_ecap2_hwmod;
88 static struct omap_hwmod am33xx_gpmc_hwmod;
89 static struct omap_hwmod am33xx_lcdc_hwmod;
90 static struct omap_hwmod am33xx_mailbox_hwmod;
91 static struct omap_hwmod am33xx_cpgmac0_hwmod;
92 static struct omap_hwmod am33xx_mdio_hwmod;
94 /*
95 * ERRATA: (Yet to conform from IP team)
96 * As per the observation, in order to disable the cpsw clock/module
97 * from already enabled state, module level reset assertion is
98 * required; without reset the clock/module won't enter into
99 * idle state at all.
100 * Also, as per observation (have not conformed yet), we have to
101 * assert reset signal for all cpsw (4) submodules.
102 */
104 /* OCP SYSSTATUS bit shifts/masks */
105 #define SOFT_RESETDONE_SHIFT 0
106 #define SOFT_RESETDONE_MASK (1 << SOFT_RESETDONE_SHIFT)
108 #define MAX_MODULE_SOFTRESET_WAIT 10000
110 static int am33xx_cpgmac_reset(struct omap_hwmod *oh)
111 {
112 int i;
113 int ret = 0;
115 pr_debug("%s: resetting via Module SOFTRESET bit\n", oh->name);
117 for (i = 0; i < oh->slaves_cnt; i++) {
118 int c = 0;
119 void __iomem *va_start;
120 struct omap_hwmod_ocp_if *os;
121 struct omap_hwmod_addr_space *mem;
123 os = oh->slaves[i];
124 /* FIXME: Only first instance's OCP_RST is asserted */
125 mem = &os->addr[0];
127 va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
128 if (!va_start) {
129 pr_err("%s: Could not ioremap (%x)\n",
130 oh->name, mem->pa_start);
131 ret = -ENOMEM;
132 break;
133 }
134 /* Assert reset signal */
135 writel(1, va_start + oh->class->sysc->rst_offs);
136 omap_test_timeout(((readl(va_start + oh->class->sysc->rst_offs)
137 & SOFT_RESETDONE_MASK) == 0),
138 MAX_MODULE_SOFTRESET_WAIT, c);
140 if (c == MAX_MODULE_SOFTRESET_WAIT) {
141 pr_warning("%s: softreset failed (waited %d usec)\n",
142 oh->name, MAX_MODULE_SOFTRESET_WAIT);
143 ret = -ETIMEDOUT;
144 }
145 }
147 return ret;
148 }
150 /*
151 * Interconnects hwmod structures
152 * hwmods that compose the global AM33XX OCP interconnect
153 */
155 /* MPU -> L3_SLOW Peripheral interface */
156 static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = {
157 .master = &am33xx_mpu_hwmod,
158 .slave = &am33xx_l3slow_hwmod,
159 .user = OCP_USER_MPU,
160 };
162 /* L3 SLOW -> L4_PER Peripheral interface */
163 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = {
164 .master = &am33xx_l3slow_hwmod,
165 .slave = &am33xx_l4per_hwmod,
166 .user = OCP_USER_MPU,
167 };
169 /* L3 SLOW -> L4_WKUP Peripheral interface */
170 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = {
171 .master = &am33xx_l3slow_hwmod,
172 .slave = &am33xx_l4wkup_hwmod,
173 .user = OCP_USER_MPU,
174 };
176 /* Master interfaces on the L4_WKUP interconnect */
177 static struct omap_hwmod_ocp_if *am33xx_l3_slow_masters[] = {
178 &am33xx_l3_slow__l4_per,
179 &am33xx_l3_slow__l4_wkup,
180 };
182 /* Slave interfaces on the L3_SLOW interconnect */
183 static struct omap_hwmod_ocp_if *am33xx_l3_slow_slaves[] = {
184 &am33xx_mpu__l3_slow,
185 };
187 static struct omap_hwmod am33xx_l3slow_hwmod = {
188 .name = "l3_slow",
189 .class = &l3_hwmod_class,
190 .clkdm_name = "l3s_clkdm",
191 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
192 .masters = am33xx_l3_slow_masters,
193 .masters_cnt = ARRAY_SIZE(am33xx_l3_slow_masters),
194 .slaves = am33xx_l3_slow_slaves,
195 .slaves_cnt = ARRAY_SIZE(am33xx_l3_slow_slaves),
196 };
198 /* L4 PER -> DCAN0 */
199 static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
200 {
201 .pa_start = 0x481CC000,
202 .pa_end = 0x481CC000 + SZ_4K - 1,
203 .flags = ADDR_TYPE_RT
204 },
205 { }
206 };
208 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
209 .master = &am33xx_l4per_hwmod,
210 .slave = &am33xx_dcan0_hwmod,
211 .clk = "dcan0_ick",
212 .addr = am33xx_dcan0_addrs,
213 .user = OCP_USER_MPU | OCP_USER_SDMA,
214 };
216 /* L4 PER -> DCAN1 */
217 static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
218 {
219 .pa_start = 0x481D0000,
220 .pa_end = 0x481D0000 + SZ_4K - 1,
221 .flags = ADDR_TYPE_RT
222 },
223 { }
224 };
226 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
227 .master = &am33xx_l4per_hwmod,
228 .slave = &am33xx_dcan1_hwmod,
229 .clk = "dcan1_ick",
230 .addr = am33xx_dcan1_addrs,
231 .user = OCP_USER_MPU | OCP_USER_SDMA,
232 };
234 /* L4 PER -> GPIO2 */
235 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
236 {
237 .pa_start = 0x4804C000,
238 .pa_end = 0x4804C000 + SZ_4K - 1,
239 .flags = ADDR_TYPE_RT,
240 },
241 { }
242 };
244 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
245 .master = &am33xx_l4per_hwmod,
246 .slave = &am33xx_gpio1_hwmod,
247 .clk = "l4ls_gclk",
248 .addr = am33xx_gpio1_addrs,
249 .user = OCP_USER_MPU | OCP_USER_SDMA,
250 };
252 /* L4 PER -> GPIO3 */
253 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
254 {
255 .pa_start = 0x481AC000,
256 .pa_end = 0x481AC000 + SZ_4K - 1,
257 .flags = ADDR_TYPE_RT,
258 },
259 { }
260 };
262 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
263 .master = &am33xx_l4per_hwmod,
264 .slave = &am33xx_gpio2_hwmod,
265 .clk = "l4ls_gclk",
266 .addr = am33xx_gpio2_addrs,
267 .user = OCP_USER_MPU | OCP_USER_SDMA,
268 };
270 /* L4 PER -> GPIO4 */
271 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
272 {
273 .pa_start = 0x481AE000,
274 .pa_end = 0x481AE000 + SZ_4K - 1,
275 .flags = ADDR_TYPE_RT,
276 },
277 { }
278 };
280 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
281 .master = &am33xx_l4per_hwmod,
282 .slave = &am33xx_gpio3_hwmod,
283 .clk = "l4ls_gclk",
284 .addr = am33xx_gpio3_addrs,
285 .user = OCP_USER_MPU | OCP_USER_SDMA,
286 };
288 /* Master interfaces on the L4_PER interconnect */
289 static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = {
290 &am33xx_l4_per__dcan0,
291 &am33xx_l4_per__dcan1,
292 &am33xx_l4_per__gpio1,
293 &am33xx_l4_per__gpio2,
294 &am33xx_l4_per__gpio3,
295 };
297 /* Slave interfaces on the L4_PER interconnect */
298 static struct omap_hwmod_ocp_if *am33xx_l4_per_slaves[] = {
299 &am33xx_l3_slow__l4_per,
300 };
302 static struct omap_hwmod am33xx_l4per_hwmod = {
303 .name = "l4_per",
304 .class = &l4_hwmod_class,
305 .clkdm_name = "l4ls_clkdm",
306 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
307 .masters = am33xx_l4_per_masters,
308 .masters_cnt = ARRAY_SIZE(am33xx_l4_per_masters),
309 .slaves = am33xx_l4_per_slaves,
310 .slaves_cnt = ARRAY_SIZE(am33xx_l4_per_slaves),
311 };
313 /* L4 WKUP -> I2C1 */
314 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
315 {
316 .pa_start = 0x44E0B000,
317 .pa_end = 0x44E0B000 + SZ_4K - 1,
318 .flags = ADDR_TYPE_RT,
319 },
320 { }
321 };
323 static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = {
324 .master = &am33xx_l4wkup_hwmod,
325 .slave = &am33xx_i2c1_hwmod,
326 .addr = am33xx_i2c1_addr_space,
327 .user = OCP_USER_MPU,
328 };
330 /* L4 WKUP -> GPIO1 */
331 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
332 {
333 .pa_start = 0x44E07000,
334 .pa_end = 0x44E07000 + SZ_4K - 1,
335 .flags = ADDR_TYPE_RT,
336 },
337 { }
338 };
340 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
341 .master = &am33xx_l4wkup_hwmod,
342 .slave = &am33xx_gpio0_hwmod,
343 .clk = "l4ls_gclk",
344 .addr = am33xx_gpio0_addrs,
345 .user = OCP_USER_MPU | OCP_USER_SDMA,
346 };
348 /* Master interfaces on the L4_WKUP interconnect */
349 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = {
350 &am33xx_l4_wkup__gpio0,
351 };
352 /* Slave interfaces on the L4_WKUP interconnect */
353 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_slaves[] = {
354 &am33xx_l3_slow__l4_wkup,
355 };
357 static struct omap_hwmod am33xx_l4wkup_hwmod = {
358 .name = "l4_wkup",
359 .class = &l4_hwmod_class,
360 .clkdm_name = "l4_wkup_clkdm",
361 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
362 .masters = am33xx_l4_wkup_masters,
363 .masters_cnt = ARRAY_SIZE(am33xx_l4_wkup_masters),
364 .slaves = am33xx_l4_wkup_slaves,
365 .slaves_cnt = ARRAY_SIZE(am33xx_l4_wkup_slaves),
366 };
368 /* adc_tsc */
369 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
370 .rev_offs = 0x00,
371 .sysc_offs = 0x10,
372 .sysc_flags = SYSC_HAS_SIDLEMODE,
373 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
374 SIDLE_SMART_WKUP),
375 .sysc_fields = &omap_hwmod_sysc_type2,
376 };
378 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
379 .name = "adc_tsc",
380 .sysc = &am33xx_adc_tsc_sysc,
381 };
383 /* L4 WKUP -> ADC_TSC */
384 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
385 {
386 .pa_start = 0x44E0D000,
387 .pa_end = 0x44E0D000 + SZ_8K - 1,
388 .flags = ADDR_TYPE_RT
389 },
390 { }
391 };
393 static struct omap_hwmod_ocp_if am33xx_l4_wkup_adc_tsc = {
394 .master = &am33xx_l4wkup_hwmod,
395 .slave = &am33xx_adc_tsc_hwmod,
396 .clk = "adc_tsc_ick",
397 .addr = am33xx_adc_tsc_addrs,
398 .user = OCP_USER_MPU,
399 };
401 static struct omap_hwmod_ocp_if *am33xx_adc_tsc_slaves[] = {
402 &am33xx_l4_wkup_adc_tsc,
403 };
405 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
406 { .irq = 16 },
407 { .irq = -1 }
408 };
410 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
411 .name = "adc_tsc",
412 .class = &am33xx_adc_tsc_hwmod_class,
413 .clkdm_name = "l4_wkup_clkdm",
414 .mpu_irqs = am33xx_adc_tsc_irqs,
415 .main_clk = "adc_tsc_fck",
416 .prcm = {
417 .omap4 = {
418 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
419 .modulemode = MODULEMODE_SWCTRL,
420 },
421 },
422 .slaves = am33xx_adc_tsc_slaves,
423 .slaves_cnt = ARRAY_SIZE(am33xx_adc_tsc_slaves),
424 };
426 /* 'aes' class */
427 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
428 .name = "aes",
429 };
431 /* aes0 */
432 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
433 { .irq = 102 },
434 { .irq = -1 }
435 };
437 static struct omap_hwmod_dma_info am33xx_aes0_dma[] = {
438 { .dma_req = AM33XX_DMA_AESEIP36T0_DOUT },
439 { .dma_req = AM33XX_DMA_AESEIP36T0_DIN },
440 { .dma_req = -1 }
441 };
443 static struct omap_hwmod am33xx_aes0_hwmod = {
444 .name = "aes0",
445 .class = &am33xx_aes_hwmod_class,
446 .clkdm_name = "l3_clkdm",
447 .mpu_irqs = am33xx_aes0_irqs,
448 .sdma_reqs = am33xx_aes0_dma,
449 .main_clk = "aes0_fck",
450 .prcm = {
451 .omap4 = {
452 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
453 .modulemode = MODULEMODE_SWCTRL,
454 },
455 },
456 };
458 /* cefuse */
459 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
460 .name = "cefuse",
461 };
463 static struct omap_hwmod am33xx_cefuse_hwmod = {
464 .name = "cefuse",
465 .class = &am33xx_cefuse_hwmod_class,
466 .clkdm_name = "l4_cefuse_clkdm",
467 .main_clk = "cefuse_fck",
468 .prcm = {
469 .omap4 = {
470 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
471 .modulemode = MODULEMODE_SWCTRL,
472 },
473 },
474 };
476 /* clkdiv32k */
477 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
478 .name = "clkdiv32k",
479 };
481 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
482 .name = "clkdiv32k",
483 .class = &am33xx_clkdiv32k_hwmod_class,
484 .clkdm_name = "clk_24mhz_clkdm",
485 .main_clk = "clkdiv32k_ick",
486 .prcm = {
487 .omap4 = {
488 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
489 .modulemode = MODULEMODE_SWCTRL,
490 },
491 },
492 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
493 };
495 /* control */
496 static struct omap_hwmod_class am33xx_control_hwmod_class = {
497 .name = "control",
498 };
500 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
501 { .irq = 8 },
502 { .irq = -1 }
503 };
505 static struct omap_hwmod am33xx_control_hwmod = {
506 .name = "control",
507 .class = &am33xx_control_hwmod_class,
508 .clkdm_name = "l4_wkup_clkdm",
509 .mpu_irqs = am33xx_control_irqs,
510 .main_clk = "control_fck",
511 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
512 .prcm = {
513 .omap4 = {
514 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
515 .modulemode = MODULEMODE_SWCTRL,
516 },
517 },
518 };
520 /* cpgmac0 */
521 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
522 .rev_offs = 0x0,
523 .sysc_offs = 0x8,
524 .syss_offs = 0x4,
525 .rst_offs = 0x8,
526 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
527 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
528 MSTANDBY_NO),
529 .sysc_fields = &omap_hwmod_sysc_type3,
530 };
532 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
533 .name = "cpsw",
534 .sysc = &am33xx_cpgmac_sysc,
535 .reset = am33xx_cpgmac_reset,
536 };
538 /* Used by driver */
539 struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
540 /* cpsw ss */
541 {
542 .pa_start = 0x4A100000,
543 .pa_end = 0x4A100000 + SZ_2K - 1,
544 .flags = ADDR_MAP_ON_INIT,
545 },
546 /* cpsw wr */
547 {
548 .pa_start = 0x4A101200,
549 .pa_end = 0x4A101200 + SZ_256 - 1,
550 .flags = ADDR_TYPE_RT,
551 },
552 { }
553 };
555 struct omap_hwmod_ocp_if am33xx_l3_main__cpgmac0 = {
556 .master = &am33xx_l3_main_hwmod,
557 .slave = &am33xx_cpgmac0_hwmod,
558 .addr = am33xx_cpgmac0_addr_space,
559 .user = OCP_USER_MPU,
560 };
562 struct omap_hwmod_addr_space am33xx_cpsw_sl1_addr_space[] = {
563 /* cpsw sl1 */
564 {
565 .pa_start = 0x4A100D84,
566 .pa_end = 0x4A100D84 + SZ_32 - 1,
567 .flags = ADDR_TYPE_RT,
568 },
569 { }
570 };
572 struct omap_hwmod_ocp_if am33xx_l3_main__cpsw_sl1 = {
573 .master = &am33xx_l3_main_hwmod,
574 .slave = &am33xx_cpgmac0_hwmod,
575 .addr = am33xx_cpsw_sl1_addr_space,
576 .user = OCP_USER_MPU,
577 };
579 struct omap_hwmod_addr_space am33xx_cpsw_sl2_addr_space[] = {
580 /* cpsw sl2 */
581 {
582 .pa_start = 0x4A100DC4,
583 .pa_end = 0x4A100DC4 + SZ_32 - 1,
584 .flags = ADDR_TYPE_RT,
585 },
586 { }
587 };
589 struct omap_hwmod_ocp_if am33xx_l3_main__cpsw_sl2 = {
590 .master = &am33xx_l3_main_hwmod,
591 .slave = &am33xx_cpgmac0_hwmod,
592 .addr = am33xx_cpsw_sl2_addr_space,
593 .user = OCP_USER_MPU,
594 };
596 struct omap_hwmod_addr_space am33xx_cpsw_cpdma_addr_space[] = {
597 /* cpsw cpdma */
598 {
599 .pa_start = 0x4A100814,
600 .pa_end = 0x4A100814 + SZ_32 - 1,
601 .flags = ADDR_TYPE_RT,
602 },
603 { }
604 };
606 struct omap_hwmod_ocp_if am33xx_l3_main__cpsw_cpdma = {
607 .master = &am33xx_l3_main_hwmod,
608 .slave = &am33xx_cpgmac0_hwmod,
609 .addr = am33xx_cpsw_cpdma_addr_space,
610 .user = OCP_USER_MPU,
611 };
613 static struct omap_hwmod_ocp_if *am33xx_cpgmac0_slaves[] = {
614 &am33xx_l3_main__cpgmac0,
615 &am33xx_l3_main__cpsw_sl1,
616 &am33xx_l3_main__cpsw_sl2,
617 &am33xx_l3_main__cpsw_cpdma,
618 };
620 static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
621 { .name = "c0_rx_thresh_pend", .irq = 40 },
622 { .name = "c0_rx_pend", .irq = 93 },
623 { .name = "c0_tx_pend", .irq = 94 },
624 { .name = "c0_misc_pend", .irq = 43 },
625 { .irq = -1 }
626 };
628 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
629 .name = "cpgmac0",
630 .class = &am33xx_cpgmac0_hwmod_class,
631 .clkdm_name = "cpsw_125mhz_clkdm",
632 .mpu_irqs = am33xx_cpgmac0_irqs,
633 .main_clk = "cpgmac0_ick",
634 .prcm = {
635 .omap4 = {
636 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
637 .modulemode = MODULEMODE_SWCTRL,
638 },
639 },
640 .slaves = am33xx_cpgmac0_slaves,
641 .slaves_cnt = ARRAY_SIZE(am33xx_cpgmac0_slaves),
642 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
643 HWMOD_SWSUP_RESET_BEFORE_IDLE),
644 };
646 /* mdio class */
647 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
648 .name = "davinci_mdio",
649 };
651 struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
652 {
653 .pa_start = 0x4A101000,
654 .pa_end = 0x4A101000 + SZ_256 - 1,
655 .flags = ADDR_MAP_ON_INIT,
656 },
657 { }
658 };
660 struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
661 .master = &am33xx_cpgmac0_hwmod,
662 .slave = &am33xx_mdio_hwmod,
663 .addr = am33xx_mdio_addr_space,
664 .user = OCP_USER_MPU,
665 };
667 static struct omap_hwmod_ocp_if *am33xx_mdio_slaves[] = {
668 &am33xx_cpgmac0__mdio,
669 };
671 static struct omap_hwmod am33xx_mdio_hwmod = {
672 .name = "mdio",
673 .class = &am33xx_mdio_hwmod_class,
674 .clkdm_name = "cpsw_125mhz_clkdm",
675 .main_clk = "cpgmac0_ick",
676 .slaves = am33xx_mdio_slaves,
677 .slaves_cnt = ARRAY_SIZE(am33xx_mdio_slaves),
678 };
680 /* 'dcan' class */
681 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
682 .name = "d_can",
683 };
685 /* dcan0 slave ports */
686 static struct omap_hwmod_ocp_if *am33xx_dcan0_slaves[] = {
687 &am33xx_l4_per__dcan0,
688 };
690 /* dcan0 */
691 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
692 { .name = "d_can_ms", .irq = 52 },
693 { .name = "d_can_mo", .irq = 53 },
694 { .irq = -1 }
695 };
697 static struct omap_hwmod am33xx_dcan0_hwmod = {
698 .name = "d_can0",
699 .class = &am33xx_dcan_hwmod_class,
700 .clkdm_name = "l4ls_clkdm",
701 .mpu_irqs = am33xx_dcan0_irqs,
702 .main_clk = "dcan0_fck",
703 .prcm = {
704 .omap4 = {
705 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
706 .modulemode = MODULEMODE_SWCTRL,
707 },
708 },
709 .slaves = am33xx_dcan0_slaves,
710 .slaves_cnt = ARRAY_SIZE(am33xx_dcan0_slaves),
711 };
713 /* dcan1 slave ports */
714 static struct omap_hwmod_ocp_if *am33xx_dcan1_slaves[] = {
715 &am33xx_l4_per__dcan1,
716 };
718 /* dcan1 */
719 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
720 { .name = "d_can_ms", .irq = 55 },
721 { .name = "d_can_mo", .irq = 56 },
722 { .irq = -1 }
723 };
725 static struct omap_hwmod am33xx_dcan1_hwmod = {
726 .name = "d_can1",
727 .class = &am33xx_dcan_hwmod_class,
728 .clkdm_name = "l4ls_clkdm",
729 .mpu_irqs = am33xx_dcan1_irqs,
730 .main_clk = "dcan1_fck",
731 .prcm = {
732 .omap4 = {
733 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
734 .modulemode = MODULEMODE_SWCTRL,
735 },
736 },
737 .slaves = am33xx_dcan1_slaves,
738 .slaves_cnt = ARRAY_SIZE(am33xx_dcan1_slaves),
739 };
741 /* debugss */
742 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
743 .name = "debugss",
744 };
746 static struct omap_hwmod am33xx_debugss_hwmod = {
747 .name = "debugss",
748 .class = &am33xx_debugss_hwmod_class,
749 .clkdm_name = "l3_aon_clkdm",
750 .main_clk = "debugss_ick",
751 #ifdef CONFIG_DEBUG_JTAG_ENABLE
752 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
753 #endif
754 .prcm = {
755 .omap4 = {
756 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
757 .modulemode = MODULEMODE_SWCTRL,
758 },
759 },
760 };
762 /* elm */
763 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
764 .rev_offs = 0x0000,
765 .sysc_offs = 0x0010,
766 .syss_offs = 0x0014,
767 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
768 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
769 SYSS_HAS_RESET_STATUS),
770 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
771 .sysc_fields = &omap_hwmod_sysc_type1,
772 };
774 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
775 .name = "elm",
776 .sysc = &am33xx_elm_sysc,
777 };
779 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
780 { .irq = 4 },
781 { .irq = -1 }
782 };
784 struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
785 {
786 .pa_start = 0x48080000,
787 .pa_end = 0x48080000 + SZ_8K - 1,
788 .flags = ADDR_TYPE_RT
789 },
790 { }
791 };
793 struct omap_hwmod_ocp_if am33xx_l4_core__elm = {
794 .master = &am33xx_l4per_hwmod,
795 .slave = &am33xx_elm_hwmod,
796 .addr = am33xx_elm_addr_space,
797 .user = OCP_USER_MPU,
798 };
800 static struct omap_hwmod_ocp_if *am33xx_elm_slaves[] = {
801 &am33xx_l4_core__elm,
802 };
804 static struct omap_hwmod am33xx_elm_hwmod = {
805 .name = "elm",
806 .class = &am33xx_elm_hwmod_class,
807 .clkdm_name = "l4ls_clkdm",
808 .mpu_irqs = am33xx_elm_irqs,
809 .main_clk = "elm_fck",
810 .prcm = {
811 .omap4 = {
812 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
813 .modulemode = MODULEMODE_SWCTRL,
814 },
815 },
816 .slaves = am33xx_elm_slaves,
817 .slaves_cnt = ARRAY_SIZE(am33xx_elm_slaves),
818 };
820 /* emif_fw */
821 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
822 .name = "emif_fw",
823 };
825 static struct omap_hwmod am33xx_emif_fw_hwmod = {
826 .name = "emif_fw",
827 .class = &am33xx_emif_fw_hwmod_class,
828 .clkdm_name = "l4fw_clkdm",
829 .main_clk = "emif_fw_fck",
830 .flags = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
831 .prcm = {
832 .omap4 = {
833 .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
834 .modulemode = MODULEMODE_SWCTRL,
835 },
836 },
837 };
839 /* 'epwmss' class */
840 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
841 .rev_offs = 0x0,
842 .sysc_offs = 0x4,
843 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
844 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
845 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
846 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
847 .sysc_fields = &omap_hwmod_sysc_type2,
848 };
850 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
851 .name = "epwmss",
852 .sysc = &am33xx_epwmss_sysc,
853 };
855 /* ehrpwm0 */
856 static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
857 { .irq = 86 },
858 { .irq = 58 },
859 { .irq = -1 }
860 };
862 struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
863 /*
864 * Splitting the resources to handle access of PWMSS config space and module
865 * specific part independently
866 */
867 {
868 .pa_start = 0x48300000,
869 .pa_end = 0x48300000 + SZ_16 - 1,
870 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT
871 },
872 {
873 .pa_start = 0x48300000 + SZ_512,
874 .pa_end = 0x48300000 + SZ_512 + SZ_256 - 1,
875 .flags = ADDR_TYPE_RT
876 },
877 { }
878 };
880 struct omap_hwmod_ocp_if am33xx_l4_core__ehrpwm0 = {
881 .master = &am33xx_l4per_hwmod,
882 .slave = &am33xx_ehrpwm0_hwmod,
883 .addr = am33xx_ehrpwm0_addr_space,
884 .user = OCP_USER_MPU,
885 };
887 static struct omap_hwmod_ocp_if *am33xx_ehrpwm0_slaves[] = {
888 &am33xx_l4_core__ehrpwm0,
889 };
891 static struct omap_hwmod_opt_clk ehrpwm0_opt_clks[] = {
892 { .role = "tbclk", .clk = "ehrpwm0_tbclk" },
893 };
895 static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
896 .name = "ehrpwm.0",
897 .mpu_irqs = am33xx_ehrpwm0_irqs,
898 .class = &am33xx_epwmss_hwmod_class,
899 .main_clk = "epwmss0_fck",
900 .clkdm_name = "l4ls_clkdm",
901 .prcm = {
902 .omap4 = {
903 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
904 .modulemode = MODULEMODE_SWCTRL,
905 },
906 },
907 .slaves = am33xx_ehrpwm0_slaves,
908 .slaves_cnt = ARRAY_SIZE(am33xx_ehrpwm0_slaves),
909 .opt_clks = ehrpwm0_opt_clks,
910 .opt_clks_cnt = ARRAY_SIZE(ehrpwm0_opt_clks),
911 };
913 /* ehrpwm1 */
914 static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
915 { .irq = 87 },
916 { .irq = 59 },
917 { .irq = -1 }
918 };
920 struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
921 /*
922 * Splitting the resources to handle access of PWMSS config space and module
923 * specific part independently
924 */
925 {
926 .pa_start = 0x48302000,
927 .pa_end = 0x48302000 + SZ_16 - 1,
928 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT
929 },
930 {
931 .pa_start = 0x48302000 + SZ_512,
932 .pa_end = 0x48302000 + SZ_512 + SZ_256 - 1,
933 .flags = ADDR_TYPE_RT
934 },
935 { }
936 };
938 struct omap_hwmod_ocp_if am33xx_l4_core__ehrpwm1 = {
939 .master = &am33xx_l4per_hwmod,
940 .slave = &am33xx_ehrpwm1_hwmod,
941 .addr = am33xx_ehrpwm1_addr_space,
942 .user = OCP_USER_MPU,
943 };
945 static struct omap_hwmod_ocp_if *am33xx_ehrpwm1_slaves[] = {
946 &am33xx_l4_core__ehrpwm1,
947 };
949 static struct omap_hwmod_opt_clk ehrpwm1_opt_clks[] = {
950 { .role = "tbclk", .clk = "ehrpwm1_tbclk" },
951 };
953 static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
954 .name = "ehrpwm.1",
955 .mpu_irqs = am33xx_ehrpwm1_irqs,
956 .class = &am33xx_epwmss_hwmod_class,
957 .main_clk = "epwmss1_fck",
958 .clkdm_name = "l4ls_clkdm",
959 .prcm = {
960 .omap4 = {
961 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
962 .modulemode = MODULEMODE_SWCTRL,
963 },
964 },
965 .slaves = am33xx_ehrpwm1_slaves,
966 .slaves_cnt = ARRAY_SIZE(am33xx_ehrpwm1_slaves),
967 .opt_clks = ehrpwm1_opt_clks,
968 .opt_clks_cnt = ARRAY_SIZE(ehrpwm1_opt_clks),
969 };
971 /* ehrpwm2 */
972 static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
973 { .irq = 39 },
974 { .irq = 60 },
975 { .irq = -1 }
976 };
978 struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
979 /*
980 * Splitting the resources to handle access of PWMSS config space and module
981 * specific part independently
982 */
983 {
984 .pa_start = 0x48304000,
985 .pa_end = 0x48304000 + SZ_16 - 1,
986 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT
987 },
988 {
989 .pa_start = 0x48304000 + SZ_512,
990 .pa_end = 0x48304000 + SZ_512 + SZ_256 - 1,
991 .flags = ADDR_TYPE_RT
992 },
993 { }
994 };
996 struct omap_hwmod_ocp_if am33xx_l4_core__ehrpwm2 = {
997 .master = &am33xx_l4per_hwmod,
998 .slave = &am33xx_ehrpwm2_hwmod,
999 .addr = am33xx_ehrpwm2_addr_space,
1000 .user = OCP_USER_MPU,
1001 };
1003 static struct omap_hwmod_ocp_if *am33xx_ehrpwm2_slaves[] = {
1004 &am33xx_l4_core__ehrpwm2,
1005 };
1007 static struct omap_hwmod_opt_clk ehrpwm2_opt_clks[] = {
1008 { .role = "tbclk", .clk = "ehrpwm2_tbclk" },
1009 };
1011 static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
1012 .name = "ehrpwm.2",
1013 .mpu_irqs = am33xx_ehrpwm2_irqs,
1014 .class = &am33xx_epwmss_hwmod_class,
1015 .main_clk = "epwmss2_fck",
1016 .clkdm_name = "l4ls_clkdm",
1017 .prcm = {
1018 .omap4 = {
1019 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
1020 .modulemode = MODULEMODE_SWCTRL,
1021 },
1022 },
1023 .slaves = am33xx_ehrpwm2_slaves,
1024 .slaves_cnt = ARRAY_SIZE(am33xx_ehrpwm2_slaves),
1025 .opt_clks = ehrpwm2_opt_clks,
1026 .opt_clks_cnt = ARRAY_SIZE(ehrpwm2_opt_clks),
1027 };
1029 /* ecap0 */
1030 static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
1031 { .irq = 31 },
1032 { .irq = -1 }
1033 };
1035 struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
1036 /*
1037 * Splitting the resources to handle access of PWMSS config space and module
1038 * specific part independently
1039 */
1040 {
1041 .pa_start = 0x48300000,
1042 .pa_end = 0x48300000 + SZ_16 - 1,
1043 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT
1044 },
1045 {
1046 .pa_start = 0x48300000 + SZ_256,
1047 .pa_end = 0x48300000 + SZ_256 + SZ_256 - 1,
1048 .flags = ADDR_TYPE_RT
1049 },
1050 { }
1051 };
1053 struct omap_hwmod_ocp_if am33xx_l4_core__ecap0 = {
1054 .master = &am33xx_l4per_hwmod,
1055 .slave = &am33xx_ecap0_hwmod,
1056 .addr = am33xx_ecap0_addr_space,
1057 .user = OCP_USER_MPU,
1058 };
1060 static struct omap_hwmod_ocp_if *am33xx_ecap0_slaves[] = {
1061 &am33xx_l4_core__ecap0,
1062 };
1064 static struct omap_hwmod am33xx_ecap0_hwmod = {
1065 .name = "ecap.0",
1066 .mpu_irqs = am33xx_ecap0_irqs,
1067 .class = &am33xx_epwmss_hwmod_class,
1068 .main_clk = "epwmss0_fck",
1069 .clkdm_name = "l4ls_clkdm",
1070 .prcm = {
1071 .omap4 = {
1072 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
1073 .modulemode = MODULEMODE_SWCTRL,
1074 },
1075 },
1076 .slaves = am33xx_ecap0_slaves,
1077 .slaves_cnt = ARRAY_SIZE(am33xx_ecap0_slaves),
1078 };
1080 /* ecap1 */
1081 static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
1082 { .irq = 47 },
1083 { .irq = -1 }
1084 };
1086 struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
1087 /*
1088 * Splitting the resources to handle access of PWMSS config space and module
1089 * specific part independently
1090 */
1091 {
1092 .pa_start = 0x48302000,
1093 .pa_end = 0x48302000 + SZ_16 - 1,
1094 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT
1095 },
1096 {
1097 .pa_start = 0x48302000 + SZ_256,
1098 .pa_end = 0x48302000 + SZ_256 + SZ_256 - 1,
1099 .flags = ADDR_TYPE_RT
1100 },
1101 { }
1102 };
1104 struct omap_hwmod_ocp_if am33xx_l4_core__ecap1 = {
1105 .master = &am33xx_l4per_hwmod,
1106 .slave = &am33xx_ecap1_hwmod,
1107 .addr = am33xx_ecap1_addr_space,
1108 .user = OCP_USER_MPU,
1109 };
1111 static struct omap_hwmod_ocp_if *am33xx_ecap1_slaves[] = {
1112 &am33xx_l4_core__ecap1,
1113 };
1115 static struct omap_hwmod am33xx_ecap1_hwmod = {
1116 .name = "ecap.1",
1117 .mpu_irqs = am33xx_ecap1_irqs,
1118 .class = &am33xx_epwmss_hwmod_class,
1119 .main_clk = "epwmss1_fck",
1120 .clkdm_name = "l4ls_clkdm",
1121 .prcm = {
1122 .omap4 = {
1123 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
1124 .modulemode = MODULEMODE_SWCTRL,
1125 },
1126 },
1127 .slaves = am33xx_ecap1_slaves,
1128 .slaves_cnt = ARRAY_SIZE(am33xx_ecap1_slaves),
1129 };
1131 /* ecap2 */
1132 static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
1133 { .irq = 61 },
1134 { .irq = -1 }
1135 };
1137 struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
1138 /*
1139 * Splitting the resources to handle access of PWMSS config space and module
1140 * specific part independently
1141 */
1142 {
1143 .pa_start = 0x48304000,
1144 .pa_end = 0x48304000 + SZ_16 - 1,
1145 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT
1146 },
1147 {
1148 .pa_start = 0x48304000 + SZ_256,
1149 .pa_end = 0x48304000 + SZ_256 + SZ_256 - 1,
1150 .flags = ADDR_TYPE_RT
1151 },
1152 { }
1153 };
1155 struct omap_hwmod_ocp_if am33xx_l4_core__ecap2 = {
1156 .master = &am33xx_l4per_hwmod,
1157 .slave = &am33xx_ecap2_hwmod,
1158 .addr = am33xx_ecap2_addr_space,
1159 .user = OCP_USER_MPU,
1160 };
1162 static struct omap_hwmod_ocp_if *am33xx_ecap2_slaves[] = {
1163 &am33xx_l4_core__ecap2,
1164 };
1166 static struct omap_hwmod am33xx_ecap2_hwmod = {
1167 .name = "ecap.2",
1168 .mpu_irqs = am33xx_ecap2_irqs,
1169 .class = &am33xx_epwmss_hwmod_class,
1170 .clkdm_name = "l4ls_clkdm",
1171 .main_clk = "epwmss2_fck",
1172 .prcm = {
1173 .omap4 = {
1174 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
1175 .modulemode = MODULEMODE_SWCTRL,
1176 },
1177 },
1178 .slaves = am33xx_ecap2_slaves,
1179 .slaves_cnt = ARRAY_SIZE(am33xx_ecap2_slaves),
1180 };
1182 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
1183 .rev_offs = 0x0000,
1184 .sysc_offs = 0x0010,
1185 .syss_offs = 0x0114,
1186 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1187 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1188 SYSS_HAS_RESET_STATUS),
1189 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1190 SIDLE_SMART_WKUP),
1191 .sysc_fields = &omap_hwmod_sysc_type1,
1192 };
1194 /* 'gpio' class */
1195 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
1196 .name = "gpio",
1197 .sysc = &am33xx_gpio_sysc,
1198 .rev = 2,
1199 };
1201 static struct omap_gpio_dev_attr gpio_dev_attr = {
1202 .bank_width = 32,
1203 .dbck_flag = true,
1204 };
1206 /* gpio0 */
1207 static struct omap_hwmod_ocp_if *am33xx_gpio0_slaves[] = {
1208 &am33xx_l4_wkup__gpio0,
1209 };
1211 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
1212 { .role = "dbclk", .clk = "gpio0_dbclk" },
1213 };
1215 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
1216 { .irq = 96 },
1217 { .irq = -1 }
1218 };
1220 static struct omap_hwmod am33xx_gpio0_hwmod = {
1221 .name = "gpio1",
1222 .class = &am33xx_gpio_hwmod_class,
1223 .clkdm_name = "l4_wkup_clkdm",
1224 .mpu_irqs = am33xx_gpio0_irqs,
1225 .main_clk = "gpio0_ick",
1226 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET | HWMOD_INIT_NO_RESET,
1227 .prcm = {
1228 .omap4 = {
1229 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
1230 .modulemode = MODULEMODE_SWCTRL,
1231 },
1232 },
1233 .opt_clks = gpio0_opt_clks,
1234 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
1235 .dev_attr = &gpio_dev_attr,
1236 .slaves = am33xx_gpio0_slaves,
1237 .slaves_cnt = ARRAY_SIZE(am33xx_gpio0_slaves),
1238 };
1240 /* gpio1 */
1241 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
1242 { .irq = 98 },
1243 { .irq = -1 }
1244 };
1246 static struct omap_hwmod_ocp_if *am33xx_gpio1_slaves[] = {
1247 &am33xx_l4_per__gpio1,
1248 };
1250 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1251 { .role = "dbclk", .clk = "gpio1_dbclk" },
1252 };
1254 static struct omap_hwmod am33xx_gpio1_hwmod = {
1255 .name = "gpio2",
1256 .class = &am33xx_gpio_hwmod_class,
1257 .clkdm_name = "l4ls_clkdm",
1258 .mpu_irqs = am33xx_gpio1_irqs,
1259 .main_clk = "gpio1_ick",
1260 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1261 .prcm = {
1262 .omap4 = {
1263 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
1264 .modulemode = MODULEMODE_SWCTRL,
1265 },
1266 },
1267 .opt_clks = gpio1_opt_clks,
1268 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1269 .dev_attr = &gpio_dev_attr,
1270 .slaves = am33xx_gpio1_slaves,
1271 .slaves_cnt = ARRAY_SIZE(am33xx_gpio1_slaves),
1272 };
1274 /* gpio2 */
1275 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
1276 { .irq = 32 },
1277 { .irq = -1 }
1278 };
1280 static struct omap_hwmod_ocp_if *am33xx_gpio2_slaves[] = {
1281 &am33xx_l4_per__gpio2,
1282 };
1284 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1285 { .role = "dbclk", .clk = "gpio2_dbclk" },
1286 };
1288 static struct omap_hwmod am33xx_gpio2_hwmod = {
1289 .name = "gpio3",
1290 .class = &am33xx_gpio_hwmod_class,
1291 .clkdm_name = "l4ls_clkdm",
1292 .mpu_irqs = am33xx_gpio2_irqs,
1293 .main_clk = "gpio2_ick",
1294 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1295 .prcm = {
1296 .omap4 = {
1297 .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
1298 .modulemode = MODULEMODE_SWCTRL,
1299 },
1300 },
1301 .opt_clks = gpio2_opt_clks,
1302 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1303 .dev_attr = &gpio_dev_attr,
1304 .slaves = am33xx_gpio2_slaves,
1305 .slaves_cnt = ARRAY_SIZE(am33xx_gpio2_slaves),
1306 };
1308 /* gpio3 */
1309 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
1310 { .irq = 62 },
1311 { .irq = -1 }
1312 };
1314 static struct omap_hwmod_ocp_if *am33xx_gpio3_slaves[] = {
1315 &am33xx_l4_per__gpio3,
1316 };
1318 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1319 { .role = "dbclk", .clk = "gpio3_dbclk" },
1320 };
1322 static struct omap_hwmod am33xx_gpio3_hwmod = {
1323 .name = "gpio4",
1324 .class = &am33xx_gpio_hwmod_class,
1325 .clkdm_name = "l4ls_clkdm",
1326 .mpu_irqs = am33xx_gpio3_irqs,
1327 .main_clk = "gpio3_ick",
1328 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1329 .prcm = {
1330 .omap4 = {
1331 .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
1332 .modulemode = MODULEMODE_SWCTRL,
1333 },
1334 },
1335 .opt_clks = gpio3_opt_clks,
1336 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1337 .dev_attr = &gpio_dev_attr,
1338 .slaves = am33xx_gpio3_slaves,
1339 .slaves_cnt = ARRAY_SIZE(am33xx_gpio3_slaves),
1340 };
1342 /* gpmc */
1343 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
1344 .rev_offs = 0x0,
1345 .sysc_offs = 0x10,
1346 .syss_offs = 0x14,
1347 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1348 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1349 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1350 .sysc_fields = &omap_hwmod_sysc_type1,
1351 };
1353 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
1354 .name = "gpmc",
1355 .sysc = &gpmc_sysc,
1356 };
1358 struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
1359 {
1360 .pa_start = 0x50000000,
1361 .pa_end = 0x50000000 + SZ_8K - 1,
1362 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
1363 },
1364 { }
1365 };
1367 struct omap_hwmod_ocp_if am33xx_l3_main__gpmc = {
1368 .master = &am33xx_l3_main_hwmod,
1369 .slave = &am33xx_gpmc_hwmod,
1370 .addr = am33xx_gpmc_addr_space,
1371 .user = OCP_USER_MPU,
1372 };
1374 static struct omap_hwmod_ocp_if *am33xx_gpmc_slaves[] = {
1375 &am33xx_l3_main__gpmc,
1376 };
1378 static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
1379 { .irq = 100 },
1380 { .irq = -1 }
1381 };
1383 static struct omap_hwmod am33xx_gpmc_hwmod = {
1384 .name = "gpmc",
1385 .class = &am33xx_gpmc_hwmod_class,
1386 .clkdm_name = "l3s_clkdm",
1387 .mpu_irqs = am33xx_gpmc_irqs,
1388 .main_clk = "gpmc_fck",
1389 .prcm = {
1390 .omap4 = {
1391 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
1392 .modulemode = MODULEMODE_SWCTRL,
1393 },
1394 },
1395 .slaves = am33xx_gpmc_slaves,
1396 .slaves_cnt = ARRAY_SIZE(am33xx_gpmc_slaves),
1397 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
1398 HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1399 };
1401 /* 'i2c' class */
1402 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
1403 .sysc_offs = 0x0010,
1404 .syss_offs = 0x0090,
1405 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1406 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1407 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1408 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1409 SIDLE_SMART_WKUP),
1410 .sysc_fields = &omap_hwmod_sysc_type1,
1411 };
1413 static struct omap_i2c_dev_attr i2c_dev_attr = {
1414 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1415 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1416 };
1418 static struct omap_hwmod_class i2c_class = {
1419 .name = "i2c",
1420 .sysc = &am33xx_i2c_sysc,
1421 .rev = OMAP_I2C_IP_VERSION_2,
1422 .reset = &omap_i2c_reset,
1423 };
1425 /* I2C1 */
1426 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1427 { .irq = 70 },
1428 { .irq = -1 }
1429 };
1431 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
1432 { .name = "tx", .dma_req = 0, },
1433 { .name = "rx", .dma_req = 0, },
1434 { .dma_req = -1 }
1435 };
1437 static struct omap_hwmod_ocp_if *am33xx_i2c1_slaves[] = {
1438 &am33xx_l4_wkup_i2c1,
1439 };
1441 static struct omap_hwmod am33xx_i2c1_hwmod = {
1442 .name = "i2c1",
1443 .class = &i2c_class,
1444 .clkdm_name = "l4_wkup_clkdm",
1445 .mpu_irqs = i2c1_mpu_irqs,
1446 .main_clk = "i2c1_fck",
1447 .sdma_reqs = i2c1_edma_reqs,
1448 .flags = HWMOD_16BIT_REG,
1449 .prcm = {
1450 .omap4 = {
1451 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
1452 .modulemode = MODULEMODE_SWCTRL,
1453 },
1454 },
1455 .dev_attr = &i2c_dev_attr,
1456 .slaves = am33xx_i2c1_slaves,
1457 .slaves_cnt = ARRAY_SIZE(am33xx_i2c1_slaves),
1458 };
1460 /* i2c2 */
1461 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
1462 {
1463 .pa_start = 0x4802A000,
1464 .pa_end = 0x4802A000 + SZ_4K - 1,
1465 .flags = ADDR_TYPE_RT,
1466 },
1467 { }
1468 };
1470 static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = {
1471 .master = &am33xx_l4per_hwmod,
1472 .slave = &am33xx_i2c2_hwmod,
1473 .addr = am33xx_i2c2_addr_space,
1474 .user = OCP_USER_MPU,
1475 };
1477 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1478 { .irq = 71 },
1479 { .irq = -1 }
1480 };
1482 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
1483 { .name = "tx", .dma_req = 0, },
1484 { .name = "rx", .dma_req = 0, },
1485 { .dma_req = -1 }
1486 };
1488 static struct omap_hwmod_ocp_if *am33xx_i2c2_slaves[] = {
1489 &am335_l4_per_i2c2,
1490 };
1492 static struct omap_hwmod am33xx_i2c2_hwmod = {
1493 .name = "i2c2",
1494 .class = &i2c_class,
1495 .clkdm_name = "l4ls_clkdm",
1496 .mpu_irqs = i2c2_mpu_irqs,
1497 .main_clk = "i2c2_fck",
1498 .sdma_reqs = i2c2_edma_reqs,
1499 .flags = HWMOD_16BIT_REG,
1500 .prcm = {
1501 .omap4 = {
1502 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
1503 .modulemode = MODULEMODE_SWCTRL,
1504 },
1505 },
1506 .dev_attr = &i2c_dev_attr,
1507 .slaves = am33xx_i2c2_slaves,
1508 .slaves_cnt = ARRAY_SIZE(am33xx_i2c2_slaves),
1509 };
1511 /* I2C3 */
1512 static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
1513 {
1514 .pa_start = 0x4819C000,
1515 .pa_end = 0x4819C000 + SZ_4K - 1,
1516 .flags = ADDR_TYPE_RT
1517 },
1518 { }
1519 };
1521 static struct omap_hwmod_ocp_if am335_l4_per_i2c3 = {
1522 .master = &am33xx_l4per_hwmod,
1523 .slave = &am33xx_i2c3_hwmod,
1524 .addr = am33xx_i2c3_addr_space,
1525 .user = OCP_USER_MPU,
1526 };
1528 static struct omap_hwmod_ocp_if *am33xx_i2c3_slaves[] = {
1529 &am335_l4_per_i2c3,
1530 };
1532 static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
1533 { .name = "tx", .dma_req = 0, },
1534 { .name = "rx", .dma_req = 0, },
1535 { .dma_req = -1 }
1536 };
1538 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1539 { .irq = 30 },
1540 { .irq = -1 }
1541 };
1543 static struct omap_hwmod am33xx_i2c3_hwmod = {
1544 .name = "i2c3",
1545 .class = &i2c_class,
1546 .clkdm_name = "l4ls_clkdm",
1547 .mpu_irqs = i2c3_mpu_irqs,
1548 .main_clk = "i2c3_fck",
1549 .sdma_reqs = i2c3_edma_reqs,
1550 .flags = HWMOD_16BIT_REG,
1551 .prcm = {
1552 .omap4 = {
1553 .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
1554 .modulemode = MODULEMODE_SWCTRL,
1555 },
1556 },
1557 .dev_attr = &i2c_dev_attr,
1558 .slaves = am33xx_i2c3_slaves,
1559 .slaves_cnt = ARRAY_SIZE(am33xx_i2c3_slaves),
1560 };
1563 /* ieee5000 */
1564 static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = {
1565 .name = "ieee5000",
1566 };
1568 static struct omap_hwmod am33xx_ieee5000_hwmod = {
1569 .name = "ieee5000",
1570 .class = &am33xx_ieee5000_hwmod_class,
1571 .clkdm_name = "l3s_clkdm",
1572 .main_clk = "ieee5000_fck",
1573 .prcm = {
1574 .omap4 = {
1575 .clkctrl_offs = AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET,
1576 .modulemode = MODULEMODE_SWCTRL,
1577 },
1578 },
1579 };
1582 /* 'l3' class */
1583 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
1584 .name = "l3",
1585 };
1587 /* l4_hs */
1588 static struct omap_hwmod am33xx_l4_hs_hwmod = {
1589 .name = "l4_hs",
1590 .class = &am33xx_l3_hwmod_class,
1591 .clkdm_name = "l4hs_clkdm",
1592 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1593 .prcm = {
1594 .omap4 = {
1595 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
1596 .modulemode = MODULEMODE_SWCTRL,
1597 },
1598 },
1599 };
1601 /* l3_instr */
1602 static struct omap_hwmod am33xx_l3_instr_hwmod = {
1603 .name = "l3_instr",
1604 .class = &am33xx_l3_hwmod_class,
1605 .clkdm_name = "l3_clkdm",
1606 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1607 .prcm = {
1608 .omap4 = {
1609 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
1610 .modulemode = MODULEMODE_SWCTRL,
1611 },
1612 },
1613 };
1615 /* l3_main */
1616 static struct omap_hwmod am33xx_l3_main_hwmod = {
1617 .name = "l3_main",
1618 .class = &am33xx_l3_hwmod_class,
1619 .clkdm_name = "l3_clkdm",
1620 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1621 .prcm = {
1622 .omap4 = {
1623 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
1624 .modulemode = MODULEMODE_SWCTRL,
1625 },
1626 },
1627 };
1629 /* 'l4fw' class */
1630 static struct omap_hwmod_class am33xx_l4fw_hwmod_class = {
1631 .name = "l4fw",
1632 };
1634 /* l4fw */
1635 static struct omap_hwmod am33xx_l4fw_hwmod = {
1636 .name = "l4fw",
1637 .class = &am33xx_l4fw_hwmod_class,
1638 .clkdm_name = "l4fw_clkdm",
1639 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1640 .prcm = {
1641 .omap4 = {
1642 .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
1643 .modulemode = MODULEMODE_SWCTRL,
1644 },
1645 },
1646 };
1648 /* 'l4ls' class */
1649 static struct omap_hwmod_class am33xx_l4ls_hwmod_class = {
1650 .name = "l4ls",
1651 };
1653 /* l4ls */
1654 static struct omap_hwmod am33xx_l4ls_hwmod = {
1655 .name = "l4ls",
1656 .class = &am33xx_l4ls_hwmod_class,
1657 .clkdm_name = "l4ls_clkdm",
1658 .main_clk = "l4ls_gclk",
1659 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1660 .prcm = {
1661 .omap4 = {
1662 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
1663 .modulemode = MODULEMODE_SWCTRL,
1664 },
1665 },
1666 };
1668 /* lcdc */
1669 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
1670 .rev_offs = 0x0,
1671 .sysc_offs = 0x54,
1672 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
1673 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1674 .sysc_fields = &omap_hwmod_sysc_type2,
1675 };
1677 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1678 .name = "lcdc",
1679 .sysc = &lcdc_sysc,
1680 };
1682 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1683 { .irq = 36 },
1684 { .irq = -1 }
1685 };
1687 struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
1688 {
1689 .pa_start = 0x4830E000,
1690 .pa_end = 0x4830E000 + SZ_8K - 1,
1691 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
1692 },
1693 { }
1694 };
1696 struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
1697 .master = &am33xx_l3_main_hwmod,
1698 .slave = &am33xx_lcdc_hwmod,
1699 .addr = am33xx_lcdc_addr_space,
1700 .user = OCP_USER_MPU,
1701 };
1703 static struct omap_hwmod_ocp_if *am33xx_lcdc_slaves[] = {
1704 &am33xx_l3_main__lcdc,
1705 };
1707 static struct omap_hwmod am33xx_lcdc_hwmod = {
1708 .name = "lcdc",
1709 .class = &am33xx_lcdc_hwmod_class,
1710 .clkdm_name = "lcdc_clkdm",
1711 .mpu_irqs = am33xx_lcdc_irqs,
1712 .main_clk = "lcdc_fck",
1713 .prcm = {
1714 .omap4 = {
1715 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1716 .modulemode = MODULEMODE_SWCTRL,
1717 },
1718 },
1719 .slaves = am33xx_lcdc_slaves,
1720 .slaves_cnt = ARRAY_SIZE(am33xx_lcdc_slaves),
1721 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1722 };
1724 /*
1725 * 'mailbox' class
1726 * mailbox module allowing communication between the on-chip processors using a
1727 * queued mailbox-interrupt mechanism.
1728 */
1730 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1731 .rev_offs = 0x0000,
1732 .sysc_offs = 0x0010,
1733 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1734 SYSC_HAS_SOFTRESET),
1735 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1736 .sysc_fields = &omap_hwmod_sysc_type2,
1737 };
1739 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1740 .name = "mailbox",
1741 .sysc = &am33xx_mailbox_sysc,
1742 };
1744 static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1745 { .irq = 77 },
1746 { .irq = -1 }
1747 };
1749 static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
1750 {
1751 .pa_start = 0x480C8000,
1752 .pa_end = 0x480C8000 + (SZ_4K - 1),
1753 .flags = ADDR_TYPE_RT
1754 },
1755 { }
1756 };
1758 /* l4_cfg -> mailbox */
1759 static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
1760 .master = &am33xx_l4per_hwmod,
1761 .slave = &am33xx_mailbox_hwmod,
1762 .addr = am33xx_mailbox_addrs,
1763 .user = OCP_USER_MPU,
1764 };
1766 static struct omap_hwmod_ocp_if *am33xx_mailbox_slaves[] = {
1767 &am33xx_l4_per__mailbox,
1768 };
1770 static struct omap_hwmod am33xx_mailbox_hwmod = {
1771 .name = "mailbox",
1772 .class = &am33xx_mailbox_hwmod_class,
1773 .clkdm_name = "l4ls_clkdm",
1774 .mpu_irqs = am33xx_mailbox_irqs,
1775 .main_clk = "mailbox0_fck",
1776 .prcm = {
1777 .omap4 = {
1778 .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1779 .modulemode = MODULEMODE_SWCTRL,
1780 },
1781 },
1782 .slaves = am33xx_mailbox_slaves,
1783 .slaves_cnt = ARRAY_SIZE(am33xx_mailbox_slaves),
1784 };
1786 /* 'mcasp' class */
1788 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
1789 .rev_offs = 0x0,
1790 .sysc_offs = 0x4,
1791 .sysc_flags = SYSC_HAS_SIDLEMODE,
1792 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1793 .sysc_fields = &omap_hwmod_sysc_type3,
1794 };
1796 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1797 .name = "mcasp",
1798 .sysc = &am33xx_mcasp_sysc,
1799 };
1801 /* mcasp0 */
1802 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1803 { .name = "ax", .irq = 80, },
1804 { .name = "ar", .irq = 81, },
1805 { .irq = -1 }
1806 };
1808 static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
1809 { .name = "tx", .dma_req = AM33XX_DMA_MCASP0_X, },
1810 { .name = "rx", .dma_req = AM33XX_DMA_MCASP0_R, },
1811 { .dma_req = -1 }
1812 };
1814 static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
1815 {
1816 .pa_start = 0x48038000,
1817 .pa_end = 0x48038000 + (SZ_1K * 12) - 1,
1818 .flags = ADDR_TYPE_RT
1819 },
1820 { }
1821 };
1823 static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp0 = {
1824 .master = &am33xx_l3slow_hwmod,
1825 .slave = &am33xx_mcasp0_hwmod,
1826 .clk = "mcasp0_ick",
1827 .addr = am33xx_mcasp0_addr_space,
1828 .user = OCP_USER_MPU,
1829 };
1831 static struct omap_hwmod_ocp_if *am33xx_mcasp0_slaves[] = {
1832 &am33xx_l3_slow__mcasp0,
1833 };
1835 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1836 .name = "mcasp0",
1837 .class = &am33xx_mcasp_hwmod_class,
1838 .clkdm_name = "l3s_clkdm",
1839 .mpu_irqs = am33xx_mcasp0_irqs,
1840 .sdma_reqs = am33xx_mcasp0_edma_reqs,
1841 .main_clk = "mcasp0_fck",
1842 .prcm = {
1843 .omap4 = {
1844 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1845 .modulemode = MODULEMODE_SWCTRL,
1846 },
1847 },
1848 .slaves = am33xx_mcasp0_slaves,
1849 .slaves_cnt = ARRAY_SIZE(am33xx_mcasp0_slaves),
1850 };
1852 /* mcasp1 */
1853 static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
1854 { .name = "ax", .irq = 82, },
1855 { .name = "ar", .irq = 83, },
1856 { .irq = -1 }
1857 };
1859 static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
1860 { .name = "tx", .dma_req = AM33XX_DMA_MCASP1_X, },
1861 { .name = "rx", .dma_req = AM33XX_DMA_MCASP1_R, },
1862 { .dma_req = -1 }
1863 };
1866 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
1867 {
1868 .pa_start = 0x4803C000,
1869 .pa_end = 0x4803C000 + (SZ_1K * 12) - 1,
1870 .flags = ADDR_TYPE_RT
1871 },
1872 { }
1873 };
1875 static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp1 = {
1876 .master = &am33xx_l3slow_hwmod,
1877 .slave = &am33xx_mcasp1_hwmod,
1878 .clk = "mcasp1_ick",
1879 .addr = am33xx_mcasp1_addr_space,
1880 .user = OCP_USER_MPU,
1881 };
1883 static struct omap_hwmod_ocp_if *am33xx_mcasp1_slaves[] = {
1884 &am33xx_l3_slow__mcasp1,
1885 };
1887 static struct omap_hwmod am33xx_mcasp1_hwmod = {
1888 .name = "mcasp1",
1889 .class = &am33xx_mcasp_hwmod_class,
1890 .clkdm_name = "l3s_clkdm",
1891 .mpu_irqs = am33xx_mcasp1_irqs,
1892 .sdma_reqs = am33xx_mcasp1_edma_reqs,
1893 .main_clk = "mcasp1_fck",
1894 .prcm = {
1895 .omap4 = {
1896 .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
1897 .modulemode = MODULEMODE_SWCTRL,
1898 },
1899 },
1900 .slaves = am33xx_mcasp1_slaves,
1901 .slaves_cnt = ARRAY_SIZE(am33xx_mcasp1_slaves),
1902 };
1904 /* 'mmc' class */
1905 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1906 .rev_offs = 0x1fc,
1907 .sysc_offs = 0x10,
1908 .syss_offs = 0x14,
1909 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1910 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1911 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1912 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1913 .sysc_fields = &omap_hwmod_sysc_type1,
1914 };
1916 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1917 .name = "mmc",
1918 .sysc = &am33xx_mmc_sysc,
1919 };
1921 /* mmc0 */
1922 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1923 { .irq = 64 },
1924 { .irq = -1 }
1925 };
1927 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1928 { .name = "tx", .dma_req = 24, },
1929 { .name = "rx", .dma_req = 25, },
1930 { .dma_req = -1 }
1931 };
1933 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
1934 {
1935 .pa_start = 0x48060100,
1936 .pa_end = 0x48060100 + SZ_4K - 1,
1937 .flags = ADDR_TYPE_RT,
1938 },
1939 { }
1940 };
1942 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc0 = {
1943 .master = &am33xx_l4ls_hwmod,
1944 .slave = &am33xx_mmc0_hwmod,
1945 .clk = "mmc0_ick",
1946 .addr = am33xx_mmc0_addr_space,
1947 .user = OCP_USER_MPU,
1948 };
1950 static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = {
1951 &am33xx_l4ls__mmc0,
1952 };
1954 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1955 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1956 };
1958 static struct omap_hwmod am33xx_mmc0_hwmod = {
1959 .name = "mmc1",
1960 .class = &am33xx_mmc_hwmod_class,
1961 .clkdm_name = "l4ls_clkdm",
1962 .mpu_irqs = am33xx_mmc0_irqs,
1963 .main_clk = "mmc0_fck",
1964 .sdma_reqs = am33xx_mmc0_edma_reqs,
1965 .prcm = {
1966 .omap4 = {
1967 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1968 .modulemode = MODULEMODE_SWCTRL,
1969 },
1970 },
1971 .dev_attr = &am33xx_mmc0_dev_attr,
1972 .slaves = am33xx_mmc0_slaves,
1973 .slaves_cnt = ARRAY_SIZE(am33xx_mmc0_slaves),
1974 };
1976 /* mmc1 */
1977 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1978 { .irq = 28 },
1979 { .irq = -1 }
1980 };
1982 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1983 { .name = "tx", .dma_req = 2, },
1984 { .name = "rx", .dma_req = 3, },
1985 { .dma_req = -1 }
1986 };
1988 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
1989 {
1990 .pa_start = 0x481D8100,
1991 .pa_end = 0x481D8100 + SZ_4K - 1,
1992 .flags = ADDR_TYPE_RT,
1993 },
1994 { }
1995 };
1997 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc1 = {
1998 .master = &am33xx_l4ls_hwmod,
1999 .slave = &am33xx_mmc1_hwmod,
2000 .clk = "mmc1_ick",
2001 .addr = am33xx_mmc1_addr_space,
2002 .user = OCP_USER_MPU,
2003 };
2005 static struct omap_hwmod_ocp_if *am33xx_mmc1_slaves[] = {
2006 &am33xx_l4ls__mmc1,
2007 };
2009 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
2010 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2011 };
2013 static struct omap_hwmod am33xx_mmc1_hwmod = {
2014 .name = "mmc2",
2015 .class = &am33xx_mmc_hwmod_class,
2016 .clkdm_name = "l4ls_clkdm",
2017 .mpu_irqs = am33xx_mmc1_irqs,
2018 .main_clk = "mmc1_fck",
2019 .sdma_reqs = am33xx_mmc1_edma_reqs,
2020 .prcm = {
2021 .omap4 = {
2022 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
2023 .modulemode = MODULEMODE_SWCTRL,
2024 },
2025 },
2026 .dev_attr = &am33xx_mmc1_dev_attr,
2027 .slaves = am33xx_mmc1_slaves,
2028 .slaves_cnt = ARRAY_SIZE(am33xx_mmc1_slaves),
2029 };
2031 /* mmc2 */
2032 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
2033 { .irq = 29 },
2034 { .irq = -1 }
2035 };
2037 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
2038 { .name = "tx", .dma_req = 64, },
2039 { .name = "rx", .dma_req = 65, },
2040 { .dma_req = -1 }
2041 };
2043 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
2044 {
2045 .pa_start = 0x47810100,
2046 .pa_end = 0x47810100 + SZ_64K - 1,
2047 .flags = ADDR_TYPE_RT,
2048 },
2049 { }
2050 };
2052 static struct omap_hwmod_ocp_if am33xx_l3_main__mmc2 = {
2053 .master = &am33xx_l3_main_hwmod,
2054 .slave = &am33xx_mmc2_hwmod,
2055 .clk = "mmc2_ick",
2056 .addr = am33xx_mmc2_addr_space,
2057 .user = OCP_USER_MPU,
2058 };
2060 static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = {
2061 &am33xx_l3_main__mmc2,
2062 };
2064 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
2065 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2066 };
2067 static struct omap_hwmod am33xx_mmc2_hwmod = {
2068 .name = "mmc3",
2069 .class = &am33xx_mmc_hwmod_class,
2070 .clkdm_name = "l3s_clkdm",
2071 .mpu_irqs = am33xx_mmc2_irqs,
2072 .main_clk = "mmc2_fck",
2073 .sdma_reqs = am33xx_mmc2_edma_reqs,
2074 .prcm = {
2075 .omap4 = {
2076 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
2077 .modulemode = MODULEMODE_SWCTRL,
2078 },
2079 },
2080 .dev_attr = &am33xx_mmc2_dev_attr,
2081 .slaves = am33xx_mmc2_slaves,
2082 .slaves_cnt = ARRAY_SIZE(am33xx_mmc2_slaves),
2083 };
2085 /* Master interfaces on the MPU interconnect */
2086 static struct omap_hwmod_ocp_if *am33xx_l3_mpu_masters[] = {
2087 &am33xx_mpu__l3_slow,
2088 };
2090 /* mpu */
2091 static struct omap_hwmod am33xx_mpu_hwmod = {
2092 .name = "mpu",
2093 .class = &mpu_hwmod_class,
2094 .clkdm_name = "mpu_clkdm",
2095 .main_clk = "mpu_fck",
2096 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
2097 .prcm = {
2098 .omap4 = {
2099 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
2100 .modulemode = MODULEMODE_SWCTRL,
2101 },
2102 },
2103 .masters = am33xx_l3_mpu_masters,
2104 .masters_cnt = ARRAY_SIZE(am33xx_l3_mpu_masters),
2105 };
2107 /* ocmcram */
2108 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
2109 .name = "ocmcram",
2110 };
2112 static struct omap_hwmod am33xx_ocmcram_hwmod = {
2113 .name = "ocmcram",
2114 .class = &am33xx_ocmcram_hwmod_class,
2115 .clkdm_name = "l3_clkdm",
2116 .main_clk = "ocmcram_ick",
2117 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
2118 .prcm = {
2119 .omap4 = {
2120 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
2121 .modulemode = MODULEMODE_SWCTRL,
2122 },
2123 },
2124 };
2126 /* ocpwp */
2127 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
2128 .name = "ocpwp",
2129 };
2131 static struct omap_hwmod am33xx_ocpwp_hwmod = {
2132 .name = "ocpwp",
2133 .class = &am33xx_ocpwp_hwmod_class,
2134 .clkdm_name = "l4ls_clkdm",
2135 .main_clk = "ocpwp_fck",
2136 .prcm = {
2137 .omap4 = {
2138 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
2139 .modulemode = MODULEMODE_SWCTRL,
2140 },
2141 },
2142 };
2144 /* rtc */
2145 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
2146 .name = "rtc",
2147 };
2149 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
2150 { .irq = 75 },
2151 { .irq = -1 }
2152 };
2154 static struct omap_hwmod am33xx_rtc_hwmod = {
2155 .name = "rtc",
2156 .class = &am33xx_rtc_hwmod_class,
2157 .clkdm_name = "l4_rtc_clkdm",
2158 .mpu_irqs = am33xx_rtc_irqs,
2159 .main_clk = "rtc_fck",
2160 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), /* ??? */
2161 .prcm = {
2162 .omap4 = {
2163 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
2164 .modulemode = MODULEMODE_SWCTRL,
2165 },
2166 },
2167 };
2169 /* sha0 */
2170 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
2171 .name = "sha0",
2172 };
2174 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
2175 { .irq = AM33XX_IRQ_SHAEIP57t0_P },
2176 { .irq = -1 }
2177 };
2179 static struct omap_hwmod_dma_info am33xx_sha0_dma[] = {
2180 { .dma_req = AM33XX_DMA_SHAEIP57T0_DIN },
2181 { .dma_req = -1 }
2182 };
2184 static struct omap_hwmod am33xx_sha0_hwmod = {
2185 .name = "sha0",
2186 .class = &am33xx_sha0_hwmod_class,
2187 .clkdm_name = "l3_clkdm",
2188 .mpu_irqs = am33xx_sha0_irqs,
2189 .sdma_reqs = am33xx_sha0_dma,
2190 .main_clk = "sha0_fck",
2191 .prcm = {
2192 .omap4 = {
2193 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
2194 .modulemode = MODULEMODE_SWCTRL,
2195 },
2196 },
2197 };
2199 /* 'smartreflex' class */
2200 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
2201 .name = "smartreflex",
2202 };
2204 /* smartreflex0 */
2205 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
2206 { .irq = 120 },
2207 { .irq = -1 }
2208 };
2210 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
2211 .name = "smartreflex0",
2212 .class = &am33xx_smartreflex_hwmod_class,
2213 .clkdm_name = "l4_wkup_clkdm",
2214 .mpu_irqs = am33xx_smartreflex0_irqs,
2215 .main_clk = "smartreflex0_fck",
2216 .prcm = {
2217 .omap4 = {
2218 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
2219 .modulemode = MODULEMODE_SWCTRL,
2220 },
2221 },
2222 };
2224 /* smartreflex1 */
2225 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
2226 { .irq = 121 },
2227 { .irq = -1 }
2228 };
2230 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
2231 .name = "smartreflex1",
2232 .class = &am33xx_smartreflex_hwmod_class,
2233 .clkdm_name = "l4_wkup_clkdm",
2234 .mpu_irqs = am33xx_smartreflex1_irqs,
2235 .main_clk = "smartreflex1_fck",
2236 .prcm = {
2237 .omap4 = {
2238 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
2239 .modulemode = MODULEMODE_SWCTRL,
2240 },
2241 },
2242 };
2244 /* 'spi' class */
2245 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
2246 .rev_offs = 0x0000,
2247 .sysc_offs = 0x0110,
2248 .syss_offs = 0x0114,
2249 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2250 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
2251 SYSS_HAS_RESET_STATUS),
2252 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2253 .sysc_fields = &omap_hwmod_sysc_type1,
2254 };
2256 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
2257 .name = "mcspi",
2258 .sysc = &am33xx_mcspi_sysc,
2259 .rev = OMAP4_MCSPI_REV,
2260 };
2262 /* spi0 */
2263 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
2264 { .irq = 65 },
2265 { .irq = -1 }
2266 };
2268 struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
2269 { .name = "rx0", .dma_req = 17 },
2270 { .name = "tx0", .dma_req = 16 },
2271 { .name = "rx1", .dma_req = 19 },
2272 { .name = "tx1", .dma_req = 18 },
2273 { .dma_req = -1 }
2274 };
2276 struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
2277 {
2278 .pa_start = 0x48030000,
2279 .pa_end = 0x48030000 + SZ_1K - 1,
2280 .flags = ADDR_TYPE_RT,
2281 },
2282 { }
2283 };
2285 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = {
2286 .master = &am33xx_l4per_hwmod,
2287 .slave = &am33xx_spi0_hwmod,
2288 .clk = "spi0_ick",
2289 .addr = am33xx_mcspi0_addr_space,
2290 .user = OCP_USER_MPU,
2291 };
2293 static struct omap_hwmod_ocp_if *am33xx_mcspi0_slaves[] = {
2294 &am33xx_l4_core__mcspi0,
2295 };
2297 struct omap2_mcspi_dev_attr mcspi_attrib = {
2298 .num_chipselect = 2,
2299 };
2300 static struct omap_hwmod am33xx_spi0_hwmod = {
2301 .name = "spi0",
2302 .class = &am33xx_spi_hwmod_class,
2303 .clkdm_name = "l4ls_clkdm",
2304 .mpu_irqs = am33xx_spi0_irqs,
2305 .main_clk = "spi0_fck",
2306 .sdma_reqs = am33xx_mcspi0_edma_reqs,
2307 .prcm = {
2308 .omap4 = {
2309 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
2310 .modulemode = MODULEMODE_SWCTRL,
2311 },
2312 },
2313 .dev_attr = &mcspi_attrib,
2314 .slaves = am33xx_mcspi0_slaves,
2315 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi0_slaves),
2316 };
2318 /* spi1 */
2319 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
2320 { .irq = 125 },
2321 { .irq = -1 }
2322 };
2324 struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
2325 { .name = "rx0", .dma_req = 43 },
2326 { .name = "tx0", .dma_req = 42 },
2327 { .name = "rx1", .dma_req = 45 },
2328 { .name = "tx1", .dma_req = 44 },
2329 { .dma_req = -1 }
2330 };
2332 struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
2333 {
2334 .pa_start = 0x481A0000,
2335 .pa_end = 0x481A0000 + SZ_1K - 1,
2336 .flags = ADDR_TYPE_RT,
2337 },
2338 { }
2339 };
2341 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = {
2342 .master = &am33xx_l4per_hwmod,
2343 .slave = &am33xx_spi1_hwmod,
2344 .clk = "spi1_ick",
2345 .addr = am33xx_mcspi1_addr_space,
2346 .user = OCP_USER_MPU,
2347 };
2349 static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = {
2350 &am33xx_l4_core__mcspi1,
2351 };
2352 static struct omap_hwmod am33xx_spi1_hwmod = {
2353 .name = "spi1",
2354 .class = &am33xx_spi_hwmod_class,
2355 .clkdm_name = "l4ls_clkdm",
2356 .mpu_irqs = am33xx_spi1_irqs,
2357 .main_clk = "spi1_fck",
2358 .sdma_reqs = am33xx_mcspi1_edma_reqs,
2359 .prcm = {
2360 .omap4 = {
2361 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
2362 .modulemode = MODULEMODE_SWCTRL,
2363 },
2364 },
2365 .dev_attr = &mcspi_attrib,
2366 .slaves = am33xx_mcspi1_slaves,
2367 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi1_slaves),
2368 };
2370 /* spinlock */
2371 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
2372 .name = "spinlock",
2373 };
2375 static struct omap_hwmod am33xx_spinlock_hwmod = {
2376 .name = "spinlock",
2377 .class = &am33xx_spinlock_hwmod_class,
2378 .clkdm_name = "l4ls_clkdm",
2379 .main_clk = "spinlock_fck",
2380 .prcm = {
2381 .omap4 = {
2382 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
2383 .modulemode = MODULEMODE_SWCTRL,
2384 },
2385 },
2386 };
2388 /* 'timer 0 & 2-7' class */
2389 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
2390 .rev_offs = 0x0000,
2391 .sysc_offs = 0x0010,
2392 .syss_offs = 0x0014,
2393 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2394 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2395 SIDLE_SMART_WKUP),
2396 .sysc_fields = &omap_hwmod_sysc_type2,
2397 };
2399 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
2400 .name = "timer",
2401 .sysc = &am33xx_timer_sysc,
2402 };
2404 /* timer0 */
2405 /* l4 wkup -> timer0 interface */
2406 static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = {
2407 {
2408 .pa_start = 0x44E05000,
2409 .pa_end = 0x44E05000 + SZ_1K - 1,
2410 .flags = ADDR_TYPE_RT
2411 },
2412 { }
2413 };
2415 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = {
2416 .master = &am33xx_l4wkup_hwmod,
2417 .slave = &am33xx_timer0_hwmod,
2418 .clk = "timer0_ick",
2419 .addr = am33xx_timer0_addr_space,
2420 .user = OCP_USER_MPU,
2421 };
2423 static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = {
2424 &am33xx_l4wkup__timer0,
2425 };
2427 static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = {
2428 { .irq = 66 },
2429 { .irq = -1 }
2430 };
2432 static struct omap_hwmod am33xx_timer0_hwmod = {
2433 .name = "timer0",
2434 .class = &am33xx_timer_hwmod_class,
2435 .clkdm_name = "l4_wkup_clkdm",
2436 .mpu_irqs = am33xx_timer0_irqs,
2437 .main_clk = "timer0_fck",
2438 .prcm = {
2439 .omap4 = {
2440 .clkctrl_offs = AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET,
2441 .modulemode = MODULEMODE_SWCTRL,
2442 },
2443 },
2444 .slaves = am33xx_timer0_slaves,
2445 .slaves_cnt = ARRAY_SIZE(am33xx_timer0_slaves),
2446 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
2447 };
2449 /* timer1 1ms */
2450 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
2451 .rev_offs = 0x0000,
2452 .sysc_offs = 0x0010,
2453 .syss_offs = 0x0014,
2454 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2455 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
2456 SYSS_HAS_RESET_STATUS),
2457 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2458 .sysc_fields = &omap_hwmod_sysc_type1,
2459 };
2461 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
2462 .name = "timer",
2463 .sysc = &am33xx_timer1ms_sysc,
2464 };
2466 /* l4 wkup -> timer1 interface */
2467 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
2468 {
2469 .pa_start = 0x44E31000,
2470 .pa_end = 0x44E31000 + SZ_1K - 1,
2471 .flags = ADDR_TYPE_RT
2472 },
2473 { }
2474 };
2476 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = {
2477 .master = &am33xx_l4wkup_hwmod,
2478 .slave = &am33xx_timer1_hwmod,
2479 .clk = "timer1_ick",
2480 .addr = am33xx_timer1_addr_space,
2481 .user = OCP_USER_MPU,
2482 };
2484 static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = {
2485 &am33xx_l4wkup__timer1,
2486 };
2488 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
2489 { .irq = 67 },
2490 { .irq = -1 }
2491 };
2493 static struct omap_hwmod am33xx_timer1_hwmod = {
2494 .name = "timer1",
2495 .class = &am33xx_timer1ms_hwmod_class,
2496 .clkdm_name = "l4_wkup_clkdm",
2497 .mpu_irqs = am33xx_timer1_irqs,
2498 .main_clk = "timer1_fck",
2499 .prcm = {
2500 .omap4 = {
2501 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2502 .modulemode = MODULEMODE_SWCTRL,
2503 },
2504 },
2505 .slaves = am33xx_timer1_slaves,
2506 .slaves_cnt = ARRAY_SIZE(am33xx_timer1_slaves),
2507 };
2509 /* timer2 */
2510 /* l4 per -> timer2 interface */
2511 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
2512 {
2513 .pa_start = 0x48040000,
2514 .pa_end = 0x48040000 + SZ_1K - 1,
2515 .flags = ADDR_TYPE_RT
2516 },
2517 { }
2518 };
2520 static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = {
2521 .master = &am33xx_l4per_hwmod,
2522 .slave = &am33xx_timer2_hwmod,
2523 .clk = "timer2_ick",
2524 .addr = am33xx_timer2_addr_space,
2525 .user = OCP_USER_MPU,
2526 };
2528 static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = {
2529 &am33xx_l4per__timer2,
2530 };
2532 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
2533 { .irq = 68 },
2534 { .irq = -1 }
2535 };
2537 static struct omap_hwmod am33xx_timer2_hwmod = {
2538 .name = "timer2",
2539 .class = &am33xx_timer_hwmod_class,
2540 .clkdm_name = "l4ls_clkdm",
2541 .mpu_irqs = am33xx_timer2_irqs,
2542 .main_clk = "timer2_fck",
2543 .prcm = {
2544 .omap4 = {
2545 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
2546 .modulemode = MODULEMODE_SWCTRL,
2547 },
2548 },
2549 .slaves = am33xx_timer2_slaves,
2550 .slaves_cnt = ARRAY_SIZE(am33xx_timer2_slaves),
2551 };
2553 /* timer3 */
2554 /* l4 per -> timer3 interface */
2555 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
2556 {
2557 .pa_start = 0x48042000,
2558 .pa_end = 0x48042000 + SZ_1K - 1,
2559 .flags = ADDR_TYPE_RT
2560 },
2561 { }
2562 };
2564 static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = {
2565 .master = &am33xx_l4per_hwmod,
2566 .slave = &am33xx_timer3_hwmod,
2567 .clk = "timer3_ick",
2568 .addr = am33xx_timer3_addr_space,
2569 .user = OCP_USER_MPU,
2570 };
2572 static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = {
2573 &am33xx_l4per__timer3,
2574 };
2576 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
2577 { .irq = 69 },
2578 { .irq = -1 }
2579 };
2581 static struct omap_hwmod am33xx_timer3_hwmod = {
2582 .name = "timer3",
2583 .class = &am33xx_timer_hwmod_class,
2584 .clkdm_name = "l4ls_clkdm",
2585 .mpu_irqs = am33xx_timer3_irqs,
2586 .main_clk = "timer3_fck",
2587 .prcm = {
2588 .omap4 = {
2589 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
2590 .modulemode = MODULEMODE_SWCTRL,
2591 },
2592 },
2593 .slaves = am33xx_timer3_slaves,
2594 .slaves_cnt = ARRAY_SIZE(am33xx_timer3_slaves),
2595 };
2597 /* timer4 */
2598 /* l4 per -> timer4 interface */
2599 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
2600 {
2601 .pa_start = 0x48044000,
2602 .pa_end = 0x48044000 + SZ_1K - 1,
2603 .flags = ADDR_TYPE_RT
2604 },
2605 { }
2606 };
2608 static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = {
2609 .master = &am33xx_l4per_hwmod,
2610 .slave = &am33xx_timer4_hwmod,
2611 .clk = "timer4_ick",
2612 .addr = am33xx_timer4_addr_space,
2613 .user = OCP_USER_MPU,
2614 };
2616 static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = {
2617 &am33xx_l4per__timer4,
2618 };
2620 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
2621 { .irq = 92 },
2622 { .irq = -1 }
2623 };
2625 static struct omap_hwmod am33xx_timer4_hwmod = {
2626 .name = "timer4",
2627 .class = &am33xx_timer_hwmod_class,
2628 .clkdm_name = "l4ls_clkdm",
2629 .mpu_irqs = am33xx_timer4_irqs,
2630 .main_clk = "timer4_fck",
2631 .prcm = {
2632 .omap4 = {
2633 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
2634 .modulemode = MODULEMODE_SWCTRL,
2635 },
2636 },
2637 .slaves = am33xx_timer4_slaves,
2638 .slaves_cnt = ARRAY_SIZE(am33xx_timer4_slaves),
2639 };
2641 /* timer5 */
2642 /* l4 per -> timer5 interface */
2643 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
2644 {
2645 .pa_start = 0x48046000,
2646 .pa_end = 0x48046000 + SZ_1K - 1,
2647 .flags = ADDR_TYPE_RT
2648 },
2649 { }
2650 };
2652 static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = {
2653 .master = &am33xx_l4per_hwmod,
2654 .slave = &am33xx_timer5_hwmod,
2655 .clk = "timer5_ick",
2656 .addr = am33xx_timer5_addr_space,
2657 .user = OCP_USER_MPU,
2658 };
2660 static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = {
2661 &am33xx_l4per__timer5,
2662 };
2664 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
2665 { .irq = 93 },
2666 { .irq = -1 }
2667 };
2669 static struct omap_hwmod am33xx_timer5_hwmod = {
2670 .name = "timer5",
2671 .class = &am33xx_timer_hwmod_class,
2672 .clkdm_name = "l4ls_clkdm",
2673 .mpu_irqs = am33xx_timer5_irqs,
2674 .main_clk = "timer5_fck",
2675 .prcm = {
2676 .omap4 = {
2677 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
2678 .modulemode = MODULEMODE_SWCTRL,
2679 },
2680 },
2681 .slaves = am33xx_timer5_slaves,
2682 .slaves_cnt = ARRAY_SIZE(am33xx_timer5_slaves),
2683 };
2685 /* timer6 */
2686 /* l4 per -> timer6 interface */
2687 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
2688 {
2689 .pa_start = 0x48048000,
2690 .pa_end = 0x48048000 + SZ_1K - 1,
2691 .flags = ADDR_TYPE_RT
2692 },
2693 { }
2694 };
2696 static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = {
2697 .master = &am33xx_l4per_hwmod,
2698 .slave = &am33xx_timer6_hwmod,
2699 .clk = "timer6_ick",
2700 .addr = am33xx_timer6_addr_space,
2701 .user = OCP_USER_MPU,
2702 };
2704 static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = {
2705 &am33xx_l4per__timer6,
2706 };
2708 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
2709 { .irq = 94 },
2710 { .irq = -1 }
2711 };
2713 static struct omap_hwmod am33xx_timer6_hwmod = {
2714 .name = "timer6",
2715 .class = &am33xx_timer_hwmod_class,
2716 .clkdm_name = "l4ls_clkdm",
2717 .mpu_irqs = am33xx_timer6_irqs,
2718 .main_clk = "timer6_fck",
2719 .prcm = {
2720 .omap4 = {
2721 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
2722 .modulemode = MODULEMODE_SWCTRL,
2723 },
2724 },
2725 .slaves = am33xx_timer6_slaves,
2726 .slaves_cnt = ARRAY_SIZE(am33xx_timer6_slaves),
2727 };
2729 /* timer7 */
2730 /* l4 per -> timer7 interface */
2731 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
2732 {
2733 .pa_start = 0x4804A000,
2734 .pa_end = 0x4804A000 + SZ_1K - 1,
2735 .flags = ADDR_TYPE_RT
2736 },
2737 { }
2738 };
2740 static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = {
2741 .master = &am33xx_l4per_hwmod,
2742 .slave = &am33xx_timer7_hwmod,
2743 .clk = "timer7_ick",
2744 .addr = am33xx_timer7_addr_space,
2745 .user = OCP_USER_MPU,
2746 };
2748 static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = {
2749 &am33xx_l4per__timer7,
2750 };
2752 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
2753 { .irq = 95 },
2754 { .irq = -1 }
2755 };
2757 static struct omap_hwmod am33xx_timer7_hwmod = {
2758 .name = "timer7",
2759 .class = &am33xx_timer_hwmod_class,
2760 .clkdm_name = "l4ls_clkdm",
2761 .mpu_irqs = am33xx_timer7_irqs,
2762 .main_clk = "timer7_fck",
2763 .prcm = {
2764 .omap4 = {
2765 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
2766 .modulemode = MODULEMODE_SWCTRL,
2767 },
2768 },
2769 .slaves = am33xx_timer7_slaves,
2770 .slaves_cnt = ARRAY_SIZE(am33xx_timer7_slaves),
2771 };
2773 /* tpcc */
2774 #define AM33XX_TPCC_BASE 0x49000000
2775 #define AM33XX_TPTC0_BASE 0x49800000
2776 #define AM33XX_TPTC1_BASE 0x49900000
2777 #define AM33XX_TPTC2_BASE 0x49a00000
2779 /* 'tpcc' class */
2780 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
2781 .name = "tpcc",
2782 };
2784 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
2785 { .name = "edma0", .irq = 12 },
2786 { .name = "edma0_mperr", .irq = 13, },
2787 { .name = "edma0_err", .irq = 14 },
2788 { .irq = -1 }
2789 };
2791 static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
2792 {
2793 .name = "edma_cc0",
2794 .pa_start = AM33XX_TPCC_BASE,
2795 .pa_end = AM33XX_TPCC_BASE + SZ_32K - 1,
2796 .flags = ADDR_TYPE_RT
2797 },
2798 { }
2799 };
2801 static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
2802 .master = &am33xx_l3_main_hwmod,
2803 .slave = &am33xx_tpcc_hwmod,
2804 .addr = am33xx_tpcc_addr_space,
2805 .user = OCP_USER_MPU,
2806 };
2808 static struct omap_hwmod_ocp_if *am33xx_tpcc_slaves[] = {
2809 &am33xx_l3_main__tpcc,
2810 };
2812 static struct omap_hwmod am33xx_tpcc_hwmod = {
2813 .name = "tpcc",
2814 .class = &am33xx_tpcc_hwmod_class,
2815 .clkdm_name = "l3_clkdm",
2816 .mpu_irqs = am33xx_tpcc_irqs,
2817 .main_clk = "tpcc_ick",
2818 .prcm = {
2819 .omap4 = {
2820 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
2821 .modulemode = MODULEMODE_SWCTRL,
2822 },
2823 },
2824 .slaves = am33xx_tpcc_slaves,
2825 .slaves_cnt = ARRAY_SIZE(am33xx_tpcc_slaves),
2826 };
2828 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
2829 .rev_offs = 0x0,
2830 .sysc_offs = 0x10,
2831 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2832 SYSC_HAS_MIDLEMODE),
2833 .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
2834 .sysc_fields = &omap_hwmod_sysc_type2,
2835 };
2837 /* 'tptc' class */
2838 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
2839 .name = "tptc",
2840 .sysc = &am33xx_tptc_sysc,
2841 };
2843 /* tptc0 */
2844 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
2845 { .irq = 112 },
2846 { .irq = -1 }
2847 };
2849 struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
2850 {
2851 .name = "edma_tc0",
2852 .pa_start = AM33XX_TPTC0_BASE,
2853 .pa_end = AM33XX_TPTC0_BASE + SZ_8K - 1,
2854 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2855 },
2856 { }
2857 };
2859 struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
2860 .master = &am33xx_l3_main_hwmod,
2861 .slave = &am33xx_tptc0_hwmod,
2862 .addr = am33xx_tptc0_addr_space,
2863 .user = OCP_USER_MPU,
2864 };
2866 static struct omap_hwmod_ocp_if *am33xx_tptc0_slaves[] = {
2867 &am33xx_l3_main__tptc0,
2868 };
2870 static struct omap_hwmod am33xx_tptc0_hwmod = {
2871 .name = "tptc0",
2872 .class = &am33xx_tptc_hwmod_class,
2873 .clkdm_name = "l3_clkdm",
2874 .mpu_irqs = am33xx_tptc0_irqs,
2875 .main_clk = "tptc0_ick",
2876 .prcm = {
2877 .omap4 = {
2878 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
2879 .modulemode = MODULEMODE_SWCTRL,
2880 },
2881 },
2882 .slaves = am33xx_tptc0_slaves,
2883 .slaves_cnt = ARRAY_SIZE(am33xx_tptc0_slaves),
2884 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
2885 };
2887 /* tptc1 */
2888 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
2889 { .irq = 113 },
2890 { .irq = -1 }
2891 };
2893 struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
2894 {
2895 .name = "edma_tc1",
2896 .pa_start = AM33XX_TPTC1_BASE,
2897 .pa_end = AM33XX_TPTC1_BASE + SZ_8K - 1,
2898 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2899 },
2900 { }
2901 };
2903 struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
2904 .master = &am33xx_l3_main_hwmod,
2905 .slave = &am33xx_tptc1_hwmod,
2906 .addr = am33xx_tptc1_addr_space,
2907 .user = OCP_USER_MPU,
2908 };
2910 static struct omap_hwmod_ocp_if *am33xx_tptc1_slaves[] = {
2911 &am33xx_l3_main__tptc1,
2912 };
2914 static struct omap_hwmod am33xx_tptc1_hwmod = {
2915 .name = "tptc1",
2916 .class = &am33xx_tptc_hwmod_class,
2917 .clkdm_name = "l3_clkdm",
2918 .mpu_irqs = am33xx_tptc1_irqs,
2919 .main_clk = "tptc1_ick",
2920 .prcm = {
2921 .omap4 = {
2922 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
2923 .modulemode = MODULEMODE_SWCTRL,
2924 },
2925 },
2926 .slaves = am33xx_tptc1_slaves,
2927 .slaves_cnt = ARRAY_SIZE(am33xx_tptc1_slaves),
2928 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
2929 };
2931 /* tptc2 */
2932 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
2933 { .irq = 114 },
2934 { .irq = -1 }
2935 };
2937 struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
2938 {
2939 .name = "edma_tc2",
2940 .pa_start = AM33XX_TPTC2_BASE,
2941 .pa_end = AM33XX_TPTC2_BASE + SZ_8K - 1,
2942 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2943 },
2944 { }
2945 };
2947 struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
2948 .master = &am33xx_l3_main_hwmod,
2949 .slave = &am33xx_tptc2_hwmod,
2950 .addr = am33xx_tptc2_addr_space,
2951 .user = OCP_USER_MPU,
2952 };
2954 static struct omap_hwmod_ocp_if *am33xx_tptc2_slaves[] = {
2955 &am33xx_l3_main__tptc2,
2956 };
2958 static struct omap_hwmod am33xx_tptc2_hwmod = {
2959 .name = "tptc2",
2960 .class = &am33xx_tptc_hwmod_class,
2961 .clkdm_name = "l3_clkdm",
2962 .mpu_irqs = am33xx_tptc2_irqs,
2963 .main_clk = "tptc2_ick",
2964 .prcm = {
2965 .omap4 = {
2966 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
2967 .modulemode = MODULEMODE_SWCTRL,
2968 },
2969 },
2970 .slaves = am33xx_tptc2_slaves,
2971 .slaves_cnt = ARRAY_SIZE(am33xx_tptc2_slaves),
2972 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
2973 };
2975 /* 'uart' class */
2976 static struct omap_hwmod_class_sysconfig uart_sysc = {
2977 .rev_offs = 0x50,
2978 .sysc_offs = 0x54,
2979 .syss_offs = 0x58,
2980 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2981 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2982 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2983 SIDLE_SMART_WKUP),
2984 .sysc_fields = &omap_hwmod_sysc_type1,
2985 };
2987 static struct omap_hwmod_class uart_class = {
2988 .name = "uart",
2989 .sysc = &uart_sysc,
2990 };
2992 /* uart1 */
2993 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
2994 { .name = "tx", .dma_req = 26, },
2995 { .name = "rx", .dma_req = 27, },
2996 { .dma_req = -1 }
2997 };
2999 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
3000 {
3001 .pa_start = 0x44E09000,
3002 .pa_end = 0x44E09000 + SZ_8K - 1,
3003 .flags = ADDR_TYPE_RT,
3004 },
3005 { }
3006 };
3008 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
3009 .master = &am33xx_l4wkup_hwmod,
3010 .slave = &am33xx_uart1_hwmod,
3011 .clk = "uart1_ick",
3012 .addr = am33xx_uart1_addr_space,
3013 .user = OCP_USER_MPU,
3014 };
3016 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
3017 { .irq = 72 },
3018 { .irq = -1 }
3019 };
3021 static struct omap_hwmod_ocp_if *am33xx_uart1_slaves[] = {
3022 &am33xx_l4_wkup__uart1,
3023 };
3025 static struct omap_hwmod am33xx_uart1_hwmod = {
3026 .name = "uart1",
3027 .class = &uart_class,
3028 .clkdm_name = "l4_wkup_clkdm",
3029 .mpu_irqs = am33xx_uart1_irqs,
3030 .main_clk = "uart1_fck",
3031 .sdma_reqs = uart1_edma_reqs,
3032 .prcm = {
3033 .omap4 = {
3034 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
3035 .modulemode = MODULEMODE_SWCTRL,
3036 },
3037 },
3038 .slaves = am33xx_uart1_slaves,
3039 .slaves_cnt = ARRAY_SIZE(am33xx_uart1_slaves),
3040 };
3042 /* uart2 */
3043 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
3044 {
3045 .pa_start = 0x48022000,
3046 .pa_end = 0x48022000 + SZ_8K - 1,
3047 .flags = ADDR_TYPE_RT,
3048 },
3049 { }
3050 };
3052 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
3053 .slave = &am33xx_uart2_hwmod,
3054 .clk = "uart2_ick",
3055 .addr = am33xx_uart2_addr_space,
3056 .user = OCP_USER_MPU,
3057 };
3059 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
3060 { .irq = 73 },
3061 { .irq = -1 }
3062 };
3064 static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = {
3065 &am33xx_l4_ls__uart2,
3066 };
3068 static struct omap_hwmod am33xx_uart2_hwmod = {
3069 .name = "uart2",
3070 .class = &uart_class,
3071 .clkdm_name = "l4ls_clkdm",
3072 .mpu_irqs = am33xx_uart2_irqs,
3073 .main_clk = "uart2_fck",
3074 .sdma_reqs = uart1_edma_reqs,
3075 .prcm = {
3076 .omap4 = {
3077 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
3078 .modulemode = MODULEMODE_SWCTRL,
3079 },
3080 },
3081 .slaves = am33xx_uart2_slaves,
3082 .slaves_cnt = ARRAY_SIZE(am33xx_uart2_slaves),
3083 };
3085 /* uart3 */
3086 static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
3087 { .name = "tx", .dma_req = 30, },
3088 { .name = "rx", .dma_req = 31, },
3089 { .dma_req = -1 }
3090 };
3092 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
3093 {
3094 .pa_start = 0x48024000,
3095 .pa_end = 0x48024000 + SZ_8K - 1,
3096 .flags = ADDR_TYPE_RT,
3097 },
3098 { }
3099 };
3101 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
3102 .slave = &am33xx_uart3_hwmod,
3103 .clk = "uart3_ick",
3104 .addr = am33xx_uart3_addr_space,
3105 .user = OCP_USER_MPU,
3106 };
3108 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
3109 { .irq = 74 },
3110 { .irq = -1 }
3111 };
3113 static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = {
3114 &am33xx_l4_ls__uart3,
3115 };
3117 static struct omap_hwmod am33xx_uart3_hwmod = {
3118 .name = "uart3",
3119 .class = &uart_class,
3120 .clkdm_name = "l4ls_clkdm",
3121 .mpu_irqs = am33xx_uart3_irqs,
3122 .main_clk = "uart3_fck",
3123 .sdma_reqs = uart3_edma_reqs,
3124 .prcm = {
3125 .omap4 = {
3126 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
3127 .modulemode = MODULEMODE_SWCTRL,
3128 },
3129 },
3130 .slaves = am33xx_uart3_slaves,
3131 .slaves_cnt = ARRAY_SIZE(am33xx_uart3_slaves),
3132 };
3134 /* uart4 */
3135 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
3136 {
3137 .pa_start = 0x481A6000,
3138 .pa_end = 0x481A6000 + SZ_8K - 1,
3139 .flags = ADDR_TYPE_RT,
3140 },
3141 { }
3142 };
3144 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
3145 .slave = &am33xx_uart4_hwmod,
3146 .clk = "uart4_ick",
3147 .addr = am33xx_uart4_addr_space,
3148 .user = OCP_USER_MPU,
3149 };
3151 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
3152 { .irq = 44 },
3153 { .irq = -1 }
3154 };
3156 static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = {
3157 &am33xx_l4_ls__uart4,
3158 };
3160 static struct omap_hwmod am33xx_uart4_hwmod = {
3161 .name = "uart4",
3162 .class = &uart_class,
3163 .mpu_irqs = am33xx_uart4_irqs,
3164 .main_clk = "uart4_fck",
3165 .clkdm_name = "l4ls_clkdm",
3166 .sdma_reqs = uart1_edma_reqs,
3167 .prcm = {
3168 .omap4 = {
3169 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
3170 .modulemode = MODULEMODE_SWCTRL,
3171 },
3172 },
3173 .slaves = am33xx_uart4_slaves,
3174 .slaves_cnt = ARRAY_SIZE(am33xx_uart4_slaves),
3175 };
3177 /* uart5 */
3178 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
3179 {
3180 .pa_start = 0x481A8000,
3181 .pa_end = 0x481A8000 + SZ_8K - 1,
3182 .flags = ADDR_TYPE_RT,
3183 },
3184 { }
3185 };
3187 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
3188 .slave = &am33xx_uart5_hwmod,
3189 .clk = "uart5_ick",
3190 .addr = am33xx_uart5_addr_space,
3191 .user = OCP_USER_MPU,
3192 };
3194 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
3195 { .irq = 45 },
3196 { .irq = -1 }
3197 };
3199 static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = {
3200 &am33xx_l4_ls__uart5,
3201 };
3203 static struct omap_hwmod am33xx_uart5_hwmod = {
3204 .name = "uart5",
3205 .class = &uart_class,
3206 .clkdm_name = "l4ls_clkdm",
3207 .mpu_irqs = am33xx_uart5_irqs,
3208 .main_clk = "uart5_fck",
3209 .sdma_reqs = uart1_edma_reqs,
3210 .prcm = {
3211 .omap4 = {
3212 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
3213 .modulemode = MODULEMODE_SWCTRL,
3214 },
3215 },
3216 .slaves = am33xx_uart5_slaves,
3217 .slaves_cnt = ARRAY_SIZE(am33xx_uart5_slaves),
3218 };
3220 /* uart6 */
3221 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
3222 {
3223 .pa_start = 0x481AA000,
3224 .pa_end = 0x481AA000 + SZ_8K - 1,
3225 .flags = ADDR_TYPE_RT,
3226 },
3227 { }
3228 };
3230 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
3231 .slave = &am33xx_uart6_hwmod,
3232 .clk = "uart6_ick",
3233 .addr = am33xx_uart6_addr_space,
3234 .user = OCP_USER_MPU,
3235 };
3237 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
3238 { .irq = 46 },
3239 { .irq = -1 }
3240 };
3242 static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = {
3243 &am33xx_l4_ls__uart6,
3244 };
3246 static struct omap_hwmod am33xx_uart6_hwmod = {
3247 .name = "uart6",
3248 .class = &uart_class,
3249 .clkdm_name = "l4ls_clkdm",
3250 .mpu_irqs = am33xx_uart6_irqs,
3251 .main_clk = "uart6_fck",
3252 .sdma_reqs = uart1_edma_reqs,
3253 .prcm = {
3254 .omap4 = {
3255 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
3256 .modulemode = MODULEMODE_SWCTRL,
3257 },
3258 },
3259 .slaves = am33xx_uart6_slaves,
3260 .slaves_cnt = ARRAY_SIZE(am33xx_uart6_slaves),
3261 };
3263 /* 'wd_timer' class */
3264 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
3265 .name = "wd_timer",
3266 };
3268 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
3269 {
3270 .pa_start = 0x44E35000,
3271 .pa_end = 0x44E35000 + SZ_4K - 1,
3272 .flags = ADDR_TYPE_RT
3273 },
3274 { }
3275 };
3277 /* l4_wkup -> wd_timer1 */
3278 static struct omap_hwmod_ocp_if am33xx_l4wkup__wd_timer1 = {
3279 .master = &am33xx_l4wkup_hwmod,
3280 .slave = &am33xx_wd_timer1_hwmod,
3281 .addr = am33xx_wd_timer1_addrs,
3282 .user = OCP_USER_MPU,
3283 };
3285 static struct omap_hwmod_ocp_if *am33xx_wd_timer1_slaves[] = {
3286 &am33xx_l4wkup__wd_timer1,
3287 };
3289 /*
3290 * TODO: device.c file uses hardcoded name for watchdog timer
3291 * driver "wd_timer2, so we are also using same name as of now...
3292 */
3293 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
3294 .name = "wd_timer2",
3295 .class = &am33xx_wd_timer_hwmod_class,
3296 .clkdm_name = "l4_wkup_clkdm",
3297 .main_clk = "wdt1_fck",
3298 .prcm = {
3299 .omap4 = {
3300 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
3301 .modulemode = MODULEMODE_SWCTRL,
3302 },
3303 },
3304 .slaves = am33xx_wd_timer1_slaves,
3305 .slaves_cnt = ARRAY_SIZE(am33xx_wd_timer1_slaves),
3306 };
3308 /* wkup_m3 */
3309 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
3310 .name = "wkup_m3",
3311 };
3313 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
3314 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
3315 };
3317 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
3318 .name = "wkup_m3",
3319 .class = &am33xx_wkup_m3_hwmod_class,
3320 .clkdm_name = "l4_wkup_aon_clkdm",
3321 .main_clk = "wkup_m3_fck",
3322 .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */
3323 .prcm = {
3324 .omap4 = {
3325 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
3326 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
3327 .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
3328 .modulemode = MODULEMODE_SWCTRL,
3329 },
3330 },
3331 .rst_lines = am33xx_wkup_m3_resets,
3332 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
3333 };
3335 /* usbss */
3336 /* L3 SLOW -> USBSS interface */
3337 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
3338 {
3339 .name = "usbss",
3340 .pa_start = 0x47400000,
3341 .pa_end = 0x47400000 + SZ_4K - 1,
3342 .flags = ADDR_TYPE_RT
3343 },
3344 {
3345 .name = "musb0",
3346 .pa_start = 0x47401000,
3347 .pa_end = 0x47401000 + SZ_2K - 1,
3348 .flags = ADDR_TYPE_RT
3349 },
3350 {
3351 .name = "musb1",
3352 .pa_start = 0x47401800,
3353 .pa_end = 0x47401800 + SZ_2K - 1,
3354 .flags = ADDR_TYPE_RT
3355 },
3356 { }
3357 };
3359 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
3360 .rev_offs = 0x0,
3361 .sysc_offs = 0x10,
3362 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
3363 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3364 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3365 .sysc_fields = &omap_hwmod_sysc_type2,
3366 };
3368 static struct omap_hwmod_class am33xx_usbotg_class = {
3369 .name = "usbotg",
3370 .sysc = &am33xx_usbhsotg_sysc,
3371 };
3373 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
3374 { .name = "usbss-irq", .irq = 17, },
3375 { .name = "musb0-irq", .irq = 18, },
3376 { .name = "musb1-irq", .irq = 19, },
3377 { .irq = -1, },
3378 };
3380 static struct omap_hwmod_ocp_if am33xx_l3_slow__usbss = {
3381 .master = &am33xx_l3slow_hwmod,
3382 .slave = &am33xx_usbss_hwmod,
3383 .clk = "usbotg_ick",
3384 .addr = am33xx_usbss_addr_space,
3385 .user = OCP_USER_MPU,
3386 .flags = OCPIF_SWSUP_IDLE,
3387 };
3389 static struct omap_hwmod_ocp_if *am33xx_usbss_slaves[] = {
3390 &am33xx_l3_slow__usbss,
3391 };
3393 static struct omap_hwmod am33xx_usbss_hwmod = {
3394 .name = "usb_otg_hs",
3395 .class = &am33xx_usbotg_class,
3396 .clkdm_name = "l3s_clkdm",
3397 .mpu_irqs = am33xx_usbss_mpu_irqs,
3398 .main_clk = "usbotg_fck",
3399 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
3400 .prcm = {
3401 .omap4 = {
3402 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
3403 .modulemode = MODULEMODE_SWCTRL,
3404 },
3405 },
3406 .slaves = am33xx_usbss_slaves,
3407 .slaves_cnt = ARRAY_SIZE(am33xx_usbss_slaves),
3408 .class = &am33xx_usbotg_class,
3409 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
3410 };
3412 /* gfx */
3413 /* Pseudo hwmod for reset control purpose only */
3414 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
3415 .name = "gfx",
3416 };
3418 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
3419 { .name = "gfx", .rst_shift = 0, .st_shift = 0 },
3420 };
3422 static struct omap_hwmod am33xx_gfx_hwmod = {
3423 .name = "gfx",
3424 .class = &am33xx_gfx_hwmod_class,
3425 .clkdm_name = "gfx_l3_clkdm",
3426 .main_clk = "gfx_fclk",
3427 .prcm = {
3428 .omap4 = {
3429 .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
3430 .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
3431 .rstst_offs = AM33XX_RM_GFX_RSTST_OFFSET,
3432 .modulemode = MODULEMODE_SWCTRL,
3433 },
3434 },
3435 .rst_lines = am33xx_gfx_resets,
3436 .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
3437 };
3439 /* PRUSS */
3440 /* Pseudo hwmod for reset control purpose only */
3441 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
3442 .name = "pruss",
3443 };
3445 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
3446 { .name = "pruss", .rst_shift = 1 },
3447 };
3449 static struct omap_hwmod am33xx_pruss_hwmod = {
3450 .name = "pruss",
3451 .class = &am33xx_pruss_hwmod_class,
3452 .clkdm_name = "pruss_ocp_clkdm",
3453 .main_clk = "pruss_uart_gclk",
3454 .prcm = {
3455 .omap4 = {
3456 .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
3457 .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
3458 .rstst_offs = AM33XX_RM_PER_RSTST_OFFSET,
3459 .modulemode = MODULEMODE_SWCTRL,
3460 },
3461 },
3462 .rst_lines = am33xx_pruss_resets,
3463 .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
3464 };
3466 static __initdata struct omap_hwmod *am33xx_hwmods[] = {
3467 /* l3 class */
3468 &am33xx_l3_instr_hwmod,
3469 &am33xx_l3_main_hwmod,
3470 /* l3s class */
3471 &am33xx_l3slow_hwmod,
3472 /* l4hs class */
3473 &am33xx_l4_hs_hwmod,
3474 /* l4fw class */
3475 &am33xx_l4fw_hwmod,
3476 /* l4ls class */
3477 &am33xx_l4ls_hwmod,
3478 /* l4per class */
3479 &am33xx_l4per_hwmod,
3480 /* l4wkup class */
3481 &am33xx_l4wkup_hwmod,
3482 /* clkdiv32k class */
3483 &am33xx_clkdiv32k_hwmod,
3484 /* mpu class */
3485 &am33xx_mpu_hwmod,
3486 /* adc_tsc class */
3487 &am33xx_adc_tsc_hwmod,
3488 /* aes class */
3489 &am33xx_aes0_hwmod,
3490 /* cefuse class */
3491 &am33xx_cefuse_hwmod,
3492 /* control class */
3493 &am33xx_control_hwmod,
3494 /* dcan class */
3495 &am33xx_dcan0_hwmod,
3496 &am33xx_dcan1_hwmod,
3497 /* debugss class */
3498 &am33xx_debugss_hwmod,
3499 /* elm class */
3500 &am33xx_elm_hwmod,
3501 /* emif_fw class */
3502 &am33xx_emif_fw_hwmod,
3503 /* epwmss class */
3504 &am33xx_ehrpwm0_hwmod,
3505 &am33xx_ehrpwm1_hwmod,
3506 &am33xx_ehrpwm2_hwmod,
3507 &am33xx_ecap0_hwmod,
3508 &am33xx_ecap1_hwmod,
3509 &am33xx_ecap2_hwmod,
3510 /* gpio class */
3511 &am33xx_gpio0_hwmod,
3512 &am33xx_gpio1_hwmod,
3513 &am33xx_gpio2_hwmod,
3514 &am33xx_gpio3_hwmod,
3515 /* gpmc class */
3516 &am33xx_gpmc_hwmod,
3517 /* i2c class */
3518 &am33xx_i2c1_hwmod,
3519 &am33xx_i2c2_hwmod,
3520 &am33xx_i2c3_hwmod,
3521 /* ieee5000 class */
3522 &am33xx_ieee5000_hwmod,
3523 /* mailbox class */
3524 &am33xx_mailbox_hwmod,
3525 /* mcasp class */
3526 &am33xx_mcasp0_hwmod,
3527 &am33xx_mcasp1_hwmod,
3528 /* mmc class */
3529 &am33xx_mmc0_hwmod,
3530 &am33xx_mmc1_hwmod,
3531 &am33xx_mmc2_hwmod,
3532 /* ocmcram class */
3533 &am33xx_ocmcram_hwmod,
3534 /* ocpwp class */
3535 &am33xx_ocpwp_hwmod,
3536 /* rtc class */
3537 &am33xx_rtc_hwmod,
3538 /* sha0 class */
3539 &am33xx_sha0_hwmod,
3540 /* smartreflex class */
3541 &am33xx_smartreflex0_hwmod,
3542 &am33xx_smartreflex1_hwmod,
3543 /* spi class */
3544 &am33xx_spi0_hwmod,
3545 &am33xx_spi1_hwmod,
3546 /* spinlock class */
3547 &am33xx_spinlock_hwmod,
3548 /* uart class */
3549 &am33xx_uart1_hwmod,
3550 &am33xx_uart2_hwmod,
3551 &am33xx_uart3_hwmod,
3552 &am33xx_uart4_hwmod,
3553 &am33xx_uart5_hwmod,
3554 &am33xx_uart6_hwmod,
3555 /* timer class */
3556 &am33xx_timer0_hwmod,
3557 &am33xx_timer1_hwmod,
3558 &am33xx_timer2_hwmod,
3559 &am33xx_timer3_hwmod,
3560 &am33xx_timer4_hwmod,
3561 &am33xx_timer5_hwmod,
3562 &am33xx_timer6_hwmod,
3563 &am33xx_timer7_hwmod,
3564 /* wkup_m3 class */
3565 &am33xx_wkup_m3_hwmod,
3566 /* wd_timer class */
3567 &am33xx_wd_timer1_hwmod,
3568 /* usbss hwmod */
3569 &am33xx_usbss_hwmod,
3570 /* cpgmac0 class */
3571 &am33xx_cpgmac0_hwmod,
3572 /* mdio class */
3573 &am33xx_mdio_hwmod,
3574 /* tptc class */
3575 &am33xx_tptc0_hwmod,
3576 &am33xx_tptc1_hwmod,
3577 &am33xx_tptc2_hwmod,
3578 /* tpcc class */
3579 &am33xx_tpcc_hwmod,
3580 /* LCDC class */
3581 &am33xx_lcdc_hwmod,
3582 /* gfx/sgx */
3583 &am33xx_gfx_hwmod,
3584 /* pruss */
3585 &am33xx_pruss_hwmod,
3586 NULL,
3587 };
3589 int __init am33xx_hwmod_init(void)
3590 {
3591 return omap_hwmod_register(am33xx_hwmods);
3592 }