1 /*
2 * Hardware modules present on the AM33XX chips
3 *
4 * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
17 #include <linux/io.h>
19 #include <plat/omap_hwmod.h>
20 #include <plat/cpu.h>
21 #include <plat/gpio.h>
22 #include <plat/dma.h>
23 #include <plat/mmc.h>
24 #include <plat/mcspi.h>
26 #include "omap_hwmod_common_data.h"
27 #include "control.h"
28 #include "cm33xx.h"
30 /* Backward references (IPs with Bus Master capability) */
31 static struct omap_hwmod am33xx_mpu_hwmod;
32 static struct omap_hwmod am33xx_l3slow_hwmod;
33 static struct omap_hwmod am33xx_l4wkup_hwmod;
34 static struct omap_hwmod am33xx_l4per_hwmod;
35 static struct omap_hwmod am33xx_uart1_hwmod;
36 static struct omap_hwmod am33xx_uart2_hwmod;
37 static struct omap_hwmod am33xx_uart3_hwmod;
38 static struct omap_hwmod am33xx_uart4_hwmod;
39 static struct omap_hwmod am33xx_uart5_hwmod;
40 static struct omap_hwmod am33xx_uart6_hwmod;
41 static struct omap_hwmod am33xx_timer0_hwmod;
42 static struct omap_hwmod am33xx_timer1_hwmod;
43 static struct omap_hwmod am33xx_timer2_hwmod;
44 static struct omap_hwmod am33xx_timer3_hwmod;
45 static struct omap_hwmod am33xx_timer4_hwmod;
46 static struct omap_hwmod am33xx_timer5_hwmod;
47 static struct omap_hwmod am33xx_timer6_hwmod;
48 static struct omap_hwmod am33xx_timer7_hwmod;
49 static struct omap_hwmod am33xx_wd_timer1_hwmod;
50 static struct omap_hwmod am33xx_cpgmac0_hwmod;
51 static struct omap_hwmod am33xx_icss_hwmod;
52 static struct omap_hwmod am33xx_ieee5000_hwmod;
53 static struct omap_hwmod am33xx_tptc0_hwmod;
54 static struct omap_hwmod am33xx_tptc1_hwmod;
55 static struct omap_hwmod am33xx_tptc2_hwmod;
56 static struct omap_hwmod am33xx_gpio0_hwmod;
57 static struct omap_hwmod am33xx_gpio1_hwmod;
58 static struct omap_hwmod am33xx_gpio2_hwmod;
59 static struct omap_hwmod am33xx_gpio3_hwmod;
60 static struct omap_hwmod am33xx_i2c1_hwmod;
61 static struct omap_hwmod am33xx_i2c2_hwmod;
62 static struct omap_hwmod am33xx_usbss_hwmod;
63 static struct omap_hwmod am33xx_mmc0_hwmod;
64 static struct omap_hwmod am33xx_mmc1_hwmod;
65 static struct omap_hwmod am33xx_mmc2_hwmod;
66 static struct omap_hwmod am33xx_spi0_hwmod;
67 static struct omap_hwmod am33xx_spi1_hwmod;
68 static struct omap_hwmod am33xx_elm_hwmod;
70 /*
71 * Interconnects hwmod structures
72 * hwmods that compose the global AM33XX OCP interconnect
73 */
75 /* MPU -> L3_SLOW Peripheral interface */
76 static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = {
77 .master = &am33xx_mpu_hwmod,
78 .slave = &am33xx_l3slow_hwmod,
79 .user = OCP_USER_MPU,
80 };
82 /* L3 SLOW -> L4_PER Peripheral interface */
83 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = {
84 .master = &am33xx_l3slow_hwmod,
85 .slave = &am33xx_l4per_hwmod,
86 .user = OCP_USER_MPU,
87 };
89 /* L3 SLOW -> L4_WKUP Peripheral interface */
90 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = {
91 .master = &am33xx_l3slow_hwmod,
92 .slave = &am33xx_l4wkup_hwmod,
93 .user = OCP_USER_MPU,
94 };
96 /* Master interfaces on the L4_WKUP interconnect */
97 static struct omap_hwmod_ocp_if *am33xx_l3_slow_masters[] = {
98 &am33xx_l3_slow__l4_per,
99 &am33xx_l3_slow__l4_wkup,
100 };
102 /* Slave interfaces on the L3_SLOW interconnect */
103 static struct omap_hwmod_ocp_if *am33xx_l3_slow_slaves[] = {
104 &am33xx_mpu__l3_slow,
105 };
107 static struct omap_hwmod am33xx_l3slow_hwmod = {
108 .name = "l3_slow",
109 .class = &l3_hwmod_class,
110 .clkdm_name = "l3s_clkdm",
111 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
112 .masters = am33xx_l3_slow_masters,
113 .masters_cnt = ARRAY_SIZE(am33xx_l3_slow_masters),
114 .slaves = am33xx_l3_slow_slaves,
115 .slaves_cnt = ARRAY_SIZE(am33xx_l3_slow_slaves),
116 };
118 /* L4 PER -> GPIO2 */
119 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
120 {
121 .pa_start = AM33XX_GPIO1_BASE,
122 .pa_end = AM33XX_GPIO1_BASE + SZ_4K - 1,
123 .flags = ADDR_TYPE_RT
124 },
125 { }
126 };
128 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
129 .master = &am33xx_l4per_hwmod,
130 .slave = &am33xx_gpio1_hwmod,
131 .clk = "l4ls_fck",
132 .addr = am33xx_gpio1_addrs,
133 .user = OCP_USER_MPU | OCP_USER_SDMA,
134 };
136 /* L4 PER -> GPIO3 */
137 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
138 {
139 .pa_start = AM33XX_GPIO2_BASE,
140 .pa_end = AM33XX_GPIO2_BASE + SZ_4K - 1,
141 .flags = ADDR_TYPE_RT
142 },
143 { }
144 };
146 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
147 .master = &am33xx_l4per_hwmod,
148 .slave = &am33xx_gpio2_hwmod,
149 .clk = "l4ls_fck",
150 .addr = am33xx_gpio2_addrs,
151 .user = OCP_USER_MPU | OCP_USER_SDMA,
152 };
154 /* L4 PER -> GPIO4 */
155 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
156 {
157 .pa_start = AM33XX_GPIO3_BASE,
158 .pa_end = AM33XX_GPIO3_BASE + SZ_4K - 1,
159 .flags = ADDR_TYPE_RT
160 },
161 { }
162 };
164 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
165 .master = &am33xx_l4per_hwmod,
166 .slave = &am33xx_gpio3_hwmod,
167 .clk = "l4ls_fck",
168 .addr = am33xx_gpio3_addrs,
169 .user = OCP_USER_MPU | OCP_USER_SDMA,
170 };
172 /* Master interfaces on the L4_PER interconnect */
173 static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = {
174 &am33xx_l4_per__gpio1,
175 &am33xx_l4_per__gpio2,
176 &am33xx_l4_per__gpio3,
177 };
178 /* Slave interfaces on the L4_PER interconnect */
179 static struct omap_hwmod_ocp_if *am33xx_l4_per_slaves[] = {
180 &am33xx_l3_slow__l4_per,
181 };
183 static struct omap_hwmod am33xx_l4per_hwmod = {
184 .name = "l4_per",
185 .class = &l4_hwmod_class,
186 .clkdm_name = "l4ls_clkdm",
187 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
188 .masters = am33xx_l4_per_masters,
189 .masters_cnt = ARRAY_SIZE(am33xx_l4_per_masters),
190 .slaves = am33xx_l4_per_slaves,
191 .slaves_cnt = ARRAY_SIZE(am33xx_l4_per_slaves),
192 };
194 /* L4 WKUP -> I2C1 */
195 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
196 {
197 .pa_start = AM33XX_I2C0_BASE,
198 .pa_end = AM33XX_I2C0_BASE + SZ_4K - 1,
199 .flags = ADDR_TYPE_RT
200 },
201 { }
202 };
204 static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = {
205 .master = &am33xx_l4wkup_hwmod,
206 .slave = &am33xx_i2c1_hwmod,
207 .addr = am33xx_i2c1_addr_space,
208 .user = OCP_USER_MPU,
209 };
211 /* L4 WKUP -> GPIO1 */
212 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
213 {
214 .pa_start = AM33XX_GPIO0_BASE,
215 .pa_end = AM33XX_GPIO0_BASE + SZ_4K - 1,
216 .flags = ADDR_TYPE_RT
217 },
218 { }
219 };
221 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
222 .master = &am33xx_l4wkup_hwmod,
223 .slave = &am33xx_gpio0_hwmod,
224 .clk = "l4ls_fck",
225 .addr = am33xx_gpio0_addrs,
226 .user = OCP_USER_MPU | OCP_USER_SDMA,
227 };
229 /* Master interfaces on the L4_WKUP interconnect */
230 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = {
231 &am33xx_l4_wkup__gpio0,
232 };
233 /* Slave interfaces on the L4_WKUP interconnect */
234 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_slaves[] = {
235 &am33xx_l3_slow__l4_wkup,
236 };
238 static struct omap_hwmod am33xx_l4wkup_hwmod = {
239 .name = "l4_wkup",
240 .class = &l4_hwmod_class,
241 .clkdm_name = "l4_wkup_clkdm",
242 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
243 .masters = am33xx_l4_wkup_masters,
244 .masters_cnt = ARRAY_SIZE(am33xx_l4_wkup_masters),
245 .slaves = am33xx_l4_wkup_slaves,
246 .slaves_cnt = ARRAY_SIZE(am33xx_l4_wkup_slaves),
247 };
249 /* 'adc_tsc' class */
250 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
251 .name = "adc_tsc",
252 };
254 /* adc_tsc */
255 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
256 { .irq = AM33XX_IRQ_TSC },
257 { .irq = -1 }
258 };
260 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
261 .name = "adc_tsc",
262 .class = &am33xx_adc_tsc_hwmod_class,
263 .mpu_irqs = am33xx_adc_tsc_irqs,
264 .main_clk = "adc_tsc_fck",
265 .clkdm_name = "l4_wkup_clkdm",
266 .prcm = {
267 .omap4 = {
268 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
269 .modulemode = MODULEMODE_SWCTRL,
270 },
271 },
272 };
274 /* 'aes' class */
275 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
276 .name = "aes",
277 };
279 /* aes0 */
280 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
281 { .irq = AM33XX_IRQ_AESEIP36t0_S },
282 { .irq = -1 }
283 };
285 static struct omap_hwmod am33xx_aes0_hwmod = {
286 .name = "aes0",
287 .class = &am33xx_aes_hwmod_class,
288 .mpu_irqs = am33xx_aes0_irqs,
289 .main_clk = "aes0_fck",
290 .clkdm_name = "l3_clkdm",
291 .prcm = {
292 .omap4 = {
293 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
294 .modulemode = MODULEMODE_SWCTRL,
295 },
296 },
297 };
299 /* 'cefuse' class */
300 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
301 .name = "cefuse",
302 };
304 /* cefuse */
305 static struct omap_hwmod am33xx_cefuse_hwmod = {
306 .name = "cefuse",
307 .class = &am33xx_cefuse_hwmod_class,
308 .main_clk = "cefuse_fck",
309 .clkdm_name = "l4_cefuse_clkdm",
310 .prcm = {
311 .omap4 = {
312 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
313 .modulemode = MODULEMODE_SWCTRL,
314 },
315 },
316 };
318 /* 'clkdiv32k' class */
319 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
320 .name = "clkdiv32k",
321 };
323 /* clkdiv32k */
324 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
325 .name = "clkdiv32k",
326 .class = &am33xx_clkdiv32k_hwmod_class,
327 .main_clk = "clkdiv32k_fck",
328 .clkdm_name = "clk_24mhz_clkdm",
329 .prcm = {
330 .omap4 = {
331 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
332 .modulemode = MODULEMODE_SWCTRL,
333 },
334 },
335 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
336 };
338 /* 'control' class */
339 static struct omap_hwmod_class am33xx_control_hwmod_class = {
340 .name = "control",
341 };
343 /* control */
344 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
345 { .irq = AM33XX_IRQ_CONTROL_PLATFORM },
346 { .irq = -1 }
347 };
349 static struct omap_hwmod am33xx_control_hwmod = {
350 .name = "control",
351 .class = &am33xx_control_hwmod_class,
352 .mpu_irqs = am33xx_control_irqs,
353 .main_clk = "control_fck",
354 .clkdm_name = "l4_wkup_clkdm",
355 .prcm = {
356 .omap4 = {
357 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
358 .modulemode = MODULEMODE_SWCTRL,
359 },
360 },
361 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
362 };
364 /* 'cpgmac0' class */
365 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
366 .name = "cpgmac0",
367 };
369 /* cpgmac0 */
370 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
371 .name = "cpgmac0",
372 .class = &am33xx_cpgmac0_hwmod_class,
373 .main_clk = "cpgmac0_fck",
374 .clkdm_name = "cpsw_125mhz_clkdm",
375 .prcm = {
376 .omap4 = {
377 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
378 .modulemode = MODULEMODE_SWCTRL,
379 },
380 },
381 };
383 /* 'dcan' class */
384 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
385 .name = "dcan",
386 };
388 /* dcan0 */
389 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
390 { .irq = AM33XX_IRQ_DCAN0_0 },
391 { .irq = -1 }
392 };
394 static struct omap_hwmod am33xx_dcan0_hwmod = {
395 .name = "dcan0",
396 .class = &am33xx_dcan_hwmod_class,
397 .mpu_irqs = am33xx_dcan0_irqs,
398 .main_clk = "dcan0_fck",
399 .clkdm_name = "l4ls_clkdm",
400 .prcm = {
401 .omap4 = {
402 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
403 .modulemode = MODULEMODE_SWCTRL,
404 },
405 },
406 };
408 /* dcan1 */
409 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
410 { .irq = AM33XX_IRQ_DCAN1_0 },
411 { .irq = -1 }
412 };
413 static struct omap_hwmod am33xx_dcan1_hwmod = {
414 .name = "dcan1",
415 .class = &am33xx_dcan_hwmod_class,
416 .mpu_irqs = am33xx_dcan1_irqs,
417 .main_clk = "dcan1_fck",
418 .clkdm_name = "l4ls_clkdm",
419 .prcm = {
420 .omap4 = {
421 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
422 .modulemode = MODULEMODE_SWCTRL,
423 },
424 },
425 };
427 /* 'debugss' class */
428 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
429 .name = "debugss",
430 };
432 /* debugss */
433 static struct omap_hwmod am33xx_debugss_hwmod = {
434 .name = "debugss",
435 .class = &am33xx_debugss_hwmod_class,
436 .main_clk = "debugss_fck",
437 .clkdm_name = "l3_aon_clkdm",
438 .prcm = {
439 .omap4 = {
440 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
441 .modulemode = MODULEMODE_SWCTRL,
442 },
443 },
444 #ifdef CONFIG_DEBUG_JTAG_ENABLE
445 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
446 #endif
447 };
449 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
450 .rev_offs = 0x0000,
451 .sysc_offs = 0x0010,
452 .syss_offs = 0x0014,
453 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
454 SYSC_HAS_SOFTRESET |
455 SYSS_HAS_RESET_STATUS),
456 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
457 .sysc_fields = &omap_hwmod_sysc_type1,
458 };
459 /* 'elm' class */
460 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
461 .name = "elm",
462 .sysc = &am33xx_elm_sysc,
463 };
465 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
466 { .irq = AM33XX_IRQ_ELM },
467 { .irq = -1 }
468 };
470 struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
471 {
472 .pa_start = AM33XX_ELM_BASE,
473 .pa_end = AM33XX_ELM_BASE + SZ_8K - 1,
474 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
475 },
476 { }
477 };
479 struct omap_hwmod_ocp_if am33xx_l4_core__elm = {
480 .master = &am33xx_l4per_hwmod,
481 .slave = &am33xx_elm_hwmod,
482 .addr = am33xx_elm_addr_space,
483 .user = OCP_USER_MPU,
484 };
486 static struct omap_hwmod_ocp_if *am33xx_elm_slaves[] = {
487 &am33xx_l4_core__elm,
488 };
490 /* elm */
491 static struct omap_hwmod am33xx_elm_hwmod = {
492 .name = "elm",
493 .class = &am33xx_elm_hwmod_class,
494 .mpu_irqs = am33xx_elm_irqs,
495 .main_clk = "elm_fck",
496 .clkdm_name = "l4ls_clkdm",
497 .slaves = am33xx_elm_slaves,
498 .slaves_cnt = ARRAY_SIZE(am33xx_elm_slaves),
499 .prcm = {
500 .omap4 = {
501 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
502 .modulemode = MODULEMODE_SWCTRL,
503 },
504 },
505 };
507 /* 'emif_fw' class */
508 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
509 .name = "emif_fw",
510 };
512 /* emif_fw */
513 static struct omap_hwmod am33xx_emif_fw_hwmod = {
514 .name = "emif_fw",
515 .class = &am33xx_emif_fw_hwmod_class,
516 .main_clk = "emif_fw_fck",
517 .clkdm_name = "l4fw_clkdm",
518 .prcm = {
519 .omap4 = {
520 .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
521 .modulemode = MODULEMODE_SWCTRL,
522 },
523 },
524 .flags = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
525 };
527 /* 'epwmss' class */
528 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
529 .name = "epwmss",
530 };
532 /* epwmss0 */
533 static struct omap_hwmod am33xx_epwmss0_hwmod = {
534 .name = "epwmss0",
535 .class = &am33xx_epwmss_hwmod_class,
536 .main_clk = "epwmss0_fck",
537 .clkdm_name = "l4ls_clkdm",
538 .prcm = {
539 .omap4 = {
540 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
541 .modulemode = MODULEMODE_SWCTRL,
542 },
543 },
544 };
546 /* epwmss1 */
547 static struct omap_hwmod am33xx_epwmss1_hwmod = {
548 .name = "epwmss1",
549 .class = &am33xx_epwmss_hwmod_class,
550 .main_clk = "epwmss1_fck",
551 .clkdm_name = "l4ls_clkdm",
552 .prcm = {
553 .omap4 = {
554 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
555 .modulemode = MODULEMODE_SWCTRL,
556 },
557 },
558 };
560 /* epwmss2 */
561 static struct omap_hwmod am33xx_epwmss2_hwmod = {
562 .name = "epwmss2",
563 .class = &am33xx_epwmss_hwmod_class,
564 .main_clk = "epwmss2_fck",
565 .clkdm_name = "l4ls_clkdm",
566 .prcm = {
567 .omap4 = {
568 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
569 .modulemode = MODULEMODE_SWCTRL,
570 },
571 },
572 };
574 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
575 .rev_offs = 0x0000,
576 .sysc_offs = 0x0010,
577 .syss_offs = 0x0114,
578 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
579 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
580 SYSS_HAS_RESET_STATUS),
581 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
582 SIDLE_SMART_WKUP),
583 .sysc_fields = &omap_hwmod_sysc_type1,
584 };
586 /* 'gpio' class */
587 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
588 .name = "gpio",
589 .sysc = &am33xx_gpio_sysc,
590 .rev = 2,
591 };
593 /* gpio dev_attr */
594 static struct omap_gpio_dev_attr gpio_dev_attr = {
595 .bank_width = 32,
596 .dbck_flag = true,
597 };
599 /* gpio0 */
600 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
601 { .irq = AM33XX_IRQ_GPIO0_1 },
602 { .irq = -1 }
603 };
605 /* gpio0 slave ports */
606 static struct omap_hwmod_ocp_if *am33xx_gpio0_slaves[] = {
607 &am33xx_l4_wkup__gpio0,
608 };
610 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
611 { .role = "dbclk", .clk = "gpio0_dbclk" },
612 };
614 /* gpio0 */
615 static struct omap_hwmod am33xx_gpio0_hwmod = {
616 .name = "gpio1",
617 .class = &am33xx_gpio_hwmod_class,
618 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
619 .mpu_irqs = am33xx_gpio0_irqs,
620 .main_clk = "gpio0_fck",
621 .clkdm_name = "l4_wkup_clkdm",
622 .prcm = {
623 .omap4 = {
624 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
625 .modulemode = MODULEMODE_SWCTRL,
626 },
627 },
628 .opt_clks = gpio0_opt_clks,
629 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
630 .dev_attr = &gpio_dev_attr,
631 .slaves = am33xx_gpio0_slaves,
632 .slaves_cnt = ARRAY_SIZE(am33xx_gpio0_slaves),
633 };
635 /* gpio1 */
636 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
637 { .irq = AM33XX_IRQ_GPIO1_1 },
638 { .irq = -1 }
639 };
641 /* gpio1 slave ports */
642 static struct omap_hwmod_ocp_if *am33xx_gpio1_slaves[] = {
643 &am33xx_l4_per__gpio1,
644 };
646 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
647 { .role = "dbclk", .clk = "gpio1_dbclk" },
648 };
650 static struct omap_hwmod am33xx_gpio1_hwmod = {
651 .name = "gpio2",
652 .class = &am33xx_gpio_hwmod_class,
653 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
654 .mpu_irqs = am33xx_gpio1_irqs,
655 .main_clk = "gpio1_fck",
656 .clkdm_name = "l4ls_clkdm",
657 .prcm = {
658 .omap4 = {
659 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
660 .modulemode = MODULEMODE_SWCTRL,
661 },
662 },
663 .opt_clks = gpio1_opt_clks,
664 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
665 .dev_attr = &gpio_dev_attr,
666 .slaves = am33xx_gpio1_slaves,
667 .slaves_cnt = ARRAY_SIZE(am33xx_gpio1_slaves),
668 };
670 /* gpio2 */
671 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
672 { .irq = AM33XX_IRQ_GPIO2_1 },
673 { .irq = -1 }
674 };
676 /* gpio2 slave ports */
677 static struct omap_hwmod_ocp_if *am33xx_gpio2_slaves[] = {
678 &am33xx_l4_per__gpio2,
679 };
681 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
682 { .role = "dbclk", .clk = "gpio2_dbclk" },
683 };
685 /* gpio2 */
686 static struct omap_hwmod am33xx_gpio2_hwmod = {
687 .name = "gpio3",
688 .class = &am33xx_gpio_hwmod_class,
689 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
690 .mpu_irqs = am33xx_gpio2_irqs,
691 .main_clk = "gpio2_fck",
692 .clkdm_name = "l4ls_clkdm",
693 .prcm = {
694 .omap4 = {
695 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
696 .modulemode = MODULEMODE_SWCTRL,
697 },
698 },
699 .opt_clks = gpio2_opt_clks,
700 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
701 .dev_attr = &gpio_dev_attr,
702 .slaves = am33xx_gpio2_slaves,
703 .slaves_cnt = ARRAY_SIZE(am33xx_gpio2_slaves),
704 };
706 /* gpio3 */
707 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
708 { .irq = AM33XX_IRQ_GPIO3_1 },
709 { .irq = -1 }
710 };
712 /* gpio3 slave ports */
713 static struct omap_hwmod_ocp_if *am33xx_gpio3_slaves[] = {
714 &am33xx_l4_per__gpio3,
715 };
717 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
718 { .role = "dbclk", .clk = "gpio3_dbclk" },
719 };
721 /* gpio3 */
722 static struct omap_hwmod am33xx_gpio3_hwmod = {
723 .name = "gpio4",
724 .class = &am33xx_gpio_hwmod_class,
725 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
726 .mpu_irqs = am33xx_gpio3_irqs,
727 .main_clk = "gpio3_fck",
728 .clkdm_name = "l4ls_clkdm",
729 .prcm = {
730 .omap4 = {
731 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
732 .modulemode = MODULEMODE_SWCTRL,
733 },
734 },
735 .opt_clks = gpio3_opt_clks,
736 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
737 .dev_attr = &gpio_dev_attr,
738 .slaves = am33xx_gpio3_slaves,
739 .slaves_cnt = ARRAY_SIZE(am33xx_gpio3_slaves),
740 };
742 /* 'gpmc' class */
744 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
745 .name = "gpmc",
746 };
748 /* gpmc */
749 static struct omap_hwmod am33xx_gpmc_hwmod = {
750 .name = "gpmc",
751 .class = &am33xx_gpmc_hwmod_class,
752 .main_clk = "gpmc_fck",
753 .clkdm_name = "l3s_clkdm",
754 .prcm = {
755 .omap4 = {
756 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
757 .modulemode = MODULEMODE_SWCTRL,
758 },
759 },
760 };
762 /* 'i2c' class */
764 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
765 .sysc_offs = 0x0010,
766 .syss_offs = 0x0090,
767 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
768 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
769 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
770 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
771 SIDLE_SMART_WKUP),
772 .sysc_fields = &omap_hwmod_sysc_type1,
773 };
775 static struct omap_i2c_dev_attr i2c_dev_attr = {
776 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
777 };
779 static struct omap_hwmod_class i2c_class = {
780 .name = "i2c",
781 .sysc = &am33xx_i2c_sysc,
782 .rev = OMAP_I2C_IP_VERSION_2,
783 .reset = &omap_i2c_reset,
784 };
786 /* I2C1 */
787 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
788 { .irq = AM33XX_IRQ_MSHSI2COCP0 },
789 { .irq = -1 }
790 };
792 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
793 { .name = "tx", .dma_req = 0, },
794 { .name = "rx", .dma_req = 0, },
795 { .dma_req = -1 }
796 };
798 static struct omap_hwmod_ocp_if *am33xx_i2c1_slaves[] = {
799 &am33xx_l4_wkup_i2c1,
800 };
802 static struct omap_hwmod am33xx_i2c1_hwmod = {
803 .name = "i2c1",
804 .mpu_irqs = i2c1_mpu_irqs,
805 .sdma_reqs = i2c1_edma_reqs,
806 .main_clk = "i2c1_fck",
807 .clkdm_name = "l4_wkup_clkdm",
808 .prcm = {
809 .omap4 = {
810 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
811 .modulemode = MODULEMODE_SWCTRL,
812 },
813 },
814 .flags = HWMOD_16BIT_REG,
815 .dev_attr = &i2c_dev_attr,
816 .slaves = am33xx_i2c1_slaves,
817 .slaves_cnt = ARRAY_SIZE(am33xx_i2c1_slaves),
818 .class = &i2c_class,
819 };
821 /* i2c2 */
822 /* l4 per -> i2c2 */
823 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
824 {
825 .pa_start = AM33XX_I2C1_BASE,
826 .pa_end = AM33XX_I2C1_BASE + SZ_4K - 1,
827 .flags = ADDR_TYPE_RT
828 },
829 { }
830 };
832 static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = {
833 .master = &am33xx_l4per_hwmod,
834 .slave = &am33xx_i2c2_hwmod,
835 .addr = am33xx_i2c2_addr_space,
836 .user = OCP_USER_MPU,
837 };
839 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
840 { .irq = AM33XX_IRQ_MSHSI2COCP1 },
841 { .irq = -1 }
842 };
844 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
845 { .name = "tx", .dma_req = 0, },
846 { .name = "rx", .dma_req = 0, },
847 { .dma_req = -1 }
848 };
850 static struct omap_hwmod_ocp_if *am33xx_i2c2_slaves[] = {
851 &am335_l4_per_i2c2,
852 };
854 static struct omap_hwmod am33xx_i2c2_hwmod = {
855 .name = "i2c2",
856 .mpu_irqs = i2c2_mpu_irqs,
857 .sdma_reqs = i2c2_edma_reqs,
858 .main_clk = "i2c2_fck",
859 .clkdm_name = "l4ls_clkdm",
860 .prcm = {
861 .omap4 = {
862 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
863 .modulemode = MODULEMODE_SWCTRL,
864 },
865 },
866 .flags = HWMOD_16BIT_REG,
867 .dev_attr = &i2c_dev_attr,
868 .slaves = am33xx_i2c2_slaves,
869 .slaves_cnt = ARRAY_SIZE(am33xx_i2c2_slaves),
870 .class = &i2c_class,
871 };
873 /* 'icss' class */
874 static struct omap_hwmod_class am33xx_icss_hwmod_class = {
875 .name = "icss",
876 };
878 /* icss */
879 static struct omap_hwmod am33xx_icss_hwmod = {
880 .name = "icss",
881 .class = &am33xx_icss_hwmod_class,
882 .main_clk = "icss_fck",
883 .clkdm_name = "icss_ocp_clkdm",
884 .prcm = {
885 .omap4 = {
886 .clkctrl_offs = AM33XX_CM_PER_ICSS_CLKCTRL_OFFSET,
887 .modulemode = MODULEMODE_SWCTRL,
888 },
889 },
890 };
892 /* 'ieee5000' class */
893 static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = {
894 .name = "ieee5000",
895 };
897 /* ieee5000 */
898 static struct omap_hwmod am33xx_ieee5000_hwmod = {
899 .name = "ieee5000",
900 .class = &am33xx_ieee5000_hwmod_class,
901 .main_clk = "ieee5000_fck",
902 .clkdm_name = "l3s_clkdm",
903 .prcm = {
904 .omap4 = {
905 .clkctrl_offs = AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET,
906 .modulemode = MODULEMODE_SWCTRL,
907 },
908 },
909 };
912 /* 'l3' class */
913 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
914 .name = "l3",
915 };
917 /* l4_hs */
918 static struct omap_hwmod am33xx_l4_hs_hwmod = {
919 .name = "l4_hs",
920 .class = &am33xx_l3_hwmod_class,
921 .clkdm_name = "l4hs_clkdm",
922 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
923 .prcm = {
924 .omap4 = {
925 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
926 .modulemode = MODULEMODE_SWCTRL,
927 },
928 },
929 };
931 /* l3_instr */
932 static struct omap_hwmod am33xx_l3_instr_hwmod = {
933 .name = "l3_instr",
934 .class = &am33xx_l3_hwmod_class,
935 .clkdm_name = "l3_clkdm",
936 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
937 .prcm = {
938 .omap4 = {
939 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
940 .modulemode = MODULEMODE_SWCTRL,
941 },
942 },
943 };
945 /* l3_main */
946 static struct omap_hwmod am33xx_l3_main_hwmod = {
947 .name = "l3_main",
948 .class = &am33xx_l3_hwmod_class,
949 .clkdm_name = "l3_clkdm",
950 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
951 .prcm = {
952 .omap4 = {
953 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
954 .modulemode = MODULEMODE_SWCTRL,
955 },
956 },
957 };
959 /* 'l4fw' class */
960 static struct omap_hwmod_class am33xx_l4fw_hwmod_class = {
961 .name = "l4fw",
962 };
964 /* l4fw */
965 static struct omap_hwmod am33xx_l4fw_hwmod = {
966 .name = "l4fw",
967 .class = &am33xx_l4fw_hwmod_class,
968 .clkdm_name = "l4fw_clkdm",
969 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
970 .prcm = {
971 .omap4 = {
972 .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
973 .modulemode = MODULEMODE_SWCTRL,
974 },
975 },
976 };
978 /* 'l4ls' class */
979 static struct omap_hwmod_class am33xx_l4ls_hwmod_class = {
980 .name = "l4ls",
981 };
983 /* l4ls */
984 static struct omap_hwmod am33xx_l4ls_hwmod = {
985 .name = "l4ls",
986 .class = &am33xx_l4ls_hwmod_class,
987 .main_clk = "l4ls_fck",
988 .clkdm_name = "l4ls_clkdm",
989 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
990 .prcm = {
991 .omap4 = {
992 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
993 .modulemode = MODULEMODE_SWCTRL,
994 },
995 },
996 };
998 /* 'lcdc' class */
999 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1000 .name = "lcdc",
1001 };
1003 /* lcdc */
1004 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1005 { .irq = AM33XX_IRQ_LCD },
1006 { .irq = -1 }
1007 };
1009 static struct omap_hwmod am33xx_lcdc_hwmod = {
1010 .name = "lcdc",
1011 .class = &am33xx_lcdc_hwmod_class,
1012 .mpu_irqs = am33xx_lcdc_irqs,
1013 .main_clk = "lcdc_fck",
1014 .clkdm_name = "lcdc_clkdm",
1015 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1016 .prcm = {
1017 .omap4 = {
1018 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1019 .modulemode = MODULEMODE_SWCTRL,
1020 },
1021 },
1022 };
1024 /*
1025 * 'mailbox' class
1026 * mailbox module allowing communication between the on-chip processors using a
1027 * queued mailbox-interrupt mechanism.
1028 */
1030 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1031 .rev_offs = 0x0000,
1032 .sysc_offs = 0x0010,
1033 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1034 SYSC_HAS_SOFTRESET),
1035 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1036 .sysc_fields = &omap_hwmod_sysc_type2,
1037 };
1039 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1040 .name = "mailbox",
1041 .sysc = &am33xx_mailbox_sysc,
1042 };
1044 /* mailbox */
1045 static struct omap_hwmod am33xx_mailbox_hwmod;
1046 static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1047 { .irq = AM33XX_IRQ_MAILBOX },
1048 { .irq = -1 }
1049 };
1051 static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
1052 {
1053 .pa_start = AM33XX_MAILBOX0_BASE,
1054 .pa_end = AM33XX_MAILBOX0_BASE + (SZ_4K - 1),
1055 .flags = ADDR_TYPE_RT
1056 },
1057 { }
1058 };
1060 /* l4_cfg -> mailbox */
1061 static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
1062 .master = &am33xx_l4per_hwmod,
1063 .slave = &am33xx_mailbox_hwmod,
1064 .addr = am33xx_mailbox_addrs,
1065 .user = OCP_USER_MPU,
1066 };
1068 /* mailbox slave ports */
1069 static struct omap_hwmod_ocp_if *am33xx_mailbox_slaves[] = {
1070 &am33xx_l4_per__mailbox,
1071 };
1073 static struct omap_hwmod am33xx_mailbox_hwmod = {
1074 .name = "mailbox",
1075 .class = &am33xx_mailbox_hwmod_class,
1076 .clkdm_name = "l4ls_clkdm",
1077 .mpu_irqs = am33xx_mailbox_irqs,
1078 .main_clk = "mailbox0_fck",
1079 .prcm = {
1080 .omap4 = {
1081 .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1082 .modulemode = MODULEMODE_SWCTRL,
1083 },
1084 },
1085 .slaves = am33xx_mailbox_slaves,
1086 .slaves_cnt = ARRAY_SIZE(am33xx_mailbox_slaves),
1087 };
1089 /* 'mcasp' class */
1090 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1091 .name = "mcasp",
1092 };
1094 /* mcasp0 */
1095 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1096 { .irq = 80 },
1097 { .irq = -1 }
1098 };
1100 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1101 .name = "mcasp0",
1102 .class = &am33xx_mcasp_hwmod_class,
1103 .mpu_irqs = am33xx_mcasp0_irqs,
1104 .main_clk = "mcasp0_fck",
1105 .clkdm_name = "l3s_clkdm",
1106 .prcm = {
1107 .omap4 = {
1108 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1109 .modulemode = MODULEMODE_SWCTRL,
1110 },
1111 },
1112 };
1114 /* 'mmc' class */
1116 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1117 .rev_offs = 0x1fc,
1118 .sysc_offs = 0x10,
1119 .syss_offs = 0x14,
1120 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1121 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1122 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1123 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1124 .sysc_fields = &omap_hwmod_sysc_type1,
1125 };
1127 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1128 .name = "mmc",
1129 .sysc = &am33xx_mmc_sysc,
1130 };
1132 /* mmc0 */
1133 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1134 { .irq = AM33XX_IRQ_MMCHS0 },
1135 { .irq = -1 }
1136 };
1138 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1139 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS0_W, },
1140 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS0_R, },
1141 { .dma_req = -1 }
1142 };
1144 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
1145 {
1146 .pa_start = AM33XX_MMC0_BASE,
1147 .pa_end = AM33XX_MMC0_BASE + SZ_4K - 1,
1148 .flags = ADDR_TYPE_RT
1149 },
1150 { }
1151 };
1153 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc0 = {
1154 .master = &am33xx_l4ls_hwmod,
1155 .slave = &am33xx_mmc0_hwmod,
1156 .clk = "mmc0_ick",
1157 .addr = am33xx_mmc0_addr_space,
1158 .user = OCP_USER_MPU,
1159 };
1161 static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = {
1162 &am33xx_l4ls__mmc0,
1163 };
1165 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1166 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1167 };
1169 static struct omap_hwmod am33xx_mmc0_hwmod = {
1170 .name = "mmc1",
1171 .class = &am33xx_mmc_hwmod_class,
1172 .mpu_irqs = am33xx_mmc0_irqs,
1173 .sdma_reqs = am33xx_mmc0_edma_reqs,
1174 .main_clk = "mmc0_fck",
1175 .clkdm_name = "l4ls_clkdm",
1176 .prcm = {
1177 .omap4 = {
1178 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1179 .modulemode = MODULEMODE_SWCTRL,
1180 },
1181 },
1182 .dev_attr = &am33xx_mmc0_dev_attr,
1183 .slaves = am33xx_mmc0_slaves,
1184 .slaves_cnt = ARRAY_SIZE(am33xx_mmc0_slaves),
1185 };
1187 /* mmc1 */
1188 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1189 { .irq = AM33XX_IRQ_MMCHS1 },
1190 { .irq = -1 }
1191 };
1193 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1194 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS1_W, },
1195 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS1_R, },
1196 { .dma_req = -1 }
1197 };
1199 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
1200 {
1201 .pa_start = AM33XX_MMC1_BASE,
1202 .pa_end = AM33XX_MMC1_BASE + SZ_4K - 1,
1203 .flags = ADDR_TYPE_RT
1204 },
1205 { }
1206 };
1208 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc1 = {
1209 .master = &am33xx_l4ls_hwmod,
1210 .slave = &am33xx_mmc1_hwmod,
1211 .clk = "mmc1_ick",
1212 .addr = am33xx_mmc1_addr_space,
1213 .user = OCP_USER_MPU,
1214 };
1216 static struct omap_hwmod_ocp_if *am33xx_mmc1_slaves[] = {
1217 &am33xx_l4ls__mmc1,
1218 };
1220 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1221 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1222 };
1224 static struct omap_hwmod am33xx_mmc1_hwmod = {
1225 .name = "mmc2",
1226 .class = &am33xx_mmc_hwmod_class,
1227 .mpu_irqs = am33xx_mmc1_irqs,
1228 .sdma_reqs = am33xx_mmc1_edma_reqs,
1229 .main_clk = "mmc1_fck",
1230 .clkdm_name = "l4ls_clkdm",
1231 .prcm = {
1232 .omap4 = {
1233 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1234 .modulemode = MODULEMODE_SWCTRL,
1235 },
1236 },
1237 .dev_attr = &am33xx_mmc1_dev_attr,
1238 .slaves = am33xx_mmc1_slaves,
1239 .slaves_cnt = ARRAY_SIZE(am33xx_mmc1_slaves),
1240 };
1242 /* mmc2 */
1243 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1244 { .irq = AM33XX_IRQ_MMCHS2 },
1245 { .irq = -1 }
1246 };
1248 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1249 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS2_W, },
1250 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS2_R, },
1251 { .dma_req = -1 }
1252 };
1254 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
1255 {
1256 .pa_start = AM33XX_MMC2_BASE,
1257 .pa_end = AM33XX_MMC2_BASE + SZ_64K - 1,
1258 .flags = ADDR_TYPE_RT
1259 },
1260 { }
1261 };
1263 static struct omap_hwmod_ocp_if am33xx_l3_main__mmc2 = {
1264 .master = &am33xx_l3_main_hwmod,
1265 .slave = &am33xx_mmc2_hwmod,
1266 .clk = "mmc2_ick",
1267 .addr = am33xx_mmc2_addr_space,
1268 .user = OCP_USER_MPU,
1269 };
1271 static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = {
1272 &am33xx_l3_main__mmc2,
1273 };
1275 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1276 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1277 };
1278 static struct omap_hwmod am33xx_mmc2_hwmod = {
1279 .name = "mmc3",
1280 .class = &am33xx_mmc_hwmod_class,
1281 .mpu_irqs = am33xx_mmc2_irqs,
1282 .sdma_reqs = am33xx_mmc2_edma_reqs,
1283 .main_clk = "mmc2_fck",
1284 .clkdm_name = "l3s_clkdm",
1285 .prcm = {
1286 .omap4 = {
1287 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1288 .modulemode = MODULEMODE_SWCTRL,
1289 },
1290 },
1291 .dev_attr = &am33xx_mmc2_dev_attr,
1292 .slaves = am33xx_mmc2_slaves,
1293 .slaves_cnt = ARRAY_SIZE(am33xx_mmc2_slaves),
1294 };
1296 /* Master interfaces on the MPU interconnect */
1297 static struct omap_hwmod_ocp_if *am33xx_l3_mpu_masters[] = {
1298 &am33xx_mpu__l3_slow,
1299 };
1301 /* mpu */
1302 static struct omap_hwmod am33xx_mpu_hwmod = {
1303 .name = "mpu",
1304 .class = &mpu_hwmod_class,
1305 .masters = am33xx_l3_mpu_masters,
1306 .masters_cnt = ARRAY_SIZE(am33xx_l3_mpu_masters),
1307 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1308 .main_clk = "mpu_fck",
1309 .clkdm_name = "mpu_clkdm",
1310 .prcm = {
1311 .omap4 = {
1312 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1313 .modulemode = MODULEMODE_SWCTRL,
1314 },
1315 },
1316 };
1318 /* 'ocmcram' class */
1319 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
1320 .name = "ocmcram",
1321 };
1323 /* ocmcram */
1324 static struct omap_hwmod am33xx_ocmcram_hwmod = {
1325 .name = "ocmcram",
1326 .class = &am33xx_ocmcram_hwmod_class,
1327 .main_clk = "ocmcram_fck",
1328 .clkdm_name = "l3_clkdm",
1329 .prcm = {
1330 .omap4 = {
1331 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
1332 .modulemode = MODULEMODE_SWCTRL,
1333 },
1334 },
1335 };
1337 /* 'ocpwp' class */
1338 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
1339 .name = "ocpwp",
1340 };
1342 /* ocpwp */
1343 static struct omap_hwmod am33xx_ocpwp_hwmod = {
1344 .name = "ocpwp",
1345 .class = &am33xx_ocpwp_hwmod_class,
1346 .main_clk = "ocpwp_fck",
1347 .clkdm_name = "l4ls_clkdm",
1348 .prcm = {
1349 .omap4 = {
1350 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
1351 .modulemode = MODULEMODE_SWCTRL,
1352 },
1353 },
1354 };
1356 /* 'rtc' class */
1357 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1358 .name = "rtc",
1359 };
1361 /* rtc */
1362 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1363 { .irq = AM33XX_IRQ_RTC_TIMER },
1364 { .irq = -1 }
1365 };
1367 static struct omap_hwmod am33xx_rtc_hwmod = {
1368 .name = "rtc",
1369 .class = &am33xx_rtc_hwmod_class,
1370 .mpu_irqs = am33xx_rtc_irqs,
1371 .main_clk = "rtc_fck",
1372 .clkdm_name = "l4_rtc_clkdm",
1373 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1374 .prcm = {
1375 .omap4 = {
1376 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1377 .modulemode = MODULEMODE_SWCTRL,
1378 },
1379 },
1380 };
1382 /* 'sha0' class */
1383 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
1384 .name = "sha0",
1385 };
1387 /* sha0 */
1388 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
1389 { .irq = AM33XX_IRQ_SHAEIP57t0_S },
1390 { .irq = -1 }
1391 };
1393 static struct omap_hwmod am33xx_sha0_hwmod = {
1394 .name = "sha0",
1395 .class = &am33xx_sha0_hwmod_class,
1396 .mpu_irqs = am33xx_sha0_irqs,
1397 .main_clk = "sha0_fck",
1398 .clkdm_name = "l3_clkdm",
1399 .prcm = {
1400 .omap4 = {
1401 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
1402 .modulemode = MODULEMODE_SWCTRL,
1403 },
1404 },
1405 };
1407 /* 'smartreflex' class */
1408 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
1409 .name = "smartreflex",
1410 };
1412 /* smartreflex0 */
1413 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
1414 { .irq = AM33XX_IRQ_SMARTREFLEX0 },
1415 { .irq = -1 }
1416 };
1418 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
1419 .name = "smartreflex0",
1420 .class = &am33xx_smartreflex_hwmod_class,
1421 .mpu_irqs = am33xx_smartreflex0_irqs,
1422 .main_clk = "smartreflex0_fck",
1423 .clkdm_name = "l4_wkup_clkdm",
1424 .prcm = {
1425 .omap4 = {
1426 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
1427 .modulemode = MODULEMODE_SWCTRL,
1428 },
1429 },
1430 };
1432 /* smartreflex1 */
1433 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
1434 { .irq = AM33XX_IRQ_SMARTREFLEX1 },
1435 { .irq = -1 }
1436 };
1438 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
1439 .name = "smartreflex1",
1440 .class = &am33xx_smartreflex_hwmod_class,
1441 .mpu_irqs = am33xx_smartreflex1_irqs,
1442 .main_clk = "smartreflex1_fck",
1443 .clkdm_name = "l4_wkup_clkdm",
1444 .prcm = {
1445 .omap4 = {
1446 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
1447 .modulemode = MODULEMODE_SWCTRL,
1448 },
1449 },
1450 };
1452 /* 'spi' class */
1454 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1455 .rev_offs = 0x0000,
1456 .sysc_offs = 0x0110,
1457 .syss_offs = 0x0114,
1458 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1459 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1460 SYSS_HAS_RESET_STATUS),
1461 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1462 .sysc_fields = &omap_hwmod_sysc_type1,
1463 };
1465 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1466 .name = "mcspi",
1467 .sysc = &am33xx_mcspi_sysc,
1468 .rev = OMAP4_MCSPI_REV,
1469 };
1471 /* spi0 */
1472 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1473 { .irq = AM33XX_IRQ_MCSPIOCP0 },
1474 { .irq = -1 }
1475 };
1477 struct omap_hwmod_dma_info am33xx_mcspi0_sdma_reqs[] = {
1478 { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0R },
1479 { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0W },
1480 { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1R },
1481 { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1W },
1482 { .dma_req = -1 }
1483 };
1485 struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
1486 {
1487 .pa_start = AM33XX_SPI0_BASE,
1488 .pa_end = AM33XX_SPI0_BASE + SZ_1K - 1,
1489 .flags = ADDR_TYPE_RT
1490 },
1491 { }
1492 };
1494 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = {
1495 .master = &am33xx_l4per_hwmod,
1496 .slave = &am33xx_spi0_hwmod,
1497 .clk = "spi0_ick",
1498 .addr = am33xx_mcspi0_addr_space,
1499 .user = OCP_USER_MPU,
1500 };
1502 static struct omap_hwmod_ocp_if *am33xx_mcspi0_slaves[] = {
1503 &am33xx_l4_core__mcspi0,
1504 };
1506 struct omap2_mcspi_dev_attr mcspi_attrib = {
1507 .num_chipselect = 2,
1508 };
1509 static struct omap_hwmod am33xx_spi0_hwmod = {
1510 .name = "spi0",
1511 .class = &am33xx_spi_hwmod_class,
1512 .mpu_irqs = am33xx_spi0_irqs,
1513 .sdma_reqs = am33xx_mcspi0_sdma_reqs,
1514 .main_clk = "spi0_fck",
1515 .clkdm_name = "l4ls_clkdm",
1516 .prcm = {
1517 .omap4 = {
1518 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1519 .modulemode = MODULEMODE_SWCTRL,
1520 },
1521 },
1522 .dev_attr = &mcspi_attrib,
1523 .slaves = am33xx_mcspi0_slaves,
1524 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi0_slaves),
1525 };
1527 /* spi1 */
1528 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1529 { .irq = AM33XX_IRQ_SPI1 },
1530 { .irq = -1 }
1531 };
1533 struct omap_hwmod_dma_info am33xx_mcspi1_sdma_reqs[] = {
1534 { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0R },
1535 { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0W },
1536 { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1R },
1537 { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1W },
1538 { .dma_req = -1 }
1539 };
1541 struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
1542 {
1543 .pa_start = AM33XX_SPI1_BASE,
1544 .pa_end = AM33XX_SPI1_BASE + SZ_1K - 1,
1545 .flags = ADDR_TYPE_RT
1546 },
1547 { }
1548 };
1550 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = {
1551 .master = &am33xx_l4per_hwmod,
1552 .slave = &am33xx_spi1_hwmod,
1553 .clk = "spi1_ick",
1554 .addr = am33xx_mcspi1_addr_space,
1555 .user = OCP_USER_MPU,
1556 };
1558 static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = {
1559 &am33xx_l4_core__mcspi1,
1560 };
1561 static struct omap_hwmod am33xx_spi1_hwmod = {
1562 .name = "spi1",
1563 .class = &am33xx_spi_hwmod_class,
1564 .mpu_irqs = am33xx_spi1_irqs,
1565 .sdma_reqs = am33xx_mcspi1_sdma_reqs,
1566 .main_clk = "spi1_fck",
1567 .clkdm_name = "l4ls_clkdm",
1568 .prcm = {
1569 .omap4 = {
1570 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1571 .modulemode = MODULEMODE_SWCTRL,
1572 },
1573 },
1574 .dev_attr = &mcspi_attrib,
1575 .slaves = am33xx_mcspi1_slaves,
1576 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi1_slaves),
1577 };
1579 /* 'spinlock' class */
1580 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1581 .name = "spinlock",
1582 };
1584 /* spinlock */
1585 static struct omap_hwmod am33xx_spinlock_hwmod = {
1586 .name = "spinlock",
1587 .class = &am33xx_spinlock_hwmod_class,
1588 .main_clk = "spinlock_fck",
1589 .clkdm_name = "l4ls_clkdm",
1590 .prcm = {
1591 .omap4 = {
1592 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1593 .modulemode = MODULEMODE_SWCTRL,
1594 },
1595 },
1596 };
1598 /* 'timer 0 & 2-7' class */
1599 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1600 .rev_offs = 0x0000,
1601 .sysc_offs = 0x0010,
1602 .syss_offs = 0x0014,
1603 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1604 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1605 SIDLE_SMART_WKUP),
1606 .sysc_fields = &omap_hwmod_sysc_type2,
1607 };
1609 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1610 .name = "timer",
1611 .sysc = &am33xx_timer_sysc,
1612 };
1614 /* timer0 */
1615 /* l4 wkup -> timer0 interface */
1616 static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = {
1617 {
1618 .pa_start = AM33XX_TIMER0_BASE,
1619 .pa_end = AM33XX_TIMER0_BASE + SZ_1K - 1,
1620 .flags = ADDR_TYPE_RT
1621 },
1622 { }
1623 };
1625 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = {
1626 .master = &am33xx_l4wkup_hwmod,
1627 .slave = &am33xx_timer0_hwmod,
1628 .clk = "timer0_ick",
1629 .addr = am33xx_timer0_addr_space,
1630 .user = OCP_USER_MPU,
1631 };
1633 static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = {
1634 &am33xx_l4wkup__timer0,
1635 };
1637 static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = {
1638 { .irq = AM33XX_IRQ_DMTIMER0 },
1639 { .irq = -1 }
1640 };
1642 static struct omap_hwmod am33xx_timer0_hwmod = {
1643 .name = "timer0",
1644 .class = &am33xx_timer_hwmod_class,
1645 .mpu_irqs = am33xx_timer0_irqs,
1646 .main_clk = "timer0_fck",
1647 .clkdm_name = "l4_wkup_clkdm",
1648 .prcm = {
1649 .omap4 = {
1650 .clkctrl_offs = AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET,
1651 .modulemode = MODULEMODE_SWCTRL,
1652 },
1653 },
1654 .slaves = am33xx_timer0_slaves,
1655 .slaves_cnt = ARRAY_SIZE(am33xx_timer0_slaves),
1656 };
1658 /* timer1 1ms */
1659 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1660 .rev_offs = 0x0000,
1661 .sysc_offs = 0x0010,
1662 .syss_offs = 0x0014,
1663 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1664 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1665 SYSS_HAS_RESET_STATUS),
1666 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1667 .sysc_fields = &omap_hwmod_sysc_type1,
1668 };
1670 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1671 .name = "timer",
1672 .sysc = &am33xx_timer1ms_sysc,
1673 };
1675 /* l4 wkup -> timer1 interface */
1676 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
1677 {
1678 .pa_start = AM33XX_TIMER1_BASE,
1679 .pa_end = AM33XX_TIMER1_BASE + SZ_1K - 1,
1680 .flags = ADDR_TYPE_RT
1681 },
1682 { }
1683 };
1685 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = {
1686 .master = &am33xx_l4wkup_hwmod,
1687 .slave = &am33xx_timer1_hwmod,
1688 .clk = "timer1_ick",
1689 .addr = am33xx_timer1_addr_space,
1690 .user = OCP_USER_MPU,
1691 };
1693 static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = {
1694 &am33xx_l4wkup__timer1,
1695 };
1697 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
1698 { .irq = AM33XX_IRQ_DMTIMER1 },
1699 { .irq = -1 }
1700 };
1702 static struct omap_hwmod am33xx_timer1_hwmod = {
1703 .name = "timer1",
1704 .class = &am33xx_timer1ms_hwmod_class,
1705 .mpu_irqs = am33xx_timer1_irqs,
1706 .main_clk = "timer1_fck",
1707 .clkdm_name = "l4_wkup_clkdm",
1708 .prcm = {
1709 .omap4 = {
1710 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1711 .modulemode = MODULEMODE_SWCTRL,
1712 },
1713 },
1714 .slaves = am33xx_timer1_slaves,
1715 .slaves_cnt = ARRAY_SIZE(am33xx_timer1_slaves),
1716 };
1718 /* timer2 */
1719 /* l4 per -> timer2 interface */
1720 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
1721 {
1722 .pa_start = AM33XX_TIMER2_BASE,
1723 .pa_end = AM33XX_TIMER2_BASE + SZ_1K - 1,
1724 .flags = ADDR_TYPE_RT
1725 },
1726 { }
1727 };
1729 static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = {
1730 .master = &am33xx_l4per_hwmod,
1731 .slave = &am33xx_timer2_hwmod,
1732 .clk = "timer2_ick",
1733 .addr = am33xx_timer2_addr_space,
1734 .user = OCP_USER_MPU,
1735 };
1737 static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = {
1738 &am33xx_l4per__timer2,
1739 };
1741 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
1742 { .irq = AM33XX_IRQ_DMTIMER2 },
1743 { .irq = -1 }
1744 };
1746 static struct omap_hwmod am33xx_timer2_hwmod = {
1747 .name = "timer2",
1748 .class = &am33xx_timer_hwmod_class,
1749 .mpu_irqs = am33xx_timer2_irqs,
1750 .main_clk = "timer2_fck",
1751 .prcm = {
1752 .omap4 = {
1753 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1754 .modulemode = MODULEMODE_SWCTRL,
1755 },
1756 },
1757 .slaves = am33xx_timer2_slaves,
1758 .slaves_cnt = ARRAY_SIZE(am33xx_timer2_slaves),
1759 .clkdm_name = "l4ls_clkdm",
1760 };
1762 /* timer3 */
1763 /* l4 per -> timer3 interface */
1764 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
1765 {
1766 .pa_start = AM33XX_TIMER3_BASE,
1767 .pa_end = AM33XX_TIMER3_BASE + SZ_1K - 1,
1768 .flags = ADDR_TYPE_RT
1769 },
1770 { }
1771 };
1773 static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = {
1774 .master = &am33xx_l4per_hwmod,
1775 .slave = &am33xx_timer3_hwmod,
1776 .clk = "timer3_ick",
1777 .addr = am33xx_timer3_addr_space,
1778 .user = OCP_USER_MPU,
1779 };
1781 static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = {
1782 &am33xx_l4per__timer3,
1783 };
1785 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
1786 { .irq = AM33XX_IRQ_DMTIMER3 },
1787 { .irq = -1 }
1788 };
1790 static struct omap_hwmod am33xx_timer3_hwmod = {
1791 .name = "timer3",
1792 .class = &am33xx_timer_hwmod_class,
1793 .mpu_irqs = am33xx_timer3_irqs,
1794 .main_clk = "timer3_fck",
1795 .clkdm_name = "l4ls_clkdm",
1796 .prcm = {
1797 .omap4 = {
1798 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1799 .modulemode = MODULEMODE_SWCTRL,
1800 },
1801 },
1802 .slaves = am33xx_timer3_slaves,
1803 .slaves_cnt = ARRAY_SIZE(am33xx_timer3_slaves),
1804 };
1806 /* timer4 */
1807 /* l4 per -> timer4 interface */
1808 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
1809 {
1810 .pa_start = AM33XX_TIMER4_BASE,
1811 .pa_end = AM33XX_TIMER4_BASE + SZ_1K - 1,
1812 .flags = ADDR_TYPE_RT
1813 },
1814 { }
1815 };
1817 static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = {
1818 .master = &am33xx_l4per_hwmod,
1819 .slave = &am33xx_timer4_hwmod,
1820 .clk = "timer4_ick",
1821 .addr = am33xx_timer4_addr_space,
1822 .user = OCP_USER_MPU,
1823 };
1825 static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = {
1826 &am33xx_l4per__timer4,
1827 };
1829 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
1830 { .irq = AM33XX_IRQ_DMTIMER4 },
1831 { .irq = -1 }
1832 };
1834 static struct omap_hwmod am33xx_timer4_hwmod = {
1835 .name = "timer4",
1836 .class = &am33xx_timer_hwmod_class,
1837 .mpu_irqs = am33xx_timer4_irqs,
1838 .main_clk = "timer4_fck",
1839 .prcm = {
1840 .omap4 = {
1841 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1842 .modulemode = MODULEMODE_SWCTRL,
1843 },
1844 },
1845 .slaves = am33xx_timer4_slaves,
1846 .slaves_cnt = ARRAY_SIZE(am33xx_timer4_slaves),
1847 .clkdm_name = "l4ls_clkdm",
1848 };
1851 /* timer5 */
1852 /* l4 per -> timer5 interface */
1853 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
1854 {
1855 .pa_start = AM33XX_TIMER5_BASE,
1856 .pa_end = AM33XX_TIMER5_BASE + SZ_1K - 1,
1857 .flags = ADDR_TYPE_RT
1858 },
1859 { }
1860 };
1862 static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = {
1863 .master = &am33xx_l4per_hwmod,
1864 .slave = &am33xx_timer5_hwmod,
1865 .clk = "timer5_ick",
1866 .addr = am33xx_timer5_addr_space,
1867 .user = OCP_USER_MPU,
1868 };
1870 static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = {
1871 &am33xx_l4per__timer5,
1872 };
1874 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
1875 { .irq = AM33XX_IRQ_DMTIMER5 },
1876 { .irq = -1 }
1877 };
1879 static struct omap_hwmod am33xx_timer5_hwmod = {
1880 .name = "timer5",
1881 .class = &am33xx_timer_hwmod_class,
1882 .mpu_irqs = am33xx_timer5_irqs,
1883 .main_clk = "timer5_fck",
1884 .prcm = {
1885 .omap4 = {
1886 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1887 .modulemode = MODULEMODE_SWCTRL,
1888 },
1889 },
1890 .slaves = am33xx_timer5_slaves,
1891 .slaves_cnt = ARRAY_SIZE(am33xx_timer5_slaves),
1892 .clkdm_name = "l4ls_clkdm",
1893 };
1895 /* timer6 */
1896 /* l4 per -> timer6 interface */
1897 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
1898 {
1899 .pa_start = AM33XX_TIMER6_BASE,
1900 .pa_end = AM33XX_TIMER6_BASE + SZ_1K - 1,
1901 .flags = ADDR_TYPE_RT
1902 },
1903 { }
1904 };
1906 static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = {
1907 .master = &am33xx_l4per_hwmod,
1908 .slave = &am33xx_timer6_hwmod,
1909 .clk = "timer6_ick",
1910 .addr = am33xx_timer6_addr_space,
1911 .user = OCP_USER_MPU,
1912 };
1914 static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = {
1915 &am33xx_l4per__timer6,
1916 };
1918 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
1919 { .irq = AM33XX_IRQ_DMTIMER6 },
1920 { .irq = -1 }
1921 };
1923 static struct omap_hwmod am33xx_timer6_hwmod = {
1924 .name = "timer6",
1925 .class = &am33xx_timer_hwmod_class,
1926 .mpu_irqs = am33xx_timer6_irqs,
1927 .main_clk = "timer6_fck",
1928 .prcm = {
1929 .omap4 = {
1930 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
1931 .modulemode = MODULEMODE_SWCTRL,
1932 },
1933 },
1934 .slaves = am33xx_timer6_slaves,
1935 .slaves_cnt = ARRAY_SIZE(am33xx_timer6_slaves),
1936 .clkdm_name = "l4ls_clkdm",
1937 };
1939 /* timer7 */
1940 /* l4 per -> timer7 interface */
1941 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
1942 {
1943 .pa_start = AM33XX_TIMER7_BASE,
1944 .pa_end = AM33XX_TIMER7_BASE + SZ_1K - 1,
1945 .flags = ADDR_TYPE_RT
1946 },
1947 { }
1948 };
1950 static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = {
1951 .master = &am33xx_l4per_hwmod,
1952 .slave = &am33xx_timer7_hwmod,
1953 .clk = "timer7_ick",
1954 .addr = am33xx_timer7_addr_space,
1955 .user = OCP_USER_MPU,
1956 };
1958 static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = {
1959 &am33xx_l4per__timer7,
1960 };
1962 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
1963 { .irq = AM33XX_IRQ_DMTIMER7 },
1964 { .irq = -1 }
1965 };
1967 static struct omap_hwmod am33xx_timer7_hwmod = {
1968 .name = "timer7",
1969 .class = &am33xx_timer_hwmod_class,
1970 .mpu_irqs = am33xx_timer7_irqs,
1971 .main_clk = "timer7_fck",
1972 .prcm = {
1973 .omap4 = {
1974 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
1975 .modulemode = MODULEMODE_SWCTRL,
1976 },
1977 },
1978 .slaves = am33xx_timer7_slaves,
1979 .slaves_cnt = ARRAY_SIZE(am33xx_timer7_slaves),
1980 .clkdm_name = "l4ls_clkdm",
1981 };
1983 /* 'tpcc' class */
1984 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1985 .name = "tpcc",
1986 };
1988 /* tpcc */
1989 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
1990 { .irq = AM33XX_IRQ_TPCC0_INT_PO0 },
1991 { .irq = -1 },
1992 };
1994 static struct omap_hwmod am33xx_tpcc_hwmod = {
1995 .name = "tpcc",
1996 .class = &am33xx_tpcc_hwmod_class,
1997 .mpu_irqs = am33xx_tpcc_irqs,
1998 .main_clk = "tpcc_ick",
1999 .clkdm_name = "l3_clkdm",
2000 .prcm = {
2001 .omap4 = {
2002 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
2003 .modulemode = MODULEMODE_SWCTRL,
2004 },
2005 },
2006 };
2008 /* 'tptc' class */
2009 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
2010 .name = "tptc",
2011 };
2013 /* tptc0 */
2014 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
2015 { .irq = AM33XX_IRQ_TPTC0 },
2016 { .irq = -1 }
2017 };
2019 static struct omap_hwmod am33xx_tptc0_hwmod = {
2020 .name = "tptc0",
2021 .class = &am33xx_tptc_hwmod_class,
2022 .mpu_irqs = am33xx_tptc0_irqs,
2023 .main_clk = "tptc0_ick",
2024 .clkdm_name = "l3_clkdm",
2025 .prcm = {
2026 .omap4 = {
2027 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
2028 .modulemode = MODULEMODE_SWCTRL,
2029 },
2030 },
2031 };
2033 /* tptc1 */
2034 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
2035 { .irq = AM33XX_IRQ_TPTC1 },
2036 { .irq = -1 }
2037 };
2039 static struct omap_hwmod am33xx_tptc1_hwmod = {
2040 .name = "tptc1",
2041 .class = &am33xx_tptc_hwmod_class,
2042 .mpu_irqs = am33xx_tptc1_irqs,
2043 .main_clk = "tptc1_ick",
2044 .clkdm_name = "l3_clkdm",
2045 .prcm = {
2046 .omap4 = {
2047 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
2048 .modulemode = MODULEMODE_SWCTRL,
2049 },
2050 },
2051 };
2053 /* tptc2 */
2054 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
2055 { .irq = AM33XX_IRQ_TPTC2 },
2056 { .irq = -1 }
2057 };
2059 static struct omap_hwmod am33xx_tptc2_hwmod = {
2060 .name = "tptc2",
2061 .class = &am33xx_tptc_hwmod_class,
2062 .mpu_irqs = am33xx_tptc2_irqs,
2063 .main_clk = "tptc2_ick",
2064 .clkdm_name = "l3_clkdm",
2065 .prcm = {
2066 .omap4 = {
2067 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
2068 .modulemode = MODULEMODE_SWCTRL,
2069 },
2070 },
2071 };
2073 /* 'uart' class */
2074 static struct omap_hwmod_class_sysconfig uart_sysc = {
2075 .rev_offs = 0x50,
2076 .sysc_offs = 0x54,
2077 .syss_offs = 0x58,
2078 .sysc_flags = (SYSC_HAS_SIDLEMODE |
2079 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2080 SYSC_HAS_AUTOIDLE),
2081 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2082 .sysc_fields = &omap_hwmod_sysc_type1,
2083 };
2085 static struct omap_hwmod_class uart_class = {
2086 .name = "uart",
2087 .sysc = &uart_sysc,
2088 };
2090 /* uart1 */
2091 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
2092 { .name = "tx", .dma_req = 26, },
2093 { .name = "rx", .dma_req = 27, },
2094 { .dma_req = -1 }
2095 };
2097 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
2098 {
2099 .pa_start = AM33XX_UART1_BASE,
2100 .pa_end = AM33XX_UART1_BASE + SZ_8K - 1,
2101 .flags = ADDR_TYPE_RT
2102 },
2103 { }
2104 };
2106 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
2107 .master = &am33xx_l4wkup_hwmod,
2108 .slave = &am33xx_uart1_hwmod,
2109 .clk = "uart1_ick",
2110 .addr = am33xx_uart1_addr_space,
2111 .user = OCP_USER_MPU,
2112 };
2114 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
2115 { .irq = AM33XX_IRQ_UART0 },
2116 { .irq = -1 }
2117 };
2119 static struct omap_hwmod_ocp_if *am33xx_uart1_slaves[] = {
2120 &am33xx_l4_wkup__uart1,
2121 };
2123 static struct omap_hwmod am33xx_uart1_hwmod = {
2124 .name = "uart1",
2125 .class = &uart_class,
2126 .mpu_irqs = am33xx_uart1_irqs,
2127 .sdma_reqs = uart1_edma_reqs,
2128 .main_clk = "uart1_fck",
2129 .clkdm_name = "l4_wkup_clkdm",
2130 .prcm = {
2131 .omap4 = {
2132 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
2133 .modulemode = MODULEMODE_SWCTRL,
2134 },
2135 },
2136 .slaves = am33xx_uart1_slaves,
2137 .slaves_cnt = ARRAY_SIZE(am33xx_uart1_slaves),
2138 };
2140 /* uart2 */
2141 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
2142 {
2143 .pa_start = AM33XX_UART2_BASE,
2144 .pa_end = AM33XX_UART2_BASE + SZ_8K - 1,
2145 .flags = ADDR_TYPE_RT
2146 },
2147 { }
2148 };
2150 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
2151 .slave = &am33xx_uart2_hwmod,
2152 .clk = "uart2_ick",
2153 .addr = am33xx_uart2_addr_space,
2154 .user = OCP_USER_MPU,
2155 };
2157 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
2158 { .irq = AM33XX_IRQ_UART1 },
2159 { .irq = -1 }
2160 };
2162 static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = {
2163 &am33xx_l4_ls__uart2,
2164 };
2166 static struct omap_hwmod am33xx_uart2_hwmod = {
2167 .name = "uart2",
2168 .class = &uart_class,
2169 .mpu_irqs = am33xx_uart2_irqs,
2170 .main_clk = "uart2_fck",
2171 .clkdm_name = "l4ls_clkdm",
2172 .sdma_reqs = uart1_edma_reqs,
2173 .prcm = {
2174 .omap4 = {
2175 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
2176 .modulemode = MODULEMODE_SWCTRL,
2177 },
2178 },
2179 .slaves = am33xx_uart2_slaves,
2180 .slaves_cnt = ARRAY_SIZE(am33xx_uart2_slaves),
2181 };
2183 /* uart3 */
2184 static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
2185 { .name = "tx", .dma_req = 30, },
2186 { .name = "rx", .dma_req = 31, },
2187 { .dma_req = -1 }
2188 };
2190 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
2191 {
2192 .pa_start = AM33XX_UART3_BASE,
2193 .pa_end = AM33XX_UART3_BASE + SZ_8K - 1,
2194 .flags = ADDR_TYPE_RT
2195 },
2196 { }
2197 };
2199 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
2200 .slave = &am33xx_uart3_hwmod,
2201 .clk = "uart3_ick",
2202 .addr = am33xx_uart3_addr_space,
2203 .user = OCP_USER_MPU,
2204 };
2206 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2207 { .irq = AM33XX_IRQ_UART2 },
2208 { .irq = -1 }
2209 };
2211 static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = {
2212 &am33xx_l4_ls__uart3,
2213 };
2215 static struct omap_hwmod am33xx_uart3_hwmod = {
2216 .name = "uart3",
2217 .class = &uart_class,
2218 .mpu_irqs = am33xx_uart3_irqs,
2219 .main_clk = "uart3_fck",
2220 .clkdm_name = "l4ls_clkdm",
2221 .sdma_reqs = uart3_edma_reqs,
2222 .prcm = {
2223 .omap4 = {
2224 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
2225 .modulemode = MODULEMODE_SWCTRL,
2226 },
2227 },
2228 .slaves = am33xx_uart3_slaves,
2229 .slaves_cnt = ARRAY_SIZE(am33xx_uart3_slaves),
2230 };
2232 /* uart4 */
2233 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
2234 {
2235 .pa_start = AM33XX_UART4_BASE,
2236 .pa_end = AM33XX_UART4_BASE + SZ_8K - 1,
2237 .flags = ADDR_TYPE_RT
2238 },
2239 { }
2240 };
2242 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
2243 .slave = &am33xx_uart4_hwmod,
2244 .clk = "uart4_ick",
2245 .addr = am33xx_uart4_addr_space,
2246 .user = OCP_USER_MPU,
2247 };
2249 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2250 { .irq = AM33XX_IRQ_UART3 },
2251 { .irq = -1 }
2252 };
2254 static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = {
2255 &am33xx_l4_ls__uart4,
2256 };
2258 static struct omap_hwmod am33xx_uart4_hwmod = {
2259 .name = "uart4",
2260 .class = &uart_class,
2261 .mpu_irqs = am33xx_uart4_irqs,
2262 .main_clk = "uart4_fck",
2263 .clkdm_name = "l4ls_clkdm",
2264 .sdma_reqs = uart1_edma_reqs,
2265 .prcm = {
2266 .omap4 = {
2267 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
2268 .modulemode = MODULEMODE_SWCTRL,
2269 },
2270 },
2271 .slaves = am33xx_uart4_slaves,
2272 .slaves_cnt = ARRAY_SIZE(am33xx_uart4_slaves),
2273 };
2275 /* uart5 */
2276 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
2277 {
2278 .pa_start = AM33XX_UART5_BASE,
2279 .pa_end = AM33XX_UART5_BASE + SZ_8K - 1,
2280 .flags = ADDR_TYPE_RT
2281 },
2282 { }
2283 };
2285 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
2286 .slave = &am33xx_uart5_hwmod,
2287 .clk = "uart5_ick",
2288 .addr = am33xx_uart5_addr_space,
2289 .user = OCP_USER_MPU,
2290 };
2292 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2293 { .irq = AM33XX_IRQ_UART4 },
2294 { .irq = -1 }
2295 };
2297 static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = {
2298 &am33xx_l4_ls__uart5,
2299 };
2301 static struct omap_hwmod am33xx_uart5_hwmod = {
2302 .name = "uart5",
2303 .class = &uart_class,
2304 .mpu_irqs = am33xx_uart5_irqs,
2305 .main_clk = "uart5_fck",
2306 .clkdm_name = "l4ls_clkdm",
2307 .sdma_reqs = uart1_edma_reqs,
2308 .prcm = {
2309 .omap4 = {
2310 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2311 .modulemode = MODULEMODE_SWCTRL,
2312 },
2313 },
2314 .slaves = am33xx_uart5_slaves,
2315 .slaves_cnt = ARRAY_SIZE(am33xx_uart5_slaves),
2316 };
2318 /* uart6 */
2319 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
2320 {
2321 .pa_start = AM33XX_UART6_BASE,
2322 .pa_end = AM33XX_UART6_BASE + SZ_8K - 1,
2323 .flags = ADDR_TYPE_RT
2324 },
2325 { }
2326 };
2328 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
2329 .slave = &am33xx_uart6_hwmod,
2330 .clk = "uart6_ick",
2331 .addr = am33xx_uart6_addr_space,
2332 .user = OCP_USER_MPU,
2333 };
2335 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2336 { .irq = AM33XX_IRQ_UART5 },
2337 { .irq = -1 }
2338 };
2340 static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = {
2341 &am33xx_l4_ls__uart6,
2342 };
2344 static struct omap_hwmod am33xx_uart6_hwmod = {
2345 .name = "uart6",
2346 .class = &uart_class,
2347 .mpu_irqs = am33xx_uart6_irqs,
2348 .main_clk = "uart6_fck",
2349 .clkdm_name = "l4ls_clkdm",
2350 .sdma_reqs = uart1_edma_reqs,
2351 .prcm = {
2352 .omap4 = {
2353 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2354 .modulemode = MODULEMODE_SWCTRL,
2355 },
2356 },
2357 .slaves = am33xx_uart6_slaves,
2358 .slaves_cnt = ARRAY_SIZE(am33xx_uart6_slaves),
2359 };
2361 /* 'wd_timer' class */
2362 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2363 .name = "wd_timer",
2364 };
2366 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
2367 {
2368 .pa_start = AM33XX_WDT1_BASE,
2369 .pa_end = AM33XX_WDT1_BASE + SZ_4K - 1,
2370 .flags = ADDR_TYPE_RT
2371 },
2372 { }
2373 };
2375 /* l4_wkup -> wd_timer1 */
2376 static struct omap_hwmod_ocp_if am33xx_l4wkup__wd_timer1 = {
2377 .master = &am33xx_l4wkup_hwmod,
2378 .slave = &am33xx_wd_timer1_hwmod,
2379 .addr = am33xx_wd_timer1_addrs,
2380 .user = OCP_USER_MPU,
2381 };
2383 /* wd_timer1 slave ports */
2384 static struct omap_hwmod_ocp_if *am33xx_wd_timer1_slaves[] = {
2385 &am33xx_l4wkup__wd_timer1,
2386 };
2388 /* wd_timer1 */
2389 /*
2390 * TODO: device.c file uses hardcoded name for watchdog
2391 timer driver "wd_timer2, so we are also using
2392 same name as of now...
2393 */
2394 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2395 .name = "wd_timer2",
2396 .class = &am33xx_wd_timer_hwmod_class,
2397 .main_clk = "wd_timer1_fck",
2398 .clkdm_name = "l4_wkup_clkdm",
2399 .prcm = {
2400 .omap4 = {
2401 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2402 .modulemode = MODULEMODE_SWCTRL,
2403 },
2404 },
2405 .slaves = am33xx_wd_timer1_slaves,
2406 .slaves_cnt = ARRAY_SIZE(am33xx_wd_timer1_slaves),
2407 };
2409 /* wdt0 */
2410 static struct omap_hwmod_irq_info am33xx_wdt0_irqs[] = {
2411 { .irq = AM33XX_IRQ_WDT0 },
2412 { .irq = -1 },
2413 };
2415 static struct omap_hwmod am33xx_wdt0_hwmod = {
2416 .name = "wdt0",
2417 .class = &am33xx_wd_timer_hwmod_class,
2418 .mpu_irqs = am33xx_wdt0_irqs,
2419 .main_clk = "wdt0_fck",
2420 .clkdm_name = "l4_wkup_clkdm",
2421 .prcm = {
2422 .omap4 = {
2423 .clkctrl_offs = AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET,
2424 .modulemode = MODULEMODE_SWCTRL,
2425 },
2426 },
2427 };
2429 /* 'wkup_m3' class */
2430 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
2431 .name = "wkup_m3",
2432 };
2434 /* wkup_m3 */
2435 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
2436 .name = "wkup_m3",
2437 .class = &am33xx_wkup_m3_hwmod_class,
2438 .clkdm_name = "l4_wkup_aon_clkdm",
2439 .main_clk = "wkup_m3_fck",
2440 .prcm = {
2441 .omap4 = {
2442 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
2443 .modulemode = MODULEMODE_SWCTRL,
2444 },
2445 },
2446 };
2448 /* L3 SLOW -> USBSS interface */
2449 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
2450 {
2451 .name = "usbss",
2452 .pa_start = AM33XX_USBSS_BASE,
2453 .pa_end = AM33XX_USBSS_BASE + SZ_4K - 1,
2454 .flags = ADDR_TYPE_RT
2455 },
2456 {
2457 .name = "musb0",
2458 .pa_start = AM33XX_USB0_BASE,
2459 .pa_end = AM33XX_USB0_BASE + SZ_2K - 1,
2460 .flags = ADDR_TYPE_RT
2461 },
2462 {
2463 .name = "musb1",
2464 .pa_start = AM33XX_USB1_BASE,
2465 .pa_end = AM33XX_USB1_BASE + SZ_2K - 1,
2466 .flags = ADDR_TYPE_RT
2467 },
2468 { }
2469 };
2471 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2472 .rev_offs = 0x0,
2473 .sysc_offs = 0x10,
2474 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2475 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2476 .sysc_fields = &omap_hwmod_sysc_type1,
2477 };
2479 static struct omap_hwmod_class am33xx_usbotg_class = {
2480 .name = "usbotg",
2481 .sysc = &am33xx_usbhsotg_sysc,
2482 };
2484 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2485 { .name = "usbss-irq", .irq = AM33XX_IRQ_USBSS, },
2486 { .name = "musb0-irq", .irq = AM33XX_IRQ_USB0, },
2487 { .name = "musb1-irq", .irq = AM33XX_IRQ_USB1, },
2488 { .irq = -1, },
2489 };
2491 static struct omap_hwmod_ocp_if am33xx_l3_slow__usbss = {
2492 .master = &am33xx_l3slow_hwmod,
2493 .slave = &am33xx_usbss_hwmod,
2494 .addr = am33xx_usbss_addr_space,
2495 .user = OCP_USER_MPU,
2496 .flags = OCPIF_SWSUP_IDLE,
2497 };
2499 static struct omap_hwmod_ocp_if *am33xx_usbss_slaves[] = {
2500 &am33xx_l3_slow__usbss,
2501 };
2503 static struct omap_hwmod_opt_clk usbss_opt_clks[] = {
2504 { .role = "clkdcoldo", .clk = "usbotg_fck" },
2505 };
2507 static struct omap_hwmod am33xx_usbss_hwmod = {
2508 .name = "usb_otg_hs",
2509 .mpu_irqs = am33xx_usbss_mpu_irqs,
2510 .main_clk = "usbotg_ick",
2511 .clkdm_name = "l4ls_clkdm",
2512 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2513 .prcm = {
2514 .omap4 = {
2515 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2516 .modulemode = MODULEMODE_SWCTRL,
2517 },
2518 },
2519 .opt_clks = usbss_opt_clks,
2520 .opt_clks_cnt = ARRAY_SIZE(usbss_opt_clks),
2521 .slaves = am33xx_usbss_slaves,
2522 .slaves_cnt = ARRAY_SIZE(am33xx_usbss_slaves),
2523 .class = &am33xx_usbotg_class,
2524 };
2526 static __initdata struct omap_hwmod *am33xx_hwmods[] = {
2527 /* l3 class */
2528 &am33xx_l3_instr_hwmod,
2529 &am33xx_l3_main_hwmod,
2530 /* l3s class */
2531 &am33xx_l3slow_hwmod,
2532 /* l4hs class */
2533 &am33xx_l4_hs_hwmod,
2534 /* l4fw class */
2535 &am33xx_l4fw_hwmod,
2536 /* l4ls class */
2537 &am33xx_l4ls_hwmod,
2538 /* l4per class */
2539 &am33xx_l4per_hwmod,
2540 /* l4wkup class */
2541 &am33xx_l4wkup_hwmod,
2543 /* clkdiv32k class */
2544 &am33xx_clkdiv32k_hwmod,
2545 /* mpu class */
2546 &am33xx_mpu_hwmod,
2547 /* adc_tsc class */
2548 &am33xx_adc_tsc_hwmod,
2549 /* aes class */
2550 &am33xx_aes0_hwmod,
2551 /* cefuse class */
2552 &am33xx_cefuse_hwmod,
2553 /* control class */
2554 &am33xx_control_hwmod,
2555 /* dcan class */
2556 &am33xx_dcan0_hwmod,
2557 &am33xx_dcan1_hwmod,
2558 /* debugss class */
2559 &am33xx_debugss_hwmod,
2560 /* elm class */
2561 &am33xx_elm_hwmod,
2562 /* emif_fw class */
2563 &am33xx_emif_fw_hwmod,
2564 /* epwmss class */
2565 &am33xx_epwmss0_hwmod,
2566 &am33xx_epwmss1_hwmod,
2567 &am33xx_epwmss2_hwmod,
2568 /* gpio class */
2569 &am33xx_gpio0_hwmod,
2570 &am33xx_gpio1_hwmod,
2571 &am33xx_gpio2_hwmod,
2572 &am33xx_gpio3_hwmod,
2573 /* gpmc class */
2574 &am33xx_gpmc_hwmod,
2575 /* i2c class */
2576 &am33xx_i2c1_hwmod,
2577 &am33xx_i2c2_hwmod,
2578 /* icss class */
2579 &am33xx_icss_hwmod,
2580 /* ieee5000 class */
2581 &am33xx_ieee5000_hwmod,
2582 /* mailbox class */
2583 &am33xx_mailbox_hwmod,
2584 /* mcasp class */
2585 &am33xx_mcasp0_hwmod,
2586 /* mmc class */
2587 &am33xx_mmc0_hwmod,
2588 &am33xx_mmc1_hwmod,
2589 &am33xx_mmc2_hwmod,
2590 /* ocmcram class */
2591 &am33xx_ocmcram_hwmod,
2592 /* ocpwp class */
2593 &am33xx_ocpwp_hwmod,
2594 /* sha0 class */
2595 &am33xx_sha0_hwmod,
2596 /* smartreflex class */
2597 &am33xx_smartreflex0_hwmod,
2598 &am33xx_smartreflex1_hwmod,
2599 /* spi class */
2600 &am33xx_spi0_hwmod,
2601 &am33xx_spi1_hwmod,
2602 /* spinlock class */
2603 &am33xx_spinlock_hwmod,
2604 /* uart class */
2605 &am33xx_uart1_hwmod,
2606 &am33xx_uart2_hwmod,
2607 &am33xx_uart3_hwmod,
2608 &am33xx_uart4_hwmod,
2609 &am33xx_uart5_hwmod,
2610 &am33xx_uart6_hwmod,
2611 /* timer class */
2612 &am33xx_timer0_hwmod,
2613 &am33xx_timer1_hwmod,
2614 &am33xx_timer2_hwmod,
2615 &am33xx_timer3_hwmod,
2616 &am33xx_timer4_hwmod,
2617 &am33xx_timer5_hwmod,
2618 &am33xx_timer6_hwmod,
2619 &am33xx_timer7_hwmod,
2620 /* wkup_m3 class */
2621 &am33xx_wkup_m3_hwmod,
2622 /* wd_timer class */
2623 &am33xx_wd_timer1_hwmod,
2624 /* usbss hwmod */
2625 &am33xx_usbss_hwmod,
2626 /* cpgmac0 class */
2627 &am33xx_cpgmac0_hwmod,
2628 &am33xx_wdt0_hwmod, /* Secure WDT */
2629 /* tptc class */
2630 &am33xx_tptc0_hwmod,
2631 &am33xx_tptc1_hwmod,
2632 &am33xx_tptc2_hwmod,
2633 /* tpcc class */
2634 &am33xx_tpcc_hwmod,
2635 /* LCDC class */
2636 &am33xx_lcdc_hwmod,
2637 /* rtc */
2638 &am33xx_rtc_hwmod,
2639 NULL,
2640 };
2642 int __init am33xx_hwmod_init(void)
2643 {
2644 return omap_hwmod_register(am33xx_hwmods);
2645 }