1 /*
2 * Hardware modules present on the AM33XX chips
3 *
4 * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
17 #include <linux/io.h>
19 #include <plat/omap_hwmod.h>
20 #include <plat/i2c.h>
21 #include <plat/cpu.h>
22 #include <plat/gpio.h>
23 #include <plat/dma.h>
24 #include <plat/mmc.h>
25 #include <plat/mcspi.h>
27 #include "omap_hwmod_common_data.h"
28 #include "control.h"
29 #include "cm33xx.h"
30 #include "prm33xx.h"
32 /* Backward references (IPs with Bus Master capability) */
33 static struct omap_hwmod am33xx_mpu_hwmod;
34 static struct omap_hwmod am33xx_l3_main_hwmod;
35 static struct omap_hwmod am33xx_l3slow_hwmod;
36 static struct omap_hwmod am33xx_l4wkup_hwmod;
37 static struct omap_hwmod am33xx_l4per_hwmod;
38 static struct omap_hwmod am33xx_uart1_hwmod;
39 static struct omap_hwmod am33xx_uart2_hwmod;
40 static struct omap_hwmod am33xx_uart3_hwmod;
41 static struct omap_hwmod am33xx_uart4_hwmod;
42 static struct omap_hwmod am33xx_uart5_hwmod;
43 static struct omap_hwmod am33xx_uart6_hwmod;
44 static struct omap_hwmod am33xx_timer0_hwmod;
45 static struct omap_hwmod am33xx_timer1_hwmod;
46 static struct omap_hwmod am33xx_timer2_hwmod;
47 static struct omap_hwmod am33xx_timer3_hwmod;
48 static struct omap_hwmod am33xx_timer4_hwmod;
49 static struct omap_hwmod am33xx_timer5_hwmod;
50 static struct omap_hwmod am33xx_timer6_hwmod;
51 static struct omap_hwmod am33xx_timer7_hwmod;
52 static struct omap_hwmod am33xx_wd_timer1_hwmod;
53 static struct omap_hwmod am33xx_cpgmac0_hwmod;
54 static struct omap_hwmod am33xx_icss_hwmod;
55 static struct omap_hwmod am33xx_ieee5000_hwmod;
56 static struct omap_hwmod am33xx_tptc0_hwmod;
57 static struct omap_hwmod am33xx_tptc1_hwmod;
58 static struct omap_hwmod am33xx_tptc2_hwmod;
59 static struct omap_hwmod am33xx_gpio0_hwmod;
60 static struct omap_hwmod am33xx_gpio1_hwmod;
61 static struct omap_hwmod am33xx_gpio2_hwmod;
62 static struct omap_hwmod am33xx_gpio3_hwmod;
63 static struct omap_hwmod am33xx_i2c1_hwmod;
64 static struct omap_hwmod am33xx_i2c2_hwmod;
65 static struct omap_hwmod am33xx_usbss_hwmod;
66 static struct omap_hwmod am33xx_mmc0_hwmod;
67 static struct omap_hwmod am33xx_mmc1_hwmod;
68 static struct omap_hwmod am33xx_mmc2_hwmod;
69 static struct omap_hwmod am33xx_spi0_hwmod;
70 static struct omap_hwmod am33xx_spi1_hwmod;
71 static struct omap_hwmod am33xx_elm_hwmod;
72 static struct omap_hwmod am33xx_adc_tsc_hwmod;
73 static struct omap_hwmod am33xx_tpcc_hwmod;
74 static struct omap_hwmod am33xx_mcasp0_hwmod;
75 static struct omap_hwmod am33xx_mcasp1_hwmod;
76 static struct omap_hwmod am33xx_epwmss0_hwmod;
77 static struct omap_hwmod am33xx_epwmss1_hwmod;
78 static struct omap_hwmod am33xx_epwmss2_hwmod;
79 static struct omap_hwmod am33xx_gpmc_hwmod;
80 static struct omap_hwmod am33xx_lcdc_hwmod;
82 /*
83 * Interconnects hwmod structures
84 * hwmods that compose the global AM33XX OCP interconnect
85 */
87 /* MPU -> L3_SLOW Peripheral interface */
88 static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = {
89 .master = &am33xx_mpu_hwmod,
90 .slave = &am33xx_l3slow_hwmod,
91 .user = OCP_USER_MPU,
92 };
94 /* L3 SLOW -> L4_PER Peripheral interface */
95 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = {
96 .master = &am33xx_l3slow_hwmod,
97 .slave = &am33xx_l4per_hwmod,
98 .user = OCP_USER_MPU,
99 };
101 /* L3 SLOW -> L4_WKUP Peripheral interface */
102 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = {
103 .master = &am33xx_l3slow_hwmod,
104 .slave = &am33xx_l4wkup_hwmod,
105 .user = OCP_USER_MPU,
106 };
108 /* Master interfaces on the L4_WKUP interconnect */
109 static struct omap_hwmod_ocp_if *am33xx_l3_slow_masters[] = {
110 &am33xx_l3_slow__l4_per,
111 &am33xx_l3_slow__l4_wkup,
112 };
114 /* Slave interfaces on the L3_SLOW interconnect */
115 static struct omap_hwmod_ocp_if *am33xx_l3_slow_slaves[] = {
116 &am33xx_mpu__l3_slow,
117 };
119 static struct omap_hwmod am33xx_l3slow_hwmod = {
120 .name = "l3_slow",
121 .class = &l3_hwmod_class,
122 .clkdm_name = "l3s_clkdm",
123 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
124 .masters = am33xx_l3_slow_masters,
125 .masters_cnt = ARRAY_SIZE(am33xx_l3_slow_masters),
126 .slaves = am33xx_l3_slow_slaves,
127 .slaves_cnt = ARRAY_SIZE(am33xx_l3_slow_slaves),
128 };
130 /* L4 PER -> GPIO2 */
131 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
132 {
133 .pa_start = AM33XX_GPIO1_BASE,
134 .pa_end = AM33XX_GPIO1_BASE + SZ_4K - 1,
135 .flags = ADDR_TYPE_RT
136 },
137 { }
138 };
140 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
141 .master = &am33xx_l4per_hwmod,
142 .slave = &am33xx_gpio1_hwmod,
143 .clk = "l4ls_fck",
144 .addr = am33xx_gpio1_addrs,
145 .user = OCP_USER_MPU | OCP_USER_SDMA,
146 };
148 /* L4 PER -> GPIO3 */
149 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
150 {
151 .pa_start = AM33XX_GPIO2_BASE,
152 .pa_end = AM33XX_GPIO2_BASE + SZ_4K - 1,
153 .flags = ADDR_TYPE_RT
154 },
155 { }
156 };
158 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
159 .master = &am33xx_l4per_hwmod,
160 .slave = &am33xx_gpio2_hwmod,
161 .clk = "l4ls_fck",
162 .addr = am33xx_gpio2_addrs,
163 .user = OCP_USER_MPU | OCP_USER_SDMA,
164 };
166 /* L4 PER -> GPIO4 */
167 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
168 {
169 .pa_start = AM33XX_GPIO3_BASE,
170 .pa_end = AM33XX_GPIO3_BASE + SZ_4K - 1,
171 .flags = ADDR_TYPE_RT
172 },
173 { }
174 };
176 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
177 .master = &am33xx_l4per_hwmod,
178 .slave = &am33xx_gpio3_hwmod,
179 .clk = "l4ls_fck",
180 .addr = am33xx_gpio3_addrs,
181 .user = OCP_USER_MPU | OCP_USER_SDMA,
182 };
184 /* Master interfaces on the L4_PER interconnect */
185 static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = {
186 &am33xx_l4_per__gpio1,
187 &am33xx_l4_per__gpio2,
188 &am33xx_l4_per__gpio3,
189 };
190 /* Slave interfaces on the L4_PER interconnect */
191 static struct omap_hwmod_ocp_if *am33xx_l4_per_slaves[] = {
192 &am33xx_l3_slow__l4_per,
193 };
195 static struct omap_hwmod am33xx_l4per_hwmod = {
196 .name = "l4_per",
197 .class = &l4_hwmod_class,
198 .clkdm_name = "l4ls_clkdm",
199 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
200 .masters = am33xx_l4_per_masters,
201 .masters_cnt = ARRAY_SIZE(am33xx_l4_per_masters),
202 .slaves = am33xx_l4_per_slaves,
203 .slaves_cnt = ARRAY_SIZE(am33xx_l4_per_slaves),
204 };
206 /* L4 WKUP -> I2C1 */
207 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
208 {
209 .pa_start = AM33XX_I2C0_BASE,
210 .pa_end = AM33XX_I2C0_BASE + SZ_4K - 1,
211 .flags = ADDR_TYPE_RT
212 },
213 { }
214 };
216 static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = {
217 .master = &am33xx_l4wkup_hwmod,
218 .slave = &am33xx_i2c1_hwmod,
219 .addr = am33xx_i2c1_addr_space,
220 .user = OCP_USER_MPU,
221 };
223 /* L4 WKUP -> GPIO1 */
224 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
225 {
226 .pa_start = AM33XX_GPIO0_BASE,
227 .pa_end = AM33XX_GPIO0_BASE + SZ_4K - 1,
228 .flags = ADDR_TYPE_RT
229 },
230 { }
231 };
233 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
234 .master = &am33xx_l4wkup_hwmod,
235 .slave = &am33xx_gpio0_hwmod,
236 .clk = "l4ls_fck",
237 .addr = am33xx_gpio0_addrs,
238 .user = OCP_USER_MPU | OCP_USER_SDMA,
239 };
241 /* L4 WKUP -> ADC_TSC */
242 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
243 {
244 .pa_start = AM33XX_TSC_BASE,
245 .pa_end = AM33XX_TSC_BASE + SZ_8K - 1,
246 .flags = ADDR_TYPE_RT
247 },
248 { }
249 };
251 static struct omap_hwmod_ocp_if am33xx_l4_wkup_adc_tsc = {
252 .master = &am33xx_l4wkup_hwmod,
253 .slave = &am33xx_adc_tsc_hwmod,
254 .addr = am33xx_adc_tsc_addrs,
255 .user = OCP_USER_MPU,
256 };
258 /* Master interfaces on the L4_WKUP interconnect */
259 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = {
260 &am33xx_l4_wkup__gpio0,
261 };
262 /* Slave interfaces on the L4_WKUP interconnect */
263 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_slaves[] = {
264 &am33xx_l3_slow__l4_wkup,
265 };
267 static struct omap_hwmod am33xx_l4wkup_hwmod = {
268 .name = "l4_wkup",
269 .class = &l4_hwmod_class,
270 .clkdm_name = "l4_wkup_clkdm",
271 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
272 .masters = am33xx_l4_wkup_masters,
273 .masters_cnt = ARRAY_SIZE(am33xx_l4_wkup_masters),
274 .slaves = am33xx_l4_wkup_slaves,
275 .slaves_cnt = ARRAY_SIZE(am33xx_l4_wkup_slaves),
276 };
278 /* 'adc_tsc' class */
279 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
280 .name = "adc_tsc",
281 };
283 /* adc_tsc */
284 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
285 { .irq = AM33XX_IRQ_TSC },
286 { .irq = -1 }
287 };
289 static struct omap_hwmod_ocp_if *am33xx_adc_tsc_slaves[] = {
290 &am33xx_l4_wkup_adc_tsc,
291 };
293 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
294 .name = "adc_tsc",
295 .class = &am33xx_adc_tsc_hwmod_class,
296 .mpu_irqs = am33xx_adc_tsc_irqs,
297 .main_clk = "adc_tsc_fck",
298 .clkdm_name = "l4_wkup_clkdm",
299 .prcm = {
300 .omap4 = {
301 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
302 .modulemode = MODULEMODE_SWCTRL,
303 },
304 },
305 .flags = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
306 .slaves = am33xx_adc_tsc_slaves,
307 .slaves_cnt = ARRAY_SIZE(am33xx_adc_tsc_slaves),
308 };
310 /* 'aes' class */
311 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
312 .name = "aes",
313 };
315 /* aes0 */
316 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
317 { .irq = AM33XX_IRQ_AESEIP36t0_S },
318 { .irq = -1 }
319 };
321 static struct omap_hwmod am33xx_aes0_hwmod = {
322 .name = "aes0",
323 .class = &am33xx_aes_hwmod_class,
324 .mpu_irqs = am33xx_aes0_irqs,
325 .main_clk = "aes0_fck",
326 .clkdm_name = "l3_clkdm",
327 .prcm = {
328 .omap4 = {
329 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
330 .modulemode = MODULEMODE_SWCTRL,
331 },
332 },
333 };
335 /* 'cefuse' class */
336 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
337 .name = "cefuse",
338 };
340 /* cefuse */
341 static struct omap_hwmod am33xx_cefuse_hwmod = {
342 .name = "cefuse",
343 .class = &am33xx_cefuse_hwmod_class,
344 .main_clk = "cefuse_fck",
345 .clkdm_name = "l4_cefuse_clkdm",
346 .prcm = {
347 .omap4 = {
348 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
349 .modulemode = MODULEMODE_SWCTRL,
350 },
351 },
352 };
354 /* 'clkdiv32k' class */
355 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
356 .name = "clkdiv32k",
357 };
359 /* clkdiv32k */
360 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
361 .name = "clkdiv32k",
362 .class = &am33xx_clkdiv32k_hwmod_class,
363 .main_clk = "clkdiv32k_fck",
364 .clkdm_name = "clk_24mhz_clkdm",
365 .prcm = {
366 .omap4 = {
367 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
368 .modulemode = MODULEMODE_SWCTRL,
369 },
370 },
371 };
373 /* 'control' class */
374 static struct omap_hwmod_class am33xx_control_hwmod_class = {
375 .name = "control",
376 };
378 /* control */
379 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
380 { .irq = AM33XX_IRQ_CONTROL_PLATFORM },
381 { .irq = -1 }
382 };
384 static struct omap_hwmod am33xx_control_hwmod = {
385 .name = "control",
386 .class = &am33xx_control_hwmod_class,
387 .mpu_irqs = am33xx_control_irqs,
388 .main_clk = "control_fck",
389 .clkdm_name = "l4_wkup_clkdm",
390 .prcm = {
391 .omap4 = {
392 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
393 .modulemode = MODULEMODE_SWCTRL,
394 },
395 },
396 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
397 };
399 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
400 .rev_offs = 0x0,
401 .sysc_offs = 0x8,
402 .syss_offs = 0x4,
403 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE
404 | SYSS_HAS_RESET_STATUS),
405 .idlemodes = (SIDLE_FORCE | SIDLE_NO |
406 MSTANDBY_FORCE | MSTANDBY_NO),
407 .sysc_fields = &omap_hwmod_sysc_type3,
408 };
410 /* 'cpgmac' class */
411 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
412 .name = "cpgmac0",
413 .sysc = &am33xx_cpgmac_sysc,
414 };
416 /* cpgmac0 - has 4 IRQs */
417 #if 0
418 static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
419 { .irq = AM33XX_IRQ_TPTC0 },
420 { .irq = -1 }
421 };
422 #endif
424 struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
425 {
426 .pa_start = AM33XX_CPSW_SS_BASE,
427 .pa_end = AM33XX_CPSW_SS_BASE + SZ_8K - 1,
428 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
429 },
430 { }
431 };
433 struct omap_hwmod_ocp_if am33xx_l3_main__cpgmac0 = {
434 .master = &am33xx_l3_main_hwmod,
435 .slave = &am33xx_cpgmac0_hwmod,
436 .addr = am33xx_cpgmac0_addr_space,
437 .user = OCP_USER_MPU,
438 };
440 static struct omap_hwmod_ocp_if *am33xx_cpgmac0_slaves[] = {
441 &am33xx_l3_main__cpgmac0,
442 };
444 /* cpgmac0 */
445 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
446 .name = "cpgmac0",
447 .class = &am33xx_cpgmac0_hwmod_class,
448 .main_clk = "cpgmac0_fck",
449 .clkdm_name = "cpsw_125mhz_clkdm",
450 .prcm = {
451 .omap4 = {
452 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
453 .modulemode = MODULEMODE_SWCTRL,
454 },
455 },
456 .slaves = am33xx_cpgmac0_slaves,
457 .slaves_cnt = ARRAY_SIZE(am33xx_cpgmac0_slaves),
458 };
460 /* 'dcan' class */
461 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
462 .name = "dcan",
463 };
465 /* dcan0 */
466 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
467 { .irq = AM33XX_IRQ_DCAN0_0 },
468 { .irq = -1 }
469 };
471 static struct omap_hwmod am33xx_dcan0_hwmod = {
472 .name = "dcan0",
473 .class = &am33xx_dcan_hwmod_class,
474 .mpu_irqs = am33xx_dcan0_irqs,
475 .main_clk = "dcan0_fck",
476 .clkdm_name = "l4ls_clkdm",
477 .prcm = {
478 .omap4 = {
479 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
480 .modulemode = MODULEMODE_SWCTRL,
481 },
482 },
483 };
485 /* dcan1 */
486 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
487 { .irq = AM33XX_IRQ_DCAN1_0 },
488 { .irq = -1 }
489 };
490 static struct omap_hwmod am33xx_dcan1_hwmod = {
491 .name = "dcan1",
492 .class = &am33xx_dcan_hwmod_class,
493 .mpu_irqs = am33xx_dcan1_irqs,
494 .main_clk = "dcan1_fck",
495 .clkdm_name = "l4ls_clkdm",
496 .prcm = {
497 .omap4 = {
498 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
499 .modulemode = MODULEMODE_SWCTRL,
500 },
501 },
502 };
504 /* 'debugss' class */
505 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
506 .name = "debugss",
507 };
509 /* debugss */
510 static struct omap_hwmod am33xx_debugss_hwmod = {
511 .name = "debugss",
512 .class = &am33xx_debugss_hwmod_class,
513 .main_clk = "debugss_fck",
514 .clkdm_name = "l3_aon_clkdm",
515 .prcm = {
516 .omap4 = {
517 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
518 .modulemode = MODULEMODE_SWCTRL,
519 },
520 },
521 #ifdef CONFIG_DEBUG_JTAG_ENABLE
522 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
523 #endif
524 };
526 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
527 .rev_offs = 0x0000,
528 .sysc_offs = 0x0010,
529 .syss_offs = 0x0014,
530 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
531 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
532 SYSS_HAS_RESET_STATUS),
533 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
534 .sysc_fields = &omap_hwmod_sysc_type1,
535 };
536 /* 'elm' class */
537 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
538 .name = "elm",
539 .sysc = &am33xx_elm_sysc,
540 };
542 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
543 { .irq = AM33XX_IRQ_ELM },
544 { .irq = -1 }
545 };
547 struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
548 {
549 .pa_start = AM33XX_ELM_BASE,
550 .pa_end = AM33XX_ELM_BASE + SZ_8K - 1,
551 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
552 },
553 { }
554 };
556 struct omap_hwmod_ocp_if am33xx_l4_core__elm = {
557 .master = &am33xx_l4per_hwmod,
558 .slave = &am33xx_elm_hwmod,
559 .addr = am33xx_elm_addr_space,
560 .user = OCP_USER_MPU,
561 };
563 static struct omap_hwmod_ocp_if *am33xx_elm_slaves[] = {
564 &am33xx_l4_core__elm,
565 };
567 /* elm */
568 static struct omap_hwmod am33xx_elm_hwmod = {
569 .name = "elm",
570 .class = &am33xx_elm_hwmod_class,
571 .mpu_irqs = am33xx_elm_irqs,
572 .main_clk = "elm_fck",
573 .clkdm_name = "l4ls_clkdm",
574 .slaves = am33xx_elm_slaves,
575 .slaves_cnt = ARRAY_SIZE(am33xx_elm_slaves),
576 .prcm = {
577 .omap4 = {
578 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
579 .modulemode = MODULEMODE_SWCTRL,
580 },
581 },
582 };
584 /* 'emif_fw' class */
585 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
586 .name = "emif_fw",
587 };
589 /* emif_fw */
590 static struct omap_hwmod am33xx_emif_fw_hwmod = {
591 .name = "emif_fw",
592 .class = &am33xx_emif_fw_hwmod_class,
593 .main_clk = "emif_fw_fck",
594 .clkdm_name = "l4fw_clkdm",
595 .prcm = {
596 .omap4 = {
597 .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
598 .modulemode = MODULEMODE_SWCTRL,
599 },
600 },
601 .flags = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
602 };
604 /* 'epwmss' class */
605 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
606 .rev_offs = 0x0,
607 .sysc_offs = 0x10,
608 .sysc_flags = SYSC_HAS_SIDLEMODE,
609 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
610 SIDLE_SMART_WKUP),
611 .sysc_fields = &omap_hwmod_sysc_type2,
612 };
614 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
615 .name = "epwmss",
616 .sysc = &am33xx_epwmss_sysc,
617 };
619 /* epwmss0 */
620 static struct omap_hwmod_irq_info am33xx_epwmss0_irqs[] = {
621 { .irq = AM33XX_IRQ_PWMSS0_EPWM },
622 { .irq = AM33XX_IRQ_PWMSS0 },
623 { .irq = AM33XX_IRQ_PWMSS0_ECAP },
624 { .irq = -1 }
625 };
627 struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
628 {
629 .pa_start = AM33XX_EPWMSS0_BASE,
630 .pa_end = AM33XX_EPWMSS0_BASE + SZ_4K - 1,
631 .flags = ADDR_TYPE_RT
632 },
633 { }
634 };
636 struct omap_hwmod_ocp_if am33xx_l4_core__epwmss0 = {
637 .master = &am33xx_l4per_hwmod,
638 .slave = &am33xx_epwmss0_hwmod,
639 .addr = am33xx_epwmss0_addr_space,
640 .user = OCP_USER_MPU,
641 };
643 static struct omap_hwmod_ocp_if *am33xx_epwmss0_slaves[] = {
644 &am33xx_l4_core__epwmss0,
645 };
647 static struct omap_hwmod am33xx_epwmss0_hwmod = {
648 .name = "epwmss0",
649 .mpu_irqs = am33xx_epwmss0_irqs,
650 .class = &am33xx_epwmss_hwmod_class,
651 .main_clk = "epwmss0_fck",
652 .clkdm_name = "l4ls_clkdm",
653 .prcm = {
654 .omap4 = {
655 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
656 .modulemode = MODULEMODE_SWCTRL,
657 },
658 },
659 .slaves = am33xx_epwmss0_slaves,
660 .slaves_cnt = ARRAY_SIZE(am33xx_epwmss0_slaves),
661 };
663 /* epwmss1 */
664 static struct omap_hwmod_irq_info am33xx_epwmss1_irqs[] = {
665 { .irq = AM33XX_IRQ_PWMSS1_EPWM },
666 { .irq = AM33XX_IRQ_PWMSS1 },
667 { .irq = AM33XX_IRQ_PWMSS1_ECAP },
668 { .irq = -1 }
669 };
671 struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
672 {
673 .pa_start = AM33XX_EPWMSS1_BASE,
674 .pa_end = AM33XX_EPWMSS1_BASE + SZ_4K - 1,
675 .flags = ADDR_TYPE_RT
676 },
677 { }
678 };
680 struct omap_hwmod_ocp_if am33xx_l4_core__epwmss1 = {
681 .master = &am33xx_l4per_hwmod,
682 .slave = &am33xx_epwmss1_hwmod,
683 .addr = am33xx_epwmss1_addr_space,
684 .user = OCP_USER_MPU,
685 };
687 static struct omap_hwmod_ocp_if *am33xx_epwmss1_slaves[] = {
688 &am33xx_l4_core__epwmss1,
689 };
691 static struct omap_hwmod am33xx_epwmss1_hwmod = {
692 .name = "epwmss1",
693 .mpu_irqs = am33xx_epwmss1_irqs,
694 .class = &am33xx_epwmss_hwmod_class,
695 .main_clk = "epwmss1_fck",
696 .clkdm_name = "l4ls_clkdm",
697 .prcm = {
698 .omap4 = {
699 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
700 .modulemode = MODULEMODE_SWCTRL,
701 },
702 },
703 .slaves = am33xx_epwmss1_slaves,
704 .slaves_cnt = ARRAY_SIZE(am33xx_epwmss1_slaves),
705 };
707 /* epwmss2 */
708 static struct omap_hwmod_irq_info am33xx_epwmss2_irqs[] = {
709 { .irq = AM33XX_IRQ_PWMSS2_EPWM },
710 { .irq = AM33XX_IRQ_PWMSS2 },
711 { .irq = AM33XX_IRQ_PWMSS2_ECAP },
712 { .irq = -1 }
713 };
715 struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
716 {
717 .pa_start = AM33XX_EPWMSS2_BASE,
718 .pa_end = AM33XX_EPWMSS2_BASE + SZ_4K - 1,
719 .flags = ADDR_TYPE_RT
720 },
721 { }
722 };
724 struct omap_hwmod_ocp_if am33xx_l4_core__epwmss2 = {
725 .master = &am33xx_l4per_hwmod,
726 .slave = &am33xx_epwmss2_hwmod,
727 .addr = am33xx_epwmss2_addr_space,
728 .user = OCP_USER_MPU,
729 };
731 static struct omap_hwmod_ocp_if *am33xx_epwmss2_slaves[] = {
732 &am33xx_l4_core__epwmss2,
733 };
735 static struct omap_hwmod am33xx_epwmss2_hwmod = {
736 .name = "epwmss2",
737 .mpu_irqs = am33xx_epwmss2_irqs,
738 .class = &am33xx_epwmss_hwmod_class,
739 .main_clk = "epwmss2_fck",
740 .clkdm_name = "l4ls_clkdm",
741 .prcm = {
742 .omap4 = {
743 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
744 .modulemode = MODULEMODE_SWCTRL,
745 },
746 },
747 .slaves = am33xx_epwmss2_slaves,
748 .slaves_cnt = ARRAY_SIZE(am33xx_epwmss2_slaves),
749 };
751 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
752 .rev_offs = 0x0000,
753 .sysc_offs = 0x0010,
754 .syss_offs = 0x0114,
755 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
756 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
757 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
758 SIDLE_SMART_WKUP),
759 .sysc_fields = &omap_hwmod_sysc_type1,
760 };
762 /* 'gpio' class */
763 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
764 .name = "gpio",
765 .sysc = &am33xx_gpio_sysc,
766 .rev = 2,
767 };
769 /* gpio dev_attr */
770 static struct omap_gpio_dev_attr gpio_dev_attr = {
771 .bank_width = 32,
772 .dbck_flag = true,
773 };
775 /* gpio0 */
776 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
777 { .irq = AM33XX_IRQ_GPIO0_1 },
778 { .irq = -1 }
779 };
781 /* gpio0 slave ports */
782 static struct omap_hwmod_ocp_if *am33xx_gpio0_slaves[] = {
783 &am33xx_l4_wkup__gpio0,
784 };
786 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
787 { .role = "dbclk", .clk = "gpio0_dbclk" },
788 { .role = "fclk", .clk = "gpio0_fck" },
789 };
791 /* gpio0 */
792 static struct omap_hwmod am33xx_gpio0_hwmod = {
793 .name = "gpio1",
794 .class = &am33xx_gpio_hwmod_class,
795 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
796 .mpu_irqs = am33xx_gpio0_irqs,
797 .main_clk = "gpio0_fck",
798 .clkdm_name = "l4_wkup_clkdm",
799 .prcm = {
800 .omap4 = {
801 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
802 .modulemode = MODULEMODE_SWCTRL,
803 },
804 },
805 .opt_clks = gpio0_opt_clks,
806 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
807 .dev_attr = &gpio_dev_attr,
808 .slaves = am33xx_gpio0_slaves,
809 .slaves_cnt = ARRAY_SIZE(am33xx_gpio0_slaves),
810 };
812 /* gpio1 */
813 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
814 { .irq = AM33XX_IRQ_GPIO1_1 },
815 { .irq = -1 }
816 };
818 /* gpio1 slave ports */
819 static struct omap_hwmod_ocp_if *am33xx_gpio1_slaves[] = {
820 &am33xx_l4_per__gpio1,
821 };
823 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
824 { .role = "dbclk", .clk = "gpio1_dbclk" },
825 { .role = "fclk", .clk = "gpio1_fck" },
826 };
828 static struct omap_hwmod am33xx_gpio1_hwmod = {
829 .name = "gpio2",
830 .class = &am33xx_gpio_hwmod_class,
831 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
832 .mpu_irqs = am33xx_gpio1_irqs,
833 .main_clk = "gpio1_fck",
834 .clkdm_name = "l4ls_clkdm",
835 .prcm = {
836 .omap4 = {
837 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
838 .modulemode = MODULEMODE_SWCTRL,
839 },
840 },
841 .opt_clks = gpio1_opt_clks,
842 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
843 .dev_attr = &gpio_dev_attr,
844 .slaves = am33xx_gpio1_slaves,
845 .slaves_cnt = ARRAY_SIZE(am33xx_gpio1_slaves),
846 };
848 /* gpio2 */
849 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
850 { .irq = AM33XX_IRQ_GPIO2_1 },
851 { .irq = -1 }
852 };
854 /* gpio2 slave ports */
855 static struct omap_hwmod_ocp_if *am33xx_gpio2_slaves[] = {
856 &am33xx_l4_per__gpio2,
857 };
859 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
860 { .role = "dbclk", .clk = "gpio2_dbclk" },
861 { .role = "fclk", .clk = "gpio2_fck" },
862 };
864 /* gpio2 */
865 static struct omap_hwmod am33xx_gpio2_hwmod = {
866 .name = "gpio3",
867 .class = &am33xx_gpio_hwmod_class,
868 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
869 .mpu_irqs = am33xx_gpio2_irqs,
870 .main_clk = "gpio2_fck",
871 .clkdm_name = "l4ls_clkdm",
872 .prcm = {
873 .omap4 = {
874 .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
875 .modulemode = MODULEMODE_SWCTRL,
876 },
877 },
878 .opt_clks = gpio2_opt_clks,
879 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
880 .dev_attr = &gpio_dev_attr,
881 .slaves = am33xx_gpio2_slaves,
882 .slaves_cnt = ARRAY_SIZE(am33xx_gpio2_slaves),
883 };
885 /* gpio3 */
886 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
887 { .irq = AM33XX_IRQ_GPIO3_1 },
888 { .irq = -1 }
889 };
891 /* gpio3 slave ports */
892 static struct omap_hwmod_ocp_if *am33xx_gpio3_slaves[] = {
893 &am33xx_l4_per__gpio3,
894 };
896 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
897 { .role = "dbclk", .clk = "gpio3_dbclk" },
898 { .role = "fclk", .clk = "gpio3_fck" },
899 };
901 /* gpio3 */
902 static struct omap_hwmod am33xx_gpio3_hwmod = {
903 .name = "gpio4",
904 .class = &am33xx_gpio_hwmod_class,
905 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
906 .mpu_irqs = am33xx_gpio3_irqs,
907 .main_clk = "gpio3_fck",
908 .clkdm_name = "l4ls_clkdm",
909 .prcm = {
910 .omap4 = {
911 .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
912 .modulemode = MODULEMODE_SWCTRL,
913 },
914 },
915 .opt_clks = gpio3_opt_clks,
916 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
917 .dev_attr = &gpio_dev_attr,
918 .slaves = am33xx_gpio3_slaves,
919 .slaves_cnt = ARRAY_SIZE(am33xx_gpio3_slaves),
920 };
922 /* 'gpmc' class */
923 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
924 .rev_offs = 0x0,
925 .sysc_offs = 0x10,
926 .syss_offs = 0x14,
927 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
928 SYSC_HAS_MIDLEMODE),
929 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
930 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
931 .sysc_fields = &omap_hwmod_sysc_type4,
932 };
934 struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
935 {
936 .pa_start = 0x50000000,
937 .pa_end = 0x50000000 + SZ_8K - 1,
938 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
939 },
940 { }
941 };
943 struct omap_hwmod_ocp_if am33xx_l3_main__gpmc = {
944 .master = &am33xx_l3_main_hwmod,
945 .slave = &am33xx_gpmc_hwmod,
946 .addr = am33xx_gpmc_addr_space,
947 .user = OCP_USER_MPU,
948 };
950 static struct omap_hwmod_ocp_if *am33xx_gpmc_slaves[] = {
951 &am33xx_l3_main__gpmc,
952 };
954 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
955 .name = "gpmc",
956 .sysc = &gpmc_sysc,
957 };
959 /* gpmc */
960 static struct omap_hwmod am33xx_gpmc_hwmod = {
961 .name = "gpmc",
962 .class = &am33xx_gpmc_hwmod_class,
963 .main_clk = "gpmc_fck",
964 .clkdm_name = "l3s_clkdm",
965 .prcm = {
966 .omap4 = {
967 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
968 .modulemode = MODULEMODE_SWCTRL,
969 },
970 },
971 .slaves = am33xx_gpmc_slaves,
972 .slaves_cnt = ARRAY_SIZE(am33xx_gpmc_slaves),
973 };
975 /* 'i2c' class */
977 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
978 .sysc_offs = 0x0010,
979 .syss_offs = 0x0090,
980 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
981 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
982 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
983 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
984 SIDLE_SMART_WKUP),
985 .sysc_fields = &omap_hwmod_sysc_type1,
986 };
988 static struct omap_i2c_dev_attr i2c_dev_attr = {
989 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
990 };
992 static struct omap_hwmod_class i2c_class = {
993 .name = "i2c",
994 .sysc = &am33xx_i2c_sysc,
995 .rev = OMAP_I2C_IP_VERSION_2,
996 .reset = &omap_i2c_reset,
997 };
999 /* I2C1 */
1000 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1001 { .irq = AM33XX_IRQ_MSHSI2COCP0 },
1002 { .irq = -1 }
1003 };
1005 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
1006 { .name = "tx", .dma_req = 0, },
1007 { .name = "rx", .dma_req = 0, },
1008 { .dma_req = -1 }
1009 };
1011 static struct omap_hwmod_ocp_if *am33xx_i2c1_slaves[] = {
1012 &am33xx_l4_wkup_i2c1,
1013 };
1015 static struct omap_hwmod am33xx_i2c1_hwmod = {
1016 .name = "i2c1",
1017 .mpu_irqs = i2c1_mpu_irqs,
1018 .sdma_reqs = i2c1_edma_reqs,
1019 .main_clk = "i2c1_fck",
1020 .clkdm_name = "l4_wkup_clkdm",
1021 .prcm = {
1022 .omap4 = {
1023 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
1024 .modulemode = MODULEMODE_SWCTRL,
1025 },
1026 },
1027 .flags = HWMOD_16BIT_REG,
1028 .dev_attr = &i2c_dev_attr,
1029 .slaves = am33xx_i2c1_slaves,
1030 .slaves_cnt = ARRAY_SIZE(am33xx_i2c1_slaves),
1031 .class = &i2c_class,
1032 };
1034 /* i2c2 */
1035 /* l4 per -> i2c2 */
1036 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
1037 {
1038 .pa_start = AM33XX_I2C1_BASE,
1039 .pa_end = AM33XX_I2C1_BASE + SZ_4K - 1,
1040 .flags = ADDR_TYPE_RT
1041 },
1042 { }
1043 };
1045 static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = {
1046 .master = &am33xx_l4per_hwmod,
1047 .slave = &am33xx_i2c2_hwmod,
1048 .addr = am33xx_i2c2_addr_space,
1049 .user = OCP_USER_MPU,
1050 };
1052 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1053 { .irq = AM33XX_IRQ_MSHSI2COCP1 },
1054 { .irq = -1 }
1055 };
1057 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
1058 { .name = "tx", .dma_req = 0, },
1059 { .name = "rx", .dma_req = 0, },
1060 { .dma_req = -1 }
1061 };
1063 static struct omap_hwmod_ocp_if *am33xx_i2c2_slaves[] = {
1064 &am335_l4_per_i2c2,
1065 };
1067 static struct omap_hwmod am33xx_i2c2_hwmod = {
1068 .name = "i2c2",
1069 .mpu_irqs = i2c2_mpu_irqs,
1070 .sdma_reqs = i2c2_edma_reqs,
1071 .main_clk = "i2c2_fck",
1072 .clkdm_name = "l4ls_clkdm",
1073 .prcm = {
1074 .omap4 = {
1075 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
1076 .modulemode = MODULEMODE_SWCTRL,
1077 },
1078 },
1079 .flags = HWMOD_16BIT_REG,
1080 .dev_attr = &i2c_dev_attr,
1081 .slaves = am33xx_i2c2_slaves,
1082 .slaves_cnt = ARRAY_SIZE(am33xx_i2c2_slaves),
1083 .class = &i2c_class,
1084 };
1086 /* 'icss' class */
1087 static struct omap_hwmod_class am33xx_icss_hwmod_class = {
1088 .name = "icss",
1089 };
1091 /* icss */
1092 static struct omap_hwmod am33xx_icss_hwmod = {
1093 .name = "icss",
1094 .class = &am33xx_icss_hwmod_class,
1095 .main_clk = "icss_fck",
1096 .clkdm_name = "icss_ocp_clkdm",
1097 .prcm = {
1098 .omap4 = {
1099 .clkctrl_offs = AM33XX_CM_PER_ICSS_CLKCTRL_OFFSET,
1100 .modulemode = MODULEMODE_SWCTRL,
1101 },
1102 },
1103 };
1105 /* 'ieee5000' class */
1106 static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = {
1107 .name = "ieee5000",
1108 };
1110 /* ieee5000 */
1111 static struct omap_hwmod am33xx_ieee5000_hwmod = {
1112 .name = "ieee5000",
1113 .class = &am33xx_ieee5000_hwmod_class,
1114 .main_clk = "ieee5000_fck",
1115 .clkdm_name = "l3s_clkdm",
1116 .prcm = {
1117 .omap4 = {
1118 .clkctrl_offs = AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET,
1119 .modulemode = MODULEMODE_SWCTRL,
1120 },
1121 },
1122 };
1125 /* 'l3' class */
1126 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
1127 .name = "l3",
1128 };
1130 /* l4_hs */
1131 static struct omap_hwmod am33xx_l4_hs_hwmod = {
1132 .name = "l4_hs",
1133 .class = &am33xx_l3_hwmod_class,
1134 .clkdm_name = "l4hs_clkdm",
1135 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1136 .prcm = {
1137 .omap4 = {
1138 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
1139 .modulemode = MODULEMODE_SWCTRL,
1140 },
1141 },
1142 };
1144 /* l3_instr */
1145 static struct omap_hwmod am33xx_l3_instr_hwmod = {
1146 .name = "l3_instr",
1147 .class = &am33xx_l3_hwmod_class,
1148 .clkdm_name = "l3_clkdm",
1149 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1150 .prcm = {
1151 .omap4 = {
1152 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
1153 .modulemode = MODULEMODE_SWCTRL,
1154 },
1155 },
1156 };
1158 /* l3_main */
1159 static struct omap_hwmod am33xx_l3_main_hwmod = {
1160 .name = "l3_main",
1161 .class = &am33xx_l3_hwmod_class,
1162 .clkdm_name = "l3_clkdm",
1163 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1164 .prcm = {
1165 .omap4 = {
1166 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
1167 .modulemode = MODULEMODE_SWCTRL,
1168 },
1169 },
1170 };
1172 /* 'l4fw' class */
1173 static struct omap_hwmod_class am33xx_l4fw_hwmod_class = {
1174 .name = "l4fw",
1175 };
1177 /* l4fw */
1178 static struct omap_hwmod am33xx_l4fw_hwmod = {
1179 .name = "l4fw",
1180 .class = &am33xx_l4fw_hwmod_class,
1181 .clkdm_name = "l4fw_clkdm",
1182 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1183 .prcm = {
1184 .omap4 = {
1185 .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
1186 .modulemode = MODULEMODE_SWCTRL,
1187 },
1188 },
1189 };
1191 /* 'l4ls' class */
1192 static struct omap_hwmod_class am33xx_l4ls_hwmod_class = {
1193 .name = "l4ls",
1194 };
1196 /* l4ls */
1197 static struct omap_hwmod am33xx_l4ls_hwmod = {
1198 .name = "l4ls",
1199 .class = &am33xx_l4ls_hwmod_class,
1200 .main_clk = "l4ls_fck",
1201 .clkdm_name = "l4ls_clkdm",
1202 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1203 .prcm = {
1204 .omap4 = {
1205 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
1206 .modulemode = MODULEMODE_SWCTRL,
1207 },
1208 },
1209 };
1211 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
1212 .rev_offs = 0x0,
1213 .sysc_offs = 0x54,
1214 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
1215 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1216 .sysc_fields = &omap_hwmod_sysc_type2,
1217 };
1219 /* 'lcdc' class */
1220 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1221 .name = "lcdc",
1222 .sysc = &lcdc_sysc,
1223 };
1225 /* lcdc */
1226 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1227 { .irq = AM33XX_IRQ_LCD },
1228 { .irq = -1 }
1229 };
1231 struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
1232 {
1233 .pa_start = 0x4830E000,
1234 .pa_end = 0x4830E000 + SZ_8K - 1,
1235 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
1236 },
1237 { }
1238 };
1240 struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
1241 .master = &am33xx_l3_main_hwmod,
1242 .slave = &am33xx_lcdc_hwmod,
1243 .addr = am33xx_lcdc_addr_space,
1244 .user = OCP_USER_MPU,
1245 };
1247 static struct omap_hwmod_ocp_if *am33xx_lcdc_slaves[] = {
1248 &am33xx_l3_main__lcdc,
1249 };
1251 static struct omap_hwmod am33xx_lcdc_hwmod = {
1252 .name = "lcdc",
1253 .class = &am33xx_lcdc_hwmod_class,
1254 .mpu_irqs = am33xx_lcdc_irqs,
1255 .main_clk = "lcdc_fck",
1256 .clkdm_name = "lcdc_clkdm",
1257 .prcm = {
1258 .omap4 = {
1259 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1260 .modulemode = MODULEMODE_SWCTRL,
1261 },
1262 },
1263 .slaves = am33xx_lcdc_slaves,
1264 .slaves_cnt = ARRAY_SIZE(am33xx_lcdc_slaves),
1265 };
1267 /*
1268 * 'mailbox' class
1269 * mailbox module allowing communication between the on-chip processors using a
1270 * queued mailbox-interrupt mechanism.
1271 */
1273 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1274 .rev_offs = 0x0000,
1275 .sysc_offs = 0x0010,
1276 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1277 SYSC_HAS_SOFTRESET),
1278 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1279 .sysc_fields = &omap_hwmod_sysc_type2,
1280 };
1282 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1283 .name = "mailbox",
1284 .sysc = &am33xx_mailbox_sysc,
1285 };
1287 /* mailbox */
1288 static struct omap_hwmod am33xx_mailbox_hwmod;
1289 static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1290 { .irq = AM33XX_IRQ_MAILBOX },
1291 { .irq = -1 }
1292 };
1294 static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
1295 {
1296 .pa_start = AM33XX_MAILBOX0_BASE,
1297 .pa_end = AM33XX_MAILBOX0_BASE + (SZ_4K - 1),
1298 .flags = ADDR_TYPE_RT
1299 },
1300 { }
1301 };
1303 /* l4_cfg -> mailbox */
1304 static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
1305 .master = &am33xx_l4per_hwmod,
1306 .slave = &am33xx_mailbox_hwmod,
1307 .addr = am33xx_mailbox_addrs,
1308 .user = OCP_USER_MPU,
1309 };
1311 /* mailbox slave ports */
1312 static struct omap_hwmod_ocp_if *am33xx_mailbox_slaves[] = {
1313 &am33xx_l4_per__mailbox,
1314 };
1316 static struct omap_hwmod am33xx_mailbox_hwmod = {
1317 .name = "mailbox",
1318 .class = &am33xx_mailbox_hwmod_class,
1319 .clkdm_name = "l4ls_clkdm",
1320 .mpu_irqs = am33xx_mailbox_irqs,
1321 .main_clk = "mailbox0_fck",
1322 .prcm = {
1323 .omap4 = {
1324 .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1325 .modulemode = MODULEMODE_SWCTRL,
1326 },
1327 },
1328 .slaves = am33xx_mailbox_slaves,
1329 .slaves_cnt = ARRAY_SIZE(am33xx_mailbox_slaves),
1330 };
1332 /* 'mcasp' class */
1333 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1334 .name = "mcasp",
1335 };
1337 /* mcasp0 */
1338 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1339 { .name = "ax", .irq = AM33XX_IRQ_MCASP0_AX, },
1340 { .name = "ar", .irq = AM33XX_IRQ_MCASP0_AR, },
1341 { .irq = -1 }
1342 };
1344 static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
1345 {
1346 .pa_start = AM33XX_ASP0_BASE,
1347 .pa_end = AM33XX_ASP0_BASE + (SZ_1K * 12) - 1,
1348 .flags = ADDR_TYPE_RT
1349 },
1350 { }
1351 };
1353 static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp0 = {
1354 .master = &am33xx_l3slow_hwmod,
1355 .slave = &am33xx_mcasp0_hwmod,
1356 .clk = "mcasp0_ick",
1357 .addr = am33xx_mcasp0_addr_space,
1358 .user = OCP_USER_MPU,
1359 };
1361 static struct omap_hwmod_ocp_if *am33xx_mcasp0_slaves[] = {
1362 &am33xx_l3_slow__mcasp0,
1363 };
1365 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1366 .name = "mcasp0",
1367 .class = &am33xx_mcasp_hwmod_class,
1368 .mpu_irqs = am33xx_mcasp0_irqs,
1369 .main_clk = "mcasp0_fck",
1370 .clkdm_name = "l3s_clkdm",
1371 .prcm = {
1372 .omap4 = {
1373 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1374 .modulemode = MODULEMODE_SWCTRL,
1375 },
1376 },
1377 .slaves = am33xx_mcasp0_slaves,
1378 .slaves_cnt = ARRAY_SIZE(am33xx_mcasp0_slaves),
1379 };
1381 /* mcasp1 */
1382 static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
1383 { .name = "ax", .irq = AM33XX_IRQ_MCASP1_AX, },
1384 { .name = "ar", .irq = AM33XX_IRQ_MCASP1_AR, },
1385 { .irq = -1 }
1386 };
1388 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
1389 {
1390 .pa_start = AM33XX_ASP1_BASE,
1391 .pa_end = AM33XX_ASP1_BASE + (SZ_1K * 12) - 1,
1392 .flags = ADDR_TYPE_RT
1393 },
1394 { }
1395 };
1397 static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp1 = {
1398 .master = &am33xx_l3slow_hwmod,
1399 .slave = &am33xx_mcasp1_hwmod,
1400 .clk = "mcasp1_ick",
1401 .addr = am33xx_mcasp1_addr_space,
1402 .user = OCP_USER_MPU,
1403 };
1405 static struct omap_hwmod_ocp_if *am33xx_mcasp1_slaves[] = {
1406 &am33xx_l3_slow__mcasp1,
1407 };
1409 static struct omap_hwmod am33xx_mcasp1_hwmod = {
1410 .name = "mcasp1",
1411 .class = &am33xx_mcasp_hwmod_class,
1412 .mpu_irqs = am33xx_mcasp1_irqs,
1413 .main_clk = "mcasp1_fck",
1414 .clkdm_name = "l3s_clkdm",
1415 .prcm = {
1416 .omap4 = {
1417 .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
1418 .modulemode = MODULEMODE_SWCTRL,
1419 },
1420 },
1421 .slaves = am33xx_mcasp1_slaves,
1422 .slaves_cnt = ARRAY_SIZE(am33xx_mcasp1_slaves),
1423 };
1426 /* 'mmc' class */
1428 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1429 .rev_offs = 0x1fc,
1430 .sysc_offs = 0x10,
1431 .syss_offs = 0x14,
1432 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1433 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1434 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1435 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1436 .sysc_fields = &omap_hwmod_sysc_type1,
1437 };
1439 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1440 .name = "mmc",
1441 .sysc = &am33xx_mmc_sysc,
1442 };
1444 /* mmc0 */
1445 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1446 { .irq = AM33XX_IRQ_MMCHS0 },
1447 { .irq = -1 }
1448 };
1450 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1451 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS0_W, },
1452 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS0_R, },
1453 { .dma_req = -1 }
1454 };
1456 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
1457 {
1458 .pa_start = AM33XX_MMC0_BASE,
1459 .pa_end = AM33XX_MMC0_BASE + SZ_4K - 1,
1460 .flags = ADDR_TYPE_RT
1461 },
1462 { }
1463 };
1465 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc0 = {
1466 .master = &am33xx_l4ls_hwmod,
1467 .slave = &am33xx_mmc0_hwmod,
1468 .clk = "mmc0_ick",
1469 .addr = am33xx_mmc0_addr_space,
1470 .user = OCP_USER_MPU,
1471 };
1473 static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = {
1474 &am33xx_l4ls__mmc0,
1475 };
1477 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1478 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1479 };
1481 static struct omap_hwmod am33xx_mmc0_hwmod = {
1482 .name = "mmc1",
1483 .class = &am33xx_mmc_hwmod_class,
1484 .mpu_irqs = am33xx_mmc0_irqs,
1485 .sdma_reqs = am33xx_mmc0_edma_reqs,
1486 .main_clk = "mmc0_fck",
1487 .clkdm_name = "l4ls_clkdm",
1488 .prcm = {
1489 .omap4 = {
1490 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1491 .modulemode = MODULEMODE_SWCTRL,
1492 },
1493 },
1494 .dev_attr = &am33xx_mmc0_dev_attr,
1495 .slaves = am33xx_mmc0_slaves,
1496 .slaves_cnt = ARRAY_SIZE(am33xx_mmc0_slaves),
1497 };
1499 /* mmc1 */
1500 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1501 { .irq = AM33XX_IRQ_MMCHS1 },
1502 { .irq = -1 }
1503 };
1505 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1506 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS1_W, },
1507 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS1_R, },
1508 { .dma_req = -1 }
1509 };
1511 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
1512 {
1513 .pa_start = AM33XX_MMC1_BASE,
1514 .pa_end = AM33XX_MMC1_BASE + SZ_4K - 1,
1515 .flags = ADDR_TYPE_RT
1516 },
1517 { }
1518 };
1520 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc1 = {
1521 .master = &am33xx_l4ls_hwmod,
1522 .slave = &am33xx_mmc1_hwmod,
1523 .clk = "mmc1_ick",
1524 .addr = am33xx_mmc1_addr_space,
1525 .user = OCP_USER_MPU,
1526 };
1528 static struct omap_hwmod_ocp_if *am33xx_mmc1_slaves[] = {
1529 &am33xx_l4ls__mmc1,
1530 };
1532 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1533 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1534 };
1536 static struct omap_hwmod am33xx_mmc1_hwmod = {
1537 .name = "mmc2",
1538 .class = &am33xx_mmc_hwmod_class,
1539 .mpu_irqs = am33xx_mmc1_irqs,
1540 .sdma_reqs = am33xx_mmc1_edma_reqs,
1541 .main_clk = "mmc1_fck",
1542 .clkdm_name = "l4ls_clkdm",
1543 .prcm = {
1544 .omap4 = {
1545 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1546 .modulemode = MODULEMODE_SWCTRL,
1547 },
1548 },
1549 .dev_attr = &am33xx_mmc1_dev_attr,
1550 .slaves = am33xx_mmc1_slaves,
1551 .slaves_cnt = ARRAY_SIZE(am33xx_mmc1_slaves),
1552 };
1554 /* mmc2 */
1555 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1556 { .irq = AM33XX_IRQ_MMCHS2 },
1557 { .irq = -1 }
1558 };
1560 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1561 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS2_W, },
1562 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS2_R, },
1563 { .dma_req = -1 }
1564 };
1566 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
1567 {
1568 .pa_start = AM33XX_MMC2_BASE,
1569 .pa_end = AM33XX_MMC2_BASE + SZ_64K - 1,
1570 .flags = ADDR_TYPE_RT
1571 },
1572 { }
1573 };
1575 static struct omap_hwmod_ocp_if am33xx_l3_main__mmc2 = {
1576 .master = &am33xx_l3_main_hwmod,
1577 .slave = &am33xx_mmc2_hwmod,
1578 .clk = "mmc2_ick",
1579 .addr = am33xx_mmc2_addr_space,
1580 .user = OCP_USER_MPU,
1581 };
1583 static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = {
1584 &am33xx_l3_main__mmc2,
1585 };
1587 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1588 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1589 };
1590 static struct omap_hwmod am33xx_mmc2_hwmod = {
1591 .name = "mmc3",
1592 .class = &am33xx_mmc_hwmod_class,
1593 .mpu_irqs = am33xx_mmc2_irqs,
1594 .sdma_reqs = am33xx_mmc2_edma_reqs,
1595 .main_clk = "mmc2_fck",
1596 .clkdm_name = "l3s_clkdm",
1597 .prcm = {
1598 .omap4 = {
1599 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1600 .modulemode = MODULEMODE_SWCTRL,
1601 },
1602 },
1603 .dev_attr = &am33xx_mmc2_dev_attr,
1604 .slaves = am33xx_mmc2_slaves,
1605 .slaves_cnt = ARRAY_SIZE(am33xx_mmc2_slaves),
1606 };
1608 /* Master interfaces on the MPU interconnect */
1609 static struct omap_hwmod_ocp_if *am33xx_l3_mpu_masters[] = {
1610 &am33xx_mpu__l3_slow,
1611 };
1613 /* mpu */
1614 static struct omap_hwmod am33xx_mpu_hwmod = {
1615 .name = "mpu",
1616 .class = &mpu_hwmod_class,
1617 .masters = am33xx_l3_mpu_masters,
1618 .masters_cnt = ARRAY_SIZE(am33xx_l3_mpu_masters),
1619 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1620 .main_clk = "mpu_fck",
1621 .clkdm_name = "mpu_clkdm",
1622 .prcm = {
1623 .omap4 = {
1624 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1625 .modulemode = MODULEMODE_SWCTRL,
1626 },
1627 },
1628 };
1630 /* 'ocmcram' class */
1631 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
1632 .name = "ocmcram",
1633 };
1635 /* ocmcram */
1636 static struct omap_hwmod am33xx_ocmcram_hwmod = {
1637 .name = "ocmcram",
1638 .class = &am33xx_ocmcram_hwmod_class,
1639 .main_clk = "ocmcram_fck",
1640 .clkdm_name = "l3_clkdm",
1641 .prcm = {
1642 .omap4 = {
1643 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
1644 .modulemode = MODULEMODE_SWCTRL,
1645 },
1646 },
1647 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1648 };
1650 /* 'ocpwp' class */
1651 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
1652 .name = "ocpwp",
1653 };
1655 /* ocpwp */
1656 static struct omap_hwmod am33xx_ocpwp_hwmod = {
1657 .name = "ocpwp",
1658 .class = &am33xx_ocpwp_hwmod_class,
1659 .main_clk = "ocpwp_fck",
1660 .clkdm_name = "l4ls_clkdm",
1661 .prcm = {
1662 .omap4 = {
1663 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
1664 .modulemode = MODULEMODE_SWCTRL,
1665 },
1666 },
1667 };
1669 /* 'rtc' class */
1670 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1671 .name = "rtc",
1672 };
1674 /* rtc */
1675 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1676 { .irq = AM33XX_IRQ_RTC_TIMER },
1677 { .irq = -1 }
1678 };
1680 static struct omap_hwmod am33xx_rtc_hwmod = {
1681 .name = "rtc",
1682 .class = &am33xx_rtc_hwmod_class,
1683 .mpu_irqs = am33xx_rtc_irqs,
1684 .main_clk = "rtc_fck",
1685 .clkdm_name = "l4_rtc_clkdm",
1686 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), /* ??? */
1687 .prcm = {
1688 .omap4 = {
1689 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1690 .modulemode = MODULEMODE_SWCTRL,
1691 },
1692 },
1693 };
1695 /* 'sha0' class */
1696 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
1697 .name = "sha0",
1698 };
1700 /* sha0 */
1701 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
1702 { .irq = AM33XX_IRQ_SHAEIP57t0_S },
1703 { .irq = -1 }
1704 };
1706 static struct omap_hwmod am33xx_sha0_hwmod = {
1707 .name = "sha0",
1708 .class = &am33xx_sha0_hwmod_class,
1709 .mpu_irqs = am33xx_sha0_irqs,
1710 .main_clk = "sha0_fck",
1711 .clkdm_name = "l3_clkdm",
1712 .prcm = {
1713 .omap4 = {
1714 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
1715 .modulemode = MODULEMODE_SWCTRL,
1716 },
1717 },
1718 };
1720 /* 'smartreflex' class */
1721 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
1722 .name = "smartreflex",
1723 };
1725 /* smartreflex0 */
1726 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
1727 { .irq = AM33XX_IRQ_SMARTREFLEX0 },
1728 { .irq = -1 }
1729 };
1731 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
1732 .name = "smartreflex0",
1733 .class = &am33xx_smartreflex_hwmod_class,
1734 .mpu_irqs = am33xx_smartreflex0_irqs,
1735 .main_clk = "smartreflex0_fck",
1736 .clkdm_name = "l4_wkup_clkdm",
1737 .prcm = {
1738 .omap4 = {
1739 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
1740 .modulemode = MODULEMODE_SWCTRL,
1741 },
1742 },
1743 };
1745 /* smartreflex1 */
1746 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
1747 { .irq = AM33XX_IRQ_SMARTREFLEX1 },
1748 { .irq = -1 }
1749 };
1751 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
1752 .name = "smartreflex1",
1753 .class = &am33xx_smartreflex_hwmod_class,
1754 .mpu_irqs = am33xx_smartreflex1_irqs,
1755 .main_clk = "smartreflex1_fck",
1756 .clkdm_name = "l4_wkup_clkdm",
1757 .prcm = {
1758 .omap4 = {
1759 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
1760 .modulemode = MODULEMODE_SWCTRL,
1761 },
1762 },
1763 };
1765 /* 'spi' class */
1767 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1768 .rev_offs = 0x0000,
1769 .sysc_offs = 0x0110,
1770 .syss_offs = 0x0114,
1771 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1772 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1773 SYSS_HAS_RESET_STATUS),
1774 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1775 .sysc_fields = &omap_hwmod_sysc_type1,
1776 };
1778 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1779 .name = "mcspi",
1780 .sysc = &am33xx_mcspi_sysc,
1781 .rev = OMAP4_MCSPI_REV,
1782 };
1784 /* spi0 */
1785 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1786 { .irq = AM33XX_IRQ_MCSPIOCP0 },
1787 { .irq = -1 }
1788 };
1790 struct omap_hwmod_dma_info am33xx_mcspi0_sdma_reqs[] = {
1791 { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0R },
1792 { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0W },
1793 { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1R },
1794 { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1W },
1795 { .dma_req = -1 }
1796 };
1798 struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
1799 {
1800 .pa_start = AM33XX_SPI0_BASE,
1801 .pa_end = AM33XX_SPI0_BASE + SZ_1K - 1,
1802 .flags = ADDR_TYPE_RT
1803 },
1804 { }
1805 };
1807 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = {
1808 .master = &am33xx_l4per_hwmod,
1809 .slave = &am33xx_spi0_hwmod,
1810 .clk = "spi0_ick",
1811 .addr = am33xx_mcspi0_addr_space,
1812 .user = OCP_USER_MPU,
1813 };
1815 static struct omap_hwmod_ocp_if *am33xx_mcspi0_slaves[] = {
1816 &am33xx_l4_core__mcspi0,
1817 };
1819 struct omap2_mcspi_dev_attr mcspi_attrib = {
1820 .num_chipselect = 2,
1821 };
1822 static struct omap_hwmod am33xx_spi0_hwmod = {
1823 .name = "spi0",
1824 .class = &am33xx_spi_hwmod_class,
1825 .mpu_irqs = am33xx_spi0_irqs,
1826 .sdma_reqs = am33xx_mcspi0_sdma_reqs,
1827 .main_clk = "spi0_fck",
1828 .clkdm_name = "l4ls_clkdm",
1829 .prcm = {
1830 .omap4 = {
1831 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1832 .modulemode = MODULEMODE_SWCTRL,
1833 },
1834 },
1835 .dev_attr = &mcspi_attrib,
1836 .slaves = am33xx_mcspi0_slaves,
1837 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi0_slaves),
1838 };
1840 /* spi1 */
1841 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1842 { .irq = AM33XX_IRQ_SPI1 },
1843 { .irq = -1 }
1844 };
1846 struct omap_hwmod_dma_info am33xx_mcspi1_sdma_reqs[] = {
1847 { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0R },
1848 { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0W },
1849 { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1R },
1850 { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1W },
1851 { .dma_req = -1 }
1852 };
1854 struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
1855 {
1856 .pa_start = AM33XX_SPI1_BASE,
1857 .pa_end = AM33XX_SPI1_BASE + SZ_1K - 1,
1858 .flags = ADDR_TYPE_RT
1859 },
1860 { }
1861 };
1863 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = {
1864 .master = &am33xx_l4per_hwmod,
1865 .slave = &am33xx_spi1_hwmod,
1866 .clk = "spi1_ick",
1867 .addr = am33xx_mcspi1_addr_space,
1868 .user = OCP_USER_MPU,
1869 };
1871 static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = {
1872 &am33xx_l4_core__mcspi1,
1873 };
1874 static struct omap_hwmod am33xx_spi1_hwmod = {
1875 .name = "spi1",
1876 .class = &am33xx_spi_hwmod_class,
1877 .mpu_irqs = am33xx_spi1_irqs,
1878 .sdma_reqs = am33xx_mcspi1_sdma_reqs,
1879 .main_clk = "spi1_fck",
1880 .clkdm_name = "l4ls_clkdm",
1881 .prcm = {
1882 .omap4 = {
1883 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1884 .modulemode = MODULEMODE_SWCTRL,
1885 },
1886 },
1887 .dev_attr = &mcspi_attrib,
1888 .slaves = am33xx_mcspi1_slaves,
1889 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi1_slaves),
1890 };
1892 /* 'spinlock' class */
1893 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1894 .name = "spinlock",
1895 };
1897 /* spinlock */
1898 static struct omap_hwmod am33xx_spinlock_hwmod = {
1899 .name = "spinlock",
1900 .class = &am33xx_spinlock_hwmod_class,
1901 .main_clk = "spinlock_fck",
1902 .clkdm_name = "l4ls_clkdm",
1903 .prcm = {
1904 .omap4 = {
1905 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1906 .modulemode = MODULEMODE_SWCTRL,
1907 },
1908 },
1909 };
1911 /* 'timer 0 & 2-7' class */
1912 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1913 .rev_offs = 0x0000,
1914 .sysc_offs = 0x0010,
1915 .syss_offs = 0x0014,
1916 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1917 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1918 SIDLE_SMART_WKUP),
1919 .sysc_fields = &omap_hwmod_sysc_type2,
1920 };
1922 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1923 .name = "timer",
1924 .sysc = &am33xx_timer_sysc,
1925 };
1927 /* timer0 */
1928 /* l4 wkup -> timer0 interface */
1929 static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = {
1930 {
1931 .pa_start = AM33XX_TIMER0_BASE,
1932 .pa_end = AM33XX_TIMER0_BASE + SZ_1K - 1,
1933 .flags = ADDR_TYPE_RT
1934 },
1935 { }
1936 };
1938 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = {
1939 .master = &am33xx_l4wkup_hwmod,
1940 .slave = &am33xx_timer0_hwmod,
1941 .clk = "timer0_ick",
1942 .addr = am33xx_timer0_addr_space,
1943 .user = OCP_USER_MPU,
1944 };
1946 static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = {
1947 &am33xx_l4wkup__timer0,
1948 };
1950 static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = {
1951 { .irq = AM33XX_IRQ_DMTIMER0 },
1952 { .irq = -1 }
1953 };
1955 static struct omap_hwmod am33xx_timer0_hwmod = {
1956 .name = "timer0",
1957 .class = &am33xx_timer_hwmod_class,
1958 .mpu_irqs = am33xx_timer0_irqs,
1959 .main_clk = "timer0_fck",
1960 .clkdm_name = "l4_wkup_clkdm",
1961 .prcm = {
1962 .omap4 = {
1963 .clkctrl_offs = AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET,
1964 .modulemode = MODULEMODE_SWCTRL,
1965 },
1966 },
1967 .slaves = am33xx_timer0_slaves,
1968 .slaves_cnt = ARRAY_SIZE(am33xx_timer0_slaves),
1969 };
1971 /* timer1 1ms */
1972 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1973 .rev_offs = 0x0000,
1974 .sysc_offs = 0x0010,
1975 .syss_offs = 0x0014,
1976 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1977 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1978 SYSS_HAS_RESET_STATUS),
1979 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1980 .sysc_fields = &omap_hwmod_sysc_type1,
1981 };
1983 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1984 .name = "timer",
1985 .sysc = &am33xx_timer1ms_sysc,
1986 };
1988 /* l4 wkup -> timer1 interface */
1989 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
1990 {
1991 .pa_start = AM33XX_TIMER1_BASE,
1992 .pa_end = AM33XX_TIMER1_BASE + SZ_1K - 1,
1993 .flags = ADDR_TYPE_RT
1994 },
1995 { }
1996 };
1998 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = {
1999 .master = &am33xx_l4wkup_hwmod,
2000 .slave = &am33xx_timer1_hwmod,
2001 .clk = "timer1_ick",
2002 .addr = am33xx_timer1_addr_space,
2003 .user = OCP_USER_MPU,
2004 };
2006 static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = {
2007 &am33xx_l4wkup__timer1,
2008 };
2010 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
2011 { .irq = AM33XX_IRQ_DMTIMER1 },
2012 { .irq = -1 }
2013 };
2015 static struct omap_hwmod am33xx_timer1_hwmod = {
2016 .name = "timer1",
2017 .class = &am33xx_timer1ms_hwmod_class,
2018 .mpu_irqs = am33xx_timer1_irqs,
2019 .main_clk = "timer1_fck",
2020 .clkdm_name = "l4_wkup_clkdm",
2021 .prcm = {
2022 .omap4 = {
2023 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2024 .modulemode = MODULEMODE_SWCTRL,
2025 },
2026 },
2027 .slaves = am33xx_timer1_slaves,
2028 .slaves_cnt = ARRAY_SIZE(am33xx_timer1_slaves),
2029 };
2031 /* timer2 */
2032 /* l4 per -> timer2 interface */
2033 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
2034 {
2035 .pa_start = AM33XX_TIMER2_BASE,
2036 .pa_end = AM33XX_TIMER2_BASE + SZ_1K - 1,
2037 .flags = ADDR_TYPE_RT
2038 },
2039 { }
2040 };
2042 static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = {
2043 .master = &am33xx_l4per_hwmod,
2044 .slave = &am33xx_timer2_hwmod,
2045 .clk = "timer2_ick",
2046 .addr = am33xx_timer2_addr_space,
2047 .user = OCP_USER_MPU,
2048 };
2050 static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = {
2051 &am33xx_l4per__timer2,
2052 };
2054 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
2055 { .irq = AM33XX_IRQ_DMTIMER2 },
2056 { .irq = -1 }
2057 };
2059 static struct omap_hwmod am33xx_timer2_hwmod = {
2060 .name = "timer2",
2061 .class = &am33xx_timer_hwmod_class,
2062 .mpu_irqs = am33xx_timer2_irqs,
2063 .main_clk = "timer2_fck",
2064 .prcm = {
2065 .omap4 = {
2066 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
2067 .modulemode = MODULEMODE_SWCTRL,
2068 },
2069 },
2070 .slaves = am33xx_timer2_slaves,
2071 .slaves_cnt = ARRAY_SIZE(am33xx_timer2_slaves),
2072 .clkdm_name = "l4ls_clkdm",
2073 };
2075 /* timer3 */
2076 /* l4 per -> timer3 interface */
2077 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
2078 {
2079 .pa_start = AM33XX_TIMER3_BASE,
2080 .pa_end = AM33XX_TIMER3_BASE + SZ_1K - 1,
2081 .flags = ADDR_TYPE_RT
2082 },
2083 { }
2084 };
2086 static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = {
2087 .master = &am33xx_l4per_hwmod,
2088 .slave = &am33xx_timer3_hwmod,
2089 .clk = "timer3_ick",
2090 .addr = am33xx_timer3_addr_space,
2091 .user = OCP_USER_MPU,
2092 };
2094 static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = {
2095 &am33xx_l4per__timer3,
2096 };
2098 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
2099 { .irq = AM33XX_IRQ_DMTIMER3 },
2100 { .irq = -1 }
2101 };
2103 static struct omap_hwmod am33xx_timer3_hwmod = {
2104 .name = "timer3",
2105 .class = &am33xx_timer_hwmod_class,
2106 .mpu_irqs = am33xx_timer3_irqs,
2107 .main_clk = "timer3_fck",
2108 .clkdm_name = "l4ls_clkdm",
2109 .prcm = {
2110 .omap4 = {
2111 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
2112 .modulemode = MODULEMODE_SWCTRL,
2113 },
2114 },
2115 .slaves = am33xx_timer3_slaves,
2116 .slaves_cnt = ARRAY_SIZE(am33xx_timer3_slaves),
2117 };
2119 /* timer4 */
2120 /* l4 per -> timer4 interface */
2121 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
2122 {
2123 .pa_start = AM33XX_TIMER4_BASE,
2124 .pa_end = AM33XX_TIMER4_BASE + SZ_1K - 1,
2125 .flags = ADDR_TYPE_RT
2126 },
2127 { }
2128 };
2130 static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = {
2131 .master = &am33xx_l4per_hwmod,
2132 .slave = &am33xx_timer4_hwmod,
2133 .clk = "timer4_ick",
2134 .addr = am33xx_timer4_addr_space,
2135 .user = OCP_USER_MPU,
2136 };
2138 static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = {
2139 &am33xx_l4per__timer4,
2140 };
2142 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
2143 { .irq = AM33XX_IRQ_DMTIMER4 },
2144 { .irq = -1 }
2145 };
2147 static struct omap_hwmod am33xx_timer4_hwmod = {
2148 .name = "timer4",
2149 .class = &am33xx_timer_hwmod_class,
2150 .mpu_irqs = am33xx_timer4_irqs,
2151 .main_clk = "timer4_fck",
2152 .prcm = {
2153 .omap4 = {
2154 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
2155 .modulemode = MODULEMODE_SWCTRL,
2156 },
2157 },
2158 .slaves = am33xx_timer4_slaves,
2159 .slaves_cnt = ARRAY_SIZE(am33xx_timer4_slaves),
2160 .clkdm_name = "l4ls_clkdm",
2161 };
2164 /* timer5 */
2165 /* l4 per -> timer5 interface */
2166 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
2167 {
2168 .pa_start = AM33XX_TIMER5_BASE,
2169 .pa_end = AM33XX_TIMER5_BASE + SZ_1K - 1,
2170 .flags = ADDR_TYPE_RT
2171 },
2172 { }
2173 };
2175 static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = {
2176 .master = &am33xx_l4per_hwmod,
2177 .slave = &am33xx_timer5_hwmod,
2178 .clk = "timer5_ick",
2179 .addr = am33xx_timer5_addr_space,
2180 .user = OCP_USER_MPU,
2181 };
2183 static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = {
2184 &am33xx_l4per__timer5,
2185 };
2187 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
2188 { .irq = AM33XX_IRQ_DMTIMER5 },
2189 { .irq = -1 }
2190 };
2192 static struct omap_hwmod am33xx_timer5_hwmod = {
2193 .name = "timer5",
2194 .class = &am33xx_timer_hwmod_class,
2195 .mpu_irqs = am33xx_timer5_irqs,
2196 .main_clk = "timer5_fck",
2197 .prcm = {
2198 .omap4 = {
2199 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
2200 .modulemode = MODULEMODE_SWCTRL,
2201 },
2202 },
2203 .slaves = am33xx_timer5_slaves,
2204 .slaves_cnt = ARRAY_SIZE(am33xx_timer5_slaves),
2205 .clkdm_name = "l4ls_clkdm",
2206 };
2208 /* timer6 */
2209 /* l4 per -> timer6 interface */
2210 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
2211 {
2212 .pa_start = AM33XX_TIMER6_BASE,
2213 .pa_end = AM33XX_TIMER6_BASE + SZ_1K - 1,
2214 .flags = ADDR_TYPE_RT
2215 },
2216 { }
2217 };
2219 static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = {
2220 .master = &am33xx_l4per_hwmod,
2221 .slave = &am33xx_timer6_hwmod,
2222 .clk = "timer6_ick",
2223 .addr = am33xx_timer6_addr_space,
2224 .user = OCP_USER_MPU,
2225 };
2227 static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = {
2228 &am33xx_l4per__timer6,
2229 };
2231 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
2232 { .irq = AM33XX_IRQ_DMTIMER6 },
2233 { .irq = -1 }
2234 };
2236 static struct omap_hwmod am33xx_timer6_hwmod = {
2237 .name = "timer6",
2238 .class = &am33xx_timer_hwmod_class,
2239 .mpu_irqs = am33xx_timer6_irqs,
2240 .main_clk = "timer6_fck",
2241 .prcm = {
2242 .omap4 = {
2243 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
2244 .modulemode = MODULEMODE_SWCTRL,
2245 },
2246 },
2247 .slaves = am33xx_timer6_slaves,
2248 .slaves_cnt = ARRAY_SIZE(am33xx_timer6_slaves),
2249 .clkdm_name = "l4ls_clkdm",
2250 };
2252 /* timer7 */
2253 /* l4 per -> timer7 interface */
2254 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
2255 {
2256 .pa_start = AM33XX_TIMER7_BASE,
2257 .pa_end = AM33XX_TIMER7_BASE + SZ_1K - 1,
2258 .flags = ADDR_TYPE_RT
2259 },
2260 { }
2261 };
2263 static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = {
2264 .master = &am33xx_l4per_hwmod,
2265 .slave = &am33xx_timer7_hwmod,
2266 .clk = "timer7_ick",
2267 .addr = am33xx_timer7_addr_space,
2268 .user = OCP_USER_MPU,
2269 };
2271 static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = {
2272 &am33xx_l4per__timer7,
2273 };
2275 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
2276 { .irq = AM33XX_IRQ_DMTIMER7 },
2277 { .irq = -1 }
2278 };
2280 static struct omap_hwmod am33xx_timer7_hwmod = {
2281 .name = "timer7",
2282 .class = &am33xx_timer_hwmod_class,
2283 .mpu_irqs = am33xx_timer7_irqs,
2284 .main_clk = "timer7_fck",
2285 .prcm = {
2286 .omap4 = {
2287 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
2288 .modulemode = MODULEMODE_SWCTRL,
2289 },
2290 },
2291 .slaves = am33xx_timer7_slaves,
2292 .slaves_cnt = ARRAY_SIZE(am33xx_timer7_slaves),
2293 .clkdm_name = "l4ls_clkdm",
2294 };
2296 /* 'tpcc' class */
2297 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
2298 .name = "tpcc",
2299 };
2301 /* tpcc */
2302 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
2303 { .name = "edma0", .irq = AM33XX_IRQ_TPCC0_INT_PO0 },
2304 { .name = "edma0_err", .irq = AM33XX_IRQ_TPCC0_ERRINT_PO },
2305 { .irq = -1 },
2306 };
2308 /* TODO move this appropriate header. */
2309 #define AM33XX_TPCC_BASE 0x49000000
2311 static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
2312 {
2313 .pa_start = AM33XX_TPCC_BASE,
2314 .pa_end = AM33XX_TPCC_BASE + SZ_32K - 1,
2315 .flags = ADDR_TYPE_RT
2316 },
2317 { }
2318 };
2320 static struct omap_hwmod_ocp_if am33xx_l3_slow__tpcc = {
2321 .master = &am33xx_l3slow_hwmod,
2322 .slave = &am33xx_tpcc_hwmod,
2323 .addr = am33xx_tpcc_addr_space,
2324 .user = OCP_USER_MPU,
2325 };
2327 static struct omap_hwmod_ocp_if *am33xx_tpcc_slaves[] = {
2328 &am33xx_l3_slow__tpcc,
2329 };
2331 static struct omap_hwmod am33xx_tpcc_hwmod = {
2332 .name = "tpcc",
2333 .class = &am33xx_tpcc_hwmod_class,
2334 .mpu_irqs = am33xx_tpcc_irqs,
2335 .main_clk = "tpcc_ick",
2336 .clkdm_name = "l3_clkdm",
2337 .prcm = {
2338 .omap4 = {
2339 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
2340 .modulemode = MODULEMODE_SWCTRL,
2341 },
2342 },
2343 .slaves = am33xx_tpcc_slaves,
2344 .slaves_cnt = ARRAY_SIZE(am33xx_tpcc_slaves),
2345 };
2347 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
2348 .rev_offs = 0x0,
2349 .sysc_offs = 0x10,
2350 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2351 SYSC_HAS_MIDLEMODE),
2352 .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
2353 .sysc_fields = &omap_hwmod_sysc_type2,
2354 };
2356 /* 'tptc' class */
2357 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
2358 .name = "tptc",
2359 .sysc = &am33xx_tptc_sysc,
2360 };
2362 /* tptc0 */
2363 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
2364 { .irq = AM33XX_IRQ_TPTC0 },
2365 { .irq = -1 }
2366 };
2368 struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
2369 {
2370 .pa_start = 0x49800000,
2371 .pa_end = 0x49800000 + SZ_8K - 1,
2372 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2373 },
2374 { }
2375 };
2377 struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
2378 .master = &am33xx_l3_main_hwmod,
2379 .slave = &am33xx_tptc0_hwmod,
2380 .addr = am33xx_tptc0_addr_space,
2381 .user = OCP_USER_MPU,
2382 };
2384 static struct omap_hwmod_ocp_if *am33xx_tptc0_slaves[] = {
2385 &am33xx_l3_main__tptc0,
2386 };
2388 static struct omap_hwmod am33xx_tptc0_hwmod = {
2389 .name = "tptc0",
2390 .class = &am33xx_tptc_hwmod_class,
2391 .mpu_irqs = am33xx_tptc0_irqs,
2392 .main_clk = "tptc0_ick",
2393 .clkdm_name = "l3_clkdm",
2394 .prcm = {
2395 .omap4 = {
2396 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
2397 .modulemode = MODULEMODE_SWCTRL,
2398 },
2399 },
2400 .slaves = am33xx_tptc0_slaves,
2401 .slaves_cnt = ARRAY_SIZE(am33xx_tptc0_slaves),
2402 };
2404 /* tptc1 */
2405 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
2406 { .irq = AM33XX_IRQ_TPTC1 },
2407 { .irq = -1 }
2408 };
2410 struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
2411 {
2412 .pa_start = 0x49900000,
2413 .pa_end = 0x49900000 + SZ_8K - 1,
2414 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2415 },
2416 { }
2417 };
2419 struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
2420 .master = &am33xx_l3_main_hwmod,
2421 .slave = &am33xx_tptc1_hwmod,
2422 .addr = am33xx_tptc1_addr_space,
2423 .user = OCP_USER_MPU,
2424 };
2426 static struct omap_hwmod_ocp_if *am33xx_tptc1_slaves[] = {
2427 &am33xx_l3_main__tptc1,
2428 };
2430 static struct omap_hwmod am33xx_tptc1_hwmod = {
2431 .name = "tptc1",
2432 .class = &am33xx_tptc_hwmod_class,
2433 .mpu_irqs = am33xx_tptc1_irqs,
2434 .main_clk = "tptc1_ick",
2435 .clkdm_name = "l3_clkdm",
2436 .prcm = {
2437 .omap4 = {
2438 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
2439 .modulemode = MODULEMODE_SWCTRL,
2440 },
2441 },
2442 .slaves = am33xx_tptc1_slaves,
2443 .slaves_cnt = ARRAY_SIZE(am33xx_tptc1_slaves),
2444 };
2446 /* tptc2 */
2447 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
2448 { .irq = AM33XX_IRQ_TPTC2 },
2449 { .irq = -1 }
2450 };
2452 struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
2453 {
2454 .pa_start = 0x49a00000,
2455 .pa_end = 0x49a00000 + SZ_8K - 1,
2456 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2457 },
2458 { }
2459 };
2461 struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
2462 .master = &am33xx_l3_main_hwmod,
2463 .slave = &am33xx_tptc2_hwmod,
2464 .addr = am33xx_tptc2_addr_space,
2465 .user = OCP_USER_MPU,
2466 };
2468 static struct omap_hwmod_ocp_if *am33xx_tptc2_slaves[] = {
2469 &am33xx_l3_main__tptc2,
2470 };
2472 static struct omap_hwmod am33xx_tptc2_hwmod = {
2473 .name = "tptc2",
2474 .class = &am33xx_tptc_hwmod_class,
2475 .mpu_irqs = am33xx_tptc2_irqs,
2476 .main_clk = "tptc2_ick",
2477 .clkdm_name = "l3_clkdm",
2478 .prcm = {
2479 .omap4 = {
2480 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
2481 .modulemode = MODULEMODE_SWCTRL,
2482 },
2483 },
2484 .slaves = am33xx_tptc2_slaves,
2485 .slaves_cnt = ARRAY_SIZE(am33xx_tptc2_slaves),
2486 };
2488 /* 'uart' class */
2489 static struct omap_hwmod_class_sysconfig uart_sysc = {
2490 .rev_offs = 0x50,
2491 .sysc_offs = 0x54,
2492 .syss_offs = 0x58,
2493 .sysc_flags = (SYSC_HAS_SIDLEMODE |
2494 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2495 SYSC_HAS_AUTOIDLE),
2496 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2497 SIDLE_SMART_WKUP),
2498 .sysc_fields = &omap_hwmod_sysc_type1,
2499 };
2501 static struct omap_hwmod_class uart_class = {
2502 .name = "uart",
2503 .sysc = &uart_sysc,
2504 };
2506 /* uart1 */
2507 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
2508 { .name = "tx", .dma_req = 26, },
2509 { .name = "rx", .dma_req = 27, },
2510 { .dma_req = -1 }
2511 };
2513 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
2514 {
2515 .pa_start = AM33XX_UART1_BASE,
2516 .pa_end = AM33XX_UART1_BASE + SZ_8K - 1,
2517 .flags = ADDR_TYPE_RT
2518 },
2519 { }
2520 };
2522 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
2523 .master = &am33xx_l4wkup_hwmod,
2524 .slave = &am33xx_uart1_hwmod,
2525 .clk = "uart1_ick",
2526 .addr = am33xx_uart1_addr_space,
2527 .user = OCP_USER_MPU,
2528 };
2530 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
2531 { .irq = AM33XX_IRQ_UART0 },
2532 { .irq = -1 }
2533 };
2535 static struct omap_hwmod_ocp_if *am33xx_uart1_slaves[] = {
2536 &am33xx_l4_wkup__uart1,
2537 };
2539 static struct omap_hwmod am33xx_uart1_hwmod = {
2540 .name = "uart1",
2541 .class = &uart_class,
2542 .mpu_irqs = am33xx_uart1_irqs,
2543 .sdma_reqs = uart1_edma_reqs,
2544 .main_clk = "uart1_fck",
2545 .clkdm_name = "l4_wkup_clkdm",
2546 .prcm = {
2547 .omap4 = {
2548 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
2549 .modulemode = MODULEMODE_SWCTRL,
2550 },
2551 },
2552 .slaves = am33xx_uart1_slaves,
2553 .slaves_cnt = ARRAY_SIZE(am33xx_uart1_slaves),
2554 };
2556 /* uart2 */
2557 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
2558 {
2559 .pa_start = AM33XX_UART2_BASE,
2560 .pa_end = AM33XX_UART2_BASE + SZ_8K - 1,
2561 .flags = ADDR_TYPE_RT
2562 },
2563 { }
2564 };
2566 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
2567 .slave = &am33xx_uart2_hwmod,
2568 .clk = "uart2_ick",
2569 .addr = am33xx_uart2_addr_space,
2570 .user = OCP_USER_MPU,
2571 };
2573 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
2574 { .irq = AM33XX_IRQ_UART1 },
2575 { .irq = -1 }
2576 };
2578 static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = {
2579 &am33xx_l4_ls__uart2,
2580 };
2582 static struct omap_hwmod am33xx_uart2_hwmod = {
2583 .name = "uart2",
2584 .class = &uart_class,
2585 .mpu_irqs = am33xx_uart2_irqs,
2586 .main_clk = "uart2_fck",
2587 .clkdm_name = "l4ls_clkdm",
2588 .sdma_reqs = uart1_edma_reqs,
2589 .prcm = {
2590 .omap4 = {
2591 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
2592 .modulemode = MODULEMODE_SWCTRL,
2593 },
2594 },
2595 .slaves = am33xx_uart2_slaves,
2596 .slaves_cnt = ARRAY_SIZE(am33xx_uart2_slaves),
2597 };
2599 /* uart3 */
2600 static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
2601 { .name = "tx", .dma_req = 30, },
2602 { .name = "rx", .dma_req = 31, },
2603 { .dma_req = -1 }
2604 };
2606 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
2607 {
2608 .pa_start = AM33XX_UART3_BASE,
2609 .pa_end = AM33XX_UART3_BASE + SZ_8K - 1,
2610 .flags = ADDR_TYPE_RT
2611 },
2612 { }
2613 };
2615 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
2616 .slave = &am33xx_uart3_hwmod,
2617 .clk = "uart3_ick",
2618 .addr = am33xx_uart3_addr_space,
2619 .user = OCP_USER_MPU,
2620 };
2622 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2623 { .irq = AM33XX_IRQ_UART2 },
2624 { .irq = -1 }
2625 };
2627 static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = {
2628 &am33xx_l4_ls__uart3,
2629 };
2631 static struct omap_hwmod am33xx_uart3_hwmod = {
2632 .name = "uart3",
2633 .class = &uart_class,
2634 .mpu_irqs = am33xx_uart3_irqs,
2635 .main_clk = "uart3_fck",
2636 .clkdm_name = "l4ls_clkdm",
2637 .sdma_reqs = uart3_edma_reqs,
2638 .prcm = {
2639 .omap4 = {
2640 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
2641 .modulemode = MODULEMODE_SWCTRL,
2642 },
2643 },
2644 .slaves = am33xx_uart3_slaves,
2645 .slaves_cnt = ARRAY_SIZE(am33xx_uart3_slaves),
2646 };
2648 /* uart4 */
2649 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
2650 {
2651 .pa_start = AM33XX_UART4_BASE,
2652 .pa_end = AM33XX_UART4_BASE + SZ_8K - 1,
2653 .flags = ADDR_TYPE_RT
2654 },
2655 { }
2656 };
2658 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
2659 .slave = &am33xx_uart4_hwmod,
2660 .clk = "uart4_ick",
2661 .addr = am33xx_uart4_addr_space,
2662 .user = OCP_USER_MPU,
2663 };
2665 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2666 { .irq = AM33XX_IRQ_UART3 },
2667 { .irq = -1 }
2668 };
2670 static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = {
2671 &am33xx_l4_ls__uart4,
2672 };
2674 static struct omap_hwmod am33xx_uart4_hwmod = {
2675 .name = "uart4",
2676 .class = &uart_class,
2677 .mpu_irqs = am33xx_uart4_irqs,
2678 .main_clk = "uart4_fck",
2679 .clkdm_name = "l4ls_clkdm",
2680 .sdma_reqs = uart1_edma_reqs,
2681 .prcm = {
2682 .omap4 = {
2683 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
2684 .modulemode = MODULEMODE_SWCTRL,
2685 },
2686 },
2687 .slaves = am33xx_uart4_slaves,
2688 .slaves_cnt = ARRAY_SIZE(am33xx_uart4_slaves),
2689 };
2691 /* uart5 */
2692 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
2693 {
2694 .pa_start = AM33XX_UART5_BASE,
2695 .pa_end = AM33XX_UART5_BASE + SZ_8K - 1,
2696 .flags = ADDR_TYPE_RT
2697 },
2698 { }
2699 };
2701 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
2702 .slave = &am33xx_uart5_hwmod,
2703 .clk = "uart5_ick",
2704 .addr = am33xx_uart5_addr_space,
2705 .user = OCP_USER_MPU,
2706 };
2708 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2709 { .irq = AM33XX_IRQ_UART4 },
2710 { .irq = -1 }
2711 };
2713 static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = {
2714 &am33xx_l4_ls__uart5,
2715 };
2717 static struct omap_hwmod am33xx_uart5_hwmod = {
2718 .name = "uart5",
2719 .class = &uart_class,
2720 .mpu_irqs = am33xx_uart5_irqs,
2721 .main_clk = "uart5_fck",
2722 .clkdm_name = "l4ls_clkdm",
2723 .sdma_reqs = uart1_edma_reqs,
2724 .prcm = {
2725 .omap4 = {
2726 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2727 .modulemode = MODULEMODE_SWCTRL,
2728 },
2729 },
2730 .slaves = am33xx_uart5_slaves,
2731 .slaves_cnt = ARRAY_SIZE(am33xx_uart5_slaves),
2732 };
2734 /* uart6 */
2735 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
2736 {
2737 .pa_start = AM33XX_UART6_BASE,
2738 .pa_end = AM33XX_UART6_BASE + SZ_8K - 1,
2739 .flags = ADDR_TYPE_RT
2740 },
2741 { }
2742 };
2744 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
2745 .slave = &am33xx_uart6_hwmod,
2746 .clk = "uart6_ick",
2747 .addr = am33xx_uart6_addr_space,
2748 .user = OCP_USER_MPU,
2749 };
2751 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2752 { .irq = AM33XX_IRQ_UART5 },
2753 { .irq = -1 }
2754 };
2756 static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = {
2757 &am33xx_l4_ls__uart6,
2758 };
2760 static struct omap_hwmod am33xx_uart6_hwmod = {
2761 .name = "uart6",
2762 .class = &uart_class,
2763 .mpu_irqs = am33xx_uart6_irqs,
2764 .main_clk = "uart6_fck",
2765 .clkdm_name = "l4ls_clkdm",
2766 .sdma_reqs = uart1_edma_reqs,
2767 .prcm = {
2768 .omap4 = {
2769 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2770 .modulemode = MODULEMODE_SWCTRL,
2771 },
2772 },
2773 .slaves = am33xx_uart6_slaves,
2774 .slaves_cnt = ARRAY_SIZE(am33xx_uart6_slaves),
2775 };
2777 /* 'wd_timer' class */
2778 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2779 .name = "wd_timer",
2780 };
2782 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
2783 {
2784 .pa_start = AM33XX_WDT1_BASE,
2785 .pa_end = AM33XX_WDT1_BASE + SZ_4K - 1,
2786 .flags = ADDR_TYPE_RT
2787 },
2788 { }
2789 };
2791 /* l4_wkup -> wd_timer1 */
2792 static struct omap_hwmod_ocp_if am33xx_l4wkup__wd_timer1 = {
2793 .master = &am33xx_l4wkup_hwmod,
2794 .slave = &am33xx_wd_timer1_hwmod,
2795 .addr = am33xx_wd_timer1_addrs,
2796 .user = OCP_USER_MPU,
2797 };
2799 /* wd_timer1 slave ports */
2800 static struct omap_hwmod_ocp_if *am33xx_wd_timer1_slaves[] = {
2801 &am33xx_l4wkup__wd_timer1,
2802 };
2804 /* wd_timer1 */
2805 /*
2806 * TODO: device.c file uses hardcoded name for watchdog
2807 timer driver "wd_timer2, so we are also using
2808 same name as of now...
2809 */
2810 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2811 .name = "wd_timer2",
2812 .class = &am33xx_wd_timer_hwmod_class,
2813 .main_clk = "wd_timer1_fck",
2814 .clkdm_name = "l4_wkup_clkdm",
2815 .prcm = {
2816 .omap4 = {
2817 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2818 .modulemode = MODULEMODE_SWCTRL,
2819 },
2820 },
2821 .slaves = am33xx_wd_timer1_slaves,
2822 .slaves_cnt = ARRAY_SIZE(am33xx_wd_timer1_slaves),
2823 };
2825 /* wdt0 */
2826 static struct omap_hwmod_irq_info am33xx_wdt0_irqs[] = {
2827 { .irq = AM33XX_IRQ_WDT0 },
2828 { .irq = -1 },
2829 };
2831 static struct omap_hwmod am33xx_wdt0_hwmod = {
2832 .name = "wdt0",
2833 .class = &am33xx_wd_timer_hwmod_class,
2834 .mpu_irqs = am33xx_wdt0_irqs,
2835 .main_clk = "wdt0_fck",
2836 .clkdm_name = "l4_wkup_clkdm",
2837 .prcm = {
2838 .omap4 = {
2839 .clkctrl_offs = AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET,
2840 .modulemode = MODULEMODE_SWCTRL,
2841 },
2842 },
2843 };
2845 /* 'wkup_m3' class */
2846 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
2847 .name = "wkup_m3",
2848 };
2850 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
2851 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
2852 };
2854 /* wkup_m3 */
2855 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
2856 .name = "wkup_m3",
2857 .class = &am33xx_wkup_m3_hwmod_class,
2858 .clkdm_name = "l4_wkup_aon_clkdm",
2859 .main_clk = "wkup_m3_fck",
2860 .rst_lines = am33xx_wkup_m3_resets,
2861 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
2862 .prcm = {
2863 .omap4 = {
2864 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
2865 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
2866 .modulemode = MODULEMODE_SWCTRL,
2867 },
2868 },
2869 .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */
2870 };
2872 /* L3 SLOW -> USBSS interface */
2873 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
2874 {
2875 .name = "usbss",
2876 .pa_start = AM33XX_USBSS_BASE,
2877 .pa_end = AM33XX_USBSS_BASE + SZ_4K - 1,
2878 .flags = ADDR_TYPE_RT
2879 },
2880 {
2881 .name = "musb0",
2882 .pa_start = AM33XX_USB0_BASE,
2883 .pa_end = AM33XX_USB0_BASE + SZ_2K - 1,
2884 .flags = ADDR_TYPE_RT
2885 },
2886 {
2887 .name = "musb1",
2888 .pa_start = AM33XX_USB1_BASE,
2889 .pa_end = AM33XX_USB1_BASE + SZ_2K - 1,
2890 .flags = ADDR_TYPE_RT
2891 },
2892 { }
2893 };
2895 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2896 .rev_offs = 0x0,
2897 .sysc_offs = 0x10,
2898 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
2899 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2900 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2901 .sysc_fields = &omap_hwmod_sysc_type4,
2902 };
2904 static struct omap_hwmod_class am33xx_usbotg_class = {
2905 .name = "usbotg",
2906 .sysc = &am33xx_usbhsotg_sysc,
2907 };
2909 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2910 { .name = "usbss-irq", .irq = AM33XX_IRQ_USBSS, },
2911 { .name = "musb0-irq", .irq = AM33XX_IRQ_USB0, },
2912 { .name = "musb1-irq", .irq = AM33XX_IRQ_USB1, },
2913 { .irq = -1, },
2914 };
2916 static struct omap_hwmod_ocp_if am33xx_l3_slow__usbss = {
2917 .master = &am33xx_l3slow_hwmod,
2918 .slave = &am33xx_usbss_hwmod,
2919 .addr = am33xx_usbss_addr_space,
2920 .user = OCP_USER_MPU,
2921 .flags = OCPIF_SWSUP_IDLE,
2922 };
2924 static struct omap_hwmod_ocp_if *am33xx_usbss_slaves[] = {
2925 &am33xx_l3_slow__usbss,
2926 };
2928 static struct omap_hwmod_opt_clk usbss_opt_clks[] = {
2929 { .role = "clkdcoldo", .clk = "usbotg_fck" },
2930 };
2932 static struct omap_hwmod am33xx_usbss_hwmod = {
2933 .name = "usb_otg_hs",
2934 .mpu_irqs = am33xx_usbss_mpu_irqs,
2935 .main_clk = "usbotg_ick",
2936 .clkdm_name = "l4ls_clkdm",
2937 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2938 .prcm = {
2939 .omap4 = {
2940 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2941 .modulemode = MODULEMODE_SWCTRL,
2942 },
2943 },
2944 .opt_clks = usbss_opt_clks,
2945 .opt_clks_cnt = ARRAY_SIZE(usbss_opt_clks),
2946 .slaves = am33xx_usbss_slaves,
2947 .slaves_cnt = ARRAY_SIZE(am33xx_usbss_slaves),
2948 .class = &am33xx_usbotg_class,
2949 };
2951 static __initdata struct omap_hwmod *am33xx_hwmods[] = {
2952 /* l3 class */
2953 &am33xx_l3_instr_hwmod,
2954 &am33xx_l3_main_hwmod,
2955 /* l3s class */
2956 &am33xx_l3slow_hwmod,
2957 /* l4hs class */
2958 &am33xx_l4_hs_hwmod,
2959 /* l4fw class */
2960 &am33xx_l4fw_hwmod,
2961 /* l4ls class */
2962 &am33xx_l4ls_hwmod,
2963 /* l4per class */
2964 &am33xx_l4per_hwmod,
2965 /* l4wkup class */
2966 &am33xx_l4wkup_hwmod,
2968 /* clkdiv32k class */
2969 &am33xx_clkdiv32k_hwmod,
2970 /* mpu class */
2971 &am33xx_mpu_hwmod,
2972 /* adc_tsc class */
2973 &am33xx_adc_tsc_hwmod,
2974 /* aes class */
2975 &am33xx_aes0_hwmod,
2976 /* cefuse class */
2977 &am33xx_cefuse_hwmod,
2978 /* control class */
2979 &am33xx_control_hwmod,
2980 /* dcan class */
2981 &am33xx_dcan0_hwmod,
2982 &am33xx_dcan1_hwmod,
2983 /* debugss class */
2984 &am33xx_debugss_hwmod,
2985 /* elm class */
2986 &am33xx_elm_hwmod,
2987 /* emif_fw class */
2988 &am33xx_emif_fw_hwmod,
2989 /* epwmss class */
2990 &am33xx_epwmss0_hwmod,
2991 &am33xx_epwmss1_hwmod,
2992 &am33xx_epwmss2_hwmod,
2993 /* gpio class */
2994 &am33xx_gpio0_hwmod,
2995 &am33xx_gpio1_hwmod,
2996 &am33xx_gpio2_hwmod,
2997 &am33xx_gpio3_hwmod,
2998 /* gpmc class */
2999 &am33xx_gpmc_hwmod,
3000 /* i2c class */
3001 &am33xx_i2c1_hwmod,
3002 &am33xx_i2c2_hwmod,
3003 /* icss class */
3004 &am33xx_icss_hwmod,
3005 /* ieee5000 class */
3006 &am33xx_ieee5000_hwmod,
3007 /* mailbox class */
3008 &am33xx_mailbox_hwmod,
3009 /* mcasp class */
3010 &am33xx_mcasp0_hwmod,
3011 &am33xx_mcasp1_hwmod,
3012 /* mmc class */
3013 &am33xx_mmc0_hwmod,
3014 &am33xx_mmc1_hwmod,
3015 &am33xx_mmc2_hwmod,
3016 /* ocmcram class */
3017 &am33xx_ocmcram_hwmod,
3018 /* ocpwp class */
3019 &am33xx_ocpwp_hwmod,
3020 /* sha0 class */
3021 &am33xx_sha0_hwmod,
3022 /* smartreflex class */
3023 &am33xx_smartreflex0_hwmod,
3024 &am33xx_smartreflex1_hwmod,
3025 /* spi class */
3026 &am33xx_spi0_hwmod,
3027 &am33xx_spi1_hwmod,
3028 /* spinlock class */
3029 &am33xx_spinlock_hwmod,
3030 /* uart class */
3031 &am33xx_uart1_hwmod,
3032 &am33xx_uart2_hwmod,
3033 &am33xx_uart3_hwmod,
3034 &am33xx_uart4_hwmod,
3035 &am33xx_uart5_hwmod,
3036 &am33xx_uart6_hwmod,
3037 /* timer class */
3038 &am33xx_timer0_hwmod,
3039 &am33xx_timer1_hwmod,
3040 &am33xx_timer2_hwmod,
3041 &am33xx_timer3_hwmod,
3042 &am33xx_timer4_hwmod,
3043 &am33xx_timer5_hwmod,
3044 &am33xx_timer6_hwmod,
3045 &am33xx_timer7_hwmod,
3046 /* wkup_m3 class */
3047 &am33xx_wkup_m3_hwmod,
3048 /* wd_timer class */
3049 &am33xx_wd_timer1_hwmod,
3050 /* usbss hwmod */
3051 &am33xx_usbss_hwmod,
3052 /* cpgmac0 class */
3053 &am33xx_cpgmac0_hwmod,
3054 &am33xx_wdt0_hwmod, /* Secure WDT */
3055 /* tptc class */
3056 &am33xx_tptc0_hwmod,
3057 &am33xx_tptc1_hwmod,
3058 &am33xx_tptc2_hwmod,
3059 /* tpcc class */
3060 &am33xx_tpcc_hwmod,
3061 /* LCDC class */
3062 &am33xx_lcdc_hwmod,
3063 /* rtc */
3064 &am33xx_rtc_hwmod,
3065 NULL,
3066 };
3068 int __init am33xx_hwmod_init(void)
3069 {
3070 return omap_hwmod_register(am33xx_hwmods);
3071 }