1 /*
2 * Hardware modules present on the AM33XX chips
3 *
4 * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
17 #include <linux/io.h>
19 #include <plat/omap_hwmod.h>
20 #include <plat/cpu.h>
21 #include <plat/gpio.h>
22 #include <plat/dma.h>
23 #include <plat/mmc.h>
24 #include <plat/mcspi.h>
26 #include "omap_hwmod_common_data.h"
27 #include "control.h"
28 #include "cm33xx.h"
30 /* Backward references (IPs with Bus Master capability) */
31 static struct omap_hwmod am33xx_mpu_hwmod;
32 static struct omap_hwmod am33xx_l3slow_hwmod;
33 static struct omap_hwmod am33xx_l4wkup_hwmod;
34 static struct omap_hwmod am33xx_l4per_hwmod;
35 static struct omap_hwmod am33xx_uart1_hwmod;
36 static struct omap_hwmod am33xx_uart2_hwmod;
37 static struct omap_hwmod am33xx_uart3_hwmod;
38 static struct omap_hwmod am33xx_uart4_hwmod;
39 static struct omap_hwmod am33xx_uart5_hwmod;
40 static struct omap_hwmod am33xx_uart6_hwmod;
41 static struct omap_hwmod am33xx_timer0_hwmod;
42 static struct omap_hwmod am33xx_timer1_hwmod;
43 static struct omap_hwmod am33xx_timer2_hwmod;
44 static struct omap_hwmod am33xx_timer3_hwmod;
45 static struct omap_hwmod am33xx_timer4_hwmod;
46 static struct omap_hwmod am33xx_timer5_hwmod;
47 static struct omap_hwmod am33xx_timer6_hwmod;
48 static struct omap_hwmod am33xx_timer7_hwmod;
49 static struct omap_hwmod am33xx_wd_timer1_hwmod;
50 static struct omap_hwmod am33xx_cpgmac0_hwmod;
51 static struct omap_hwmod am33xx_icss_hwmod;
52 static struct omap_hwmod am33xx_ieee5000_hwmod;
53 static struct omap_hwmod am33xx_tptc0_hwmod;
54 static struct omap_hwmod am33xx_tptc1_hwmod;
55 static struct omap_hwmod am33xx_tptc2_hwmod;
56 static struct omap_hwmod am33xx_gpio0_hwmod;
57 static struct omap_hwmod am33xx_gpio1_hwmod;
58 static struct omap_hwmod am33xx_gpio2_hwmod;
59 static struct omap_hwmod am33xx_gpio3_hwmod;
60 static struct omap_hwmod am33xx_i2c1_hwmod;
61 static struct omap_hwmod am33xx_i2c2_hwmod;
62 static struct omap_hwmod am33xx_usbss_hwmod;
63 static struct omap_hwmod am33xx_mmc0_hwmod;
64 static struct omap_hwmod am33xx_mmc1_hwmod;
65 static struct omap_hwmod am33xx_mmc2_hwmod;
66 static struct omap_hwmod am33xx_spi0_hwmod;
67 static struct omap_hwmod am33xx_spi1_hwmod;
69 /*
70 * Interconnects hwmod structures
71 * hwmods that compose the global AM33XX OCP interconnect
72 */
74 /* MPU -> L3_SLOW Peripheral interface */
75 static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = {
76 .master = &am33xx_mpu_hwmod,
77 .slave = &am33xx_l3slow_hwmod,
78 .user = OCP_USER_MPU,
79 };
81 /* L3 SLOW -> L4_PER Peripheral interface */
82 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = {
83 .master = &am33xx_l3slow_hwmod,
84 .slave = &am33xx_l4per_hwmod,
85 .user = OCP_USER_MPU,
86 };
88 /* L3 SLOW -> L4_WKUP Peripheral interface */
89 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = {
90 .master = &am33xx_l3slow_hwmod,
91 .slave = &am33xx_l4wkup_hwmod,
92 .user = OCP_USER_MPU,
93 };
95 /* Master interfaces on the L4_WKUP interconnect */
96 static struct omap_hwmod_ocp_if *am33xx_l3_slow_masters[] = {
97 &am33xx_l3_slow__l4_per,
98 &am33xx_l3_slow__l4_wkup,
99 };
101 /* Slave interfaces on the L3_SLOW interconnect */
102 static struct omap_hwmod_ocp_if *am33xx_l3_slow_slaves[] = {
103 &am33xx_mpu__l3_slow,
104 };
106 static struct omap_hwmod am33xx_l3slow_hwmod = {
107 .name = "l3_slow",
108 .class = &l3_hwmod_class,
109 .clkdm_name = "l3s_clkdm",
110 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
111 .masters = am33xx_l3_slow_masters,
112 .masters_cnt = ARRAY_SIZE(am33xx_l3_slow_masters),
113 .slaves = am33xx_l3_slow_slaves,
114 .slaves_cnt = ARRAY_SIZE(am33xx_l3_slow_slaves),
115 };
117 /* L4 PER -> GPIO2 */
118 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
119 {
120 .pa_start = AM33XX_GPIO1_BASE,
121 .pa_end = AM33XX_GPIO1_BASE + SZ_4K - 1,
122 .flags = ADDR_TYPE_RT
123 },
124 { }
125 };
127 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
128 .master = &am33xx_l4per_hwmod,
129 .slave = &am33xx_gpio1_hwmod,
130 .clk = "l4ls_fck",
131 .addr = am33xx_gpio1_addrs,
132 .user = OCP_USER_MPU | OCP_USER_SDMA,
133 };
135 /* L4 PER -> GPIO3 */
136 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
137 {
138 .pa_start = AM33XX_GPIO2_BASE,
139 .pa_end = AM33XX_GPIO2_BASE + SZ_4K - 1,
140 .flags = ADDR_TYPE_RT
141 },
142 { }
143 };
145 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
146 .master = &am33xx_l4per_hwmod,
147 .slave = &am33xx_gpio2_hwmod,
148 .clk = "l4ls_fck",
149 .addr = am33xx_gpio2_addrs,
150 .user = OCP_USER_MPU | OCP_USER_SDMA,
151 };
153 /* L4 PER -> GPIO4 */
154 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
155 {
156 .pa_start = AM33XX_GPIO3_BASE,
157 .pa_end = AM33XX_GPIO3_BASE + SZ_4K - 1,
158 .flags = ADDR_TYPE_RT
159 },
160 { }
161 };
163 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
164 .master = &am33xx_l4per_hwmod,
165 .slave = &am33xx_gpio3_hwmod,
166 .clk = "l4ls_fck",
167 .addr = am33xx_gpio3_addrs,
168 .user = OCP_USER_MPU | OCP_USER_SDMA,
169 };
171 /* Master interfaces on the L4_PER interconnect */
172 static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = {
173 &am33xx_l4_per__gpio1,
174 &am33xx_l4_per__gpio2,
175 &am33xx_l4_per__gpio3,
176 };
177 /* Slave interfaces on the L4_PER interconnect */
178 static struct omap_hwmod_ocp_if *am33xx_l4_per_slaves[] = {
179 &am33xx_l3_slow__l4_per,
180 };
182 static struct omap_hwmod am33xx_l4per_hwmod = {
183 .name = "l4_per",
184 .class = &l4_hwmod_class,
185 .clkdm_name = "l4ls_clkdm",
186 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
187 .masters = am33xx_l4_per_masters,
188 .masters_cnt = ARRAY_SIZE(am33xx_l4_per_masters),
189 .slaves = am33xx_l4_per_slaves,
190 .slaves_cnt = ARRAY_SIZE(am33xx_l4_per_slaves),
191 };
193 /* L4 WKUP -> I2C1 */
194 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
195 {
196 .pa_start = AM33XX_I2C0_BASE,
197 .pa_end = AM33XX_I2C0_BASE + SZ_4K - 1,
198 .flags = ADDR_TYPE_RT
199 },
200 { }
201 };
203 static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = {
204 .master = &am33xx_l4wkup_hwmod,
205 .slave = &am33xx_i2c1_hwmod,
206 .addr = am33xx_i2c1_addr_space,
207 .user = OCP_USER_MPU,
208 };
210 /* L4 WKUP -> GPIO1 */
211 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
212 {
213 .pa_start = AM33XX_GPIO0_BASE,
214 .pa_end = AM33XX_GPIO0_BASE + SZ_4K - 1,
215 .flags = ADDR_TYPE_RT
216 },
217 { }
218 };
220 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
221 .master = &am33xx_l4wkup_hwmod,
222 .slave = &am33xx_gpio0_hwmod,
223 .clk = "l4ls_fck",
224 .addr = am33xx_gpio0_addrs,
225 .user = OCP_USER_MPU | OCP_USER_SDMA,
226 };
228 /* Master interfaces on the L4_WKUP interconnect */
229 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = {
230 &am33xx_l4_wkup__gpio0,
231 };
232 /* Slave interfaces on the L4_WKUP interconnect */
233 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_slaves[] = {
234 &am33xx_l3_slow__l4_wkup,
235 };
237 static struct omap_hwmod am33xx_l4wkup_hwmod = {
238 .name = "l4_wkup",
239 .class = &l4_hwmod_class,
240 .clkdm_name = "l4_wkup_clkdm",
241 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
242 .masters = am33xx_l4_wkup_masters,
243 .masters_cnt = ARRAY_SIZE(am33xx_l4_wkup_masters),
244 .slaves = am33xx_l4_wkup_slaves,
245 .slaves_cnt = ARRAY_SIZE(am33xx_l4_wkup_slaves),
246 };
248 /* 'adc_tsc' class */
249 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
250 .name = "adc_tsc",
251 };
253 /* adc_tsc */
254 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
255 { .irq = AM33XX_IRQ_TSC },
256 { .irq = -1 }
257 };
259 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
260 .name = "adc_tsc",
261 .class = &am33xx_adc_tsc_hwmod_class,
262 .mpu_irqs = am33xx_adc_tsc_irqs,
263 .main_clk = "adc_tsc_fck",
264 .clkdm_name = "l4_wkup_clkdm",
265 .prcm = {
266 .omap4 = {
267 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
268 .modulemode = MODULEMODE_SWCTRL,
269 },
270 },
271 };
273 /* 'aes' class */
274 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
275 .name = "aes",
276 };
278 /* aes0 */
279 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
280 { .irq = AM33XX_IRQ_AESEIP36t0_S },
281 { .irq = -1 }
282 };
284 static struct omap_hwmod am33xx_aes0_hwmod = {
285 .name = "aes0",
286 .class = &am33xx_aes_hwmod_class,
287 .mpu_irqs = am33xx_aes0_irqs,
288 .main_clk = "aes0_fck",
289 .clkdm_name = "l3_clkdm",
290 .prcm = {
291 .omap4 = {
292 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
293 .modulemode = MODULEMODE_SWCTRL,
294 },
295 },
296 };
298 /* 'cefuse' class */
299 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
300 .name = "cefuse",
301 };
303 /* cefuse */
304 static struct omap_hwmod am33xx_cefuse_hwmod = {
305 .name = "cefuse",
306 .class = &am33xx_cefuse_hwmod_class,
307 .main_clk = "cefuse_fck",
308 .clkdm_name = "l4_cefuse_clkdm",
309 .prcm = {
310 .omap4 = {
311 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
312 .modulemode = MODULEMODE_SWCTRL,
313 },
314 },
315 };
317 /* 'clkdiv32k' class */
318 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
319 .name = "clkdiv32k",
320 };
322 /* clkdiv32k */
323 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
324 .name = "clkdiv32k",
325 .class = &am33xx_clkdiv32k_hwmod_class,
326 .main_clk = "clkdiv32k_fck",
327 .clkdm_name = "clk_24mhz_clkdm",
328 .prcm = {
329 .omap4 = {
330 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
331 .modulemode = MODULEMODE_SWCTRL,
332 },
333 },
334 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
335 };
337 /* 'control' class */
338 static struct omap_hwmod_class am33xx_control_hwmod_class = {
339 .name = "control",
340 };
342 /* control */
343 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
344 { .irq = AM33XX_IRQ_CONTROL_PLATFORM },
345 { .irq = -1 }
346 };
348 static struct omap_hwmod am33xx_control_hwmod = {
349 .name = "control",
350 .class = &am33xx_control_hwmod_class,
351 .mpu_irqs = am33xx_control_irqs,
352 .main_clk = "control_fck",
353 .clkdm_name = "l4_wkup_clkdm",
354 .prcm = {
355 .omap4 = {
356 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
357 .modulemode = MODULEMODE_SWCTRL,
358 },
359 },
360 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
361 };
363 /* 'cpgmac0' class */
364 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
365 .name = "cpgmac0",
366 };
368 /* cpgmac0 */
369 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
370 .name = "cpgmac0",
371 .class = &am33xx_cpgmac0_hwmod_class,
372 .main_clk = "cpgmac0_fck",
373 .clkdm_name = "cpsw_125mhz_clkdm",
374 .prcm = {
375 .omap4 = {
376 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
377 .modulemode = MODULEMODE_SWCTRL,
378 },
379 },
380 };
382 /* 'dcan' class */
383 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
384 .name = "dcan",
385 };
387 /* dcan0 */
388 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
389 { .irq = AM33XX_IRQ_DCAN0_0 },
390 { .irq = -1 }
391 };
393 static struct omap_hwmod am33xx_dcan0_hwmod = {
394 .name = "dcan0",
395 .class = &am33xx_dcan_hwmod_class,
396 .mpu_irqs = am33xx_dcan0_irqs,
397 .main_clk = "dcan0_fck",
398 .clkdm_name = "l4ls_clkdm",
399 .prcm = {
400 .omap4 = {
401 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
402 .modulemode = MODULEMODE_SWCTRL,
403 },
404 },
405 };
407 /* dcan1 */
408 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
409 { .irq = AM33XX_IRQ_DCAN1_0 },
410 { .irq = -1 }
411 };
412 static struct omap_hwmod am33xx_dcan1_hwmod = {
413 .name = "dcan1",
414 .class = &am33xx_dcan_hwmod_class,
415 .mpu_irqs = am33xx_dcan1_irqs,
416 .main_clk = "dcan1_fck",
417 .clkdm_name = "l4ls_clkdm",
418 .prcm = {
419 .omap4 = {
420 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
421 .modulemode = MODULEMODE_SWCTRL,
422 },
423 },
424 };
426 /* 'debugss' class */
427 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
428 .name = "debugss",
429 };
431 /* debugss */
432 static struct omap_hwmod am33xx_debugss_hwmod = {
433 .name = "debugss",
434 .class = &am33xx_debugss_hwmod_class,
435 .main_clk = "debugss_fck",
436 .clkdm_name = "l3_aon_clkdm",
437 .prcm = {
438 .omap4 = {
439 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
440 .modulemode = MODULEMODE_SWCTRL,
441 },
442 },
443 };
445 /* 'elm' class */
446 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
447 .name = "elm",
448 };
450 /* elm */
451 static struct omap_hwmod am33xx_elm_hwmod = {
452 .name = "elm",
453 .class = &am33xx_elm_hwmod_class,
454 .main_clk = "elm_fck",
455 .clkdm_name = "l4ls_clkdm",
456 .prcm = {
457 .omap4 = {
458 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
459 .modulemode = MODULEMODE_SWCTRL,
460 },
461 },
462 };
464 /* 'emif_fw' class */
465 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
466 .name = "emif_fw",
467 };
469 /* emif_fw */
470 static struct omap_hwmod am33xx_emif_fw_hwmod = {
471 .name = "emif_fw",
472 .class = &am33xx_emif_fw_hwmod_class,
473 .main_clk = "emif_fw_fck",
474 .clkdm_name = "l4fw_clkdm",
475 .prcm = {
476 .omap4 = {
477 .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
478 .modulemode = MODULEMODE_SWCTRL,
479 },
480 },
481 .flags = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
482 };
484 /* 'epwmss' class */
485 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
486 .name = "epwmss",
487 };
489 /* epwmss0 */
490 static struct omap_hwmod am33xx_epwmss0_hwmod = {
491 .name = "epwmss0",
492 .class = &am33xx_epwmss_hwmod_class,
493 .main_clk = "epwmss0_fck",
494 .clkdm_name = "l4ls_clkdm",
495 .prcm = {
496 .omap4 = {
497 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
498 .modulemode = MODULEMODE_SWCTRL,
499 },
500 },
501 };
503 /* epwmss1 */
504 static struct omap_hwmod am33xx_epwmss1_hwmod = {
505 .name = "epwmss1",
506 .class = &am33xx_epwmss_hwmod_class,
507 .main_clk = "epwmss1_fck",
508 .clkdm_name = "l4ls_clkdm",
509 .prcm = {
510 .omap4 = {
511 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
512 .modulemode = MODULEMODE_SWCTRL,
513 },
514 },
515 };
517 /* epwmss2 */
518 static struct omap_hwmod am33xx_epwmss2_hwmod = {
519 .name = "epwmss2",
520 .class = &am33xx_epwmss_hwmod_class,
521 .main_clk = "epwmss2_fck",
522 .clkdm_name = "l4ls_clkdm",
523 .prcm = {
524 .omap4 = {
525 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
526 .modulemode = MODULEMODE_SWCTRL,
527 },
528 },
529 };
531 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
532 .rev_offs = 0x0000,
533 .sysc_offs = 0x0010,
534 .syss_offs = 0x0114,
535 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
536 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
537 SYSS_HAS_RESET_STATUS),
538 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
539 SIDLE_SMART_WKUP),
540 .sysc_fields = &omap_hwmod_sysc_type1,
541 };
543 /* 'gpio' class */
544 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
545 .name = "gpio",
546 .sysc = &am33xx_gpio_sysc,
547 .rev = 2,
548 };
550 /* gpio dev_attr */
551 static struct omap_gpio_dev_attr gpio_dev_attr = {
552 .bank_width = 32,
553 .dbck_flag = true,
554 };
556 /* gpio0 */
557 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
558 { .irq = AM33XX_IRQ_GPIO0_1 },
559 { .irq = -1 }
560 };
562 /* gpio0 slave ports */
563 static struct omap_hwmod_ocp_if *am33xx_gpio0_slaves[] = {
564 &am33xx_l4_wkup__gpio0,
565 };
567 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
568 { .role = "dbclk", .clk = "gpio0_dbclk" },
569 };
571 /* gpio0 */
572 static struct omap_hwmod am33xx_gpio0_hwmod = {
573 .name = "gpio1",
574 .class = &am33xx_gpio_hwmod_class,
575 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
576 .mpu_irqs = am33xx_gpio0_irqs,
577 .main_clk = "gpio0_fck",
578 .clkdm_name = "l4_wkup_clkdm",
579 .prcm = {
580 .omap4 = {
581 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
582 .modulemode = MODULEMODE_SWCTRL,
583 },
584 },
585 .opt_clks = gpio0_opt_clks,
586 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
587 .dev_attr = &gpio_dev_attr,
588 .slaves = am33xx_gpio0_slaves,
589 .slaves_cnt = ARRAY_SIZE(am33xx_gpio0_slaves),
590 };
592 /* gpio1 */
593 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
594 { .irq = AM33XX_IRQ_GPIO1_1 },
595 { .irq = -1 }
596 };
598 /* gpio1 slave ports */
599 static struct omap_hwmod_ocp_if *am33xx_gpio1_slaves[] = {
600 &am33xx_l4_per__gpio1,
601 };
603 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
604 { .role = "dbclk", .clk = "gpio1_dbclk" },
605 };
607 static struct omap_hwmod am33xx_gpio1_hwmod = {
608 .name = "gpio2",
609 .class = &am33xx_gpio_hwmod_class,
610 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
611 .mpu_irqs = am33xx_gpio1_irqs,
612 .main_clk = "gpio1_fck",
613 .clkdm_name = "l4ls_clkdm",
614 .prcm = {
615 .omap4 = {
616 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
617 .modulemode = MODULEMODE_SWCTRL,
618 },
619 },
620 .opt_clks = gpio1_opt_clks,
621 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
622 .dev_attr = &gpio_dev_attr,
623 .slaves = am33xx_gpio1_slaves,
624 .slaves_cnt = ARRAY_SIZE(am33xx_gpio1_slaves),
625 };
627 /* gpio2 */
628 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
629 { .irq = AM33XX_IRQ_GPIO2_1 },
630 { .irq = -1 }
631 };
633 /* gpio2 slave ports */
634 static struct omap_hwmod_ocp_if *am33xx_gpio2_slaves[] = {
635 &am33xx_l4_per__gpio2,
636 };
638 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
639 { .role = "dbclk", .clk = "gpio2_dbclk" },
640 };
642 /* gpio2 */
643 static struct omap_hwmod am33xx_gpio2_hwmod = {
644 .name = "gpio3",
645 .class = &am33xx_gpio_hwmod_class,
646 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
647 .mpu_irqs = am33xx_gpio2_irqs,
648 .main_clk = "gpio2_fck",
649 .clkdm_name = "l4ls_clkdm",
650 .prcm = {
651 .omap4 = {
652 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
653 .modulemode = MODULEMODE_SWCTRL,
654 },
655 },
656 .opt_clks = gpio2_opt_clks,
657 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
658 .dev_attr = &gpio_dev_attr,
659 .slaves = am33xx_gpio2_slaves,
660 .slaves_cnt = ARRAY_SIZE(am33xx_gpio2_slaves),
661 };
663 /* gpio3 */
664 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
665 { .irq = AM33XX_IRQ_GPIO3_1 },
666 { .irq = -1 }
667 };
669 /* gpio3 slave ports */
670 static struct omap_hwmod_ocp_if *am33xx_gpio3_slaves[] = {
671 &am33xx_l4_per__gpio3,
672 };
674 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
675 { .role = "dbclk", .clk = "gpio3_dbclk" },
676 };
678 /* gpio3 */
679 static struct omap_hwmod am33xx_gpio3_hwmod = {
680 .name = "gpio4",
681 .class = &am33xx_gpio_hwmod_class,
682 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
683 .mpu_irqs = am33xx_gpio3_irqs,
684 .main_clk = "gpio3_fck",
685 .clkdm_name = "l4ls_clkdm",
686 .prcm = {
687 .omap4 = {
688 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
689 .modulemode = MODULEMODE_SWCTRL,
690 },
691 },
692 .opt_clks = gpio3_opt_clks,
693 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
694 .dev_attr = &gpio_dev_attr,
695 .slaves = am33xx_gpio3_slaves,
696 .slaves_cnt = ARRAY_SIZE(am33xx_gpio3_slaves),
697 };
699 /* 'gpmc' class */
701 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
702 .name = "gpmc",
703 };
705 /* gpmc */
706 static struct omap_hwmod am33xx_gpmc_hwmod = {
707 .name = "gpmc",
708 .class = &am33xx_gpmc_hwmod_class,
709 .main_clk = "gpmc_fck",
710 .clkdm_name = "l3s_clkdm",
711 .prcm = {
712 .omap4 = {
713 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
714 .modulemode = MODULEMODE_SWCTRL,
715 },
716 },
717 };
719 /* 'i2c' class */
721 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
722 .sysc_offs = 0x0010,
723 .syss_offs = 0x0090,
724 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
725 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
726 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
727 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
728 SIDLE_SMART_WKUP),
729 .sysc_fields = &omap_hwmod_sysc_type1,
730 };
732 static struct omap_i2c_dev_attr i2c_dev_attr = {
733 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
734 };
736 static struct omap_hwmod_class i2c_class = {
737 .name = "i2c",
738 .sysc = &am33xx_i2c_sysc,
739 .rev = OMAP_I2C_IP_VERSION_2,
740 .reset = &omap_i2c_reset,
741 };
743 /* I2C1 */
744 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
745 { .irq = AM33XX_IRQ_MSHSI2COCP0 },
746 { .irq = -1 }
747 };
749 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
750 { .name = "tx", .dma_req = 0, },
751 { .name = "rx", .dma_req = 0, },
752 { .dma_req = -1 }
753 };
755 static struct omap_hwmod_ocp_if *am33xx_i2c1_slaves[] = {
756 &am33xx_l4_wkup_i2c1,
757 };
759 static struct omap_hwmod am33xx_i2c1_hwmod = {
760 .name = "i2c1",
761 .mpu_irqs = i2c1_mpu_irqs,
762 .sdma_reqs = i2c1_edma_reqs,
763 .main_clk = "i2c1_fck",
764 .clkdm_name = "l4_wkup_clkdm",
765 .prcm = {
766 .omap4 = {
767 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
768 .modulemode = MODULEMODE_SWCTRL,
769 },
770 },
771 .flags = HWMOD_16BIT_REG,
772 .dev_attr = &i2c_dev_attr,
773 .slaves = am33xx_i2c1_slaves,
774 .slaves_cnt = ARRAY_SIZE(am33xx_i2c1_slaves),
775 .class = &i2c_class,
776 };
778 /* i2c2 */
779 /* l4 per -> i2c2 */
780 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
781 {
782 .pa_start = AM33XX_I2C1_BASE,
783 .pa_end = AM33XX_I2C1_BASE + SZ_4K - 1,
784 .flags = ADDR_TYPE_RT
785 },
786 { }
787 };
789 static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = {
790 .master = &am33xx_l4per_hwmod,
791 .slave = &am33xx_i2c2_hwmod,
792 .addr = am33xx_i2c2_addr_space,
793 .user = OCP_USER_MPU,
794 };
796 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
797 { .irq = AM33XX_IRQ_MSHSI2COCP1 },
798 { .irq = -1 }
799 };
801 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
802 { .name = "tx", .dma_req = 0, },
803 { .name = "rx", .dma_req = 0, },
804 { .dma_req = -1 }
805 };
807 static struct omap_hwmod_ocp_if *am33xx_i2c2_slaves[] = {
808 &am335_l4_per_i2c2,
809 };
811 static struct omap_hwmod am33xx_i2c2_hwmod = {
812 .name = "i2c2",
813 .mpu_irqs = i2c2_mpu_irqs,
814 .sdma_reqs = i2c2_edma_reqs,
815 .main_clk = "i2c2_fck",
816 .clkdm_name = "l4ls_clkdm",
817 .prcm = {
818 .omap4 = {
819 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
820 .modulemode = MODULEMODE_SWCTRL,
821 },
822 },
823 .flags = HWMOD_16BIT_REG,
824 .dev_attr = &i2c_dev_attr,
825 .slaves = am33xx_i2c2_slaves,
826 .slaves_cnt = ARRAY_SIZE(am33xx_i2c2_slaves),
827 .class = &i2c_class,
828 };
830 /* 'icss' class */
831 static struct omap_hwmod_class am33xx_icss_hwmod_class = {
832 .name = "icss",
833 };
835 /* icss */
836 static struct omap_hwmod am33xx_icss_hwmod = {
837 .name = "icss",
838 .class = &am33xx_icss_hwmod_class,
839 .main_clk = "icss_fck",
840 .clkdm_name = "icss_ocp_clkdm",
841 .prcm = {
842 .omap4 = {
843 .clkctrl_offs = AM33XX_CM_PER_ICSS_CLKCTRL_OFFSET,
844 .modulemode = MODULEMODE_SWCTRL,
845 },
846 },
847 };
849 /* 'ieee5000' class */
850 static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = {
851 .name = "ieee5000",
852 };
854 /* ieee5000 */
855 static struct omap_hwmod am33xx_ieee5000_hwmod = {
856 .name = "ieee5000",
857 .class = &am33xx_ieee5000_hwmod_class,
858 .main_clk = "ieee5000_fck",
859 .clkdm_name = "l3s_clkdm",
860 .prcm = {
861 .omap4 = {
862 .clkctrl_offs = AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET,
863 .modulemode = MODULEMODE_SWCTRL,
864 },
865 },
866 };
869 /* 'l3' class */
870 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
871 .name = "l3",
872 };
874 /* l4_hs */
875 static struct omap_hwmod am33xx_l4_hs_hwmod = {
876 .name = "l4_hs",
877 .class = &am33xx_l3_hwmod_class,
878 .clkdm_name = "l4hs_clkdm",
879 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
880 .prcm = {
881 .omap4 = {
882 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
883 .modulemode = MODULEMODE_SWCTRL,
884 },
885 },
886 };
888 /* l3_instr */
889 static struct omap_hwmod am33xx_l3_instr_hwmod = {
890 .name = "l3_instr",
891 .class = &am33xx_l3_hwmod_class,
892 .clkdm_name = "l3_clkdm",
893 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
894 .prcm = {
895 .omap4 = {
896 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
897 .modulemode = MODULEMODE_SWCTRL,
898 },
899 },
900 };
902 /* l3_main */
903 static struct omap_hwmod am33xx_l3_main_hwmod = {
904 .name = "l3_main",
905 .class = &am33xx_l3_hwmod_class,
906 .clkdm_name = "l3_clkdm",
907 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
908 .prcm = {
909 .omap4 = {
910 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
911 .modulemode = MODULEMODE_SWCTRL,
912 },
913 },
914 };
916 /* 'l4fw' class */
917 static struct omap_hwmod_class am33xx_l4fw_hwmod_class = {
918 .name = "l4fw",
919 };
921 /* l4fw */
922 static struct omap_hwmod am33xx_l4fw_hwmod = {
923 .name = "l4fw",
924 .class = &am33xx_l4fw_hwmod_class,
925 .clkdm_name = "l4fw_clkdm",
926 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
927 .prcm = {
928 .omap4 = {
929 .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
930 .modulemode = MODULEMODE_SWCTRL,
931 },
932 },
933 };
935 /* 'l4ls' class */
936 static struct omap_hwmod_class am33xx_l4ls_hwmod_class = {
937 .name = "l4ls",
938 };
940 /* l4ls */
941 static struct omap_hwmod am33xx_l4ls_hwmod = {
942 .name = "l4ls",
943 .class = &am33xx_l4ls_hwmod_class,
944 .main_clk = "l4ls_fck",
945 .clkdm_name = "l4ls_clkdm",
946 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
947 .prcm = {
948 .omap4 = {
949 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
950 .modulemode = MODULEMODE_SWCTRL,
951 },
952 },
953 };
955 /* 'lcdc' class */
956 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
957 .name = "lcdc",
958 };
960 /* lcdc */
961 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
962 { .irq = AM33XX_IRQ_LCD },
963 { .irq = -1 }
964 };
966 static struct omap_hwmod am33xx_lcdc_hwmod = {
967 .name = "lcdc",
968 .class = &am33xx_lcdc_hwmod_class,
969 .mpu_irqs = am33xx_lcdc_irqs,
970 .main_clk = "lcdc_fck",
971 .clkdm_name = "lcdc_clkdm",
972 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
973 .prcm = {
974 .omap4 = {
975 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
976 .modulemode = MODULEMODE_SWCTRL,
977 },
978 },
979 };
981 /* 'mcasp' class */
982 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
983 .name = "mcasp",
984 };
986 /* mcasp0 */
987 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
988 { .irq = 80 },
989 { .irq = -1 }
990 };
992 static struct omap_hwmod am33xx_mcasp0_hwmod = {
993 .name = "mcasp0",
994 .class = &am33xx_mcasp_hwmod_class,
995 .mpu_irqs = am33xx_mcasp0_irqs,
996 .main_clk = "mcasp0_fck",
997 .clkdm_name = "l3s_clkdm",
998 .prcm = {
999 .omap4 = {
1000 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1001 .modulemode = MODULEMODE_SWCTRL,
1002 },
1003 },
1004 };
1006 /* 'mmc' class */
1008 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1009 .rev_offs = 0x1fc,
1010 .sysc_offs = 0x10,
1011 .syss_offs = 0x14,
1012 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1013 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1014 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1015 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1016 .sysc_fields = &omap_hwmod_sysc_type1,
1017 };
1019 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1020 .name = "mmc",
1021 .sysc = &am33xx_mmc_sysc,
1022 };
1024 /* mmc0 */
1025 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1026 { .irq = AM33XX_IRQ_MMCHS0 },
1027 { .irq = -1 }
1028 };
1030 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1031 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS0_W, },
1032 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS0_R, },
1033 { .dma_req = -1 }
1034 };
1036 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
1037 {
1038 .pa_start = AM33XX_MMC0_BASE,
1039 .pa_end = AM33XX_MMC0_BASE + SZ_4K - 1,
1040 .flags = ADDR_TYPE_RT
1041 },
1042 { }
1043 };
1045 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc0 = {
1046 .master = &am33xx_l4ls_hwmod,
1047 .slave = &am33xx_mmc0_hwmod,
1048 .clk = "mmc0_ick",
1049 .addr = am33xx_mmc0_addr_space,
1050 .user = OCP_USER_MPU,
1051 };
1053 static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = {
1054 &am33xx_l4ls__mmc0,
1055 };
1057 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1058 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1059 };
1061 static struct omap_hwmod am33xx_mmc0_hwmod = {
1062 .name = "mmc1",
1063 .class = &am33xx_mmc_hwmod_class,
1064 .mpu_irqs = am33xx_mmc0_irqs,
1065 .sdma_reqs = am33xx_mmc0_edma_reqs,
1066 .main_clk = "mmc0_fck",
1067 .clkdm_name = "l4ls_clkdm",
1068 .prcm = {
1069 .omap4 = {
1070 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1071 .modulemode = MODULEMODE_SWCTRL,
1072 },
1073 },
1074 .dev_attr = &am33xx_mmc0_dev_attr,
1075 .slaves = am33xx_mmc0_slaves,
1076 .slaves_cnt = ARRAY_SIZE(am33xx_mmc0_slaves),
1077 };
1079 /* mmc1 */
1080 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1081 { .irq = AM33XX_IRQ_MMCHS1 },
1082 { .irq = -1 }
1083 };
1085 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1086 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS1_W, },
1087 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS1_R, },
1088 { .dma_req = -1 }
1089 };
1091 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
1092 {
1093 .pa_start = AM33XX_MMC1_BASE,
1094 .pa_end = AM33XX_MMC1_BASE + SZ_4K - 1,
1095 .flags = ADDR_TYPE_RT
1096 },
1097 { }
1098 };
1100 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc1 = {
1101 .master = &am33xx_l4ls_hwmod,
1102 .slave = &am33xx_mmc1_hwmod,
1103 .clk = "mmc1_ick",
1104 .addr = am33xx_mmc1_addr_space,
1105 .user = OCP_USER_MPU,
1106 };
1108 static struct omap_hwmod_ocp_if *am33xx_mmc1_slaves[] = {
1109 &am33xx_l4ls__mmc1,
1110 };
1112 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1113 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1114 };
1116 static struct omap_hwmod am33xx_mmc1_hwmod = {
1117 .name = "mmc2",
1118 .class = &am33xx_mmc_hwmod_class,
1119 .mpu_irqs = am33xx_mmc1_irqs,
1120 .sdma_reqs = am33xx_mmc1_edma_reqs,
1121 .main_clk = "mmc1_fck",
1122 .clkdm_name = "l4ls_clkdm",
1123 .prcm = {
1124 .omap4 = {
1125 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1126 .modulemode = MODULEMODE_SWCTRL,
1127 },
1128 },
1129 .dev_attr = &am33xx_mmc1_dev_attr,
1130 .slaves = am33xx_mmc1_slaves,
1131 .slaves_cnt = ARRAY_SIZE(am33xx_mmc1_slaves),
1132 };
1134 /* mmc2 */
1135 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1136 { .irq = AM33XX_IRQ_MMCHS2 },
1137 { .irq = -1 }
1138 };
1140 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1141 { .name = "tx", .dma_req = 64, },
1142 { .name = "rx", .dma_req = 65, },
1143 { .dma_req = -1 }
1144 };
1146 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1147 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS2_W, },
1148 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS2_R, },
1149 { .dma_req = -1 }
1150 };
1152 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
1153 {
1154 .pa_start = AM33XX_MMC2_BASE,
1155 .pa_end = AM33XX_MMC2_BASE + SZ_64K - 1,
1156 .flags = ADDR_TYPE_RT
1157 },
1158 { }
1159 };
1161 static struct omap_hwmod_ocp_if am33xx_l3_main__mmc2 = {
1162 .master = &am33xx_l3_main_hwmod,
1163 .slave = &am33xx_mmc2_hwmod,
1164 .clk = "mmc2_ick",
1165 .addr = am33xx_mmc2_addr_space,
1166 .user = OCP_USER_MPU,
1167 };
1169 static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = {
1170 &am33xx_l3_main__mmc2,
1171 };
1173 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1174 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1175 };
1176 static struct omap_hwmod am33xx_mmc2_hwmod = {
1177 .name = "mmc3",
1178 .class = &am33xx_mmc_hwmod_class,
1179 .mpu_irqs = am33xx_mmc2_irqs,
1180 .sdma_reqs = am33xx_mmc2_edma_reqs,
1181 .main_clk = "mmc2_fck",
1182 .clkdm_name = "l3s_clkdm",
1183 .prcm = {
1184 .omap4 = {
1185 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1186 .modulemode = MODULEMODE_SWCTRL,
1187 },
1188 },
1189 .dev_attr = &am33xx_mmc2_dev_attr,
1190 .slaves = am33xx_mmc2_slaves,
1191 .slaves_cnt = ARRAY_SIZE(am33xx_mmc2_slaves),
1192 };
1194 /* Master interfaces on the MPU interconnect */
1195 static struct omap_hwmod_ocp_if *am33xx_l3_mpu_masters[] = {
1196 &am33xx_mpu__l3_slow,
1197 };
1199 /* mpu */
1200 static struct omap_hwmod am33xx_mpu_hwmod = {
1201 .name = "mpu",
1202 .class = &mpu_hwmod_class,
1203 .masters = am33xx_l3_mpu_masters,
1204 .masters_cnt = ARRAY_SIZE(am33xx_l3_mpu_masters),
1205 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1206 .main_clk = "mpu_fck",
1207 .clkdm_name = "mpu_clkdm",
1208 .prcm = {
1209 .omap4 = {
1210 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1211 .modulemode = MODULEMODE_SWCTRL,
1212 },
1213 },
1214 };
1216 /* 'ocmcram' class */
1217 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
1218 .name = "ocmcram",
1219 };
1221 /* ocmcram */
1222 static struct omap_hwmod am33xx_ocmcram_hwmod = {
1223 .name = "ocmcram",
1224 .class = &am33xx_ocmcram_hwmod_class,
1225 .main_clk = "ocmcram_fck",
1226 .clkdm_name = "l3_clkdm",
1227 .prcm = {
1228 .omap4 = {
1229 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
1230 .modulemode = MODULEMODE_SWCTRL,
1231 },
1232 },
1233 };
1235 /* 'ocpwp' class */
1236 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
1237 .name = "ocpwp",
1238 };
1240 /* ocpwp */
1241 static struct omap_hwmod am33xx_ocpwp_hwmod = {
1242 .name = "ocpwp",
1243 .class = &am33xx_ocpwp_hwmod_class,
1244 .main_clk = "ocpwp_fck",
1245 .clkdm_name = "l4ls_clkdm",
1246 .prcm = {
1247 .omap4 = {
1248 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
1249 .modulemode = MODULEMODE_SWCTRL,
1250 },
1251 },
1252 };
1254 /* 'rtc' class */
1255 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1256 .name = "rtc",
1257 };
1259 /* rtc */
1260 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1261 { .irq = AM33XX_IRQ_RTC_TIMER },
1262 { .irq = -1 }
1263 };
1265 static struct omap_hwmod am33xx_rtc_hwmod = {
1266 .name = "rtc",
1267 .class = &am33xx_rtc_hwmod_class,
1268 .mpu_irqs = am33xx_rtc_irqs,
1269 .main_clk = "rtc_fck",
1270 .clkdm_name = "l4_rtc_clkdm",
1271 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1272 .prcm = {
1273 .omap4 = {
1274 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1275 .modulemode = MODULEMODE_SWCTRL,
1276 },
1277 },
1278 };
1280 /* 'sha0' class */
1281 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
1282 .name = "sha0",
1283 };
1285 /* sha0 */
1286 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
1287 { .irq = AM33XX_IRQ_SHAEIP57t0_S },
1288 { .irq = -1 }
1289 };
1291 static struct omap_hwmod am33xx_sha0_hwmod = {
1292 .name = "sha0",
1293 .class = &am33xx_sha0_hwmod_class,
1294 .mpu_irqs = am33xx_sha0_irqs,
1295 .main_clk = "sha0_fck",
1296 .clkdm_name = "l3_clkdm",
1297 .prcm = {
1298 .omap4 = {
1299 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
1300 .modulemode = MODULEMODE_SWCTRL,
1301 },
1302 },
1303 };
1305 /* 'smartreflex' class */
1306 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
1307 .name = "smartreflex",
1308 };
1310 /* smartreflex0 */
1311 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
1312 { .irq = AM33XX_IRQ_SMARTREFLEX0 },
1313 { .irq = -1 }
1314 };
1316 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
1317 .name = "smartreflex0",
1318 .class = &am33xx_smartreflex_hwmod_class,
1319 .mpu_irqs = am33xx_smartreflex0_irqs,
1320 .main_clk = "smartreflex0_fck",
1321 .clkdm_name = "l4_wkup_clkdm",
1322 .prcm = {
1323 .omap4 = {
1324 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
1325 .modulemode = MODULEMODE_SWCTRL,
1326 },
1327 },
1328 };
1330 /* smartreflex1 */
1331 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
1332 { .irq = AM33XX_IRQ_SMARTREFLEX1 },
1333 { .irq = -1 }
1334 };
1336 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
1337 .name = "smartreflex1",
1338 .class = &am33xx_smartreflex_hwmod_class,
1339 .mpu_irqs = am33xx_smartreflex1_irqs,
1340 .main_clk = "smartreflex1_fck",
1341 .clkdm_name = "l4_wkup_clkdm",
1342 .prcm = {
1343 .omap4 = {
1344 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
1345 .modulemode = MODULEMODE_SWCTRL,
1346 },
1347 },
1348 };
1350 /* 'spi' class */
1352 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1353 .rev_offs = 0x0000,
1354 .sysc_offs = 0x0110,
1355 .syss_offs = 0x0114,
1356 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1357 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1358 SYSS_HAS_RESET_STATUS),
1359 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1360 .sysc_fields = &omap_hwmod_sysc_type1,
1361 };
1363 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1364 .name = "mcspi",
1365 .sysc = &am33xx_mcspi_sysc,
1366 .rev = OMAP4_MCSPI_REV,
1367 };
1369 /* spi0 */
1370 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1371 { .irq = AM33XX_IRQ_MCSPIOCP0 },
1372 { .irq = -1 }
1373 };
1375 struct omap_hwmod_dma_info am33xx_mcspi0_sdma_reqs[] = {
1376 { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0R },
1377 { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0W },
1378 { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1R },
1379 { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1W },
1380 { .dma_req = -1 }
1381 };
1383 struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
1384 {
1385 .pa_start = AM33XX_SPI0_BASE,
1386 .pa_end = AM33XX_SPI0_BASE + SZ_1K - 1,
1387 .flags = ADDR_TYPE_RT
1388 },
1389 { }
1390 };
1392 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = {
1393 .master = &am33xx_l4per_hwmod,
1394 .slave = &am33xx_spi0_hwmod,
1395 .clk = "spi0_ick",
1396 .addr = am33xx_mcspi0_addr_space,
1397 .user = OCP_USER_MPU,
1398 };
1400 static struct omap_hwmod_ocp_if *am33xx_mcspi0_slaves[] = {
1401 &am33xx_l4_core__mcspi0,
1402 };
1404 struct omap2_mcspi_dev_attr mcspi_attrib = {
1405 .num_chipselect = 2,
1406 };
1407 static struct omap_hwmod am33xx_spi0_hwmod = {
1408 .name = "spi0",
1409 .class = &am33xx_spi_hwmod_class,
1410 .mpu_irqs = am33xx_spi0_irqs,
1411 .sdma_reqs = am33xx_mcspi0_sdma_reqs,
1412 .main_clk = "spi0_fck",
1413 .clkdm_name = "l4ls_clkdm",
1414 .prcm = {
1415 .omap4 = {
1416 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1417 .modulemode = MODULEMODE_SWCTRL,
1418 },
1419 },
1420 .dev_attr = &mcspi_attrib,
1421 .slaves = am33xx_mcspi0_slaves,
1422 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi0_slaves),
1423 };
1425 /* spi1 */
1426 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1427 { .irq = AM33XX_IRQ_SPI1 },
1428 { .irq = -1 }
1429 };
1431 struct omap_hwmod_dma_info am33xx_mcspi1_sdma_reqs[] = {
1432 { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0R },
1433 { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0W },
1434 { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1R },
1435 { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1W },
1436 { .dma_req = -1 }
1437 };
1439 struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
1440 {
1441 .pa_start = AM33XX_SPI1_BASE,
1442 .pa_end = AM33XX_SPI1_BASE + SZ_1K - 1,
1443 .flags = ADDR_TYPE_RT
1444 },
1445 { }
1446 };
1448 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = {
1449 .master = &am33xx_l4per_hwmod,
1450 .slave = &am33xx_spi1_hwmod,
1451 .clk = "spi1_ick",
1452 .addr = am33xx_mcspi1_addr_space,
1453 .user = OCP_USER_MPU,
1454 };
1456 static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = {
1457 &am33xx_l4_core__mcspi1,
1458 };
1459 static struct omap_hwmod am33xx_spi1_hwmod = {
1460 .name = "spi1",
1461 .class = &am33xx_spi_hwmod_class,
1462 .mpu_irqs = am33xx_spi1_irqs,
1463 .sdma_reqs = am33xx_mcspi1_sdma_reqs,
1464 .main_clk = "spi1_fck",
1465 .clkdm_name = "l4ls_clkdm",
1466 .prcm = {
1467 .omap4 = {
1468 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1469 .modulemode = MODULEMODE_SWCTRL,
1470 },
1471 },
1472 .dev_attr = &mcspi_attrib,
1473 .slaves = am33xx_mcspi1_slaves,
1474 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi1_slaves),
1475 };
1477 /* 'spinlock' class */
1478 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1479 .name = "spinlock",
1480 };
1482 /* spinlock */
1483 static struct omap_hwmod am33xx_spinlock_hwmod = {
1484 .name = "spinlock",
1485 .class = &am33xx_spinlock_hwmod_class,
1486 .main_clk = "spinlock_fck",
1487 .clkdm_name = "l4ls_clkdm",
1488 .prcm = {
1489 .omap4 = {
1490 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1491 .modulemode = MODULEMODE_SWCTRL,
1492 },
1493 },
1494 };
1496 /* 'timer 0 & 2-7' class */
1497 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1498 .rev_offs = 0x0000,
1499 .sysc_offs = 0x0010,
1500 .syss_offs = 0x0014,
1501 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1502 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1503 SIDLE_SMART_WKUP),
1504 .sysc_fields = &omap_hwmod_sysc_type2,
1505 };
1507 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1508 .name = "timer",
1509 .sysc = &am33xx_timer_sysc,
1510 };
1512 /* timer0 */
1513 /* l4 wkup -> timer0 interface */
1514 static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = {
1515 {
1516 .pa_start = AM33XX_TIMER0_BASE,
1517 .pa_end = AM33XX_TIMER0_BASE + SZ_1K - 1,
1518 .flags = ADDR_TYPE_RT
1519 },
1520 { }
1521 };
1523 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = {
1524 .master = &am33xx_l4wkup_hwmod,
1525 .slave = &am33xx_timer0_hwmod,
1526 .clk = "timer0_ick",
1527 .addr = am33xx_timer0_addr_space,
1528 .user = OCP_USER_MPU,
1529 };
1531 static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = {
1532 &am33xx_l4wkup__timer0,
1533 };
1535 static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = {
1536 { .irq = AM33XX_IRQ_DMTIMER0 },
1537 { .irq = -1 }
1538 };
1540 static struct omap_hwmod am33xx_timer0_hwmod = {
1541 .name = "timer0",
1542 .class = &am33xx_timer_hwmod_class,
1543 .mpu_irqs = am33xx_timer0_irqs,
1544 .main_clk = "timer0_fck",
1545 .clkdm_name = "l4_wkup_clkdm",
1546 .prcm = {
1547 .omap4 = {
1548 .clkctrl_offs = AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET,
1549 .modulemode = MODULEMODE_SWCTRL,
1550 },
1551 },
1552 .slaves = am33xx_timer0_slaves,
1553 .slaves_cnt = ARRAY_SIZE(am33xx_timer0_slaves),
1554 };
1556 /* timer1 1ms */
1557 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1558 .rev_offs = 0x0000,
1559 .sysc_offs = 0x0010,
1560 .syss_offs = 0x0014,
1561 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1562 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1563 SYSS_HAS_RESET_STATUS),
1564 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1565 .sysc_fields = &omap_hwmod_sysc_type1,
1566 };
1568 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1569 .name = "timer",
1570 .sysc = &am33xx_timer1ms_sysc,
1571 };
1573 /* l4 wkup -> timer1 interface */
1574 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
1575 {
1576 .pa_start = AM33XX_TIMER1_BASE,
1577 .pa_end = AM33XX_TIMER1_BASE + SZ_1K - 1,
1578 .flags = ADDR_TYPE_RT
1579 },
1580 { }
1581 };
1583 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = {
1584 .master = &am33xx_l4wkup_hwmod,
1585 .slave = &am33xx_timer1_hwmod,
1586 .clk = "timer1_ick",
1587 .addr = am33xx_timer1_addr_space,
1588 .user = OCP_USER_MPU,
1589 };
1591 static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = {
1592 &am33xx_l4wkup__timer1,
1593 };
1595 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
1596 { .irq = AM33XX_IRQ_DMTIMER1 },
1597 { .irq = -1 }
1598 };
1600 static struct omap_hwmod am33xx_timer1_hwmod = {
1601 .name = "timer1",
1602 .class = &am33xx_timer1ms_hwmod_class,
1603 .mpu_irqs = am33xx_timer1_irqs,
1604 .main_clk = "timer1_fck",
1605 .clkdm_name = "l4_wkup_clkdm",
1606 .prcm = {
1607 .omap4 = {
1608 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1609 .modulemode = MODULEMODE_SWCTRL,
1610 },
1611 },
1612 .slaves = am33xx_timer1_slaves,
1613 .slaves_cnt = ARRAY_SIZE(am33xx_timer1_slaves),
1614 };
1616 /* timer2 */
1617 /* l4 per -> timer2 interface */
1618 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
1619 {
1620 .pa_start = AM33XX_TIMER2_BASE,
1621 .pa_end = AM33XX_TIMER2_BASE + SZ_1K - 1,
1622 .flags = ADDR_TYPE_RT
1623 },
1624 { }
1625 };
1627 static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = {
1628 .master = &am33xx_l4per_hwmod,
1629 .slave = &am33xx_timer2_hwmod,
1630 .clk = "timer2_ick",
1631 .addr = am33xx_timer2_addr_space,
1632 .user = OCP_USER_MPU,
1633 };
1635 static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = {
1636 &am33xx_l4per__timer2,
1637 };
1639 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
1640 { .irq = AM33XX_IRQ_DMTIMER2 },
1641 { .irq = -1 }
1642 };
1644 static struct omap_hwmod am33xx_timer2_hwmod = {
1645 .name = "timer2",
1646 .class = &am33xx_timer_hwmod_class,
1647 .mpu_irqs = am33xx_timer2_irqs,
1648 .main_clk = "timer2_fck",
1649 .prcm = {
1650 .omap4 = {
1651 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1652 .modulemode = MODULEMODE_SWCTRL,
1653 },
1654 },
1655 .slaves = am33xx_timer2_slaves,
1656 .slaves_cnt = ARRAY_SIZE(am33xx_timer2_slaves),
1657 .clkdm_name = "l4ls_clkdm",
1658 };
1660 /* timer3 */
1661 /* l4 per -> timer3 interface */
1662 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
1663 {
1664 .pa_start = AM33XX_TIMER3_BASE,
1665 .pa_end = AM33XX_TIMER3_BASE + SZ_1K - 1,
1666 .flags = ADDR_TYPE_RT
1667 },
1668 { }
1669 };
1671 static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = {
1672 .master = &am33xx_l4per_hwmod,
1673 .slave = &am33xx_timer3_hwmod,
1674 .clk = "timer3_ick",
1675 .addr = am33xx_timer3_addr_space,
1676 .user = OCP_USER_MPU,
1677 };
1679 static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = {
1680 &am33xx_l4per__timer3,
1681 };
1683 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
1684 { .irq = AM33XX_IRQ_DMTIMER3 },
1685 { .irq = -1 }
1686 };
1688 static struct omap_hwmod am33xx_timer3_hwmod = {
1689 .name = "timer3",
1690 .class = &am33xx_timer_hwmod_class,
1691 .mpu_irqs = am33xx_timer3_irqs,
1692 .main_clk = "timer3_fck",
1693 .clkdm_name = "l4ls_clkdm",
1694 .prcm = {
1695 .omap4 = {
1696 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1697 .modulemode = MODULEMODE_SWCTRL,
1698 },
1699 },
1700 .slaves = am33xx_timer3_slaves,
1701 .slaves_cnt = ARRAY_SIZE(am33xx_timer3_slaves),
1702 };
1704 /* timer4 */
1705 /* l4 per -> timer4 interface */
1706 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
1707 {
1708 .pa_start = AM33XX_TIMER4_BASE,
1709 .pa_end = AM33XX_TIMER4_BASE + SZ_1K - 1,
1710 .flags = ADDR_TYPE_RT
1711 },
1712 { }
1713 };
1715 static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = {
1716 .master = &am33xx_l4per_hwmod,
1717 .slave = &am33xx_timer4_hwmod,
1718 .clk = "timer4_ick",
1719 .addr = am33xx_timer4_addr_space,
1720 .user = OCP_USER_MPU,
1721 };
1723 static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = {
1724 &am33xx_l4per__timer4,
1725 };
1727 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
1728 { .irq = AM33XX_IRQ_DMTIMER4 },
1729 { .irq = -1 }
1730 };
1732 static struct omap_hwmod am33xx_timer4_hwmod = {
1733 .name = "timer4",
1734 .class = &am33xx_timer_hwmod_class,
1735 .mpu_irqs = am33xx_timer4_irqs,
1736 .main_clk = "timer4_fck",
1737 .prcm = {
1738 .omap4 = {
1739 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1740 .modulemode = MODULEMODE_SWCTRL,
1741 },
1742 },
1743 .slaves = am33xx_timer4_slaves,
1744 .slaves_cnt = ARRAY_SIZE(am33xx_timer4_slaves),
1745 .clkdm_name = "l4ls_clkdm",
1746 };
1749 /* timer5 */
1750 /* l4 per -> timer5 interface */
1751 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
1752 {
1753 .pa_start = AM33XX_TIMER5_BASE,
1754 .pa_end = AM33XX_TIMER5_BASE + SZ_1K - 1,
1755 .flags = ADDR_TYPE_RT
1756 },
1757 { }
1758 };
1760 static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = {
1761 .master = &am33xx_l4per_hwmod,
1762 .slave = &am33xx_timer5_hwmod,
1763 .clk = "timer5_ick",
1764 .addr = am33xx_timer5_addr_space,
1765 .user = OCP_USER_MPU,
1766 };
1768 static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = {
1769 &am33xx_l4per__timer5,
1770 };
1772 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
1773 { .irq = AM33XX_IRQ_DMTIMER5 },
1774 { .irq = -1 }
1775 };
1777 static struct omap_hwmod am33xx_timer5_hwmod = {
1778 .name = "timer5",
1779 .class = &am33xx_timer_hwmod_class,
1780 .mpu_irqs = am33xx_timer5_irqs,
1781 .main_clk = "timer5_fck",
1782 .prcm = {
1783 .omap4 = {
1784 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1785 .modulemode = MODULEMODE_SWCTRL,
1786 },
1787 },
1788 .slaves = am33xx_timer5_slaves,
1789 .slaves_cnt = ARRAY_SIZE(am33xx_timer5_slaves),
1790 .clkdm_name = "l4ls_clkdm",
1791 };
1793 /* timer6 */
1794 /* l4 per -> timer6 interface */
1795 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
1796 {
1797 .pa_start = AM33XX_TIMER6_BASE,
1798 .pa_end = AM33XX_TIMER6_BASE + SZ_1K - 1,
1799 .flags = ADDR_TYPE_RT
1800 },
1801 { }
1802 };
1804 static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = {
1805 .master = &am33xx_l4per_hwmod,
1806 .slave = &am33xx_timer6_hwmod,
1807 .clk = "timer6_ick",
1808 .addr = am33xx_timer6_addr_space,
1809 .user = OCP_USER_MPU,
1810 };
1812 static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = {
1813 &am33xx_l4per__timer6,
1814 };
1816 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
1817 { .irq = AM33XX_IRQ_DMTIMER6 },
1818 { .irq = -1 }
1819 };
1821 static struct omap_hwmod am33xx_timer6_hwmod = {
1822 .name = "timer6",
1823 .class = &am33xx_timer_hwmod_class,
1824 .mpu_irqs = am33xx_timer6_irqs,
1825 .main_clk = "timer6_fck",
1826 .prcm = {
1827 .omap4 = {
1828 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
1829 .modulemode = MODULEMODE_SWCTRL,
1830 },
1831 },
1832 .slaves = am33xx_timer6_slaves,
1833 .slaves_cnt = ARRAY_SIZE(am33xx_timer6_slaves),
1834 .clkdm_name = "l4ls_clkdm",
1835 };
1837 /* timer7 */
1838 /* l4 per -> timer7 interface */
1839 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
1840 {
1841 .pa_start = AM33XX_TIMER7_BASE,
1842 .pa_end = AM33XX_TIMER7_BASE + SZ_1K - 1,
1843 .flags = ADDR_TYPE_RT
1844 },
1845 { }
1846 };
1848 static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = {
1849 .master = &am33xx_l4per_hwmod,
1850 .slave = &am33xx_timer7_hwmod,
1851 .clk = "timer7_ick",
1852 .addr = am33xx_timer7_addr_space,
1853 .user = OCP_USER_MPU,
1854 };
1856 static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = {
1857 &am33xx_l4per__timer7,
1858 };
1860 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
1861 { .irq = AM33XX_IRQ_DMTIMER7 },
1862 { .irq = -1 }
1863 };
1865 static struct omap_hwmod am33xx_timer7_hwmod = {
1866 .name = "timer7",
1867 .class = &am33xx_timer_hwmod_class,
1868 .mpu_irqs = am33xx_timer7_irqs,
1869 .main_clk = "timer7_fck",
1870 .prcm = {
1871 .omap4 = {
1872 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
1873 .modulemode = MODULEMODE_SWCTRL,
1874 },
1875 },
1876 .slaves = am33xx_timer7_slaves,
1877 .slaves_cnt = ARRAY_SIZE(am33xx_timer7_slaves),
1878 .clkdm_name = "l4ls_clkdm",
1879 };
1881 /* 'tpcc' class */
1882 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1883 .name = "tpcc",
1884 };
1886 /* tpcc */
1887 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
1888 { .irq = AM33XX_IRQ_TPCC0_INT_PO0 },
1889 { .irq = -1 },
1890 };
1892 static struct omap_hwmod am33xx_tpcc_hwmod = {
1893 .name = "tpcc",
1894 .class = &am33xx_tpcc_hwmod_class,
1895 .mpu_irqs = am33xx_tpcc_irqs,
1896 .main_clk = "tpcc_ick",
1897 .clkdm_name = "l3_clkdm",
1898 .prcm = {
1899 .omap4 = {
1900 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
1901 .modulemode = MODULEMODE_SWCTRL,
1902 },
1903 },
1904 };
1906 /* 'tptc' class */
1907 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1908 .name = "tptc",
1909 };
1911 /* tptc0 */
1912 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
1913 { .irq = AM33XX_IRQ_TPTC0 },
1914 { .irq = -1 }
1915 };
1917 static struct omap_hwmod am33xx_tptc0_hwmod = {
1918 .name = "tptc0",
1919 .class = &am33xx_tptc_hwmod_class,
1920 .mpu_irqs = am33xx_tptc0_irqs,
1921 .main_clk = "tptc0_ick",
1922 .clkdm_name = "l3_clkdm",
1923 .prcm = {
1924 .omap4 = {
1925 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
1926 .modulemode = MODULEMODE_SWCTRL,
1927 },
1928 },
1929 };
1931 /* tptc1 */
1932 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
1933 { .irq = AM33XX_IRQ_TPTC1 },
1934 { .irq = -1 }
1935 };
1937 static struct omap_hwmod am33xx_tptc1_hwmod = {
1938 .name = "tptc1",
1939 .class = &am33xx_tptc_hwmod_class,
1940 .mpu_irqs = am33xx_tptc1_irqs,
1941 .main_clk = "tptc1_ick",
1942 .clkdm_name = "l3_clkdm",
1943 .prcm = {
1944 .omap4 = {
1945 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
1946 .modulemode = MODULEMODE_SWCTRL,
1947 },
1948 },
1949 };
1951 /* tptc2 */
1952 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
1953 { .irq = AM33XX_IRQ_TPTC2 },
1954 { .irq = -1 }
1955 };
1957 static struct omap_hwmod am33xx_tptc2_hwmod = {
1958 .name = "tptc2",
1959 .class = &am33xx_tptc_hwmod_class,
1960 .mpu_irqs = am33xx_tptc2_irqs,
1961 .main_clk = "tptc2_ick",
1962 .clkdm_name = "l3_clkdm",
1963 .prcm = {
1964 .omap4 = {
1965 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
1966 .modulemode = MODULEMODE_SWCTRL,
1967 },
1968 },
1969 };
1971 /* 'uart' class */
1972 static struct omap_hwmod_class_sysconfig uart_sysc = {
1973 .rev_offs = 0x50,
1974 .sysc_offs = 0x54,
1975 .syss_offs = 0x58,
1976 .sysc_flags = (SYSC_HAS_SIDLEMODE |
1977 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1978 SYSC_HAS_AUTOIDLE),
1979 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1980 .sysc_fields = &omap_hwmod_sysc_type1,
1981 };
1983 static struct omap_hwmod_class uart_class = {
1984 .name = "uart",
1985 .sysc = &uart_sysc,
1986 };
1988 /* uart1 */
1989 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
1990 { .name = "tx", .dma_req = 26, },
1991 { .name = "rx", .dma_req = 27, },
1992 { .dma_req = -1 }
1993 };
1995 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
1996 {
1997 .pa_start = AM33XX_UART1_BASE,
1998 .pa_end = AM33XX_UART1_BASE + SZ_8K - 1,
1999 .flags = ADDR_TYPE_RT
2000 },
2001 { }
2002 };
2004 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
2005 .master = &am33xx_l4wkup_hwmod,
2006 .slave = &am33xx_uart1_hwmod,
2007 .clk = "uart1_ick",
2008 .addr = am33xx_uart1_addr_space,
2009 .user = OCP_USER_MPU,
2010 };
2012 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
2013 { .irq = AM33XX_IRQ_UART0 },
2014 { .irq = -1 }
2015 };
2017 static struct omap_hwmod_ocp_if *am33xx_uart1_slaves[] = {
2018 &am33xx_l4_wkup__uart1,
2019 };
2021 static struct omap_hwmod am33xx_uart1_hwmod = {
2022 .name = "uart1",
2023 .class = &uart_class,
2024 .mpu_irqs = am33xx_uart1_irqs,
2025 .sdma_reqs = uart1_edma_reqs,
2026 .main_clk = "uart1_fck",
2027 .clkdm_name = "l4_wkup_clkdm",
2028 .prcm = {
2029 .omap4 = {
2030 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
2031 .modulemode = MODULEMODE_SWCTRL,
2032 },
2033 },
2034 .slaves = am33xx_uart1_slaves,
2035 .slaves_cnt = ARRAY_SIZE(am33xx_uart1_slaves),
2036 };
2038 /* uart2 */
2039 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
2040 {
2041 .pa_start = AM33XX_UART2_BASE,
2042 .pa_end = AM33XX_UART2_BASE + SZ_8K - 1,
2043 .flags = ADDR_TYPE_RT
2044 },
2045 { }
2046 };
2048 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
2049 .slave = &am33xx_uart2_hwmod,
2050 .clk = "uart2_ick",
2051 .addr = am33xx_uart2_addr_space,
2052 .user = OCP_USER_MPU,
2053 };
2055 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
2056 { .irq = AM33XX_IRQ_UART1 },
2057 { .irq = -1 }
2058 };
2060 static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = {
2061 &am33xx_l4_ls__uart2,
2062 };
2064 static struct omap_hwmod am33xx_uart2_hwmod = {
2065 .name = "uart2",
2066 .class = &uart_class,
2067 .mpu_irqs = am33xx_uart2_irqs,
2068 .main_clk = "uart2_fck",
2069 .clkdm_name = "l4ls_clkdm",
2070 .sdma_reqs = uart1_edma_reqs,
2071 .prcm = {
2072 .omap4 = {
2073 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
2074 .modulemode = MODULEMODE_SWCTRL,
2075 },
2076 },
2077 .slaves = am33xx_uart2_slaves,
2078 .slaves_cnt = ARRAY_SIZE(am33xx_uart2_slaves),
2079 };
2081 /* uart3 */
2082 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
2083 {
2084 .pa_start = AM33XX_UART3_BASE,
2085 .pa_end = AM33XX_UART3_BASE + SZ_8K - 1,
2086 .flags = ADDR_TYPE_RT
2087 },
2088 { }
2089 };
2091 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
2092 .slave = &am33xx_uart3_hwmod,
2093 .clk = "uart3_ick",
2094 .addr = am33xx_uart3_addr_space,
2095 .user = OCP_USER_MPU,
2096 };
2098 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2099 { .irq = AM33XX_IRQ_UART2 },
2100 { .irq = -1 }
2101 };
2103 static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = {
2104 &am33xx_l4_ls__uart3,
2105 };
2107 static struct omap_hwmod am33xx_uart3_hwmod = {
2108 .name = "uart3",
2109 .class = &uart_class,
2110 .mpu_irqs = am33xx_uart3_irqs,
2111 .main_clk = "uart3_fck",
2112 .clkdm_name = "l4ls_clkdm",
2113 .sdma_reqs = uart1_edma_reqs,
2114 .prcm = {
2115 .omap4 = {
2116 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
2117 .modulemode = MODULEMODE_SWCTRL,
2118 },
2119 },
2120 .slaves = am33xx_uart3_slaves,
2121 .slaves_cnt = ARRAY_SIZE(am33xx_uart3_slaves),
2122 };
2124 /* uart4 */
2125 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
2126 {
2127 .pa_start = AM33XX_UART4_BASE,
2128 .pa_end = AM33XX_UART4_BASE + SZ_8K - 1,
2129 .flags = ADDR_TYPE_RT
2130 },
2131 { }
2132 };
2134 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
2135 .slave = &am33xx_uart4_hwmod,
2136 .clk = "uart4_ick",
2137 .addr = am33xx_uart4_addr_space,
2138 .user = OCP_USER_MPU,
2139 };
2141 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2142 { .irq = AM33XX_IRQ_UART3 },
2143 { .irq = -1 }
2144 };
2146 static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = {
2147 &am33xx_l4_ls__uart4,
2148 };
2150 static struct omap_hwmod am33xx_uart4_hwmod = {
2151 .name = "uart4",
2152 .class = &uart_class,
2153 .mpu_irqs = am33xx_uart4_irqs,
2154 .main_clk = "uart4_fck",
2155 .clkdm_name = "l4ls_clkdm",
2156 .sdma_reqs = uart1_edma_reqs,
2157 .prcm = {
2158 .omap4 = {
2159 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
2160 .modulemode = MODULEMODE_SWCTRL,
2161 },
2162 },
2163 .slaves = am33xx_uart4_slaves,
2164 .slaves_cnt = ARRAY_SIZE(am33xx_uart4_slaves),
2165 };
2167 /* uart5 */
2168 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
2169 {
2170 .pa_start = AM33XX_UART5_BASE,
2171 .pa_end = AM33XX_UART5_BASE + SZ_8K - 1,
2172 .flags = ADDR_TYPE_RT
2173 },
2174 { }
2175 };
2177 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
2178 .slave = &am33xx_uart5_hwmod,
2179 .clk = "uart5_ick",
2180 .addr = am33xx_uart5_addr_space,
2181 .user = OCP_USER_MPU,
2182 };
2184 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2185 { .irq = AM33XX_IRQ_UART4 },
2186 { .irq = -1 }
2187 };
2189 static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = {
2190 &am33xx_l4_ls__uart5,
2191 };
2193 static struct omap_hwmod am33xx_uart5_hwmod = {
2194 .name = "uart5",
2195 .class = &uart_class,
2196 .mpu_irqs = am33xx_uart5_irqs,
2197 .main_clk = "uart5_fck",
2198 .clkdm_name = "l4ls_clkdm",
2199 .sdma_reqs = uart1_edma_reqs,
2200 .prcm = {
2201 .omap4 = {
2202 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2203 .modulemode = MODULEMODE_SWCTRL,
2204 },
2205 },
2206 .slaves = am33xx_uart5_slaves,
2207 .slaves_cnt = ARRAY_SIZE(am33xx_uart5_slaves),
2208 };
2210 /* uart6 */
2211 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
2212 {
2213 .pa_start = AM33XX_UART6_BASE,
2214 .pa_end = AM33XX_UART6_BASE + SZ_8K - 1,
2215 .flags = ADDR_TYPE_RT
2216 },
2217 { }
2218 };
2220 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
2221 .slave = &am33xx_uart6_hwmod,
2222 .clk = "uart6_ick",
2223 .addr = am33xx_uart6_addr_space,
2224 .user = OCP_USER_MPU,
2225 };
2227 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2228 { .irq = AM33XX_IRQ_UART5 },
2229 { .irq = -1 }
2230 };
2232 static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = {
2233 &am33xx_l4_ls__uart6,
2234 };
2236 static struct omap_hwmod am33xx_uart6_hwmod = {
2237 .name = "uart6",
2238 .class = &uart_class,
2239 .mpu_irqs = am33xx_uart6_irqs,
2240 .main_clk = "uart6_fck",
2241 .clkdm_name = "l4ls_clkdm",
2242 .sdma_reqs = uart1_edma_reqs,
2243 .prcm = {
2244 .omap4 = {
2245 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2246 .modulemode = MODULEMODE_SWCTRL,
2247 },
2248 },
2249 .slaves = am33xx_uart6_slaves,
2250 .slaves_cnt = ARRAY_SIZE(am33xx_uart6_slaves),
2251 };
2253 /* 'wd_timer' class */
2254 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2255 .name = "wd_timer",
2256 };
2258 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
2259 {
2260 .pa_start = AM33XX_WDT1_BASE,
2261 .pa_end = AM33XX_WDT1_BASE + SZ_4K - 1,
2262 .flags = ADDR_TYPE_RT
2263 },
2264 { }
2265 };
2267 /* l4_wkup -> wd_timer1 */
2268 static struct omap_hwmod_ocp_if am33xx_l4wkup__wd_timer1 = {
2269 .master = &am33xx_l4wkup_hwmod,
2270 .slave = &am33xx_wd_timer1_hwmod,
2271 .addr = am33xx_wd_timer1_addrs,
2272 .user = OCP_USER_MPU,
2273 };
2275 /* wd_timer1 slave ports */
2276 static struct omap_hwmod_ocp_if *am33xx_wd_timer1_slaves[] = {
2277 &am33xx_l4wkup__wd_timer1,
2278 };
2280 /* wd_timer1 */
2281 /*
2282 * TODO: device.c file uses hardcoded name for watchdog
2283 timer driver "wd_timer2, so we are also using
2284 same name as of now...
2285 */
2286 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2287 .name = "wd_timer2",
2288 .class = &am33xx_wd_timer_hwmod_class,
2289 .main_clk = "wd_timer1_fck",
2290 .clkdm_name = "l4_wkup_clkdm",
2291 .prcm = {
2292 .omap4 = {
2293 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2294 .modulemode = MODULEMODE_SWCTRL,
2295 },
2296 },
2297 .slaves = am33xx_wd_timer1_slaves,
2298 .slaves_cnt = ARRAY_SIZE(am33xx_wd_timer1_slaves),
2299 };
2301 /* wdt0 */
2302 static struct omap_hwmod_irq_info am33xx_wdt0_irqs[] = {
2303 { .irq = AM33XX_IRQ_WDT0 },
2304 { .irq = -1 },
2305 };
2307 static struct omap_hwmod am33xx_wdt0_hwmod = {
2308 .name = "wdt0",
2309 .class = &am33xx_wd_timer_hwmod_class,
2310 .mpu_irqs = am33xx_wdt0_irqs,
2311 .main_clk = "wdt0_fck",
2312 .clkdm_name = "l4_wkup_clkdm",
2313 .prcm = {
2314 .omap4 = {
2315 .clkctrl_offs = AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET,
2316 .modulemode = MODULEMODE_SWCTRL,
2317 },
2318 },
2319 };
2321 /* 'wkup_m3' class */
2322 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
2323 .name = "wkup_m3",
2324 };
2326 /* wkup_m3 */
2327 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
2328 .name = "wkup_m3",
2329 .class = &am33xx_wkup_m3_hwmod_class,
2330 .clkdm_name = "l4_wkup_aon_clkdm",
2331 .main_clk = "wkup_m3_fck",
2332 .prcm = {
2333 .omap4 = {
2334 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
2335 .modulemode = MODULEMODE_SWCTRL,
2336 },
2337 },
2338 };
2340 /* L3 SLOW -> USBSS interface */
2341 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
2342 {
2343 .name = "usbss",
2344 .pa_start = AM33XX_USBSS_BASE,
2345 .pa_end = AM33XX_USBSS_BASE + SZ_4K - 1,
2346 .flags = ADDR_TYPE_RT
2347 },
2348 {
2349 .name = "musb0",
2350 .pa_start = AM33XX_USB0_BASE,
2351 .pa_end = AM33XX_USB0_BASE + SZ_2K - 1,
2352 .flags = ADDR_TYPE_RT
2353 },
2354 {
2355 .name = "musb1",
2356 .pa_start = AM33XX_USB1_BASE,
2357 .pa_end = AM33XX_USB1_BASE + SZ_2K - 1,
2358 .flags = ADDR_TYPE_RT
2359 },
2360 { }
2361 };
2363 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2364 .rev_offs = 0x0,
2365 .sysc_offs = 0x10,
2366 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2367 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2368 .sysc_fields = &omap_hwmod_sysc_type1,
2369 };
2371 static struct omap_hwmod_class am33xx_usbotg_class = {
2372 .name = "usbotg",
2373 .sysc = &am33xx_usbhsotg_sysc,
2374 };
2376 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2377 { .name = "usbss-irq", .irq = AM33XX_IRQ_USBSS, },
2378 { .name = "musb0-irq", .irq = AM33XX_IRQ_USB0, },
2379 { .name = "musb1-irq", .irq = AM33XX_IRQ_USB1, },
2380 { .irq = -1, },
2381 };
2383 static struct omap_hwmod_ocp_if am33xx_l3_slow__usbss = {
2384 .master = &am33xx_l3slow_hwmod,
2385 .slave = &am33xx_usbss_hwmod,
2386 .addr = am33xx_usbss_addr_space,
2387 .user = OCP_USER_MPU,
2388 .flags = OCPIF_SWSUP_IDLE,
2389 };
2391 static struct omap_hwmod_ocp_if *am33xx_usbss_slaves[] = {
2392 &am33xx_l3_slow__usbss,
2393 };
2395 static struct omap_hwmod_opt_clk usbss_opt_clks[] = {
2396 { .role = "clkdcoldo", .clk = "usbotg_fck" },
2397 };
2399 static struct omap_hwmod am33xx_usbss_hwmod = {
2400 .name = "usb_otg_hs",
2401 .mpu_irqs = am33xx_usbss_mpu_irqs,
2402 .main_clk = "usbotg_ick",
2403 .clkdm_name = "l4ls_clkdm",
2404 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2405 .prcm = {
2406 .omap4 = {
2407 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2408 .modulemode = MODULEMODE_SWCTRL,
2409 },
2410 },
2411 .opt_clks = usbss_opt_clks,
2412 .opt_clks_cnt = ARRAY_SIZE(usbss_opt_clks),
2413 .slaves = am33xx_usbss_slaves,
2414 .slaves_cnt = ARRAY_SIZE(am33xx_usbss_slaves),
2415 .class = &am33xx_usbotg_class,
2416 };
2418 static __initdata struct omap_hwmod *am33xx_hwmods[] = {
2419 /* l3 class */
2420 &am33xx_l3_instr_hwmod,
2421 &am33xx_l3_main_hwmod,
2422 /* l3s class */
2423 &am33xx_l3slow_hwmod,
2424 /* l4hs class */
2425 &am33xx_l4_hs_hwmod,
2426 /* l4fw class */
2427 &am33xx_l4fw_hwmod,
2428 /* l4ls class */
2429 &am33xx_l4ls_hwmod,
2430 /* l4per class */
2431 &am33xx_l4per_hwmod,
2432 /* l4wkup class */
2433 &am33xx_l4wkup_hwmod,
2435 /* clkdiv32k class */
2436 &am33xx_clkdiv32k_hwmod,
2437 /* mpu class */
2438 &am33xx_mpu_hwmod,
2439 /* adc_tsc class */
2440 &am33xx_adc_tsc_hwmod,
2441 /* aes class */
2442 &am33xx_aes0_hwmod,
2443 /* cefuse class */
2444 &am33xx_cefuse_hwmod,
2445 /* control class */
2446 &am33xx_control_hwmod,
2447 /* dcan class */
2448 &am33xx_dcan0_hwmod,
2449 &am33xx_dcan1_hwmod,
2450 /* debugss class */
2451 &am33xx_debugss_hwmod,
2452 /* elm class */
2453 &am33xx_elm_hwmod,
2454 /* emif_fw class */
2455 &am33xx_emif_fw_hwmod,
2456 /* epwmss class */
2457 &am33xx_epwmss0_hwmod,
2458 &am33xx_epwmss1_hwmod,
2459 &am33xx_epwmss2_hwmod,
2460 /* gpio class */
2461 &am33xx_gpio0_hwmod,
2462 &am33xx_gpio1_hwmod,
2463 &am33xx_gpio2_hwmod,
2464 &am33xx_gpio3_hwmod,
2465 /* gpmc class */
2466 &am33xx_gpmc_hwmod,
2467 /* i2c class */
2468 &am33xx_i2c1_hwmod,
2469 &am33xx_i2c2_hwmod,
2470 /* icss class */
2471 &am33xx_icss_hwmod,
2472 /* ieee5000 class */
2473 &am33xx_ieee5000_hwmod,
2474 /* mcasp class */
2475 &am33xx_mcasp0_hwmod,
2476 /* mmc class */
2477 &am33xx_mmc0_hwmod,
2478 &am33xx_mmc1_hwmod,
2479 &am33xx_mmc2_hwmod,
2480 /* ocmcram class */
2481 &am33xx_ocmcram_hwmod,
2482 /* ocpwp class */
2483 &am33xx_ocpwp_hwmod,
2484 /* rtc class */
2485 #if 0
2486 &am33xx_rtc_hwmod,
2487 #endif
2488 /* sha0 class */
2489 &am33xx_sha0_hwmod,
2490 /* smartreflex class */
2491 &am33xx_smartreflex0_hwmod,
2492 &am33xx_smartreflex1_hwmod,
2493 /* spi class */
2494 &am33xx_spi0_hwmod,
2495 &am33xx_spi1_hwmod,
2496 /* spinlock class */
2497 &am33xx_spinlock_hwmod,
2498 /* uart class */
2499 &am33xx_uart1_hwmod,
2500 &am33xx_uart2_hwmod,
2501 &am33xx_uart3_hwmod,
2502 &am33xx_uart4_hwmod,
2503 &am33xx_uart5_hwmod,
2504 &am33xx_uart6_hwmod,
2505 /* timer class */
2506 &am33xx_timer0_hwmod,
2507 &am33xx_timer1_hwmod,
2508 &am33xx_timer2_hwmod,
2509 &am33xx_timer3_hwmod,
2510 &am33xx_timer4_hwmod,
2511 &am33xx_timer5_hwmod,
2512 &am33xx_timer6_hwmod,
2513 &am33xx_timer7_hwmod,
2514 /* wkup_m3 class */
2515 &am33xx_wkup_m3_hwmod,
2516 /* wd_timer class */
2517 &am33xx_wd_timer1_hwmod,
2518 /* usbss hwmod */
2519 &am33xx_usbss_hwmod,
2520 /* cpgmac0 class */
2521 &am33xx_cpgmac0_hwmod,
2522 &am33xx_wdt0_hwmod, /* Secure WDT */
2523 /* tptc class */
2524 &am33xx_tptc0_hwmod,
2525 &am33xx_tptc1_hwmod,
2526 &am33xx_tptc2_hwmod,
2527 /* tpcc class */
2528 &am33xx_tpcc_hwmod,
2529 /* LCDC class */
2530 &am33xx_lcdc_hwmod,
2531 /* rtc */
2532 &am33xx_rtc_hwmod,
2533 NULL,
2534 };
2536 int __init am33xx_hwmod_init(void)
2537 {
2538 return omap_hwmod_register(am33xx_hwmods);
2539 }