5663d133e430f606bc14dd3acbbaf88b4ef2811c
1 /*
2 * Hardware modules present on the AM33XX chips
3 *
4 * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
17 #include <linux/io.h>
19 #include <plat/omap_hwmod.h>
20 #include <plat/cpu.h>
21 #include <plat/gpio.h>
22 #include <plat/dma.h>
23 #include <plat/mmc.h>
24 #include <plat/mcspi.h>
26 #include "omap_hwmod_common_data.h"
27 #include "control.h"
28 #include "cm33xx.h"
30 /* Backward references (IPs with Bus Master capability) */
31 static struct omap_hwmod am33xx_mpu_hwmod;
32 static struct omap_hwmod am33xx_l3slow_hwmod;
33 static struct omap_hwmod am33xx_l4wkup_hwmod;
34 static struct omap_hwmod am33xx_l4per_hwmod;
35 static struct omap_hwmod am33xx_uart1_hwmod;
36 static struct omap_hwmod am33xx_uart2_hwmod;
37 static struct omap_hwmod am33xx_uart3_hwmod;
38 static struct omap_hwmod am33xx_uart4_hwmod;
39 static struct omap_hwmod am33xx_uart5_hwmod;
40 static struct omap_hwmod am33xx_uart6_hwmod;
41 static struct omap_hwmod am33xx_timer0_hwmod;
42 static struct omap_hwmod am33xx_timer1_hwmod;
43 static struct omap_hwmod am33xx_timer2_hwmod;
44 static struct omap_hwmod am33xx_timer3_hwmod;
45 static struct omap_hwmod am33xx_timer4_hwmod;
46 static struct omap_hwmod am33xx_timer5_hwmod;
47 static struct omap_hwmod am33xx_timer6_hwmod;
48 static struct omap_hwmod am33xx_timer7_hwmod;
49 static struct omap_hwmod am33xx_wd_timer1_hwmod;
50 static struct omap_hwmod am33xx_cpgmac0_hwmod;
51 static struct omap_hwmod am33xx_icss_hwmod;
52 static struct omap_hwmod am33xx_ieee5000_hwmod;
53 static struct omap_hwmod am33xx_tptc0_hwmod;
54 static struct omap_hwmod am33xx_tptc1_hwmod;
55 static struct omap_hwmod am33xx_tptc2_hwmod;
56 static struct omap_hwmod am33xx_gpio0_hwmod;
57 static struct omap_hwmod am33xx_gpio1_hwmod;
58 static struct omap_hwmod am33xx_gpio2_hwmod;
59 static struct omap_hwmod am33xx_gpio3_hwmod;
60 static struct omap_hwmod am33xx_i2c1_hwmod;
61 static struct omap_hwmod am33xx_i2c2_hwmod;
62 static struct omap_hwmod am33xx_usbss_hwmod;
63 static struct omap_hwmod am33xx_mmc0_hwmod;
64 static struct omap_hwmod am33xx_mmc1_hwmod;
65 static struct omap_hwmod am33xx_mmc2_hwmod;
66 static struct omap_hwmod am33xx_spi0_hwmod;
67 static struct omap_hwmod am33xx_spi1_hwmod;
68 static struct omap_hwmod am33xx_elm_hwmod;
70 /*
71 * Interconnects hwmod structures
72 * hwmods that compose the global AM33XX OCP interconnect
73 */
75 /* MPU -> L3_SLOW Peripheral interface */
76 static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = {
77 .master = &am33xx_mpu_hwmod,
78 .slave = &am33xx_l3slow_hwmod,
79 .user = OCP_USER_MPU,
80 };
82 /* L3 SLOW -> L4_PER Peripheral interface */
83 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = {
84 .master = &am33xx_l3slow_hwmod,
85 .slave = &am33xx_l4per_hwmod,
86 .user = OCP_USER_MPU,
87 };
89 /* L3 SLOW -> L4_WKUP Peripheral interface */
90 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = {
91 .master = &am33xx_l3slow_hwmod,
92 .slave = &am33xx_l4wkup_hwmod,
93 .user = OCP_USER_MPU,
94 };
96 /* Master interfaces on the L4_WKUP interconnect */
97 static struct omap_hwmod_ocp_if *am33xx_l3_slow_masters[] = {
98 &am33xx_l3_slow__l4_per,
99 &am33xx_l3_slow__l4_wkup,
100 };
102 /* Slave interfaces on the L3_SLOW interconnect */
103 static struct omap_hwmod_ocp_if *am33xx_l3_slow_slaves[] = {
104 &am33xx_mpu__l3_slow,
105 };
107 static struct omap_hwmod am33xx_l3slow_hwmod = {
108 .name = "l3_slow",
109 .class = &l3_hwmod_class,
110 .clkdm_name = "l3s_clkdm",
111 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
112 .masters = am33xx_l3_slow_masters,
113 .masters_cnt = ARRAY_SIZE(am33xx_l3_slow_masters),
114 .slaves = am33xx_l3_slow_slaves,
115 .slaves_cnt = ARRAY_SIZE(am33xx_l3_slow_slaves),
116 };
118 /* L4 PER -> GPIO2 */
119 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
120 {
121 .pa_start = AM33XX_GPIO1_BASE,
122 .pa_end = AM33XX_GPIO1_BASE + SZ_4K - 1,
123 .flags = ADDR_TYPE_RT
124 },
125 { }
126 };
128 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
129 .master = &am33xx_l4per_hwmod,
130 .slave = &am33xx_gpio1_hwmod,
131 .clk = "l4ls_fck",
132 .addr = am33xx_gpio1_addrs,
133 .user = OCP_USER_MPU | OCP_USER_SDMA,
134 };
136 /* L4 PER -> GPIO3 */
137 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
138 {
139 .pa_start = AM33XX_GPIO2_BASE,
140 .pa_end = AM33XX_GPIO2_BASE + SZ_4K - 1,
141 .flags = ADDR_TYPE_RT
142 },
143 { }
144 };
146 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
147 .master = &am33xx_l4per_hwmod,
148 .slave = &am33xx_gpio2_hwmod,
149 .clk = "l4ls_fck",
150 .addr = am33xx_gpio2_addrs,
151 .user = OCP_USER_MPU | OCP_USER_SDMA,
152 };
154 /* L4 PER -> GPIO4 */
155 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
156 {
157 .pa_start = AM33XX_GPIO3_BASE,
158 .pa_end = AM33XX_GPIO3_BASE + SZ_4K - 1,
159 .flags = ADDR_TYPE_RT
160 },
161 { }
162 };
164 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
165 .master = &am33xx_l4per_hwmod,
166 .slave = &am33xx_gpio3_hwmod,
167 .clk = "l4ls_fck",
168 .addr = am33xx_gpio3_addrs,
169 .user = OCP_USER_MPU | OCP_USER_SDMA,
170 };
172 /* Master interfaces on the L4_PER interconnect */
173 static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = {
174 &am33xx_l4_per__gpio1,
175 &am33xx_l4_per__gpio2,
176 &am33xx_l4_per__gpio3,
177 };
178 /* Slave interfaces on the L4_PER interconnect */
179 static struct omap_hwmod_ocp_if *am33xx_l4_per_slaves[] = {
180 &am33xx_l3_slow__l4_per,
181 };
183 static struct omap_hwmod am33xx_l4per_hwmod = {
184 .name = "l4_per",
185 .class = &l4_hwmod_class,
186 .clkdm_name = "l4ls_clkdm",
187 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
188 .masters = am33xx_l4_per_masters,
189 .masters_cnt = ARRAY_SIZE(am33xx_l4_per_masters),
190 .slaves = am33xx_l4_per_slaves,
191 .slaves_cnt = ARRAY_SIZE(am33xx_l4_per_slaves),
192 };
194 /* L4 WKUP -> I2C1 */
195 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
196 {
197 .pa_start = AM33XX_I2C0_BASE,
198 .pa_end = AM33XX_I2C0_BASE + SZ_4K - 1,
199 .flags = ADDR_TYPE_RT
200 },
201 { }
202 };
204 static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = {
205 .master = &am33xx_l4wkup_hwmod,
206 .slave = &am33xx_i2c1_hwmod,
207 .addr = am33xx_i2c1_addr_space,
208 .user = OCP_USER_MPU,
209 };
211 /* L4 WKUP -> GPIO1 */
212 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
213 {
214 .pa_start = AM33XX_GPIO0_BASE,
215 .pa_end = AM33XX_GPIO0_BASE + SZ_4K - 1,
216 .flags = ADDR_TYPE_RT
217 },
218 { }
219 };
221 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
222 .master = &am33xx_l4wkup_hwmod,
223 .slave = &am33xx_gpio0_hwmod,
224 .clk = "l4ls_fck",
225 .addr = am33xx_gpio0_addrs,
226 .user = OCP_USER_MPU | OCP_USER_SDMA,
227 };
229 /* Master interfaces on the L4_WKUP interconnect */
230 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = {
231 &am33xx_l4_wkup__gpio0,
232 };
233 /* Slave interfaces on the L4_WKUP interconnect */
234 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_slaves[] = {
235 &am33xx_l3_slow__l4_wkup,
236 };
238 static struct omap_hwmod am33xx_l4wkup_hwmod = {
239 .name = "l4_wkup",
240 .class = &l4_hwmod_class,
241 .clkdm_name = "l4_wkup_clkdm",
242 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
243 .masters = am33xx_l4_wkup_masters,
244 .masters_cnt = ARRAY_SIZE(am33xx_l4_wkup_masters),
245 .slaves = am33xx_l4_wkup_slaves,
246 .slaves_cnt = ARRAY_SIZE(am33xx_l4_wkup_slaves),
247 };
249 /* 'adc_tsc' class */
250 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
251 .name = "adc_tsc",
252 };
254 /* adc_tsc */
255 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
256 { .irq = AM33XX_IRQ_TSC },
257 { .irq = -1 }
258 };
260 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
261 .name = "adc_tsc",
262 .class = &am33xx_adc_tsc_hwmod_class,
263 .mpu_irqs = am33xx_adc_tsc_irqs,
264 .main_clk = "adc_tsc_fck",
265 .clkdm_name = "l4_wkup_clkdm",
266 .prcm = {
267 .omap4 = {
268 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
269 .modulemode = MODULEMODE_SWCTRL,
270 },
271 },
272 };
274 /* 'aes' class */
275 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
276 .name = "aes",
277 };
279 /* aes0 */
280 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
281 { .irq = AM33XX_IRQ_AESEIP36t0_S },
282 { .irq = -1 }
283 };
285 static struct omap_hwmod am33xx_aes0_hwmod = {
286 .name = "aes0",
287 .class = &am33xx_aes_hwmod_class,
288 .mpu_irqs = am33xx_aes0_irqs,
289 .main_clk = "aes0_fck",
290 .clkdm_name = "l3_clkdm",
291 .prcm = {
292 .omap4 = {
293 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
294 .modulemode = MODULEMODE_SWCTRL,
295 },
296 },
297 };
299 /* 'cefuse' class */
300 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
301 .name = "cefuse",
302 };
304 /* cefuse */
305 static struct omap_hwmod am33xx_cefuse_hwmod = {
306 .name = "cefuse",
307 .class = &am33xx_cefuse_hwmod_class,
308 .main_clk = "cefuse_fck",
309 .clkdm_name = "l4_cefuse_clkdm",
310 .prcm = {
311 .omap4 = {
312 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
313 .modulemode = MODULEMODE_SWCTRL,
314 },
315 },
316 };
318 /* 'clkdiv32k' class */
319 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
320 .name = "clkdiv32k",
321 };
323 /* clkdiv32k */
324 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
325 .name = "clkdiv32k",
326 .class = &am33xx_clkdiv32k_hwmod_class,
327 .main_clk = "clkdiv32k_fck",
328 .clkdm_name = "clk_24mhz_clkdm",
329 .prcm = {
330 .omap4 = {
331 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
332 .modulemode = MODULEMODE_SWCTRL,
333 },
334 },
335 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
336 };
338 /* 'control' class */
339 static struct omap_hwmod_class am33xx_control_hwmod_class = {
340 .name = "control",
341 };
343 /* control */
344 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
345 { .irq = AM33XX_IRQ_CONTROL_PLATFORM },
346 { .irq = -1 }
347 };
349 static struct omap_hwmod am33xx_control_hwmod = {
350 .name = "control",
351 .class = &am33xx_control_hwmod_class,
352 .mpu_irqs = am33xx_control_irqs,
353 .main_clk = "control_fck",
354 .clkdm_name = "l4_wkup_clkdm",
355 .prcm = {
356 .omap4 = {
357 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
358 .modulemode = MODULEMODE_SWCTRL,
359 },
360 },
361 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
362 };
364 /* 'cpgmac0' class */
365 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
366 .name = "cpgmac0",
367 };
369 /* cpgmac0 */
370 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
371 .name = "cpgmac0",
372 .class = &am33xx_cpgmac0_hwmod_class,
373 .main_clk = "cpgmac0_fck",
374 .clkdm_name = "cpsw_125mhz_clkdm",
375 .prcm = {
376 .omap4 = {
377 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
378 .modulemode = MODULEMODE_SWCTRL,
379 },
380 },
381 };
383 /* 'dcan' class */
384 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
385 .name = "dcan",
386 };
388 /* dcan0 */
389 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
390 { .irq = AM33XX_IRQ_DCAN0_0 },
391 { .irq = -1 }
392 };
394 static struct omap_hwmod am33xx_dcan0_hwmod = {
395 .name = "dcan0",
396 .class = &am33xx_dcan_hwmod_class,
397 .mpu_irqs = am33xx_dcan0_irqs,
398 .main_clk = "dcan0_fck",
399 .clkdm_name = "l4ls_clkdm",
400 .prcm = {
401 .omap4 = {
402 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
403 .modulemode = MODULEMODE_SWCTRL,
404 },
405 },
406 };
408 /* dcan1 */
409 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
410 { .irq = AM33XX_IRQ_DCAN1_0 },
411 { .irq = -1 }
412 };
413 static struct omap_hwmod am33xx_dcan1_hwmod = {
414 .name = "dcan1",
415 .class = &am33xx_dcan_hwmod_class,
416 .mpu_irqs = am33xx_dcan1_irqs,
417 .main_clk = "dcan1_fck",
418 .clkdm_name = "l4ls_clkdm",
419 .prcm = {
420 .omap4 = {
421 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
422 .modulemode = MODULEMODE_SWCTRL,
423 },
424 },
425 };
427 /* 'debugss' class */
428 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
429 .name = "debugss",
430 };
432 /* debugss */
433 static struct omap_hwmod am33xx_debugss_hwmod = {
434 .name = "debugss",
435 .class = &am33xx_debugss_hwmod_class,
436 .main_clk = "debugss_fck",
437 .clkdm_name = "l3_aon_clkdm",
438 .prcm = {
439 .omap4 = {
440 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
441 .modulemode = MODULEMODE_SWCTRL,
442 },
443 },
444 #ifdef CONFIG_DEBUG_JTAG_ENABLE
445 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
446 #endif
447 };
449 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
450 .rev_offs = 0x0000,
451 .sysc_offs = 0x0010,
452 .syss_offs = 0x0014,
453 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
454 SYSC_HAS_SOFTRESET |
455 SYSS_HAS_RESET_STATUS),
456 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
457 .sysc_fields = &omap_hwmod_sysc_type1,
458 };
459 /* 'elm' class */
460 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
461 .name = "elm",
462 .sysc = &am33xx_elm_sysc,
463 };
465 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
466 { .irq = AM33XX_IRQ_ELM },
467 { .irq = -1 }
468 };
470 struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
471 {
472 .pa_start = AM33XX_ELM_BASE,
473 .pa_end = AM33XX_ELM_BASE + SZ_8K - 1,
474 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
475 },
476 { }
477 };
479 struct omap_hwmod_ocp_if am33xx_l4_core__elm = {
480 .master = &am33xx_l4per_hwmod,
481 .slave = &am33xx_elm_hwmod,
482 .addr = am33xx_elm_addr_space,
483 .user = OCP_USER_MPU,
484 };
486 static struct omap_hwmod_ocp_if *am33xx_elm_slaves[] = {
487 &am33xx_l4_core__elm,
488 };
490 /* elm */
491 static struct omap_hwmod am33xx_elm_hwmod = {
492 .name = "elm",
493 .class = &am33xx_elm_hwmod_class,
494 .mpu_irqs = am33xx_elm_irqs,
495 .main_clk = "elm_fck",
496 .clkdm_name = "l4ls_clkdm",
497 .slaves = am33xx_elm_slaves,
498 .slaves_cnt = ARRAY_SIZE(am33xx_elm_slaves),
499 .prcm = {
500 .omap4 = {
501 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
502 .modulemode = MODULEMODE_SWCTRL,
503 },
504 },
505 };
507 /* 'emif_fw' class */
508 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
509 .name = "emif_fw",
510 };
512 /* emif_fw */
513 static struct omap_hwmod am33xx_emif_fw_hwmod = {
514 .name = "emif_fw",
515 .class = &am33xx_emif_fw_hwmod_class,
516 .main_clk = "emif_fw_fck",
517 .clkdm_name = "l4fw_clkdm",
518 .prcm = {
519 .omap4 = {
520 .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
521 .modulemode = MODULEMODE_SWCTRL,
522 },
523 },
524 .flags = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
525 };
527 /* 'epwmss' class */
528 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
529 .name = "epwmss",
530 };
532 /* epwmss0 */
533 static struct omap_hwmod am33xx_epwmss0_hwmod = {
534 .name = "epwmss0",
535 .class = &am33xx_epwmss_hwmod_class,
536 .main_clk = "epwmss0_fck",
537 .clkdm_name = "l4ls_clkdm",
538 .prcm = {
539 .omap4 = {
540 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
541 .modulemode = MODULEMODE_SWCTRL,
542 },
543 },
544 };
546 /* epwmss1 */
547 static struct omap_hwmod am33xx_epwmss1_hwmod = {
548 .name = "epwmss1",
549 .class = &am33xx_epwmss_hwmod_class,
550 .main_clk = "epwmss1_fck",
551 .clkdm_name = "l4ls_clkdm",
552 .prcm = {
553 .omap4 = {
554 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
555 .modulemode = MODULEMODE_SWCTRL,
556 },
557 },
558 };
560 /* epwmss2 */
561 static struct omap_hwmod am33xx_epwmss2_hwmod = {
562 .name = "epwmss2",
563 .class = &am33xx_epwmss_hwmod_class,
564 .main_clk = "epwmss2_fck",
565 .clkdm_name = "l4ls_clkdm",
566 .prcm = {
567 .omap4 = {
568 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
569 .modulemode = MODULEMODE_SWCTRL,
570 },
571 },
572 };
574 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
575 .rev_offs = 0x0000,
576 .sysc_offs = 0x0010,
577 .syss_offs = 0x0114,
578 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
579 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
580 SYSS_HAS_RESET_STATUS),
581 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
582 SIDLE_SMART_WKUP),
583 .sysc_fields = &omap_hwmod_sysc_type1,
584 };
586 /* 'gpio' class */
587 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
588 .name = "gpio",
589 .sysc = &am33xx_gpio_sysc,
590 .rev = 2,
591 };
593 /* gpio dev_attr */
594 static struct omap_gpio_dev_attr gpio_dev_attr = {
595 .bank_width = 32,
596 .dbck_flag = true,
597 };
599 /* gpio0 */
600 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
601 { .irq = AM33XX_IRQ_GPIO0_1 },
602 { .irq = -1 }
603 };
605 /* gpio0 slave ports */
606 static struct omap_hwmod_ocp_if *am33xx_gpio0_slaves[] = {
607 &am33xx_l4_wkup__gpio0,
608 };
610 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
611 { .role = "dbclk", .clk = "gpio0_dbclk" },
612 };
614 /* gpio0 */
615 static struct omap_hwmod am33xx_gpio0_hwmod = {
616 .name = "gpio1",
617 .class = &am33xx_gpio_hwmod_class,
618 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
619 .mpu_irqs = am33xx_gpio0_irqs,
620 .main_clk = "gpio0_fck",
621 .clkdm_name = "l4_wkup_clkdm",
622 .prcm = {
623 .omap4 = {
624 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
625 .modulemode = MODULEMODE_SWCTRL,
626 },
627 },
628 .opt_clks = gpio0_opt_clks,
629 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
630 .dev_attr = &gpio_dev_attr,
631 .slaves = am33xx_gpio0_slaves,
632 .slaves_cnt = ARRAY_SIZE(am33xx_gpio0_slaves),
633 };
635 /* gpio1 */
636 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
637 { .irq = AM33XX_IRQ_GPIO1_1 },
638 { .irq = -1 }
639 };
641 /* gpio1 slave ports */
642 static struct omap_hwmod_ocp_if *am33xx_gpio1_slaves[] = {
643 &am33xx_l4_per__gpio1,
644 };
646 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
647 { .role = "dbclk", .clk = "gpio1_dbclk" },
648 };
650 static struct omap_hwmod am33xx_gpio1_hwmod = {
651 .name = "gpio2",
652 .class = &am33xx_gpio_hwmod_class,
653 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
654 .mpu_irqs = am33xx_gpio1_irqs,
655 .main_clk = "gpio1_fck",
656 .clkdm_name = "l4ls_clkdm",
657 .prcm = {
658 .omap4 = {
659 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
660 .modulemode = MODULEMODE_SWCTRL,
661 },
662 },
663 .opt_clks = gpio1_opt_clks,
664 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
665 .dev_attr = &gpio_dev_attr,
666 .slaves = am33xx_gpio1_slaves,
667 .slaves_cnt = ARRAY_SIZE(am33xx_gpio1_slaves),
668 };
670 /* gpio2 */
671 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
672 { .irq = AM33XX_IRQ_GPIO2_1 },
673 { .irq = -1 }
674 };
676 /* gpio2 slave ports */
677 static struct omap_hwmod_ocp_if *am33xx_gpio2_slaves[] = {
678 &am33xx_l4_per__gpio2,
679 };
681 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
682 { .role = "dbclk", .clk = "gpio2_dbclk" },
683 };
685 /* gpio2 */
686 static struct omap_hwmod am33xx_gpio2_hwmod = {
687 .name = "gpio3",
688 .class = &am33xx_gpio_hwmod_class,
689 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
690 .mpu_irqs = am33xx_gpio2_irqs,
691 .main_clk = "gpio2_fck",
692 .clkdm_name = "l4ls_clkdm",
693 .prcm = {
694 .omap4 = {
695 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
696 .modulemode = MODULEMODE_SWCTRL,
697 },
698 },
699 .opt_clks = gpio2_opt_clks,
700 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
701 .dev_attr = &gpio_dev_attr,
702 .slaves = am33xx_gpio2_slaves,
703 .slaves_cnt = ARRAY_SIZE(am33xx_gpio2_slaves),
704 };
706 /* gpio3 */
707 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
708 { .irq = AM33XX_IRQ_GPIO3_1 },
709 { .irq = -1 }
710 };
712 /* gpio3 slave ports */
713 static struct omap_hwmod_ocp_if *am33xx_gpio3_slaves[] = {
714 &am33xx_l4_per__gpio3,
715 };
717 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
718 { .role = "dbclk", .clk = "gpio3_dbclk" },
719 };
721 /* gpio3 */
722 static struct omap_hwmod am33xx_gpio3_hwmod = {
723 .name = "gpio4",
724 .class = &am33xx_gpio_hwmod_class,
725 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
726 .mpu_irqs = am33xx_gpio3_irqs,
727 .main_clk = "gpio3_fck",
728 .clkdm_name = "l4ls_clkdm",
729 .prcm = {
730 .omap4 = {
731 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
732 .modulemode = MODULEMODE_SWCTRL,
733 },
734 },
735 .opt_clks = gpio3_opt_clks,
736 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
737 .dev_attr = &gpio_dev_attr,
738 .slaves = am33xx_gpio3_slaves,
739 .slaves_cnt = ARRAY_SIZE(am33xx_gpio3_slaves),
740 };
742 /* 'gpmc' class */
744 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
745 .name = "gpmc",
746 };
748 /* gpmc */
749 static struct omap_hwmod am33xx_gpmc_hwmod = {
750 .name = "gpmc",
751 .class = &am33xx_gpmc_hwmod_class,
752 .main_clk = "gpmc_fck",
753 .clkdm_name = "l3s_clkdm",
754 .prcm = {
755 .omap4 = {
756 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
757 .modulemode = MODULEMODE_SWCTRL,
758 },
759 },
760 };
762 /* 'i2c' class */
764 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
765 .sysc_offs = 0x0010,
766 .syss_offs = 0x0090,
767 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
768 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
769 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
770 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
771 SIDLE_SMART_WKUP),
772 .sysc_fields = &omap_hwmod_sysc_type1,
773 };
775 static struct omap_i2c_dev_attr i2c_dev_attr = {
776 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
777 };
779 static struct omap_hwmod_class i2c_class = {
780 .name = "i2c",
781 .sysc = &am33xx_i2c_sysc,
782 .rev = OMAP_I2C_IP_VERSION_2,
783 .reset = &omap_i2c_reset,
784 };
786 /* I2C1 */
787 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
788 { .irq = AM33XX_IRQ_MSHSI2COCP0 },
789 { .irq = -1 }
790 };
792 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
793 { .name = "tx", .dma_req = 0, },
794 { .name = "rx", .dma_req = 0, },
795 { .dma_req = -1 }
796 };
798 static struct omap_hwmod_ocp_if *am33xx_i2c1_slaves[] = {
799 &am33xx_l4_wkup_i2c1,
800 };
802 static struct omap_hwmod am33xx_i2c1_hwmod = {
803 .name = "i2c1",
804 .mpu_irqs = i2c1_mpu_irqs,
805 .sdma_reqs = i2c1_edma_reqs,
806 .main_clk = "i2c1_fck",
807 .clkdm_name = "l4_wkup_clkdm",
808 .prcm = {
809 .omap4 = {
810 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
811 .modulemode = MODULEMODE_SWCTRL,
812 },
813 },
814 .flags = HWMOD_16BIT_REG,
815 .dev_attr = &i2c_dev_attr,
816 .slaves = am33xx_i2c1_slaves,
817 .slaves_cnt = ARRAY_SIZE(am33xx_i2c1_slaves),
818 .class = &i2c_class,
819 };
821 /* i2c2 */
822 /* l4 per -> i2c2 */
823 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
824 {
825 .pa_start = AM33XX_I2C1_BASE,
826 .pa_end = AM33XX_I2C1_BASE + SZ_4K - 1,
827 .flags = ADDR_TYPE_RT
828 },
829 { }
830 };
832 static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = {
833 .master = &am33xx_l4per_hwmod,
834 .slave = &am33xx_i2c2_hwmod,
835 .addr = am33xx_i2c2_addr_space,
836 .user = OCP_USER_MPU,
837 };
839 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
840 { .irq = AM33XX_IRQ_MSHSI2COCP1 },
841 { .irq = -1 }
842 };
844 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
845 { .name = "tx", .dma_req = 0, },
846 { .name = "rx", .dma_req = 0, },
847 { .dma_req = -1 }
848 };
850 static struct omap_hwmod_ocp_if *am33xx_i2c2_slaves[] = {
851 &am335_l4_per_i2c2,
852 };
854 static struct omap_hwmod am33xx_i2c2_hwmod = {
855 .name = "i2c2",
856 .mpu_irqs = i2c2_mpu_irqs,
857 .sdma_reqs = i2c2_edma_reqs,
858 .main_clk = "i2c2_fck",
859 .clkdm_name = "l4ls_clkdm",
860 .prcm = {
861 .omap4 = {
862 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
863 .modulemode = MODULEMODE_SWCTRL,
864 },
865 },
866 .flags = HWMOD_16BIT_REG,
867 .dev_attr = &i2c_dev_attr,
868 .slaves = am33xx_i2c2_slaves,
869 .slaves_cnt = ARRAY_SIZE(am33xx_i2c2_slaves),
870 .class = &i2c_class,
871 };
873 /* 'icss' class */
874 static struct omap_hwmod_class am33xx_icss_hwmod_class = {
875 .name = "icss",
876 };
878 /* icss */
879 static struct omap_hwmod am33xx_icss_hwmod = {
880 .name = "icss",
881 .class = &am33xx_icss_hwmod_class,
882 .main_clk = "icss_fck",
883 .clkdm_name = "icss_ocp_clkdm",
884 .prcm = {
885 .omap4 = {
886 .clkctrl_offs = AM33XX_CM_PER_ICSS_CLKCTRL_OFFSET,
887 .modulemode = MODULEMODE_SWCTRL,
888 },
889 },
890 };
892 /* 'ieee5000' class */
893 static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = {
894 .name = "ieee5000",
895 };
897 /* ieee5000 */
898 static struct omap_hwmod am33xx_ieee5000_hwmod = {
899 .name = "ieee5000",
900 .class = &am33xx_ieee5000_hwmod_class,
901 .main_clk = "ieee5000_fck",
902 .clkdm_name = "l3s_clkdm",
903 .prcm = {
904 .omap4 = {
905 .clkctrl_offs = AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET,
906 .modulemode = MODULEMODE_SWCTRL,
907 },
908 },
909 };
912 /* 'l3' class */
913 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
914 .name = "l3",
915 };
917 /* l4_hs */
918 static struct omap_hwmod am33xx_l4_hs_hwmod = {
919 .name = "l4_hs",
920 .class = &am33xx_l3_hwmod_class,
921 .clkdm_name = "l4hs_clkdm",
922 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
923 .prcm = {
924 .omap4 = {
925 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
926 .modulemode = MODULEMODE_SWCTRL,
927 },
928 },
929 };
931 /* l3_instr */
932 static struct omap_hwmod am33xx_l3_instr_hwmod = {
933 .name = "l3_instr",
934 .class = &am33xx_l3_hwmod_class,
935 .clkdm_name = "l3_clkdm",
936 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
937 .prcm = {
938 .omap4 = {
939 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
940 .modulemode = MODULEMODE_SWCTRL,
941 },
942 },
943 };
945 /* l3_main */
946 static struct omap_hwmod am33xx_l3_main_hwmod = {
947 .name = "l3_main",
948 .class = &am33xx_l3_hwmod_class,
949 .clkdm_name = "l3_clkdm",
950 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
951 .prcm = {
952 .omap4 = {
953 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
954 .modulemode = MODULEMODE_SWCTRL,
955 },
956 },
957 };
959 /* 'l4fw' class */
960 static struct omap_hwmod_class am33xx_l4fw_hwmod_class = {
961 .name = "l4fw",
962 };
964 /* l4fw */
965 static struct omap_hwmod am33xx_l4fw_hwmod = {
966 .name = "l4fw",
967 .class = &am33xx_l4fw_hwmod_class,
968 .clkdm_name = "l4fw_clkdm",
969 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
970 .prcm = {
971 .omap4 = {
972 .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
973 .modulemode = MODULEMODE_SWCTRL,
974 },
975 },
976 };
978 /* 'l4ls' class */
979 static struct omap_hwmod_class am33xx_l4ls_hwmod_class = {
980 .name = "l4ls",
981 };
983 /* l4ls */
984 static struct omap_hwmod am33xx_l4ls_hwmod = {
985 .name = "l4ls",
986 .class = &am33xx_l4ls_hwmod_class,
987 .main_clk = "l4ls_fck",
988 .clkdm_name = "l4ls_clkdm",
989 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
990 .prcm = {
991 .omap4 = {
992 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
993 .modulemode = MODULEMODE_SWCTRL,
994 },
995 },
996 };
998 /* 'lcdc' class */
999 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1000 .name = "lcdc",
1001 };
1003 /* lcdc */
1004 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1005 { .irq = AM33XX_IRQ_LCD },
1006 { .irq = -1 }
1007 };
1009 static struct omap_hwmod am33xx_lcdc_hwmod = {
1010 .name = "lcdc",
1011 .class = &am33xx_lcdc_hwmod_class,
1012 .mpu_irqs = am33xx_lcdc_irqs,
1013 .main_clk = "lcdc_fck",
1014 .clkdm_name = "lcdc_clkdm",
1015 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1016 .prcm = {
1017 .omap4 = {
1018 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1019 .modulemode = MODULEMODE_SWCTRL,
1020 },
1021 },
1022 };
1024 /* 'mcasp' class */
1025 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1026 .name = "mcasp",
1027 };
1029 /* mcasp0 */
1030 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1031 { .irq = 80 },
1032 { .irq = -1 }
1033 };
1035 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1036 .name = "mcasp0",
1037 .class = &am33xx_mcasp_hwmod_class,
1038 .mpu_irqs = am33xx_mcasp0_irqs,
1039 .main_clk = "mcasp0_fck",
1040 .clkdm_name = "l3s_clkdm",
1041 .prcm = {
1042 .omap4 = {
1043 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1044 .modulemode = MODULEMODE_SWCTRL,
1045 },
1046 },
1047 };
1049 /* 'mmc' class */
1051 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1052 .rev_offs = 0x1fc,
1053 .sysc_offs = 0x10,
1054 .syss_offs = 0x14,
1055 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1056 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1057 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1058 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1059 .sysc_fields = &omap_hwmod_sysc_type1,
1060 };
1062 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1063 .name = "mmc",
1064 .sysc = &am33xx_mmc_sysc,
1065 };
1067 /* mmc0 */
1068 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1069 { .irq = AM33XX_IRQ_MMCHS0 },
1070 { .irq = -1 }
1071 };
1073 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1074 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS0_W, },
1075 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS0_R, },
1076 { .dma_req = -1 }
1077 };
1079 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
1080 {
1081 .pa_start = AM33XX_MMC0_BASE,
1082 .pa_end = AM33XX_MMC0_BASE + SZ_4K - 1,
1083 .flags = ADDR_TYPE_RT
1084 },
1085 { }
1086 };
1088 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc0 = {
1089 .master = &am33xx_l4ls_hwmod,
1090 .slave = &am33xx_mmc0_hwmod,
1091 .clk = "mmc0_ick",
1092 .addr = am33xx_mmc0_addr_space,
1093 .user = OCP_USER_MPU,
1094 };
1096 static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = {
1097 &am33xx_l4ls__mmc0,
1098 };
1100 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1101 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1102 };
1104 static struct omap_hwmod am33xx_mmc0_hwmod = {
1105 .name = "mmc1",
1106 .class = &am33xx_mmc_hwmod_class,
1107 .mpu_irqs = am33xx_mmc0_irqs,
1108 .sdma_reqs = am33xx_mmc0_edma_reqs,
1109 .main_clk = "mmc0_fck",
1110 .clkdm_name = "l4ls_clkdm",
1111 .prcm = {
1112 .omap4 = {
1113 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1114 .modulemode = MODULEMODE_SWCTRL,
1115 },
1116 },
1117 .dev_attr = &am33xx_mmc0_dev_attr,
1118 .slaves = am33xx_mmc0_slaves,
1119 .slaves_cnt = ARRAY_SIZE(am33xx_mmc0_slaves),
1120 };
1122 /* mmc1 */
1123 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1124 { .irq = AM33XX_IRQ_MMCHS1 },
1125 { .irq = -1 }
1126 };
1128 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1129 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS1_W, },
1130 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS1_R, },
1131 { .dma_req = -1 }
1132 };
1134 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
1135 {
1136 .pa_start = AM33XX_MMC1_BASE,
1137 .pa_end = AM33XX_MMC1_BASE + SZ_4K - 1,
1138 .flags = ADDR_TYPE_RT
1139 },
1140 { }
1141 };
1143 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc1 = {
1144 .master = &am33xx_l4ls_hwmod,
1145 .slave = &am33xx_mmc1_hwmod,
1146 .clk = "mmc1_ick",
1147 .addr = am33xx_mmc1_addr_space,
1148 .user = OCP_USER_MPU,
1149 };
1151 static struct omap_hwmod_ocp_if *am33xx_mmc1_slaves[] = {
1152 &am33xx_l4ls__mmc1,
1153 };
1155 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1156 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1157 };
1159 static struct omap_hwmod am33xx_mmc1_hwmod = {
1160 .name = "mmc2",
1161 .class = &am33xx_mmc_hwmod_class,
1162 .mpu_irqs = am33xx_mmc1_irqs,
1163 .sdma_reqs = am33xx_mmc1_edma_reqs,
1164 .main_clk = "mmc1_fck",
1165 .clkdm_name = "l4ls_clkdm",
1166 .prcm = {
1167 .omap4 = {
1168 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1169 .modulemode = MODULEMODE_SWCTRL,
1170 },
1171 },
1172 .dev_attr = &am33xx_mmc1_dev_attr,
1173 .slaves = am33xx_mmc1_slaves,
1174 .slaves_cnt = ARRAY_SIZE(am33xx_mmc1_slaves),
1175 };
1177 /* mmc2 */
1178 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1179 { .irq = AM33XX_IRQ_MMCHS2 },
1180 { .irq = -1 }
1181 };
1183 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1184 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS2_W, },
1185 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS2_R, },
1186 { .dma_req = -1 }
1187 };
1189 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1190 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS2_W, },
1191 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS2_R, },
1192 { .dma_req = -1 }
1193 };
1195 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
1196 {
1197 .pa_start = AM33XX_MMC2_BASE,
1198 .pa_end = AM33XX_MMC2_BASE + SZ_64K - 1,
1199 .flags = ADDR_TYPE_RT
1200 },
1201 { }
1202 };
1204 static struct omap_hwmod_ocp_if am33xx_l3_main__mmc2 = {
1205 .master = &am33xx_l3_main_hwmod,
1206 .slave = &am33xx_mmc2_hwmod,
1207 .clk = "mmc2_ick",
1208 .addr = am33xx_mmc2_addr_space,
1209 .user = OCP_USER_MPU,
1210 };
1212 static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = {
1213 &am33xx_l3_main__mmc2,
1214 };
1216 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1217 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1218 };
1219 static struct omap_hwmod am33xx_mmc2_hwmod = {
1220 .name = "mmc3",
1221 .class = &am33xx_mmc_hwmod_class,
1222 .mpu_irqs = am33xx_mmc2_irqs,
1223 .sdma_reqs = am33xx_mmc2_edma_reqs,
1224 .main_clk = "mmc2_fck",
1225 .clkdm_name = "l3s_clkdm",
1226 .prcm = {
1227 .omap4 = {
1228 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1229 .modulemode = MODULEMODE_SWCTRL,
1230 },
1231 },
1232 .dev_attr = &am33xx_mmc2_dev_attr,
1233 .slaves = am33xx_mmc2_slaves,
1234 .slaves_cnt = ARRAY_SIZE(am33xx_mmc2_slaves),
1235 };
1237 /* Master interfaces on the MPU interconnect */
1238 static struct omap_hwmod_ocp_if *am33xx_l3_mpu_masters[] = {
1239 &am33xx_mpu__l3_slow,
1240 };
1242 /* mpu */
1243 static struct omap_hwmod am33xx_mpu_hwmod = {
1244 .name = "mpu",
1245 .class = &mpu_hwmod_class,
1246 .masters = am33xx_l3_mpu_masters,
1247 .masters_cnt = ARRAY_SIZE(am33xx_l3_mpu_masters),
1248 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1249 .main_clk = "mpu_fck",
1250 .clkdm_name = "mpu_clkdm",
1251 .prcm = {
1252 .omap4 = {
1253 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1254 .modulemode = MODULEMODE_SWCTRL,
1255 },
1256 },
1257 };
1259 /* 'ocmcram' class */
1260 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
1261 .name = "ocmcram",
1262 };
1264 /* ocmcram */
1265 static struct omap_hwmod am33xx_ocmcram_hwmod = {
1266 .name = "ocmcram",
1267 .class = &am33xx_ocmcram_hwmod_class,
1268 .main_clk = "ocmcram_fck",
1269 .clkdm_name = "l3_clkdm",
1270 .prcm = {
1271 .omap4 = {
1272 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
1273 .modulemode = MODULEMODE_SWCTRL,
1274 },
1275 },
1276 };
1278 /* 'ocpwp' class */
1279 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
1280 .name = "ocpwp",
1281 };
1283 /* ocpwp */
1284 static struct omap_hwmod am33xx_ocpwp_hwmod = {
1285 .name = "ocpwp",
1286 .class = &am33xx_ocpwp_hwmod_class,
1287 .main_clk = "ocpwp_fck",
1288 .clkdm_name = "l4ls_clkdm",
1289 .prcm = {
1290 .omap4 = {
1291 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
1292 .modulemode = MODULEMODE_SWCTRL,
1293 },
1294 },
1295 };
1297 /* 'rtc' class */
1298 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1299 .name = "rtc",
1300 };
1302 /* rtc */
1303 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1304 { .irq = AM33XX_IRQ_RTC_TIMER },
1305 { .irq = -1 }
1306 };
1308 static struct omap_hwmod am33xx_rtc_hwmod = {
1309 .name = "rtc",
1310 .class = &am33xx_rtc_hwmod_class,
1311 .mpu_irqs = am33xx_rtc_irqs,
1312 .main_clk = "rtc_fck",
1313 .clkdm_name = "l4_rtc_clkdm",
1314 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1315 .prcm = {
1316 .omap4 = {
1317 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1318 .modulemode = MODULEMODE_SWCTRL,
1319 },
1320 },
1321 };
1323 /* 'sha0' class */
1324 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
1325 .name = "sha0",
1326 };
1328 /* sha0 */
1329 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
1330 { .irq = AM33XX_IRQ_SHAEIP57t0_S },
1331 { .irq = -1 }
1332 };
1334 static struct omap_hwmod am33xx_sha0_hwmod = {
1335 .name = "sha0",
1336 .class = &am33xx_sha0_hwmod_class,
1337 .mpu_irqs = am33xx_sha0_irqs,
1338 .main_clk = "sha0_fck",
1339 .clkdm_name = "l3_clkdm",
1340 .prcm = {
1341 .omap4 = {
1342 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
1343 .modulemode = MODULEMODE_SWCTRL,
1344 },
1345 },
1346 };
1348 /* 'smartreflex' class */
1349 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
1350 .name = "smartreflex",
1351 };
1353 /* smartreflex0 */
1354 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
1355 { .irq = AM33XX_IRQ_SMARTREFLEX0 },
1356 { .irq = -1 }
1357 };
1359 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
1360 .name = "smartreflex0",
1361 .class = &am33xx_smartreflex_hwmod_class,
1362 .mpu_irqs = am33xx_smartreflex0_irqs,
1363 .main_clk = "smartreflex0_fck",
1364 .clkdm_name = "l4_wkup_clkdm",
1365 .prcm = {
1366 .omap4 = {
1367 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
1368 .modulemode = MODULEMODE_SWCTRL,
1369 },
1370 },
1371 };
1373 /* smartreflex1 */
1374 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
1375 { .irq = AM33XX_IRQ_SMARTREFLEX1 },
1376 { .irq = -1 }
1377 };
1379 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
1380 .name = "smartreflex1",
1381 .class = &am33xx_smartreflex_hwmod_class,
1382 .mpu_irqs = am33xx_smartreflex1_irqs,
1383 .main_clk = "smartreflex1_fck",
1384 .clkdm_name = "l4_wkup_clkdm",
1385 .prcm = {
1386 .omap4 = {
1387 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
1388 .modulemode = MODULEMODE_SWCTRL,
1389 },
1390 },
1391 };
1393 /* 'spi' class */
1395 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1396 .rev_offs = 0x0000,
1397 .sysc_offs = 0x0110,
1398 .syss_offs = 0x0114,
1399 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1400 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1401 SYSS_HAS_RESET_STATUS),
1402 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1403 .sysc_fields = &omap_hwmod_sysc_type1,
1404 };
1406 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1407 .name = "mcspi",
1408 .sysc = &am33xx_mcspi_sysc,
1409 .rev = OMAP4_MCSPI_REV,
1410 };
1412 /* spi0 */
1413 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1414 { .irq = AM33XX_IRQ_MCSPIOCP0 },
1415 { .irq = -1 }
1416 };
1418 struct omap_hwmod_dma_info am33xx_mcspi0_sdma_reqs[] = {
1419 { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0R },
1420 { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0W },
1421 { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1R },
1422 { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1W },
1423 { .dma_req = -1 }
1424 };
1426 struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
1427 {
1428 .pa_start = AM33XX_SPI0_BASE,
1429 .pa_end = AM33XX_SPI0_BASE + SZ_1K - 1,
1430 .flags = ADDR_TYPE_RT
1431 },
1432 { }
1433 };
1435 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = {
1436 .master = &am33xx_l4per_hwmod,
1437 .slave = &am33xx_spi0_hwmod,
1438 .clk = "spi0_ick",
1439 .addr = am33xx_mcspi0_addr_space,
1440 .user = OCP_USER_MPU,
1441 };
1443 static struct omap_hwmod_ocp_if *am33xx_mcspi0_slaves[] = {
1444 &am33xx_l4_core__mcspi0,
1445 };
1447 struct omap2_mcspi_dev_attr mcspi_attrib = {
1448 .num_chipselect = 2,
1449 };
1450 static struct omap_hwmod am33xx_spi0_hwmod = {
1451 .name = "spi0",
1452 .class = &am33xx_spi_hwmod_class,
1453 .mpu_irqs = am33xx_spi0_irqs,
1454 .sdma_reqs = am33xx_mcspi0_sdma_reqs,
1455 .main_clk = "spi0_fck",
1456 .clkdm_name = "l4ls_clkdm",
1457 .prcm = {
1458 .omap4 = {
1459 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1460 .modulemode = MODULEMODE_SWCTRL,
1461 },
1462 },
1463 .dev_attr = &mcspi_attrib,
1464 .slaves = am33xx_mcspi0_slaves,
1465 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi0_slaves),
1466 };
1468 /* spi1 */
1469 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1470 { .irq = AM33XX_IRQ_SPI1 },
1471 { .irq = -1 }
1472 };
1474 struct omap_hwmod_dma_info am33xx_mcspi1_sdma_reqs[] = {
1475 { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0R },
1476 { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0W },
1477 { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1R },
1478 { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1W },
1479 { .dma_req = -1 }
1480 };
1482 struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
1483 {
1484 .pa_start = AM33XX_SPI1_BASE,
1485 .pa_end = AM33XX_SPI1_BASE + SZ_1K - 1,
1486 .flags = ADDR_TYPE_RT
1487 },
1488 { }
1489 };
1491 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = {
1492 .master = &am33xx_l4per_hwmod,
1493 .slave = &am33xx_spi1_hwmod,
1494 .clk = "spi1_ick",
1495 .addr = am33xx_mcspi1_addr_space,
1496 .user = OCP_USER_MPU,
1497 };
1499 static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = {
1500 &am33xx_l4_core__mcspi1,
1501 };
1502 static struct omap_hwmod am33xx_spi1_hwmod = {
1503 .name = "spi1",
1504 .class = &am33xx_spi_hwmod_class,
1505 .mpu_irqs = am33xx_spi1_irqs,
1506 .sdma_reqs = am33xx_mcspi1_sdma_reqs,
1507 .main_clk = "spi1_fck",
1508 .clkdm_name = "l4ls_clkdm",
1509 .prcm = {
1510 .omap4 = {
1511 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1512 .modulemode = MODULEMODE_SWCTRL,
1513 },
1514 },
1515 .dev_attr = &mcspi_attrib,
1516 .slaves = am33xx_mcspi1_slaves,
1517 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi1_slaves),
1518 };
1520 /* 'spinlock' class */
1521 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1522 .name = "spinlock",
1523 };
1525 /* spinlock */
1526 static struct omap_hwmod am33xx_spinlock_hwmod = {
1527 .name = "spinlock",
1528 .class = &am33xx_spinlock_hwmod_class,
1529 .main_clk = "spinlock_fck",
1530 .clkdm_name = "l4ls_clkdm",
1531 .prcm = {
1532 .omap4 = {
1533 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1534 .modulemode = MODULEMODE_SWCTRL,
1535 },
1536 },
1537 };
1539 /* 'timer 0 & 2-7' class */
1540 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1541 .rev_offs = 0x0000,
1542 .sysc_offs = 0x0010,
1543 .syss_offs = 0x0014,
1544 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1545 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1546 SIDLE_SMART_WKUP),
1547 .sysc_fields = &omap_hwmod_sysc_type2,
1548 };
1550 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1551 .name = "timer",
1552 .sysc = &am33xx_timer_sysc,
1553 };
1555 /* timer0 */
1556 /* l4 wkup -> timer0 interface */
1557 static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = {
1558 {
1559 .pa_start = AM33XX_TIMER0_BASE,
1560 .pa_end = AM33XX_TIMER0_BASE + SZ_1K - 1,
1561 .flags = ADDR_TYPE_RT
1562 },
1563 { }
1564 };
1566 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = {
1567 .master = &am33xx_l4wkup_hwmod,
1568 .slave = &am33xx_timer0_hwmod,
1569 .clk = "timer0_ick",
1570 .addr = am33xx_timer0_addr_space,
1571 .user = OCP_USER_MPU,
1572 };
1574 static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = {
1575 &am33xx_l4wkup__timer0,
1576 };
1578 static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = {
1579 { .irq = AM33XX_IRQ_DMTIMER0 },
1580 { .irq = -1 }
1581 };
1583 static struct omap_hwmod am33xx_timer0_hwmod = {
1584 .name = "timer0",
1585 .class = &am33xx_timer_hwmod_class,
1586 .mpu_irqs = am33xx_timer0_irqs,
1587 .main_clk = "timer0_fck",
1588 .clkdm_name = "l4_wkup_clkdm",
1589 .prcm = {
1590 .omap4 = {
1591 .clkctrl_offs = AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET,
1592 .modulemode = MODULEMODE_SWCTRL,
1593 },
1594 },
1595 .slaves = am33xx_timer0_slaves,
1596 .slaves_cnt = ARRAY_SIZE(am33xx_timer0_slaves),
1597 };
1599 /* timer1 1ms */
1600 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1601 .rev_offs = 0x0000,
1602 .sysc_offs = 0x0010,
1603 .syss_offs = 0x0014,
1604 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1605 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1606 SYSS_HAS_RESET_STATUS),
1607 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1608 .sysc_fields = &omap_hwmod_sysc_type1,
1609 };
1611 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1612 .name = "timer",
1613 .sysc = &am33xx_timer1ms_sysc,
1614 };
1616 /* l4 wkup -> timer1 interface */
1617 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
1618 {
1619 .pa_start = AM33XX_TIMER1_BASE,
1620 .pa_end = AM33XX_TIMER1_BASE + SZ_1K - 1,
1621 .flags = ADDR_TYPE_RT
1622 },
1623 { }
1624 };
1626 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = {
1627 .master = &am33xx_l4wkup_hwmod,
1628 .slave = &am33xx_timer1_hwmod,
1629 .clk = "timer1_ick",
1630 .addr = am33xx_timer1_addr_space,
1631 .user = OCP_USER_MPU,
1632 };
1634 static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = {
1635 &am33xx_l4wkup__timer1,
1636 };
1638 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
1639 { .irq = AM33XX_IRQ_DMTIMER1 },
1640 { .irq = -1 }
1641 };
1643 static struct omap_hwmod am33xx_timer1_hwmod = {
1644 .name = "timer1",
1645 .class = &am33xx_timer1ms_hwmod_class,
1646 .mpu_irqs = am33xx_timer1_irqs,
1647 .main_clk = "timer1_fck",
1648 .clkdm_name = "l4_wkup_clkdm",
1649 .prcm = {
1650 .omap4 = {
1651 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1652 .modulemode = MODULEMODE_SWCTRL,
1653 },
1654 },
1655 .slaves = am33xx_timer1_slaves,
1656 .slaves_cnt = ARRAY_SIZE(am33xx_timer1_slaves),
1657 };
1659 /* timer2 */
1660 /* l4 per -> timer2 interface */
1661 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
1662 {
1663 .pa_start = AM33XX_TIMER2_BASE,
1664 .pa_end = AM33XX_TIMER2_BASE + SZ_1K - 1,
1665 .flags = ADDR_TYPE_RT
1666 },
1667 { }
1668 };
1670 static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = {
1671 .master = &am33xx_l4per_hwmod,
1672 .slave = &am33xx_timer2_hwmod,
1673 .clk = "timer2_ick",
1674 .addr = am33xx_timer2_addr_space,
1675 .user = OCP_USER_MPU,
1676 };
1678 static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = {
1679 &am33xx_l4per__timer2,
1680 };
1682 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
1683 { .irq = AM33XX_IRQ_DMTIMER2 },
1684 { .irq = -1 }
1685 };
1687 static struct omap_hwmod am33xx_timer2_hwmod = {
1688 .name = "timer2",
1689 .class = &am33xx_timer_hwmod_class,
1690 .mpu_irqs = am33xx_timer2_irqs,
1691 .main_clk = "timer2_fck",
1692 .prcm = {
1693 .omap4 = {
1694 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1695 .modulemode = MODULEMODE_SWCTRL,
1696 },
1697 },
1698 .slaves = am33xx_timer2_slaves,
1699 .slaves_cnt = ARRAY_SIZE(am33xx_timer2_slaves),
1700 .clkdm_name = "l4ls_clkdm",
1701 };
1703 /* timer3 */
1704 /* l4 per -> timer3 interface */
1705 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
1706 {
1707 .pa_start = AM33XX_TIMER3_BASE,
1708 .pa_end = AM33XX_TIMER3_BASE + SZ_1K - 1,
1709 .flags = ADDR_TYPE_RT
1710 },
1711 { }
1712 };
1714 static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = {
1715 .master = &am33xx_l4per_hwmod,
1716 .slave = &am33xx_timer3_hwmod,
1717 .clk = "timer3_ick",
1718 .addr = am33xx_timer3_addr_space,
1719 .user = OCP_USER_MPU,
1720 };
1722 static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = {
1723 &am33xx_l4per__timer3,
1724 };
1726 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
1727 { .irq = AM33XX_IRQ_DMTIMER3 },
1728 { .irq = -1 }
1729 };
1731 static struct omap_hwmod am33xx_timer3_hwmod = {
1732 .name = "timer3",
1733 .class = &am33xx_timer_hwmod_class,
1734 .mpu_irqs = am33xx_timer3_irqs,
1735 .main_clk = "timer3_fck",
1736 .clkdm_name = "l4ls_clkdm",
1737 .prcm = {
1738 .omap4 = {
1739 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1740 .modulemode = MODULEMODE_SWCTRL,
1741 },
1742 },
1743 .slaves = am33xx_timer3_slaves,
1744 .slaves_cnt = ARRAY_SIZE(am33xx_timer3_slaves),
1745 };
1747 /* timer4 */
1748 /* l4 per -> timer4 interface */
1749 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
1750 {
1751 .pa_start = AM33XX_TIMER4_BASE,
1752 .pa_end = AM33XX_TIMER4_BASE + SZ_1K - 1,
1753 .flags = ADDR_TYPE_RT
1754 },
1755 { }
1756 };
1758 static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = {
1759 .master = &am33xx_l4per_hwmod,
1760 .slave = &am33xx_timer4_hwmod,
1761 .clk = "timer4_ick",
1762 .addr = am33xx_timer4_addr_space,
1763 .user = OCP_USER_MPU,
1764 };
1766 static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = {
1767 &am33xx_l4per__timer4,
1768 };
1770 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
1771 { .irq = AM33XX_IRQ_DMTIMER4 },
1772 { .irq = -1 }
1773 };
1775 static struct omap_hwmod am33xx_timer4_hwmod = {
1776 .name = "timer4",
1777 .class = &am33xx_timer_hwmod_class,
1778 .mpu_irqs = am33xx_timer4_irqs,
1779 .main_clk = "timer4_fck",
1780 .prcm = {
1781 .omap4 = {
1782 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1783 .modulemode = MODULEMODE_SWCTRL,
1784 },
1785 },
1786 .slaves = am33xx_timer4_slaves,
1787 .slaves_cnt = ARRAY_SIZE(am33xx_timer4_slaves),
1788 .clkdm_name = "l4ls_clkdm",
1789 };
1792 /* timer5 */
1793 /* l4 per -> timer5 interface */
1794 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
1795 {
1796 .pa_start = AM33XX_TIMER5_BASE,
1797 .pa_end = AM33XX_TIMER5_BASE + SZ_1K - 1,
1798 .flags = ADDR_TYPE_RT
1799 },
1800 { }
1801 };
1803 static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = {
1804 .master = &am33xx_l4per_hwmod,
1805 .slave = &am33xx_timer5_hwmod,
1806 .clk = "timer5_ick",
1807 .addr = am33xx_timer5_addr_space,
1808 .user = OCP_USER_MPU,
1809 };
1811 static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = {
1812 &am33xx_l4per__timer5,
1813 };
1815 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
1816 { .irq = AM33XX_IRQ_DMTIMER5 },
1817 { .irq = -1 }
1818 };
1820 static struct omap_hwmod am33xx_timer5_hwmod = {
1821 .name = "timer5",
1822 .class = &am33xx_timer_hwmod_class,
1823 .mpu_irqs = am33xx_timer5_irqs,
1824 .main_clk = "timer5_fck",
1825 .prcm = {
1826 .omap4 = {
1827 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1828 .modulemode = MODULEMODE_SWCTRL,
1829 },
1830 },
1831 .slaves = am33xx_timer5_slaves,
1832 .slaves_cnt = ARRAY_SIZE(am33xx_timer5_slaves),
1833 .clkdm_name = "l4ls_clkdm",
1834 };
1836 /* timer6 */
1837 /* l4 per -> timer6 interface */
1838 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
1839 {
1840 .pa_start = AM33XX_TIMER6_BASE,
1841 .pa_end = AM33XX_TIMER6_BASE + SZ_1K - 1,
1842 .flags = ADDR_TYPE_RT
1843 },
1844 { }
1845 };
1847 static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = {
1848 .master = &am33xx_l4per_hwmod,
1849 .slave = &am33xx_timer6_hwmod,
1850 .clk = "timer6_ick",
1851 .addr = am33xx_timer6_addr_space,
1852 .user = OCP_USER_MPU,
1853 };
1855 static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = {
1856 &am33xx_l4per__timer6,
1857 };
1859 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
1860 { .irq = AM33XX_IRQ_DMTIMER6 },
1861 { .irq = -1 }
1862 };
1864 static struct omap_hwmod am33xx_timer6_hwmod = {
1865 .name = "timer6",
1866 .class = &am33xx_timer_hwmod_class,
1867 .mpu_irqs = am33xx_timer6_irqs,
1868 .main_clk = "timer6_fck",
1869 .prcm = {
1870 .omap4 = {
1871 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
1872 .modulemode = MODULEMODE_SWCTRL,
1873 },
1874 },
1875 .slaves = am33xx_timer6_slaves,
1876 .slaves_cnt = ARRAY_SIZE(am33xx_timer6_slaves),
1877 .clkdm_name = "l4ls_clkdm",
1878 };
1880 /* timer7 */
1881 /* l4 per -> timer7 interface */
1882 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
1883 {
1884 .pa_start = AM33XX_TIMER7_BASE,
1885 .pa_end = AM33XX_TIMER7_BASE + SZ_1K - 1,
1886 .flags = ADDR_TYPE_RT
1887 },
1888 { }
1889 };
1891 static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = {
1892 .master = &am33xx_l4per_hwmod,
1893 .slave = &am33xx_timer7_hwmod,
1894 .clk = "timer7_ick",
1895 .addr = am33xx_timer7_addr_space,
1896 .user = OCP_USER_MPU,
1897 };
1899 static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = {
1900 &am33xx_l4per__timer7,
1901 };
1903 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
1904 { .irq = AM33XX_IRQ_DMTIMER7 },
1905 { .irq = -1 }
1906 };
1908 static struct omap_hwmod am33xx_timer7_hwmod = {
1909 .name = "timer7",
1910 .class = &am33xx_timer_hwmod_class,
1911 .mpu_irqs = am33xx_timer7_irqs,
1912 .main_clk = "timer7_fck",
1913 .prcm = {
1914 .omap4 = {
1915 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
1916 .modulemode = MODULEMODE_SWCTRL,
1917 },
1918 },
1919 .slaves = am33xx_timer7_slaves,
1920 .slaves_cnt = ARRAY_SIZE(am33xx_timer7_slaves),
1921 .clkdm_name = "l4ls_clkdm",
1922 };
1924 /* 'tpcc' class */
1925 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1926 .name = "tpcc",
1927 };
1929 /* tpcc */
1930 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
1931 { .irq = AM33XX_IRQ_TPCC0_INT_PO0 },
1932 { .irq = -1 },
1933 };
1935 static struct omap_hwmod am33xx_tpcc_hwmod = {
1936 .name = "tpcc",
1937 .class = &am33xx_tpcc_hwmod_class,
1938 .mpu_irqs = am33xx_tpcc_irqs,
1939 .main_clk = "tpcc_ick",
1940 .clkdm_name = "l3_clkdm",
1941 .prcm = {
1942 .omap4 = {
1943 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
1944 .modulemode = MODULEMODE_SWCTRL,
1945 },
1946 },
1947 };
1949 /* 'tptc' class */
1950 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1951 .name = "tptc",
1952 };
1954 /* tptc0 */
1955 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
1956 { .irq = AM33XX_IRQ_TPTC0 },
1957 { .irq = -1 }
1958 };
1960 static struct omap_hwmod am33xx_tptc0_hwmod = {
1961 .name = "tptc0",
1962 .class = &am33xx_tptc_hwmod_class,
1963 .mpu_irqs = am33xx_tptc0_irqs,
1964 .main_clk = "tptc0_ick",
1965 .clkdm_name = "l3_clkdm",
1966 .prcm = {
1967 .omap4 = {
1968 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
1969 .modulemode = MODULEMODE_SWCTRL,
1970 },
1971 },
1972 };
1974 /* tptc1 */
1975 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
1976 { .irq = AM33XX_IRQ_TPTC1 },
1977 { .irq = -1 }
1978 };
1980 static struct omap_hwmod am33xx_tptc1_hwmod = {
1981 .name = "tptc1",
1982 .class = &am33xx_tptc_hwmod_class,
1983 .mpu_irqs = am33xx_tptc1_irqs,
1984 .main_clk = "tptc1_ick",
1985 .clkdm_name = "l3_clkdm",
1986 .prcm = {
1987 .omap4 = {
1988 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
1989 .modulemode = MODULEMODE_SWCTRL,
1990 },
1991 },
1992 };
1994 /* tptc2 */
1995 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
1996 { .irq = AM33XX_IRQ_TPTC2 },
1997 { .irq = -1 }
1998 };
2000 static struct omap_hwmod am33xx_tptc2_hwmod = {
2001 .name = "tptc2",
2002 .class = &am33xx_tptc_hwmod_class,
2003 .mpu_irqs = am33xx_tptc2_irqs,
2004 .main_clk = "tptc2_ick",
2005 .clkdm_name = "l3_clkdm",
2006 .prcm = {
2007 .omap4 = {
2008 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
2009 .modulemode = MODULEMODE_SWCTRL,
2010 },
2011 },
2012 };
2014 /* 'uart' class */
2015 static struct omap_hwmod_class_sysconfig uart_sysc = {
2016 .rev_offs = 0x50,
2017 .sysc_offs = 0x54,
2018 .syss_offs = 0x58,
2019 .sysc_flags = (SYSC_HAS_SIDLEMODE |
2020 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2021 SYSC_HAS_AUTOIDLE),
2022 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2023 .sysc_fields = &omap_hwmod_sysc_type1,
2024 };
2026 static struct omap_hwmod_class uart_class = {
2027 .name = "uart",
2028 .sysc = &uart_sysc,
2029 };
2031 /* uart1 */
2032 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
2033 { .name = "tx", .dma_req = 26, },
2034 { .name = "rx", .dma_req = 27, },
2035 { .dma_req = -1 }
2036 };
2038 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
2039 {
2040 .pa_start = AM33XX_UART1_BASE,
2041 .pa_end = AM33XX_UART1_BASE + SZ_8K - 1,
2042 .flags = ADDR_TYPE_RT
2043 },
2044 { }
2045 };
2047 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
2048 .master = &am33xx_l4wkup_hwmod,
2049 .slave = &am33xx_uart1_hwmod,
2050 .clk = "uart1_ick",
2051 .addr = am33xx_uart1_addr_space,
2052 .user = OCP_USER_MPU,
2053 };
2055 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
2056 { .irq = AM33XX_IRQ_UART0 },
2057 { .irq = -1 }
2058 };
2060 static struct omap_hwmod_ocp_if *am33xx_uart1_slaves[] = {
2061 &am33xx_l4_wkup__uart1,
2062 };
2064 static struct omap_hwmod am33xx_uart1_hwmod = {
2065 .name = "uart1",
2066 .class = &uart_class,
2067 .mpu_irqs = am33xx_uart1_irqs,
2068 .sdma_reqs = uart1_edma_reqs,
2069 .main_clk = "uart1_fck",
2070 .clkdm_name = "l4_wkup_clkdm",
2071 .prcm = {
2072 .omap4 = {
2073 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
2074 .modulemode = MODULEMODE_SWCTRL,
2075 },
2076 },
2077 .slaves = am33xx_uart1_slaves,
2078 .slaves_cnt = ARRAY_SIZE(am33xx_uart1_slaves),
2079 };
2081 /* uart2 */
2082 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
2083 {
2084 .pa_start = AM33XX_UART2_BASE,
2085 .pa_end = AM33XX_UART2_BASE + SZ_8K - 1,
2086 .flags = ADDR_TYPE_RT
2087 },
2088 { }
2089 };
2091 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
2092 .slave = &am33xx_uart2_hwmod,
2093 .clk = "uart2_ick",
2094 .addr = am33xx_uart2_addr_space,
2095 .user = OCP_USER_MPU,
2096 };
2098 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
2099 { .irq = AM33XX_IRQ_UART1 },
2100 { .irq = -1 }
2101 };
2103 static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = {
2104 &am33xx_l4_ls__uart2,
2105 };
2107 static struct omap_hwmod am33xx_uart2_hwmod = {
2108 .name = "uart2",
2109 .class = &uart_class,
2110 .mpu_irqs = am33xx_uart2_irqs,
2111 .main_clk = "uart2_fck",
2112 .clkdm_name = "l4ls_clkdm",
2113 .sdma_reqs = uart1_edma_reqs,
2114 .prcm = {
2115 .omap4 = {
2116 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
2117 .modulemode = MODULEMODE_SWCTRL,
2118 },
2119 },
2120 .slaves = am33xx_uart2_slaves,
2121 .slaves_cnt = ARRAY_SIZE(am33xx_uart2_slaves),
2122 };
2124 /* uart3 */
2125 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
2126 {
2127 .pa_start = AM33XX_UART3_BASE,
2128 .pa_end = AM33XX_UART3_BASE + SZ_8K - 1,
2129 .flags = ADDR_TYPE_RT
2130 },
2131 { }
2132 };
2134 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
2135 .slave = &am33xx_uart3_hwmod,
2136 .clk = "uart3_ick",
2137 .addr = am33xx_uart3_addr_space,
2138 .user = OCP_USER_MPU,
2139 };
2141 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2142 { .irq = AM33XX_IRQ_UART2 },
2143 { .irq = -1 }
2144 };
2146 static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = {
2147 &am33xx_l4_ls__uart3,
2148 };
2150 static struct omap_hwmod am33xx_uart3_hwmod = {
2151 .name = "uart3",
2152 .class = &uart_class,
2153 .mpu_irqs = am33xx_uart3_irqs,
2154 .main_clk = "uart3_fck",
2155 .clkdm_name = "l4ls_clkdm",
2156 .sdma_reqs = uart1_edma_reqs,
2157 .prcm = {
2158 .omap4 = {
2159 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
2160 .modulemode = MODULEMODE_SWCTRL,
2161 },
2162 },
2163 .slaves = am33xx_uart3_slaves,
2164 .slaves_cnt = ARRAY_SIZE(am33xx_uart3_slaves),
2165 };
2167 /* uart4 */
2168 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
2169 {
2170 .pa_start = AM33XX_UART4_BASE,
2171 .pa_end = AM33XX_UART4_BASE + SZ_8K - 1,
2172 .flags = ADDR_TYPE_RT
2173 },
2174 { }
2175 };
2177 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
2178 .slave = &am33xx_uart4_hwmod,
2179 .clk = "uart4_ick",
2180 .addr = am33xx_uart4_addr_space,
2181 .user = OCP_USER_MPU,
2182 };
2184 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2185 { .irq = AM33XX_IRQ_UART3 },
2186 { .irq = -1 }
2187 };
2189 static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = {
2190 &am33xx_l4_ls__uart4,
2191 };
2193 static struct omap_hwmod am33xx_uart4_hwmod = {
2194 .name = "uart4",
2195 .class = &uart_class,
2196 .mpu_irqs = am33xx_uart4_irqs,
2197 .main_clk = "uart4_fck",
2198 .clkdm_name = "l4ls_clkdm",
2199 .sdma_reqs = uart1_edma_reqs,
2200 .prcm = {
2201 .omap4 = {
2202 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
2203 .modulemode = MODULEMODE_SWCTRL,
2204 },
2205 },
2206 .slaves = am33xx_uart4_slaves,
2207 .slaves_cnt = ARRAY_SIZE(am33xx_uart4_slaves),
2208 };
2210 /* uart5 */
2211 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
2212 {
2213 .pa_start = AM33XX_UART5_BASE,
2214 .pa_end = AM33XX_UART5_BASE + SZ_8K - 1,
2215 .flags = ADDR_TYPE_RT
2216 },
2217 { }
2218 };
2220 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
2221 .slave = &am33xx_uart5_hwmod,
2222 .clk = "uart5_ick",
2223 .addr = am33xx_uart5_addr_space,
2224 .user = OCP_USER_MPU,
2225 };
2227 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2228 { .irq = AM33XX_IRQ_UART4 },
2229 { .irq = -1 }
2230 };
2232 static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = {
2233 &am33xx_l4_ls__uart5,
2234 };
2236 static struct omap_hwmod am33xx_uart5_hwmod = {
2237 .name = "uart5",
2238 .class = &uart_class,
2239 .mpu_irqs = am33xx_uart5_irqs,
2240 .main_clk = "uart5_fck",
2241 .clkdm_name = "l4ls_clkdm",
2242 .sdma_reqs = uart1_edma_reqs,
2243 .prcm = {
2244 .omap4 = {
2245 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2246 .modulemode = MODULEMODE_SWCTRL,
2247 },
2248 },
2249 .slaves = am33xx_uart5_slaves,
2250 .slaves_cnt = ARRAY_SIZE(am33xx_uart5_slaves),
2251 };
2253 /* uart6 */
2254 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
2255 {
2256 .pa_start = AM33XX_UART6_BASE,
2257 .pa_end = AM33XX_UART6_BASE + SZ_8K - 1,
2258 .flags = ADDR_TYPE_RT
2259 },
2260 { }
2261 };
2263 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
2264 .slave = &am33xx_uart6_hwmod,
2265 .clk = "uart6_ick",
2266 .addr = am33xx_uart6_addr_space,
2267 .user = OCP_USER_MPU,
2268 };
2270 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2271 { .irq = AM33XX_IRQ_UART5 },
2272 { .irq = -1 }
2273 };
2275 static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = {
2276 &am33xx_l4_ls__uart6,
2277 };
2279 static struct omap_hwmod am33xx_uart6_hwmod = {
2280 .name = "uart6",
2281 .class = &uart_class,
2282 .mpu_irqs = am33xx_uart6_irqs,
2283 .main_clk = "uart6_fck",
2284 .clkdm_name = "l4ls_clkdm",
2285 .sdma_reqs = uart1_edma_reqs,
2286 .prcm = {
2287 .omap4 = {
2288 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2289 .modulemode = MODULEMODE_SWCTRL,
2290 },
2291 },
2292 .slaves = am33xx_uart6_slaves,
2293 .slaves_cnt = ARRAY_SIZE(am33xx_uart6_slaves),
2294 };
2296 /* 'wd_timer' class */
2297 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2298 .name = "wd_timer",
2299 };
2301 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
2302 {
2303 .pa_start = AM33XX_WDT1_BASE,
2304 .pa_end = AM33XX_WDT1_BASE + SZ_4K - 1,
2305 .flags = ADDR_TYPE_RT
2306 },
2307 { }
2308 };
2310 /* l4_wkup -> wd_timer1 */
2311 static struct omap_hwmod_ocp_if am33xx_l4wkup__wd_timer1 = {
2312 .master = &am33xx_l4wkup_hwmod,
2313 .slave = &am33xx_wd_timer1_hwmod,
2314 .addr = am33xx_wd_timer1_addrs,
2315 .user = OCP_USER_MPU,
2316 };
2318 /* wd_timer1 slave ports */
2319 static struct omap_hwmod_ocp_if *am33xx_wd_timer1_slaves[] = {
2320 &am33xx_l4wkup__wd_timer1,
2321 };
2323 /* wd_timer1 */
2324 /*
2325 * TODO: device.c file uses hardcoded name for watchdog
2326 timer driver "wd_timer2, so we are also using
2327 same name as of now...
2328 */
2329 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2330 .name = "wd_timer2",
2331 .class = &am33xx_wd_timer_hwmod_class,
2332 .main_clk = "wd_timer1_fck",
2333 .clkdm_name = "l4_wkup_clkdm",
2334 .prcm = {
2335 .omap4 = {
2336 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2337 .modulemode = MODULEMODE_SWCTRL,
2338 },
2339 },
2340 .slaves = am33xx_wd_timer1_slaves,
2341 .slaves_cnt = ARRAY_SIZE(am33xx_wd_timer1_slaves),
2342 };
2344 /* wdt0 */
2345 static struct omap_hwmod_irq_info am33xx_wdt0_irqs[] = {
2346 { .irq = AM33XX_IRQ_WDT0 },
2347 { .irq = -1 },
2348 };
2350 static struct omap_hwmod am33xx_wdt0_hwmod = {
2351 .name = "wdt0",
2352 .class = &am33xx_wd_timer_hwmod_class,
2353 .mpu_irqs = am33xx_wdt0_irqs,
2354 .main_clk = "wdt0_fck",
2355 .clkdm_name = "l4_wkup_clkdm",
2356 .prcm = {
2357 .omap4 = {
2358 .clkctrl_offs = AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET,
2359 .modulemode = MODULEMODE_SWCTRL,
2360 },
2361 },
2362 };
2364 /* 'wkup_m3' class */
2365 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
2366 .name = "wkup_m3",
2367 };
2369 /* wkup_m3 */
2370 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
2371 .name = "wkup_m3",
2372 .class = &am33xx_wkup_m3_hwmod_class,
2373 .clkdm_name = "l4_wkup_aon_clkdm",
2374 .main_clk = "wkup_m3_fck",
2375 .prcm = {
2376 .omap4 = {
2377 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
2378 .modulemode = MODULEMODE_SWCTRL,
2379 },
2380 },
2381 };
2383 /* L3 SLOW -> USBSS interface */
2384 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
2385 {
2386 .name = "usbss",
2387 .pa_start = AM33XX_USBSS_BASE,
2388 .pa_end = AM33XX_USBSS_BASE + SZ_4K - 1,
2389 .flags = ADDR_TYPE_RT
2390 },
2391 {
2392 .name = "musb0",
2393 .pa_start = AM33XX_USB0_BASE,
2394 .pa_end = AM33XX_USB0_BASE + SZ_2K - 1,
2395 .flags = ADDR_TYPE_RT
2396 },
2397 {
2398 .name = "musb1",
2399 .pa_start = AM33XX_USB1_BASE,
2400 .pa_end = AM33XX_USB1_BASE + SZ_2K - 1,
2401 .flags = ADDR_TYPE_RT
2402 },
2403 { }
2404 };
2406 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2407 .rev_offs = 0x0,
2408 .sysc_offs = 0x10,
2409 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2410 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2411 .sysc_fields = &omap_hwmod_sysc_type1,
2412 };
2414 static struct omap_hwmod_class am33xx_usbotg_class = {
2415 .name = "usbotg",
2416 .sysc = &am33xx_usbhsotg_sysc,
2417 };
2419 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2420 { .name = "usbss-irq", .irq = AM33XX_IRQ_USBSS, },
2421 { .name = "musb0-irq", .irq = AM33XX_IRQ_USB0, },
2422 { .name = "musb1-irq", .irq = AM33XX_IRQ_USB1, },
2423 { .irq = -1, },
2424 };
2426 static struct omap_hwmod_ocp_if am33xx_l3_slow__usbss = {
2427 .master = &am33xx_l3slow_hwmod,
2428 .slave = &am33xx_usbss_hwmod,
2429 .addr = am33xx_usbss_addr_space,
2430 .user = OCP_USER_MPU,
2431 .flags = OCPIF_SWSUP_IDLE,
2432 };
2434 static struct omap_hwmod_ocp_if *am33xx_usbss_slaves[] = {
2435 &am33xx_l3_slow__usbss,
2436 };
2438 static struct omap_hwmod_opt_clk usbss_opt_clks[] = {
2439 { .role = "clkdcoldo", .clk = "usbotg_fck" },
2440 };
2442 static struct omap_hwmod am33xx_usbss_hwmod = {
2443 .name = "usb_otg_hs",
2444 .mpu_irqs = am33xx_usbss_mpu_irqs,
2445 .main_clk = "usbotg_ick",
2446 .clkdm_name = "l4ls_clkdm",
2447 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2448 .prcm = {
2449 .omap4 = {
2450 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2451 .modulemode = MODULEMODE_SWCTRL,
2452 },
2453 },
2454 .opt_clks = usbss_opt_clks,
2455 .opt_clks_cnt = ARRAY_SIZE(usbss_opt_clks),
2456 .slaves = am33xx_usbss_slaves,
2457 .slaves_cnt = ARRAY_SIZE(am33xx_usbss_slaves),
2458 .class = &am33xx_usbotg_class,
2459 };
2461 static __initdata struct omap_hwmod *am33xx_hwmods[] = {
2462 /* l3 class */
2463 &am33xx_l3_instr_hwmod,
2464 &am33xx_l3_main_hwmod,
2465 /* l3s class */
2466 &am33xx_l3slow_hwmod,
2467 /* l4hs class */
2468 &am33xx_l4_hs_hwmod,
2469 /* l4fw class */
2470 &am33xx_l4fw_hwmod,
2471 /* l4ls class */
2472 &am33xx_l4ls_hwmod,
2473 /* l4per class */
2474 &am33xx_l4per_hwmod,
2475 /* l4wkup class */
2476 &am33xx_l4wkup_hwmod,
2478 /* clkdiv32k class */
2479 &am33xx_clkdiv32k_hwmod,
2480 /* mpu class */
2481 &am33xx_mpu_hwmod,
2482 /* adc_tsc class */
2483 &am33xx_adc_tsc_hwmod,
2484 /* aes class */
2485 &am33xx_aes0_hwmod,
2486 /* cefuse class */
2487 &am33xx_cefuse_hwmod,
2488 /* control class */
2489 &am33xx_control_hwmod,
2490 /* dcan class */
2491 &am33xx_dcan0_hwmod,
2492 &am33xx_dcan1_hwmod,
2493 /* debugss class */
2494 &am33xx_debugss_hwmod,
2495 /* elm class */
2496 &am33xx_elm_hwmod,
2497 /* emif_fw class */
2498 &am33xx_emif_fw_hwmod,
2499 /* epwmss class */
2500 &am33xx_epwmss0_hwmod,
2501 &am33xx_epwmss1_hwmod,
2502 &am33xx_epwmss2_hwmod,
2503 /* gpio class */
2504 &am33xx_gpio0_hwmod,
2505 &am33xx_gpio1_hwmod,
2506 &am33xx_gpio2_hwmod,
2507 &am33xx_gpio3_hwmod,
2508 /* gpmc class */
2509 &am33xx_gpmc_hwmod,
2510 /* i2c class */
2511 &am33xx_i2c1_hwmod,
2512 &am33xx_i2c2_hwmod,
2513 /* icss class */
2514 &am33xx_icss_hwmod,
2515 /* ieee5000 class */
2516 &am33xx_ieee5000_hwmod,
2517 /* mcasp class */
2518 &am33xx_mcasp0_hwmod,
2519 /* mmc class */
2520 &am33xx_mmc0_hwmod,
2521 &am33xx_mmc1_hwmod,
2522 &am33xx_mmc2_hwmod,
2523 /* ocmcram class */
2524 &am33xx_ocmcram_hwmod,
2525 /* ocpwp class */
2526 &am33xx_ocpwp_hwmod,
2527 /* sha0 class */
2528 &am33xx_sha0_hwmod,
2529 /* smartreflex class */
2530 &am33xx_smartreflex0_hwmod,
2531 &am33xx_smartreflex1_hwmod,
2532 /* spi class */
2533 &am33xx_spi0_hwmod,
2534 &am33xx_spi1_hwmod,
2535 /* spinlock class */
2536 &am33xx_spinlock_hwmod,
2537 /* uart class */
2538 &am33xx_uart1_hwmod,
2539 &am33xx_uart2_hwmod,
2540 &am33xx_uart3_hwmod,
2541 &am33xx_uart4_hwmod,
2542 &am33xx_uart5_hwmod,
2543 &am33xx_uart6_hwmod,
2544 /* timer class */
2545 &am33xx_timer0_hwmod,
2546 &am33xx_timer1_hwmod,
2547 &am33xx_timer2_hwmod,
2548 &am33xx_timer3_hwmod,
2549 &am33xx_timer4_hwmod,
2550 &am33xx_timer5_hwmod,
2551 &am33xx_timer6_hwmod,
2552 &am33xx_timer7_hwmod,
2553 /* wkup_m3 class */
2554 &am33xx_wkup_m3_hwmod,
2555 /* wd_timer class */
2556 &am33xx_wd_timer1_hwmod,
2557 /* usbss hwmod */
2558 &am33xx_usbss_hwmod,
2559 /* cpgmac0 class */
2560 &am33xx_cpgmac0_hwmod,
2561 &am33xx_wdt0_hwmod, /* Secure WDT */
2562 /* tptc class */
2563 &am33xx_tptc0_hwmod,
2564 &am33xx_tptc1_hwmod,
2565 &am33xx_tptc2_hwmod,
2566 /* tpcc class */
2567 &am33xx_tpcc_hwmod,
2568 /* LCDC class */
2569 &am33xx_lcdc_hwmod,
2570 /* rtc */
2571 &am33xx_rtc_hwmod,
2572 NULL,
2573 };
2575 int __init am33xx_hwmod_init(void)
2576 {
2577 return omap_hwmod_register(am33xx_hwmods);
2578 }