59c0d3055ddc9dc71e6606b84c07f53e06967134
1 /*
2 * Hardware modules present on the AM33XX chips
3 *
4 * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
17 #include <linux/io.h>
19 #include <plat/omap_hwmod.h>
20 #include <plat/cpu.h>
21 #include <plat/gpio.h>
22 #include <plat/dma.h>
23 #include <plat/mmc.h>
24 #include <plat/mcspi.h>
26 #include "omap_hwmod_common_data.h"
27 #include "control.h"
28 #include "cm33xx.h"
29 #include "prm33xx.h"
31 /* Backward references (IPs with Bus Master capability) */
32 static struct omap_hwmod am33xx_mpu_hwmod;
33 static struct omap_hwmod am33xx_l3slow_hwmod;
34 static struct omap_hwmod am33xx_l4wkup_hwmod;
35 static struct omap_hwmod am33xx_l4per_hwmod;
36 static struct omap_hwmod am33xx_uart1_hwmod;
37 static struct omap_hwmod am33xx_uart2_hwmod;
38 static struct omap_hwmod am33xx_uart3_hwmod;
39 static struct omap_hwmod am33xx_uart4_hwmod;
40 static struct omap_hwmod am33xx_uart5_hwmod;
41 static struct omap_hwmod am33xx_uart6_hwmod;
42 static struct omap_hwmod am33xx_timer0_hwmod;
43 static struct omap_hwmod am33xx_timer1_hwmod;
44 static struct omap_hwmod am33xx_timer2_hwmod;
45 static struct omap_hwmod am33xx_timer3_hwmod;
46 static struct omap_hwmod am33xx_timer4_hwmod;
47 static struct omap_hwmod am33xx_timer5_hwmod;
48 static struct omap_hwmod am33xx_timer6_hwmod;
49 static struct omap_hwmod am33xx_timer7_hwmod;
50 static struct omap_hwmod am33xx_wd_timer1_hwmod;
51 static struct omap_hwmod am33xx_cpgmac0_hwmod;
52 static struct omap_hwmod am33xx_icss_hwmod;
53 static struct omap_hwmod am33xx_ieee5000_hwmod;
54 static struct omap_hwmod am33xx_tptc0_hwmod;
55 static struct omap_hwmod am33xx_tptc1_hwmod;
56 static struct omap_hwmod am33xx_tptc2_hwmod;
57 static struct omap_hwmod am33xx_gpio0_hwmod;
58 static struct omap_hwmod am33xx_gpio1_hwmod;
59 static struct omap_hwmod am33xx_gpio2_hwmod;
60 static struct omap_hwmod am33xx_gpio3_hwmod;
61 static struct omap_hwmod am33xx_i2c1_hwmod;
62 static struct omap_hwmod am33xx_i2c2_hwmod;
63 static struct omap_hwmod am33xx_usbss_hwmod;
64 static struct omap_hwmod am33xx_mmc0_hwmod;
65 static struct omap_hwmod am33xx_mmc1_hwmod;
66 static struct omap_hwmod am33xx_mmc2_hwmod;
67 static struct omap_hwmod am33xx_spi0_hwmod;
68 static struct omap_hwmod am33xx_spi1_hwmod;
69 static struct omap_hwmod am33xx_elm_hwmod;
70 static struct omap_hwmod am33xx_adc_tsc_hwmod;
71 static struct omap_hwmod am33xx_tpcc_hwmod;
73 /*
74 * Interconnects hwmod structures
75 * hwmods that compose the global AM33XX OCP interconnect
76 */
78 /* MPU -> L3_SLOW Peripheral interface */
79 static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = {
80 .master = &am33xx_mpu_hwmod,
81 .slave = &am33xx_l3slow_hwmod,
82 .user = OCP_USER_MPU,
83 };
85 /* L3 SLOW -> L4_PER Peripheral interface */
86 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = {
87 .master = &am33xx_l3slow_hwmod,
88 .slave = &am33xx_l4per_hwmod,
89 .user = OCP_USER_MPU,
90 };
92 /* L3 SLOW -> L4_WKUP Peripheral interface */
93 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = {
94 .master = &am33xx_l3slow_hwmod,
95 .slave = &am33xx_l4wkup_hwmod,
96 .user = OCP_USER_MPU,
97 };
99 /* Master interfaces on the L4_WKUP interconnect */
100 static struct omap_hwmod_ocp_if *am33xx_l3_slow_masters[] = {
101 &am33xx_l3_slow__l4_per,
102 &am33xx_l3_slow__l4_wkup,
103 };
105 /* Slave interfaces on the L3_SLOW interconnect */
106 static struct omap_hwmod_ocp_if *am33xx_l3_slow_slaves[] = {
107 &am33xx_mpu__l3_slow,
108 };
110 static struct omap_hwmod am33xx_l3slow_hwmod = {
111 .name = "l3_slow",
112 .class = &l3_hwmod_class,
113 .clkdm_name = "l3s_clkdm",
114 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
115 .masters = am33xx_l3_slow_masters,
116 .masters_cnt = ARRAY_SIZE(am33xx_l3_slow_masters),
117 .slaves = am33xx_l3_slow_slaves,
118 .slaves_cnt = ARRAY_SIZE(am33xx_l3_slow_slaves),
119 };
121 /* L4 PER -> GPIO2 */
122 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
123 {
124 .pa_start = AM33XX_GPIO1_BASE,
125 .pa_end = AM33XX_GPIO1_BASE + SZ_4K - 1,
126 .flags = ADDR_TYPE_RT
127 },
128 { }
129 };
131 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
132 .master = &am33xx_l4per_hwmod,
133 .slave = &am33xx_gpio1_hwmod,
134 .clk = "l4ls_fck",
135 .addr = am33xx_gpio1_addrs,
136 .user = OCP_USER_MPU | OCP_USER_SDMA,
137 };
139 /* L4 PER -> GPIO3 */
140 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
141 {
142 .pa_start = AM33XX_GPIO2_BASE,
143 .pa_end = AM33XX_GPIO2_BASE + SZ_4K - 1,
144 .flags = ADDR_TYPE_RT
145 },
146 { }
147 };
149 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
150 .master = &am33xx_l4per_hwmod,
151 .slave = &am33xx_gpio2_hwmod,
152 .clk = "l4ls_fck",
153 .addr = am33xx_gpio2_addrs,
154 .user = OCP_USER_MPU | OCP_USER_SDMA,
155 };
157 /* L4 PER -> GPIO4 */
158 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
159 {
160 .pa_start = AM33XX_GPIO3_BASE,
161 .pa_end = AM33XX_GPIO3_BASE + SZ_4K - 1,
162 .flags = ADDR_TYPE_RT
163 },
164 { }
165 };
167 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
168 .master = &am33xx_l4per_hwmod,
169 .slave = &am33xx_gpio3_hwmod,
170 .clk = "l4ls_fck",
171 .addr = am33xx_gpio3_addrs,
172 .user = OCP_USER_MPU | OCP_USER_SDMA,
173 };
175 /* Master interfaces on the L4_PER interconnect */
176 static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = {
177 &am33xx_l4_per__gpio1,
178 &am33xx_l4_per__gpio2,
179 &am33xx_l4_per__gpio3,
180 };
181 /* Slave interfaces on the L4_PER interconnect */
182 static struct omap_hwmod_ocp_if *am33xx_l4_per_slaves[] = {
183 &am33xx_l3_slow__l4_per,
184 };
186 static struct omap_hwmod am33xx_l4per_hwmod = {
187 .name = "l4_per",
188 .class = &l4_hwmod_class,
189 .clkdm_name = "l4ls_clkdm",
190 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
191 .masters = am33xx_l4_per_masters,
192 .masters_cnt = ARRAY_SIZE(am33xx_l4_per_masters),
193 .slaves = am33xx_l4_per_slaves,
194 .slaves_cnt = ARRAY_SIZE(am33xx_l4_per_slaves),
195 };
197 /* L4 WKUP -> I2C1 */
198 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
199 {
200 .pa_start = AM33XX_I2C0_BASE,
201 .pa_end = AM33XX_I2C0_BASE + SZ_4K - 1,
202 .flags = ADDR_TYPE_RT
203 },
204 { }
205 };
207 static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = {
208 .master = &am33xx_l4wkup_hwmod,
209 .slave = &am33xx_i2c1_hwmod,
210 .addr = am33xx_i2c1_addr_space,
211 .user = OCP_USER_MPU,
212 };
214 /* L4 WKUP -> GPIO1 */
215 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
216 {
217 .pa_start = AM33XX_GPIO0_BASE,
218 .pa_end = AM33XX_GPIO0_BASE + SZ_4K - 1,
219 .flags = ADDR_TYPE_RT
220 },
221 { }
222 };
224 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
225 .master = &am33xx_l4wkup_hwmod,
226 .slave = &am33xx_gpio0_hwmod,
227 .clk = "l4ls_fck",
228 .addr = am33xx_gpio0_addrs,
229 .user = OCP_USER_MPU | OCP_USER_SDMA,
230 };
232 /* L4 WKUP -> ADC_TSC */
233 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
234 {
235 .pa_start = AM33XX_TSC_BASE,
236 .pa_end = AM33XX_TSC_BASE + SZ_8K - 1,
237 .flags = ADDR_TYPE_RT
238 },
239 { }
240 };
242 static struct omap_hwmod_ocp_if am33xx_l4_wkup_adc_tsc = {
243 .master = &am33xx_l4wkup_hwmod,
244 .slave = &am33xx_adc_tsc_hwmod,
245 .addr = am33xx_adc_tsc_addrs,
246 .user = OCP_USER_MPU,
247 };
249 /* Master interfaces on the L4_WKUP interconnect */
250 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = {
251 &am33xx_l4_wkup__gpio0,
252 };
253 /* Slave interfaces on the L4_WKUP interconnect */
254 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_slaves[] = {
255 &am33xx_l3_slow__l4_wkup,
256 };
258 static struct omap_hwmod am33xx_l4wkup_hwmod = {
259 .name = "l4_wkup",
260 .class = &l4_hwmod_class,
261 .clkdm_name = "l4_wkup_clkdm",
262 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
263 .masters = am33xx_l4_wkup_masters,
264 .masters_cnt = ARRAY_SIZE(am33xx_l4_wkup_masters),
265 .slaves = am33xx_l4_wkup_slaves,
266 .slaves_cnt = ARRAY_SIZE(am33xx_l4_wkup_slaves),
267 };
269 /* 'adc_tsc' class */
270 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
271 .name = "adc_tsc",
272 };
274 /* adc_tsc */
275 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
276 { .irq = AM33XX_IRQ_TSC },
277 { .irq = -1 }
278 };
280 static struct omap_hwmod_ocp_if *am33xx_adc_tsc_slaves[] = {
281 &am33xx_l4_wkup_adc_tsc,
282 };
284 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
285 .name = "adc_tsc",
286 .class = &am33xx_adc_tsc_hwmod_class,
287 .mpu_irqs = am33xx_adc_tsc_irqs,
288 .main_clk = "adc_tsc_fck",
289 .clkdm_name = "l4_wkup_clkdm",
290 .prcm = {
291 .omap4 = {
292 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
293 .modulemode = MODULEMODE_SWCTRL,
294 },
295 },
296 .flags = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
297 .slaves = am33xx_adc_tsc_slaves,
298 .slaves_cnt = ARRAY_SIZE(am33xx_adc_tsc_slaves),
299 };
301 /* 'aes' class */
302 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
303 .name = "aes",
304 };
306 /* aes0 */
307 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
308 { .irq = AM33XX_IRQ_AESEIP36t0_S },
309 { .irq = -1 }
310 };
312 static struct omap_hwmod am33xx_aes0_hwmod = {
313 .name = "aes0",
314 .class = &am33xx_aes_hwmod_class,
315 .mpu_irqs = am33xx_aes0_irqs,
316 .main_clk = "aes0_fck",
317 .clkdm_name = "l3_clkdm",
318 .prcm = {
319 .omap4 = {
320 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
321 .modulemode = MODULEMODE_SWCTRL,
322 },
323 },
324 };
326 /* 'cefuse' class */
327 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
328 .name = "cefuse",
329 };
331 /* cefuse */
332 static struct omap_hwmod am33xx_cefuse_hwmod = {
333 .name = "cefuse",
334 .class = &am33xx_cefuse_hwmod_class,
335 .main_clk = "cefuse_fck",
336 .clkdm_name = "l4_cefuse_clkdm",
337 .prcm = {
338 .omap4 = {
339 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
340 .modulemode = MODULEMODE_SWCTRL,
341 },
342 },
343 };
345 /* 'clkdiv32k' class */
346 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
347 .name = "clkdiv32k",
348 };
350 /* clkdiv32k */
351 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
352 .name = "clkdiv32k",
353 .class = &am33xx_clkdiv32k_hwmod_class,
354 .main_clk = "clkdiv32k_fck",
355 .clkdm_name = "clk_24mhz_clkdm",
356 .prcm = {
357 .omap4 = {
358 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
359 .modulemode = MODULEMODE_SWCTRL,
360 },
361 },
362 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
363 };
365 /* 'control' class */
366 static struct omap_hwmod_class am33xx_control_hwmod_class = {
367 .name = "control",
368 };
370 /* control */
371 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
372 { .irq = AM33XX_IRQ_CONTROL_PLATFORM },
373 { .irq = -1 }
374 };
376 static struct omap_hwmod am33xx_control_hwmod = {
377 .name = "control",
378 .class = &am33xx_control_hwmod_class,
379 .mpu_irqs = am33xx_control_irqs,
380 .main_clk = "control_fck",
381 .clkdm_name = "l4_wkup_clkdm",
382 .prcm = {
383 .omap4 = {
384 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
385 .modulemode = MODULEMODE_SWCTRL,
386 },
387 },
388 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
389 };
391 /* 'cpgmac0' class */
392 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
393 .name = "cpgmac0",
394 };
396 /* cpgmac0 */
397 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
398 .name = "cpgmac0",
399 .class = &am33xx_cpgmac0_hwmod_class,
400 .main_clk = "cpgmac0_fck",
401 .clkdm_name = "cpsw_125mhz_clkdm",
402 .prcm = {
403 .omap4 = {
404 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
405 .modulemode = MODULEMODE_SWCTRL,
406 },
407 },
408 };
410 /* 'dcan' class */
411 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
412 .name = "dcan",
413 };
415 /* dcan0 */
416 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
417 { .irq = AM33XX_IRQ_DCAN0_0 },
418 { .irq = -1 }
419 };
421 static struct omap_hwmod am33xx_dcan0_hwmod = {
422 .name = "dcan0",
423 .class = &am33xx_dcan_hwmod_class,
424 .mpu_irqs = am33xx_dcan0_irqs,
425 .main_clk = "dcan0_fck",
426 .clkdm_name = "l4ls_clkdm",
427 .prcm = {
428 .omap4 = {
429 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
430 .modulemode = MODULEMODE_SWCTRL,
431 },
432 },
433 };
435 /* dcan1 */
436 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
437 { .irq = AM33XX_IRQ_DCAN1_0 },
438 { .irq = -1 }
439 };
440 static struct omap_hwmod am33xx_dcan1_hwmod = {
441 .name = "dcan1",
442 .class = &am33xx_dcan_hwmod_class,
443 .mpu_irqs = am33xx_dcan1_irqs,
444 .main_clk = "dcan1_fck",
445 .clkdm_name = "l4ls_clkdm",
446 .prcm = {
447 .omap4 = {
448 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
449 .modulemode = MODULEMODE_SWCTRL,
450 },
451 },
452 };
454 /* 'debugss' class */
455 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
456 .name = "debugss",
457 };
459 /* debugss */
460 static struct omap_hwmod am33xx_debugss_hwmod = {
461 .name = "debugss",
462 .class = &am33xx_debugss_hwmod_class,
463 .main_clk = "debugss_fck",
464 .clkdm_name = "l3_aon_clkdm",
465 .prcm = {
466 .omap4 = {
467 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
468 .modulemode = MODULEMODE_SWCTRL,
469 },
470 },
471 #ifdef CONFIG_DEBUG_JTAG_ENABLE
472 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
473 #endif
474 };
476 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
477 .rev_offs = 0x0000,
478 .sysc_offs = 0x0010,
479 .syss_offs = 0x0014,
480 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
481 SYSC_HAS_SOFTRESET |
482 SYSS_HAS_RESET_STATUS),
483 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
484 .sysc_fields = &omap_hwmod_sysc_type1,
485 };
486 /* 'elm' class */
487 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
488 .name = "elm",
489 .sysc = &am33xx_elm_sysc,
490 };
492 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
493 { .irq = AM33XX_IRQ_ELM },
494 { .irq = -1 }
495 };
497 struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
498 {
499 .pa_start = AM33XX_ELM_BASE,
500 .pa_end = AM33XX_ELM_BASE + SZ_8K - 1,
501 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
502 },
503 { }
504 };
506 struct omap_hwmod_ocp_if am33xx_l4_core__elm = {
507 .master = &am33xx_l4per_hwmod,
508 .slave = &am33xx_elm_hwmod,
509 .addr = am33xx_elm_addr_space,
510 .user = OCP_USER_MPU,
511 };
513 static struct omap_hwmod_ocp_if *am33xx_elm_slaves[] = {
514 &am33xx_l4_core__elm,
515 };
517 /* elm */
518 static struct omap_hwmod am33xx_elm_hwmod = {
519 .name = "elm",
520 .class = &am33xx_elm_hwmod_class,
521 .mpu_irqs = am33xx_elm_irqs,
522 .main_clk = "elm_fck",
523 .clkdm_name = "l4ls_clkdm",
524 .slaves = am33xx_elm_slaves,
525 .slaves_cnt = ARRAY_SIZE(am33xx_elm_slaves),
526 .prcm = {
527 .omap4 = {
528 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
529 .modulemode = MODULEMODE_SWCTRL,
530 },
531 },
532 };
534 /* 'emif_fw' class */
535 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
536 .name = "emif_fw",
537 };
539 /* emif_fw */
540 static struct omap_hwmod am33xx_emif_fw_hwmod = {
541 .name = "emif_fw",
542 .class = &am33xx_emif_fw_hwmod_class,
543 .main_clk = "emif_fw_fck",
544 .clkdm_name = "l4fw_clkdm",
545 .prcm = {
546 .omap4 = {
547 .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
548 .modulemode = MODULEMODE_SWCTRL,
549 },
550 },
551 .flags = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
552 };
554 /* 'epwmss' class */
555 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
556 .name = "epwmss",
557 };
559 /* epwmss0 */
560 static struct omap_hwmod am33xx_epwmss0_hwmod = {
561 .name = "epwmss0",
562 .class = &am33xx_epwmss_hwmod_class,
563 .main_clk = "epwmss0_fck",
564 .clkdm_name = "l4ls_clkdm",
565 .prcm = {
566 .omap4 = {
567 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
568 .modulemode = MODULEMODE_SWCTRL,
569 },
570 },
571 };
573 /* epwmss1 */
574 static struct omap_hwmod am33xx_epwmss1_hwmod = {
575 .name = "epwmss1",
576 .class = &am33xx_epwmss_hwmod_class,
577 .main_clk = "epwmss1_fck",
578 .clkdm_name = "l4ls_clkdm",
579 .prcm = {
580 .omap4 = {
581 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
582 .modulemode = MODULEMODE_SWCTRL,
583 },
584 },
585 };
587 /* epwmss2 */
588 static struct omap_hwmod am33xx_epwmss2_hwmod = {
589 .name = "epwmss2",
590 .class = &am33xx_epwmss_hwmod_class,
591 .main_clk = "epwmss2_fck",
592 .clkdm_name = "l4ls_clkdm",
593 .prcm = {
594 .omap4 = {
595 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
596 .modulemode = MODULEMODE_SWCTRL,
597 },
598 },
599 };
601 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
602 .rev_offs = 0x0000,
603 .sysc_offs = 0x0010,
604 .syss_offs = 0x0114,
605 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
606 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
607 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
608 SIDLE_SMART_WKUP),
609 .sysc_fields = &omap_hwmod_sysc_type1,
610 };
612 /* 'gpio' class */
613 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
614 .name = "gpio",
615 .sysc = &am33xx_gpio_sysc,
616 .rev = 2,
617 };
619 /* gpio dev_attr */
620 static struct omap_gpio_dev_attr gpio_dev_attr = {
621 .bank_width = 32,
622 .dbck_flag = true,
623 };
625 /* gpio0 */
626 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
627 { .irq = AM33XX_IRQ_GPIO0_1 },
628 { .irq = -1 }
629 };
631 /* gpio0 slave ports */
632 static struct omap_hwmod_ocp_if *am33xx_gpio0_slaves[] = {
633 &am33xx_l4_wkup__gpio0,
634 };
636 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
637 { .role = "dbclk", .clk = "gpio0_dbclk" },
638 { .role = "fclk", .clk = "gpio0_fck" },
639 };
641 /* gpio0 */
642 static struct omap_hwmod am33xx_gpio0_hwmod = {
643 .name = "gpio1",
644 .class = &am33xx_gpio_hwmod_class,
645 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
646 .mpu_irqs = am33xx_gpio0_irqs,
647 .main_clk = "gpio0_fck",
648 .clkdm_name = "l4_wkup_clkdm",
649 .prcm = {
650 .omap4 = {
651 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
652 .modulemode = MODULEMODE_SWCTRL,
653 },
654 },
655 .opt_clks = gpio0_opt_clks,
656 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
657 .dev_attr = &gpio_dev_attr,
658 .slaves = am33xx_gpio0_slaves,
659 .slaves_cnt = ARRAY_SIZE(am33xx_gpio0_slaves),
660 };
662 /* gpio1 */
663 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
664 { .irq = AM33XX_IRQ_GPIO1_1 },
665 { .irq = -1 }
666 };
668 /* gpio1 slave ports */
669 static struct omap_hwmod_ocp_if *am33xx_gpio1_slaves[] = {
670 &am33xx_l4_per__gpio1,
671 };
673 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
674 { .role = "dbclk", .clk = "gpio1_dbclk" },
675 { .role = "fclk", .clk = "gpio1_fck" },
676 };
678 static struct omap_hwmod am33xx_gpio1_hwmod = {
679 .name = "gpio2",
680 .class = &am33xx_gpio_hwmod_class,
681 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
682 .mpu_irqs = am33xx_gpio1_irqs,
683 .main_clk = "gpio1_fck",
684 .clkdm_name = "l4ls_clkdm",
685 .prcm = {
686 .omap4 = {
687 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
688 .modulemode = MODULEMODE_SWCTRL,
689 },
690 },
691 .opt_clks = gpio1_opt_clks,
692 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
693 .dev_attr = &gpio_dev_attr,
694 .slaves = am33xx_gpio1_slaves,
695 .slaves_cnt = ARRAY_SIZE(am33xx_gpio1_slaves),
696 };
698 /* gpio2 */
699 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
700 { .irq = AM33XX_IRQ_GPIO2_1 },
701 { .irq = -1 }
702 };
704 /* gpio2 slave ports */
705 static struct omap_hwmod_ocp_if *am33xx_gpio2_slaves[] = {
706 &am33xx_l4_per__gpio2,
707 };
709 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
710 { .role = "dbclk", .clk = "gpio2_dbclk" },
711 { .role = "fclk", .clk = "gpio2_fck" },
712 };
714 /* gpio2 */
715 static struct omap_hwmod am33xx_gpio2_hwmod = {
716 .name = "gpio3",
717 .class = &am33xx_gpio_hwmod_class,
718 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
719 .mpu_irqs = am33xx_gpio2_irqs,
720 .main_clk = "gpio2_fck",
721 .clkdm_name = "l4ls_clkdm",
722 .prcm = {
723 .omap4 = {
724 .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
725 .modulemode = MODULEMODE_SWCTRL,
726 },
727 },
728 .opt_clks = gpio2_opt_clks,
729 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
730 .dev_attr = &gpio_dev_attr,
731 .slaves = am33xx_gpio2_slaves,
732 .slaves_cnt = ARRAY_SIZE(am33xx_gpio2_slaves),
733 };
735 /* gpio3 */
736 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
737 { .irq = AM33XX_IRQ_GPIO3_1 },
738 { .irq = -1 }
739 };
741 /* gpio3 slave ports */
742 static struct omap_hwmod_ocp_if *am33xx_gpio3_slaves[] = {
743 &am33xx_l4_per__gpio3,
744 };
746 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
747 { .role = "dbclk", .clk = "gpio3_dbclk" },
748 { .role = "fclk", .clk = "gpio3_fck" },
749 };
751 /* gpio3 */
752 static struct omap_hwmod am33xx_gpio3_hwmod = {
753 .name = "gpio4",
754 .class = &am33xx_gpio_hwmod_class,
755 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
756 .mpu_irqs = am33xx_gpio3_irqs,
757 .main_clk = "gpio3_fck",
758 .clkdm_name = "l4ls_clkdm",
759 .prcm = {
760 .omap4 = {
761 .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
762 .modulemode = MODULEMODE_SWCTRL,
763 },
764 },
765 .opt_clks = gpio3_opt_clks,
766 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
767 .dev_attr = &gpio_dev_attr,
768 .slaves = am33xx_gpio3_slaves,
769 .slaves_cnt = ARRAY_SIZE(am33xx_gpio3_slaves),
770 };
772 /* 'gpmc' class */
774 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
775 .name = "gpmc",
776 };
778 /* gpmc */
779 static struct omap_hwmod am33xx_gpmc_hwmod = {
780 .name = "gpmc",
781 .class = &am33xx_gpmc_hwmod_class,
782 .main_clk = "gpmc_fck",
783 .clkdm_name = "l3s_clkdm",
784 .prcm = {
785 .omap4 = {
786 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
787 .modulemode = MODULEMODE_SWCTRL,
788 },
789 },
790 };
792 /* 'i2c' class */
794 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
795 .sysc_offs = 0x0010,
796 .syss_offs = 0x0090,
797 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
798 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
799 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
800 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
801 SIDLE_SMART_WKUP),
802 .sysc_fields = &omap_hwmod_sysc_type1,
803 };
805 static struct omap_i2c_dev_attr i2c_dev_attr = {
806 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
807 };
809 static struct omap_hwmod_class i2c_class = {
810 .name = "i2c",
811 .sysc = &am33xx_i2c_sysc,
812 .rev = OMAP_I2C_IP_VERSION_2,
813 .reset = &omap_i2c_reset,
814 };
816 /* I2C1 */
817 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
818 { .irq = AM33XX_IRQ_MSHSI2COCP0 },
819 { .irq = -1 }
820 };
822 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
823 { .name = "tx", .dma_req = 0, },
824 { .name = "rx", .dma_req = 0, },
825 { .dma_req = -1 }
826 };
828 static struct omap_hwmod_ocp_if *am33xx_i2c1_slaves[] = {
829 &am33xx_l4_wkup_i2c1,
830 };
832 static struct omap_hwmod am33xx_i2c1_hwmod = {
833 .name = "i2c1",
834 .mpu_irqs = i2c1_mpu_irqs,
835 .sdma_reqs = i2c1_edma_reqs,
836 .main_clk = "i2c1_fck",
837 .clkdm_name = "l4_wkup_clkdm",
838 .prcm = {
839 .omap4 = {
840 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
841 .modulemode = MODULEMODE_SWCTRL,
842 },
843 },
844 .flags = HWMOD_16BIT_REG,
845 .dev_attr = &i2c_dev_attr,
846 .slaves = am33xx_i2c1_slaves,
847 .slaves_cnt = ARRAY_SIZE(am33xx_i2c1_slaves),
848 .class = &i2c_class,
849 };
851 /* i2c2 */
852 /* l4 per -> i2c2 */
853 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
854 {
855 .pa_start = AM33XX_I2C1_BASE,
856 .pa_end = AM33XX_I2C1_BASE + SZ_4K - 1,
857 .flags = ADDR_TYPE_RT
858 },
859 { }
860 };
862 static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = {
863 .master = &am33xx_l4per_hwmod,
864 .slave = &am33xx_i2c2_hwmod,
865 .addr = am33xx_i2c2_addr_space,
866 .user = OCP_USER_MPU,
867 };
869 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
870 { .irq = AM33XX_IRQ_MSHSI2COCP1 },
871 { .irq = -1 }
872 };
874 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
875 { .name = "tx", .dma_req = 0, },
876 { .name = "rx", .dma_req = 0, },
877 { .dma_req = -1 }
878 };
880 static struct omap_hwmod_ocp_if *am33xx_i2c2_slaves[] = {
881 &am335_l4_per_i2c2,
882 };
884 static struct omap_hwmod am33xx_i2c2_hwmod = {
885 .name = "i2c2",
886 .mpu_irqs = i2c2_mpu_irqs,
887 .sdma_reqs = i2c2_edma_reqs,
888 .main_clk = "i2c2_fck",
889 .clkdm_name = "l4ls_clkdm",
890 .prcm = {
891 .omap4 = {
892 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
893 .modulemode = MODULEMODE_SWCTRL,
894 },
895 },
896 .flags = HWMOD_16BIT_REG,
897 .dev_attr = &i2c_dev_attr,
898 .slaves = am33xx_i2c2_slaves,
899 .slaves_cnt = ARRAY_SIZE(am33xx_i2c2_slaves),
900 .class = &i2c_class,
901 };
903 /* 'icss' class */
904 static struct omap_hwmod_class am33xx_icss_hwmod_class = {
905 .name = "icss",
906 };
908 /* icss */
909 static struct omap_hwmod am33xx_icss_hwmod = {
910 .name = "icss",
911 .class = &am33xx_icss_hwmod_class,
912 .main_clk = "icss_fck",
913 .clkdm_name = "icss_ocp_clkdm",
914 .prcm = {
915 .omap4 = {
916 .clkctrl_offs = AM33XX_CM_PER_ICSS_CLKCTRL_OFFSET,
917 .modulemode = MODULEMODE_SWCTRL,
918 },
919 },
920 };
922 /* 'ieee5000' class */
923 static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = {
924 .name = "ieee5000",
925 };
927 /* ieee5000 */
928 static struct omap_hwmod am33xx_ieee5000_hwmod = {
929 .name = "ieee5000",
930 .class = &am33xx_ieee5000_hwmod_class,
931 .main_clk = "ieee5000_fck",
932 .clkdm_name = "l3s_clkdm",
933 .prcm = {
934 .omap4 = {
935 .clkctrl_offs = AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET,
936 .modulemode = MODULEMODE_SWCTRL,
937 },
938 },
939 };
942 /* 'l3' class */
943 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
944 .name = "l3",
945 };
947 /* l4_hs */
948 static struct omap_hwmod am33xx_l4_hs_hwmod = {
949 .name = "l4_hs",
950 .class = &am33xx_l3_hwmod_class,
951 .clkdm_name = "l4hs_clkdm",
952 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
953 .prcm = {
954 .omap4 = {
955 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
956 .modulemode = MODULEMODE_SWCTRL,
957 },
958 },
959 };
961 /* l3_instr */
962 static struct omap_hwmod am33xx_l3_instr_hwmod = {
963 .name = "l3_instr",
964 .class = &am33xx_l3_hwmod_class,
965 .clkdm_name = "l3_clkdm",
966 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
967 .prcm = {
968 .omap4 = {
969 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
970 .modulemode = MODULEMODE_SWCTRL,
971 },
972 },
973 };
975 /* l3_main */
976 static struct omap_hwmod am33xx_l3_main_hwmod = {
977 .name = "l3_main",
978 .class = &am33xx_l3_hwmod_class,
979 .clkdm_name = "l3_clkdm",
980 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
981 .prcm = {
982 .omap4 = {
983 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
984 .modulemode = MODULEMODE_SWCTRL,
985 },
986 },
987 };
989 /* 'l4fw' class */
990 static struct omap_hwmod_class am33xx_l4fw_hwmod_class = {
991 .name = "l4fw",
992 };
994 /* l4fw */
995 static struct omap_hwmod am33xx_l4fw_hwmod = {
996 .name = "l4fw",
997 .class = &am33xx_l4fw_hwmod_class,
998 .clkdm_name = "l4fw_clkdm",
999 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1000 .prcm = {
1001 .omap4 = {
1002 .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
1003 .modulemode = MODULEMODE_SWCTRL,
1004 },
1005 },
1006 };
1008 /* 'l4ls' class */
1009 static struct omap_hwmod_class am33xx_l4ls_hwmod_class = {
1010 .name = "l4ls",
1011 };
1013 /* l4ls */
1014 static struct omap_hwmod am33xx_l4ls_hwmod = {
1015 .name = "l4ls",
1016 .class = &am33xx_l4ls_hwmod_class,
1017 .main_clk = "l4ls_fck",
1018 .clkdm_name = "l4ls_clkdm",
1019 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1020 .prcm = {
1021 .omap4 = {
1022 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
1023 .modulemode = MODULEMODE_SWCTRL,
1024 },
1025 },
1026 };
1028 /* 'lcdc' class */
1029 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1030 .name = "lcdc",
1031 };
1033 /* lcdc */
1034 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1035 { .irq = AM33XX_IRQ_LCD },
1036 { .irq = -1 }
1037 };
1039 static struct omap_hwmod am33xx_lcdc_hwmod = {
1040 .name = "lcdc",
1041 .class = &am33xx_lcdc_hwmod_class,
1042 .mpu_irqs = am33xx_lcdc_irqs,
1043 .main_clk = "lcdc_fck",
1044 .clkdm_name = "lcdc_clkdm",
1045 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1046 .prcm = {
1047 .omap4 = {
1048 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1049 .modulemode = MODULEMODE_SWCTRL,
1050 },
1051 },
1052 };
1054 /*
1055 * 'mailbox' class
1056 * mailbox module allowing communication between the on-chip processors using a
1057 * queued mailbox-interrupt mechanism.
1058 */
1060 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1061 .rev_offs = 0x0000,
1062 .sysc_offs = 0x0010,
1063 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1064 SYSC_HAS_SOFTRESET),
1065 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1066 .sysc_fields = &omap_hwmod_sysc_type2,
1067 };
1069 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1070 .name = "mailbox",
1071 .sysc = &am33xx_mailbox_sysc,
1072 };
1074 /* mailbox */
1075 static struct omap_hwmod am33xx_mailbox_hwmod;
1076 static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1077 { .irq = AM33XX_IRQ_MAILBOX },
1078 { .irq = -1 }
1079 };
1081 static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
1082 {
1083 .pa_start = AM33XX_MAILBOX0_BASE,
1084 .pa_end = AM33XX_MAILBOX0_BASE + (SZ_4K - 1),
1085 .flags = ADDR_TYPE_RT
1086 },
1087 { }
1088 };
1090 /* l4_cfg -> mailbox */
1091 static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
1092 .master = &am33xx_l4per_hwmod,
1093 .slave = &am33xx_mailbox_hwmod,
1094 .addr = am33xx_mailbox_addrs,
1095 .user = OCP_USER_MPU,
1096 };
1098 /* mailbox slave ports */
1099 static struct omap_hwmod_ocp_if *am33xx_mailbox_slaves[] = {
1100 &am33xx_l4_per__mailbox,
1101 };
1103 static struct omap_hwmod am33xx_mailbox_hwmod = {
1104 .name = "mailbox",
1105 .class = &am33xx_mailbox_hwmod_class,
1106 .clkdm_name = "l4ls_clkdm",
1107 .mpu_irqs = am33xx_mailbox_irqs,
1108 .main_clk = "mailbox0_fck",
1109 .prcm = {
1110 .omap4 = {
1111 .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1112 .modulemode = MODULEMODE_SWCTRL,
1113 },
1114 },
1115 .slaves = am33xx_mailbox_slaves,
1116 .slaves_cnt = ARRAY_SIZE(am33xx_mailbox_slaves),
1117 };
1119 /* 'mcasp' class */
1120 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1121 .name = "mcasp",
1122 };
1124 /* mcasp0 */
1125 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1126 { .irq = 80 },
1127 { .irq = -1 }
1128 };
1130 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1131 .name = "mcasp0",
1132 .class = &am33xx_mcasp_hwmod_class,
1133 .mpu_irqs = am33xx_mcasp0_irqs,
1134 .main_clk = "mcasp0_fck",
1135 .clkdm_name = "l3s_clkdm",
1136 .prcm = {
1137 .omap4 = {
1138 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1139 .modulemode = MODULEMODE_SWCTRL,
1140 },
1141 },
1142 };
1144 /* 'mmc' class */
1146 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1147 .rev_offs = 0x1fc,
1148 .sysc_offs = 0x10,
1149 .syss_offs = 0x14,
1150 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1151 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1152 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1153 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1154 .sysc_fields = &omap_hwmod_sysc_type1,
1155 };
1157 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1158 .name = "mmc",
1159 .sysc = &am33xx_mmc_sysc,
1160 };
1162 /* mmc0 */
1163 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1164 { .irq = AM33XX_IRQ_MMCHS0 },
1165 { .irq = -1 }
1166 };
1168 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1169 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS0_W, },
1170 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS0_R, },
1171 { .dma_req = -1 }
1172 };
1174 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
1175 {
1176 .pa_start = AM33XX_MMC0_BASE,
1177 .pa_end = AM33XX_MMC0_BASE + SZ_4K - 1,
1178 .flags = ADDR_TYPE_RT
1179 },
1180 { }
1181 };
1183 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc0 = {
1184 .master = &am33xx_l4ls_hwmod,
1185 .slave = &am33xx_mmc0_hwmod,
1186 .clk = "mmc0_ick",
1187 .addr = am33xx_mmc0_addr_space,
1188 .user = OCP_USER_MPU,
1189 };
1191 static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = {
1192 &am33xx_l4ls__mmc0,
1193 };
1195 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1196 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1197 };
1199 static struct omap_hwmod am33xx_mmc0_hwmod = {
1200 .name = "mmc1",
1201 .class = &am33xx_mmc_hwmod_class,
1202 .mpu_irqs = am33xx_mmc0_irqs,
1203 .sdma_reqs = am33xx_mmc0_edma_reqs,
1204 .main_clk = "mmc0_fck",
1205 .clkdm_name = "l4ls_clkdm",
1206 .prcm = {
1207 .omap4 = {
1208 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1209 .modulemode = MODULEMODE_SWCTRL,
1210 },
1211 },
1212 .dev_attr = &am33xx_mmc0_dev_attr,
1213 .slaves = am33xx_mmc0_slaves,
1214 .slaves_cnt = ARRAY_SIZE(am33xx_mmc0_slaves),
1215 };
1217 /* mmc1 */
1218 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1219 { .irq = AM33XX_IRQ_MMCHS1 },
1220 { .irq = -1 }
1221 };
1223 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1224 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS1_W, },
1225 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS1_R, },
1226 { .dma_req = -1 }
1227 };
1229 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
1230 {
1231 .pa_start = AM33XX_MMC1_BASE,
1232 .pa_end = AM33XX_MMC1_BASE + SZ_4K - 1,
1233 .flags = ADDR_TYPE_RT
1234 },
1235 { }
1236 };
1238 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc1 = {
1239 .master = &am33xx_l4ls_hwmod,
1240 .slave = &am33xx_mmc1_hwmod,
1241 .clk = "mmc1_ick",
1242 .addr = am33xx_mmc1_addr_space,
1243 .user = OCP_USER_MPU,
1244 };
1246 static struct omap_hwmod_ocp_if *am33xx_mmc1_slaves[] = {
1247 &am33xx_l4ls__mmc1,
1248 };
1250 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1251 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1252 };
1254 static struct omap_hwmod am33xx_mmc1_hwmod = {
1255 .name = "mmc2",
1256 .class = &am33xx_mmc_hwmod_class,
1257 .mpu_irqs = am33xx_mmc1_irqs,
1258 .sdma_reqs = am33xx_mmc1_edma_reqs,
1259 .main_clk = "mmc1_fck",
1260 .clkdm_name = "l4ls_clkdm",
1261 .prcm = {
1262 .omap4 = {
1263 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1264 .modulemode = MODULEMODE_SWCTRL,
1265 },
1266 },
1267 .dev_attr = &am33xx_mmc1_dev_attr,
1268 .slaves = am33xx_mmc1_slaves,
1269 .slaves_cnt = ARRAY_SIZE(am33xx_mmc1_slaves),
1270 };
1272 /* mmc2 */
1273 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1274 { .irq = AM33XX_IRQ_MMCHS2 },
1275 { .irq = -1 }
1276 };
1278 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1279 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS2_W, },
1280 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS2_R, },
1281 { .dma_req = -1 }
1282 };
1284 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
1285 {
1286 .pa_start = AM33XX_MMC2_BASE,
1287 .pa_end = AM33XX_MMC2_BASE + SZ_64K - 1,
1288 .flags = ADDR_TYPE_RT
1289 },
1290 { }
1291 };
1293 static struct omap_hwmod_ocp_if am33xx_l3_main__mmc2 = {
1294 .master = &am33xx_l3_main_hwmod,
1295 .slave = &am33xx_mmc2_hwmod,
1296 .clk = "mmc2_ick",
1297 .addr = am33xx_mmc2_addr_space,
1298 .user = OCP_USER_MPU,
1299 };
1301 static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = {
1302 &am33xx_l3_main__mmc2,
1303 };
1305 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1306 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1307 };
1308 static struct omap_hwmod am33xx_mmc2_hwmod = {
1309 .name = "mmc3",
1310 .class = &am33xx_mmc_hwmod_class,
1311 .mpu_irqs = am33xx_mmc2_irqs,
1312 .sdma_reqs = am33xx_mmc2_edma_reqs,
1313 .main_clk = "mmc2_fck",
1314 .clkdm_name = "l3s_clkdm",
1315 .prcm = {
1316 .omap4 = {
1317 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1318 .modulemode = MODULEMODE_SWCTRL,
1319 },
1320 },
1321 .dev_attr = &am33xx_mmc2_dev_attr,
1322 .slaves = am33xx_mmc2_slaves,
1323 .slaves_cnt = ARRAY_SIZE(am33xx_mmc2_slaves),
1324 };
1326 /* Master interfaces on the MPU interconnect */
1327 static struct omap_hwmod_ocp_if *am33xx_l3_mpu_masters[] = {
1328 &am33xx_mpu__l3_slow,
1329 };
1331 /* mpu */
1332 static struct omap_hwmod am33xx_mpu_hwmod = {
1333 .name = "mpu",
1334 .class = &mpu_hwmod_class,
1335 .masters = am33xx_l3_mpu_masters,
1336 .masters_cnt = ARRAY_SIZE(am33xx_l3_mpu_masters),
1337 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1338 .main_clk = "mpu_fck",
1339 .clkdm_name = "mpu_clkdm",
1340 .prcm = {
1341 .omap4 = {
1342 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1343 .modulemode = MODULEMODE_SWCTRL,
1344 },
1345 },
1346 };
1348 /* 'ocmcram' class */
1349 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
1350 .name = "ocmcram",
1351 };
1353 /* ocmcram */
1354 static struct omap_hwmod am33xx_ocmcram_hwmod = {
1355 .name = "ocmcram",
1356 .class = &am33xx_ocmcram_hwmod_class,
1357 .main_clk = "ocmcram_fck",
1358 .clkdm_name = "l3_clkdm",
1359 .prcm = {
1360 .omap4 = {
1361 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
1362 .modulemode = MODULEMODE_SWCTRL,
1363 },
1364 },
1365 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1366 };
1368 /* 'ocpwp' class */
1369 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
1370 .name = "ocpwp",
1371 };
1373 /* ocpwp */
1374 static struct omap_hwmod am33xx_ocpwp_hwmod = {
1375 .name = "ocpwp",
1376 .class = &am33xx_ocpwp_hwmod_class,
1377 .main_clk = "ocpwp_fck",
1378 .clkdm_name = "l4ls_clkdm",
1379 .prcm = {
1380 .omap4 = {
1381 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
1382 .modulemode = MODULEMODE_SWCTRL,
1383 },
1384 },
1385 };
1387 /* 'rtc' class */
1388 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1389 .name = "rtc",
1390 };
1392 /* rtc */
1393 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1394 { .irq = AM33XX_IRQ_RTC_TIMER },
1395 { .irq = -1 }
1396 };
1398 static struct omap_hwmod am33xx_rtc_hwmod = {
1399 .name = "rtc",
1400 .class = &am33xx_rtc_hwmod_class,
1401 .mpu_irqs = am33xx_rtc_irqs,
1402 .main_clk = "rtc_fck",
1403 .clkdm_name = "l4_rtc_clkdm",
1404 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1405 .prcm = {
1406 .omap4 = {
1407 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1408 .modulemode = MODULEMODE_SWCTRL,
1409 },
1410 },
1411 };
1413 /* 'sha0' class */
1414 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
1415 .name = "sha0",
1416 };
1418 /* sha0 */
1419 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
1420 { .irq = AM33XX_IRQ_SHAEIP57t0_S },
1421 { .irq = -1 }
1422 };
1424 static struct omap_hwmod am33xx_sha0_hwmod = {
1425 .name = "sha0",
1426 .class = &am33xx_sha0_hwmod_class,
1427 .mpu_irqs = am33xx_sha0_irqs,
1428 .main_clk = "sha0_fck",
1429 .clkdm_name = "l3_clkdm",
1430 .prcm = {
1431 .omap4 = {
1432 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
1433 .modulemode = MODULEMODE_SWCTRL,
1434 },
1435 },
1436 };
1438 /* 'smartreflex' class */
1439 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
1440 .name = "smartreflex",
1441 };
1443 /* smartreflex0 */
1444 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
1445 { .irq = AM33XX_IRQ_SMARTREFLEX0 },
1446 { .irq = -1 }
1447 };
1449 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
1450 .name = "smartreflex0",
1451 .class = &am33xx_smartreflex_hwmod_class,
1452 .mpu_irqs = am33xx_smartreflex0_irqs,
1453 .main_clk = "smartreflex0_fck",
1454 .clkdm_name = "l4_wkup_clkdm",
1455 .prcm = {
1456 .omap4 = {
1457 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
1458 .modulemode = MODULEMODE_SWCTRL,
1459 },
1460 },
1461 };
1463 /* smartreflex1 */
1464 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
1465 { .irq = AM33XX_IRQ_SMARTREFLEX1 },
1466 { .irq = -1 }
1467 };
1469 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
1470 .name = "smartreflex1",
1471 .class = &am33xx_smartreflex_hwmod_class,
1472 .mpu_irqs = am33xx_smartreflex1_irqs,
1473 .main_clk = "smartreflex1_fck",
1474 .clkdm_name = "l4_wkup_clkdm",
1475 .prcm = {
1476 .omap4 = {
1477 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
1478 .modulemode = MODULEMODE_SWCTRL,
1479 },
1480 },
1481 };
1483 /* 'spi' class */
1485 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1486 .rev_offs = 0x0000,
1487 .sysc_offs = 0x0110,
1488 .syss_offs = 0x0114,
1489 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1490 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1491 SYSS_HAS_RESET_STATUS),
1492 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1493 .sysc_fields = &omap_hwmod_sysc_type1,
1494 };
1496 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1497 .name = "mcspi",
1498 .sysc = &am33xx_mcspi_sysc,
1499 .rev = OMAP4_MCSPI_REV,
1500 };
1502 /* spi0 */
1503 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1504 { .irq = AM33XX_IRQ_MCSPIOCP0 },
1505 { .irq = -1 }
1506 };
1508 struct omap_hwmod_dma_info am33xx_mcspi0_sdma_reqs[] = {
1509 { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0R },
1510 { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0W },
1511 { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1R },
1512 { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1W },
1513 { .dma_req = -1 }
1514 };
1516 struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
1517 {
1518 .pa_start = AM33XX_SPI0_BASE,
1519 .pa_end = AM33XX_SPI0_BASE + SZ_1K - 1,
1520 .flags = ADDR_TYPE_RT
1521 },
1522 { }
1523 };
1525 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = {
1526 .master = &am33xx_l4per_hwmod,
1527 .slave = &am33xx_spi0_hwmod,
1528 .clk = "spi0_ick",
1529 .addr = am33xx_mcspi0_addr_space,
1530 .user = OCP_USER_MPU,
1531 };
1533 static struct omap_hwmod_ocp_if *am33xx_mcspi0_slaves[] = {
1534 &am33xx_l4_core__mcspi0,
1535 };
1537 struct omap2_mcspi_dev_attr mcspi_attrib = {
1538 .num_chipselect = 2,
1539 };
1540 static struct omap_hwmod am33xx_spi0_hwmod = {
1541 .name = "spi0",
1542 .class = &am33xx_spi_hwmod_class,
1543 .mpu_irqs = am33xx_spi0_irqs,
1544 .sdma_reqs = am33xx_mcspi0_sdma_reqs,
1545 .main_clk = "spi0_fck",
1546 .clkdm_name = "l4ls_clkdm",
1547 .prcm = {
1548 .omap4 = {
1549 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1550 .modulemode = MODULEMODE_SWCTRL,
1551 },
1552 },
1553 .dev_attr = &mcspi_attrib,
1554 .slaves = am33xx_mcspi0_slaves,
1555 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi0_slaves),
1556 };
1558 /* spi1 */
1559 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1560 { .irq = AM33XX_IRQ_SPI1 },
1561 { .irq = -1 }
1562 };
1564 struct omap_hwmod_dma_info am33xx_mcspi1_sdma_reqs[] = {
1565 { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0R },
1566 { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0W },
1567 { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1R },
1568 { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1W },
1569 { .dma_req = -1 }
1570 };
1572 struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
1573 {
1574 .pa_start = AM33XX_SPI1_BASE,
1575 .pa_end = AM33XX_SPI1_BASE + SZ_1K - 1,
1576 .flags = ADDR_TYPE_RT
1577 },
1578 { }
1579 };
1581 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = {
1582 .master = &am33xx_l4per_hwmod,
1583 .slave = &am33xx_spi1_hwmod,
1584 .clk = "spi1_ick",
1585 .addr = am33xx_mcspi1_addr_space,
1586 .user = OCP_USER_MPU,
1587 };
1589 static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = {
1590 &am33xx_l4_core__mcspi1,
1591 };
1592 static struct omap_hwmod am33xx_spi1_hwmod = {
1593 .name = "spi1",
1594 .class = &am33xx_spi_hwmod_class,
1595 .mpu_irqs = am33xx_spi1_irqs,
1596 .sdma_reqs = am33xx_mcspi1_sdma_reqs,
1597 .main_clk = "spi1_fck",
1598 .clkdm_name = "l4ls_clkdm",
1599 .prcm = {
1600 .omap4 = {
1601 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1602 .modulemode = MODULEMODE_SWCTRL,
1603 },
1604 },
1605 .dev_attr = &mcspi_attrib,
1606 .slaves = am33xx_mcspi1_slaves,
1607 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi1_slaves),
1608 };
1610 /* 'spinlock' class */
1611 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1612 .name = "spinlock",
1613 };
1615 /* spinlock */
1616 static struct omap_hwmod am33xx_spinlock_hwmod = {
1617 .name = "spinlock",
1618 .class = &am33xx_spinlock_hwmod_class,
1619 .main_clk = "spinlock_fck",
1620 .clkdm_name = "l4ls_clkdm",
1621 .prcm = {
1622 .omap4 = {
1623 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1624 .modulemode = MODULEMODE_SWCTRL,
1625 },
1626 },
1627 };
1629 /* 'timer 0 & 2-7' class */
1630 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1631 .rev_offs = 0x0000,
1632 .sysc_offs = 0x0010,
1633 .syss_offs = 0x0014,
1634 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1635 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1636 SIDLE_SMART_WKUP),
1637 .sysc_fields = &omap_hwmod_sysc_type2,
1638 };
1640 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1641 .name = "timer",
1642 .sysc = &am33xx_timer_sysc,
1643 };
1645 /* timer0 */
1646 /* l4 wkup -> timer0 interface */
1647 static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = {
1648 {
1649 .pa_start = AM33XX_TIMER0_BASE,
1650 .pa_end = AM33XX_TIMER0_BASE + SZ_1K - 1,
1651 .flags = ADDR_TYPE_RT
1652 },
1653 { }
1654 };
1656 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = {
1657 .master = &am33xx_l4wkup_hwmod,
1658 .slave = &am33xx_timer0_hwmod,
1659 .clk = "timer0_ick",
1660 .addr = am33xx_timer0_addr_space,
1661 .user = OCP_USER_MPU,
1662 };
1664 static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = {
1665 &am33xx_l4wkup__timer0,
1666 };
1668 static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = {
1669 { .irq = AM33XX_IRQ_DMTIMER0 },
1670 { .irq = -1 }
1671 };
1673 static struct omap_hwmod am33xx_timer0_hwmod = {
1674 .name = "timer0",
1675 .class = &am33xx_timer_hwmod_class,
1676 .mpu_irqs = am33xx_timer0_irqs,
1677 .main_clk = "timer0_fck",
1678 .clkdm_name = "l4_wkup_clkdm",
1679 .prcm = {
1680 .omap4 = {
1681 .clkctrl_offs = AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET,
1682 .modulemode = MODULEMODE_SWCTRL,
1683 },
1684 },
1685 .slaves = am33xx_timer0_slaves,
1686 .slaves_cnt = ARRAY_SIZE(am33xx_timer0_slaves),
1687 };
1689 /* timer1 1ms */
1690 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1691 .rev_offs = 0x0000,
1692 .sysc_offs = 0x0010,
1693 .syss_offs = 0x0014,
1694 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1695 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1696 SYSS_HAS_RESET_STATUS),
1697 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1698 .sysc_fields = &omap_hwmod_sysc_type1,
1699 };
1701 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1702 .name = "timer",
1703 .sysc = &am33xx_timer1ms_sysc,
1704 };
1706 /* l4 wkup -> timer1 interface */
1707 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
1708 {
1709 .pa_start = AM33XX_TIMER1_BASE,
1710 .pa_end = AM33XX_TIMER1_BASE + SZ_1K - 1,
1711 .flags = ADDR_TYPE_RT
1712 },
1713 { }
1714 };
1716 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = {
1717 .master = &am33xx_l4wkup_hwmod,
1718 .slave = &am33xx_timer1_hwmod,
1719 .clk = "timer1_ick",
1720 .addr = am33xx_timer1_addr_space,
1721 .user = OCP_USER_MPU,
1722 };
1724 static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = {
1725 &am33xx_l4wkup__timer1,
1726 };
1728 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
1729 { .irq = AM33XX_IRQ_DMTIMER1 },
1730 { .irq = -1 }
1731 };
1733 static struct omap_hwmod am33xx_timer1_hwmod = {
1734 .name = "timer1",
1735 .class = &am33xx_timer1ms_hwmod_class,
1736 .mpu_irqs = am33xx_timer1_irqs,
1737 .main_clk = "timer1_fck",
1738 .clkdm_name = "l4_wkup_clkdm",
1739 .prcm = {
1740 .omap4 = {
1741 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1742 .modulemode = MODULEMODE_SWCTRL,
1743 },
1744 },
1745 .slaves = am33xx_timer1_slaves,
1746 .slaves_cnt = ARRAY_SIZE(am33xx_timer1_slaves),
1747 };
1749 /* timer2 */
1750 /* l4 per -> timer2 interface */
1751 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
1752 {
1753 .pa_start = AM33XX_TIMER2_BASE,
1754 .pa_end = AM33XX_TIMER2_BASE + SZ_1K - 1,
1755 .flags = ADDR_TYPE_RT
1756 },
1757 { }
1758 };
1760 static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = {
1761 .master = &am33xx_l4per_hwmod,
1762 .slave = &am33xx_timer2_hwmod,
1763 .clk = "timer2_ick",
1764 .addr = am33xx_timer2_addr_space,
1765 .user = OCP_USER_MPU,
1766 };
1768 static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = {
1769 &am33xx_l4per__timer2,
1770 };
1772 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
1773 { .irq = AM33XX_IRQ_DMTIMER2 },
1774 { .irq = -1 }
1775 };
1777 static struct omap_hwmod am33xx_timer2_hwmod = {
1778 .name = "timer2",
1779 .class = &am33xx_timer_hwmod_class,
1780 .mpu_irqs = am33xx_timer2_irqs,
1781 .main_clk = "timer2_fck",
1782 .prcm = {
1783 .omap4 = {
1784 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1785 .modulemode = MODULEMODE_SWCTRL,
1786 },
1787 },
1788 .slaves = am33xx_timer2_slaves,
1789 .slaves_cnt = ARRAY_SIZE(am33xx_timer2_slaves),
1790 .clkdm_name = "l4ls_clkdm",
1791 };
1793 /* timer3 */
1794 /* l4 per -> timer3 interface */
1795 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
1796 {
1797 .pa_start = AM33XX_TIMER3_BASE,
1798 .pa_end = AM33XX_TIMER3_BASE + SZ_1K - 1,
1799 .flags = ADDR_TYPE_RT
1800 },
1801 { }
1802 };
1804 static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = {
1805 .master = &am33xx_l4per_hwmod,
1806 .slave = &am33xx_timer3_hwmod,
1807 .clk = "timer3_ick",
1808 .addr = am33xx_timer3_addr_space,
1809 .user = OCP_USER_MPU,
1810 };
1812 static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = {
1813 &am33xx_l4per__timer3,
1814 };
1816 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
1817 { .irq = AM33XX_IRQ_DMTIMER3 },
1818 { .irq = -1 }
1819 };
1821 static struct omap_hwmod am33xx_timer3_hwmod = {
1822 .name = "timer3",
1823 .class = &am33xx_timer_hwmod_class,
1824 .mpu_irqs = am33xx_timer3_irqs,
1825 .main_clk = "timer3_fck",
1826 .clkdm_name = "l4ls_clkdm",
1827 .prcm = {
1828 .omap4 = {
1829 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1830 .modulemode = MODULEMODE_SWCTRL,
1831 },
1832 },
1833 .slaves = am33xx_timer3_slaves,
1834 .slaves_cnt = ARRAY_SIZE(am33xx_timer3_slaves),
1835 };
1837 /* timer4 */
1838 /* l4 per -> timer4 interface */
1839 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
1840 {
1841 .pa_start = AM33XX_TIMER4_BASE,
1842 .pa_end = AM33XX_TIMER4_BASE + SZ_1K - 1,
1843 .flags = ADDR_TYPE_RT
1844 },
1845 { }
1846 };
1848 static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = {
1849 .master = &am33xx_l4per_hwmod,
1850 .slave = &am33xx_timer4_hwmod,
1851 .clk = "timer4_ick",
1852 .addr = am33xx_timer4_addr_space,
1853 .user = OCP_USER_MPU,
1854 };
1856 static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = {
1857 &am33xx_l4per__timer4,
1858 };
1860 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
1861 { .irq = AM33XX_IRQ_DMTIMER4 },
1862 { .irq = -1 }
1863 };
1865 static struct omap_hwmod am33xx_timer4_hwmod = {
1866 .name = "timer4",
1867 .class = &am33xx_timer_hwmod_class,
1868 .mpu_irqs = am33xx_timer4_irqs,
1869 .main_clk = "timer4_fck",
1870 .prcm = {
1871 .omap4 = {
1872 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1873 .modulemode = MODULEMODE_SWCTRL,
1874 },
1875 },
1876 .slaves = am33xx_timer4_slaves,
1877 .slaves_cnt = ARRAY_SIZE(am33xx_timer4_slaves),
1878 .clkdm_name = "l4ls_clkdm",
1879 };
1882 /* timer5 */
1883 /* l4 per -> timer5 interface */
1884 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
1885 {
1886 .pa_start = AM33XX_TIMER5_BASE,
1887 .pa_end = AM33XX_TIMER5_BASE + SZ_1K - 1,
1888 .flags = ADDR_TYPE_RT
1889 },
1890 { }
1891 };
1893 static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = {
1894 .master = &am33xx_l4per_hwmod,
1895 .slave = &am33xx_timer5_hwmod,
1896 .clk = "timer5_ick",
1897 .addr = am33xx_timer5_addr_space,
1898 .user = OCP_USER_MPU,
1899 };
1901 static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = {
1902 &am33xx_l4per__timer5,
1903 };
1905 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
1906 { .irq = AM33XX_IRQ_DMTIMER5 },
1907 { .irq = -1 }
1908 };
1910 static struct omap_hwmod am33xx_timer5_hwmod = {
1911 .name = "timer5",
1912 .class = &am33xx_timer_hwmod_class,
1913 .mpu_irqs = am33xx_timer5_irqs,
1914 .main_clk = "timer5_fck",
1915 .prcm = {
1916 .omap4 = {
1917 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1918 .modulemode = MODULEMODE_SWCTRL,
1919 },
1920 },
1921 .slaves = am33xx_timer5_slaves,
1922 .slaves_cnt = ARRAY_SIZE(am33xx_timer5_slaves),
1923 .clkdm_name = "l4ls_clkdm",
1924 };
1926 /* timer6 */
1927 /* l4 per -> timer6 interface */
1928 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
1929 {
1930 .pa_start = AM33XX_TIMER6_BASE,
1931 .pa_end = AM33XX_TIMER6_BASE + SZ_1K - 1,
1932 .flags = ADDR_TYPE_RT
1933 },
1934 { }
1935 };
1937 static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = {
1938 .master = &am33xx_l4per_hwmod,
1939 .slave = &am33xx_timer6_hwmod,
1940 .clk = "timer6_ick",
1941 .addr = am33xx_timer6_addr_space,
1942 .user = OCP_USER_MPU,
1943 };
1945 static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = {
1946 &am33xx_l4per__timer6,
1947 };
1949 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
1950 { .irq = AM33XX_IRQ_DMTIMER6 },
1951 { .irq = -1 }
1952 };
1954 static struct omap_hwmod am33xx_timer6_hwmod = {
1955 .name = "timer6",
1956 .class = &am33xx_timer_hwmod_class,
1957 .mpu_irqs = am33xx_timer6_irqs,
1958 .main_clk = "timer6_fck",
1959 .prcm = {
1960 .omap4 = {
1961 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
1962 .modulemode = MODULEMODE_SWCTRL,
1963 },
1964 },
1965 .slaves = am33xx_timer6_slaves,
1966 .slaves_cnt = ARRAY_SIZE(am33xx_timer6_slaves),
1967 .clkdm_name = "l4ls_clkdm",
1968 };
1970 /* timer7 */
1971 /* l4 per -> timer7 interface */
1972 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
1973 {
1974 .pa_start = AM33XX_TIMER7_BASE,
1975 .pa_end = AM33XX_TIMER7_BASE + SZ_1K - 1,
1976 .flags = ADDR_TYPE_RT
1977 },
1978 { }
1979 };
1981 static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = {
1982 .master = &am33xx_l4per_hwmod,
1983 .slave = &am33xx_timer7_hwmod,
1984 .clk = "timer7_ick",
1985 .addr = am33xx_timer7_addr_space,
1986 .user = OCP_USER_MPU,
1987 };
1989 static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = {
1990 &am33xx_l4per__timer7,
1991 };
1993 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
1994 { .irq = AM33XX_IRQ_DMTIMER7 },
1995 { .irq = -1 }
1996 };
1998 static struct omap_hwmod am33xx_timer7_hwmod = {
1999 .name = "timer7",
2000 .class = &am33xx_timer_hwmod_class,
2001 .mpu_irqs = am33xx_timer7_irqs,
2002 .main_clk = "timer7_fck",
2003 .prcm = {
2004 .omap4 = {
2005 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
2006 .modulemode = MODULEMODE_SWCTRL,
2007 },
2008 },
2009 .slaves = am33xx_timer7_slaves,
2010 .slaves_cnt = ARRAY_SIZE(am33xx_timer7_slaves),
2011 .clkdm_name = "l4ls_clkdm",
2012 };
2014 /* 'tpcc' class */
2015 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
2016 .name = "tpcc",
2017 };
2019 /* tpcc */
2020 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
2021 { .name = "edma0", .irq = AM33XX_IRQ_TPCC0_INT_PO0 },
2022 { .name = "edma0_err", .irq = AM33XX_IRQ_TPCC0_ERRINT_PO },
2023 { .irq = -1 },
2024 };
2026 /* TODO move this appropriate header. */
2027 #define AM33XX_TPCC_BASE 0x49000000
2029 static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
2030 {
2031 .pa_start = AM33XX_TPCC_BASE,
2032 .pa_end = AM33XX_TPCC_BASE + SZ_32K - 1,
2033 .flags = ADDR_TYPE_RT
2034 },
2035 { }
2036 };
2038 static struct omap_hwmod_ocp_if am33xx_l3_slow__tpcc = {
2039 .master = &am33xx_l3slow_hwmod,
2040 .slave = &am33xx_tpcc_hwmod,
2041 .addr = am33xx_tpcc_addr_space,
2042 .user = OCP_USER_MPU,
2043 };
2045 static struct omap_hwmod_ocp_if *am33xx_tpcc_slaves[] = {
2046 &am33xx_l3_slow__tpcc,
2047 };
2049 static struct omap_hwmod am33xx_tpcc_hwmod = {
2050 .name = "tpcc",
2051 .class = &am33xx_tpcc_hwmod_class,
2052 .mpu_irqs = am33xx_tpcc_irqs,
2053 .main_clk = "tpcc_ick",
2054 .clkdm_name = "l3_clkdm",
2055 .prcm = {
2056 .omap4 = {
2057 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
2058 .modulemode = MODULEMODE_SWCTRL,
2059 },
2060 },
2061 .slaves = am33xx_tpcc_slaves,
2062 .slaves_cnt = ARRAY_SIZE(am33xx_tpcc_slaves),
2063 };
2065 /* 'tptc' class */
2066 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
2067 .name = "tptc",
2068 };
2070 /* tptc0 */
2071 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
2072 { .irq = AM33XX_IRQ_TPTC0 },
2073 { .irq = -1 }
2074 };
2076 static struct omap_hwmod am33xx_tptc0_hwmod = {
2077 .name = "tptc0",
2078 .class = &am33xx_tptc_hwmod_class,
2079 .mpu_irqs = am33xx_tptc0_irqs,
2080 .main_clk = "tptc0_ick",
2081 .clkdm_name = "l3_clkdm",
2082 .prcm = {
2083 .omap4 = {
2084 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
2085 .modulemode = MODULEMODE_SWCTRL,
2086 },
2087 },
2088 };
2090 /* tptc1 */
2091 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
2092 { .irq = AM33XX_IRQ_TPTC1 },
2093 { .irq = -1 }
2094 };
2096 static struct omap_hwmod am33xx_tptc1_hwmod = {
2097 .name = "tptc1",
2098 .class = &am33xx_tptc_hwmod_class,
2099 .mpu_irqs = am33xx_tptc1_irqs,
2100 .main_clk = "tptc1_ick",
2101 .clkdm_name = "l3_clkdm",
2102 .prcm = {
2103 .omap4 = {
2104 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
2105 .modulemode = MODULEMODE_SWCTRL,
2106 },
2107 },
2108 };
2110 /* tptc2 */
2111 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
2112 { .irq = AM33XX_IRQ_TPTC2 },
2113 { .irq = -1 }
2114 };
2116 static struct omap_hwmod am33xx_tptc2_hwmod = {
2117 .name = "tptc2",
2118 .class = &am33xx_tptc_hwmod_class,
2119 .mpu_irqs = am33xx_tptc2_irqs,
2120 .main_clk = "tptc2_ick",
2121 .clkdm_name = "l3_clkdm",
2122 .prcm = {
2123 .omap4 = {
2124 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
2125 .modulemode = MODULEMODE_SWCTRL,
2126 },
2127 },
2128 };
2130 /* 'uart' class */
2131 static struct omap_hwmod_class_sysconfig uart_sysc = {
2132 .rev_offs = 0x50,
2133 .sysc_offs = 0x54,
2134 .syss_offs = 0x58,
2135 .sysc_flags = (SYSC_HAS_SIDLEMODE |
2136 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2137 SYSC_HAS_AUTOIDLE),
2138 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2139 .sysc_fields = &omap_hwmod_sysc_type1,
2140 };
2142 static struct omap_hwmod_class uart_class = {
2143 .name = "uart",
2144 .sysc = &uart_sysc,
2145 };
2147 /* uart1 */
2148 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
2149 { .name = "tx", .dma_req = 26, },
2150 { .name = "rx", .dma_req = 27, },
2151 { .dma_req = -1 }
2152 };
2154 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
2155 {
2156 .pa_start = AM33XX_UART1_BASE,
2157 .pa_end = AM33XX_UART1_BASE + SZ_8K - 1,
2158 .flags = ADDR_TYPE_RT
2159 },
2160 { }
2161 };
2163 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
2164 .master = &am33xx_l4wkup_hwmod,
2165 .slave = &am33xx_uart1_hwmod,
2166 .clk = "uart1_ick",
2167 .addr = am33xx_uart1_addr_space,
2168 .user = OCP_USER_MPU,
2169 };
2171 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
2172 { .irq = AM33XX_IRQ_UART0 },
2173 { .irq = -1 }
2174 };
2176 static struct omap_hwmod_ocp_if *am33xx_uart1_slaves[] = {
2177 &am33xx_l4_wkup__uart1,
2178 };
2180 static struct omap_hwmod am33xx_uart1_hwmod = {
2181 .name = "uart1",
2182 .class = &uart_class,
2183 .mpu_irqs = am33xx_uart1_irqs,
2184 .sdma_reqs = uart1_edma_reqs,
2185 .main_clk = "uart1_fck",
2186 .clkdm_name = "l4_wkup_clkdm",
2187 .prcm = {
2188 .omap4 = {
2189 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
2190 .modulemode = MODULEMODE_SWCTRL,
2191 },
2192 },
2193 .slaves = am33xx_uart1_slaves,
2194 .slaves_cnt = ARRAY_SIZE(am33xx_uart1_slaves),
2195 };
2197 /* uart2 */
2198 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
2199 {
2200 .pa_start = AM33XX_UART2_BASE,
2201 .pa_end = AM33XX_UART2_BASE + SZ_8K - 1,
2202 .flags = ADDR_TYPE_RT
2203 },
2204 { }
2205 };
2207 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
2208 .slave = &am33xx_uart2_hwmod,
2209 .clk = "uart2_ick",
2210 .addr = am33xx_uart2_addr_space,
2211 .user = OCP_USER_MPU,
2212 };
2214 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
2215 { .irq = AM33XX_IRQ_UART1 },
2216 { .irq = -1 }
2217 };
2219 static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = {
2220 &am33xx_l4_ls__uart2,
2221 };
2223 static struct omap_hwmod am33xx_uart2_hwmod = {
2224 .name = "uart2",
2225 .class = &uart_class,
2226 .mpu_irqs = am33xx_uart2_irqs,
2227 .main_clk = "uart2_fck",
2228 .clkdm_name = "l4ls_clkdm",
2229 .sdma_reqs = uart1_edma_reqs,
2230 .prcm = {
2231 .omap4 = {
2232 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
2233 .modulemode = MODULEMODE_SWCTRL,
2234 },
2235 },
2236 .slaves = am33xx_uart2_slaves,
2237 .slaves_cnt = ARRAY_SIZE(am33xx_uart2_slaves),
2238 };
2240 /* uart3 */
2241 static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
2242 { .name = "tx", .dma_req = 30, },
2243 { .name = "rx", .dma_req = 31, },
2244 { .dma_req = -1 }
2245 };
2247 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
2248 {
2249 .pa_start = AM33XX_UART3_BASE,
2250 .pa_end = AM33XX_UART3_BASE + SZ_8K - 1,
2251 .flags = ADDR_TYPE_RT
2252 },
2253 { }
2254 };
2256 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
2257 .slave = &am33xx_uart3_hwmod,
2258 .clk = "uart3_ick",
2259 .addr = am33xx_uart3_addr_space,
2260 .user = OCP_USER_MPU,
2261 };
2263 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2264 { .irq = AM33XX_IRQ_UART2 },
2265 { .irq = -1 }
2266 };
2268 static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = {
2269 &am33xx_l4_ls__uart3,
2270 };
2272 static struct omap_hwmod am33xx_uart3_hwmod = {
2273 .name = "uart3",
2274 .class = &uart_class,
2275 .mpu_irqs = am33xx_uart3_irqs,
2276 .main_clk = "uart3_fck",
2277 .clkdm_name = "l4ls_clkdm",
2278 .sdma_reqs = uart3_edma_reqs,
2279 .prcm = {
2280 .omap4 = {
2281 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
2282 .modulemode = MODULEMODE_SWCTRL,
2283 },
2284 },
2285 .slaves = am33xx_uart3_slaves,
2286 .slaves_cnt = ARRAY_SIZE(am33xx_uart3_slaves),
2287 };
2289 /* uart4 */
2290 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
2291 {
2292 .pa_start = AM33XX_UART4_BASE,
2293 .pa_end = AM33XX_UART4_BASE + SZ_8K - 1,
2294 .flags = ADDR_TYPE_RT
2295 },
2296 { }
2297 };
2299 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
2300 .slave = &am33xx_uart4_hwmod,
2301 .clk = "uart4_ick",
2302 .addr = am33xx_uart4_addr_space,
2303 .user = OCP_USER_MPU,
2304 };
2306 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2307 { .irq = AM33XX_IRQ_UART3 },
2308 { .irq = -1 }
2309 };
2311 static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = {
2312 &am33xx_l4_ls__uart4,
2313 };
2315 static struct omap_hwmod am33xx_uart4_hwmod = {
2316 .name = "uart4",
2317 .class = &uart_class,
2318 .mpu_irqs = am33xx_uart4_irqs,
2319 .main_clk = "uart4_fck",
2320 .clkdm_name = "l4ls_clkdm",
2321 .sdma_reqs = uart1_edma_reqs,
2322 .prcm = {
2323 .omap4 = {
2324 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
2325 .modulemode = MODULEMODE_SWCTRL,
2326 },
2327 },
2328 .slaves = am33xx_uart4_slaves,
2329 .slaves_cnt = ARRAY_SIZE(am33xx_uart4_slaves),
2330 };
2332 /* uart5 */
2333 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
2334 {
2335 .pa_start = AM33XX_UART5_BASE,
2336 .pa_end = AM33XX_UART5_BASE + SZ_8K - 1,
2337 .flags = ADDR_TYPE_RT
2338 },
2339 { }
2340 };
2342 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
2343 .slave = &am33xx_uart5_hwmod,
2344 .clk = "uart5_ick",
2345 .addr = am33xx_uart5_addr_space,
2346 .user = OCP_USER_MPU,
2347 };
2349 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2350 { .irq = AM33XX_IRQ_UART4 },
2351 { .irq = -1 }
2352 };
2354 static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = {
2355 &am33xx_l4_ls__uart5,
2356 };
2358 static struct omap_hwmod am33xx_uart5_hwmod = {
2359 .name = "uart5",
2360 .class = &uart_class,
2361 .mpu_irqs = am33xx_uart5_irqs,
2362 .main_clk = "uart5_fck",
2363 .clkdm_name = "l4ls_clkdm",
2364 .sdma_reqs = uart1_edma_reqs,
2365 .prcm = {
2366 .omap4 = {
2367 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2368 .modulemode = MODULEMODE_SWCTRL,
2369 },
2370 },
2371 .slaves = am33xx_uart5_slaves,
2372 .slaves_cnt = ARRAY_SIZE(am33xx_uart5_slaves),
2373 };
2375 /* uart6 */
2376 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
2377 {
2378 .pa_start = AM33XX_UART6_BASE,
2379 .pa_end = AM33XX_UART6_BASE + SZ_8K - 1,
2380 .flags = ADDR_TYPE_RT
2381 },
2382 { }
2383 };
2385 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
2386 .slave = &am33xx_uart6_hwmod,
2387 .clk = "uart6_ick",
2388 .addr = am33xx_uart6_addr_space,
2389 .user = OCP_USER_MPU,
2390 };
2392 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2393 { .irq = AM33XX_IRQ_UART5 },
2394 { .irq = -1 }
2395 };
2397 static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = {
2398 &am33xx_l4_ls__uart6,
2399 };
2401 static struct omap_hwmod am33xx_uart6_hwmod = {
2402 .name = "uart6",
2403 .class = &uart_class,
2404 .mpu_irqs = am33xx_uart6_irqs,
2405 .main_clk = "uart6_fck",
2406 .clkdm_name = "l4ls_clkdm",
2407 .sdma_reqs = uart1_edma_reqs,
2408 .prcm = {
2409 .omap4 = {
2410 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2411 .modulemode = MODULEMODE_SWCTRL,
2412 },
2413 },
2414 .slaves = am33xx_uart6_slaves,
2415 .slaves_cnt = ARRAY_SIZE(am33xx_uart6_slaves),
2416 };
2418 /* 'wd_timer' class */
2419 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2420 .name = "wd_timer",
2421 };
2423 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
2424 {
2425 .pa_start = AM33XX_WDT1_BASE,
2426 .pa_end = AM33XX_WDT1_BASE + SZ_4K - 1,
2427 .flags = ADDR_TYPE_RT
2428 },
2429 { }
2430 };
2432 /* l4_wkup -> wd_timer1 */
2433 static struct omap_hwmod_ocp_if am33xx_l4wkup__wd_timer1 = {
2434 .master = &am33xx_l4wkup_hwmod,
2435 .slave = &am33xx_wd_timer1_hwmod,
2436 .addr = am33xx_wd_timer1_addrs,
2437 .user = OCP_USER_MPU,
2438 };
2440 /* wd_timer1 slave ports */
2441 static struct omap_hwmod_ocp_if *am33xx_wd_timer1_slaves[] = {
2442 &am33xx_l4wkup__wd_timer1,
2443 };
2445 /* wd_timer1 */
2446 /*
2447 * TODO: device.c file uses hardcoded name for watchdog
2448 timer driver "wd_timer2, so we are also using
2449 same name as of now...
2450 */
2451 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2452 .name = "wd_timer2",
2453 .class = &am33xx_wd_timer_hwmod_class,
2454 .main_clk = "wd_timer1_fck",
2455 .clkdm_name = "l4_wkup_clkdm",
2456 .prcm = {
2457 .omap4 = {
2458 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2459 .modulemode = MODULEMODE_SWCTRL,
2460 },
2461 },
2462 .slaves = am33xx_wd_timer1_slaves,
2463 .slaves_cnt = ARRAY_SIZE(am33xx_wd_timer1_slaves),
2464 };
2466 /* wdt0 */
2467 static struct omap_hwmod_irq_info am33xx_wdt0_irqs[] = {
2468 { .irq = AM33XX_IRQ_WDT0 },
2469 { .irq = -1 },
2470 };
2472 static struct omap_hwmod am33xx_wdt0_hwmod = {
2473 .name = "wdt0",
2474 .class = &am33xx_wd_timer_hwmod_class,
2475 .mpu_irqs = am33xx_wdt0_irqs,
2476 .main_clk = "wdt0_fck",
2477 .clkdm_name = "l4_wkup_clkdm",
2478 .prcm = {
2479 .omap4 = {
2480 .clkctrl_offs = AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET,
2481 .modulemode = MODULEMODE_SWCTRL,
2482 },
2483 },
2484 };
2486 /* 'wkup_m3' class */
2487 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
2488 .name = "wkup_m3",
2489 };
2491 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
2492 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
2493 };
2495 /* wkup_m3 */
2496 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
2497 .name = "wkup_m3",
2498 .class = &am33xx_wkup_m3_hwmod_class,
2499 .clkdm_name = "l4_wkup_aon_clkdm",
2500 .main_clk = "wkup_m3_fck",
2501 .rst_lines = am33xx_wkup_m3_resets,
2502 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
2503 .prcm = {
2504 .omap4 = {
2505 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
2506 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
2507 .modulemode = MODULEMODE_SWCTRL,
2508 },
2509 },
2510 .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */
2511 };
2513 /* L3 SLOW -> USBSS interface */
2514 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
2515 {
2516 .name = "usbss",
2517 .pa_start = AM33XX_USBSS_BASE,
2518 .pa_end = AM33XX_USBSS_BASE + SZ_4K - 1,
2519 .flags = ADDR_TYPE_RT
2520 },
2521 {
2522 .name = "musb0",
2523 .pa_start = AM33XX_USB0_BASE,
2524 .pa_end = AM33XX_USB0_BASE + SZ_2K - 1,
2525 .flags = ADDR_TYPE_RT
2526 },
2527 {
2528 .name = "musb1",
2529 .pa_start = AM33XX_USB1_BASE,
2530 .pa_end = AM33XX_USB1_BASE + SZ_2K - 1,
2531 .flags = ADDR_TYPE_RT
2532 },
2533 { }
2534 };
2536 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2537 .rev_offs = 0x0,
2538 .sysc_offs = 0x10,
2539 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2540 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2541 .sysc_fields = &omap_hwmod_sysc_type1,
2542 };
2544 static struct omap_hwmod_class am33xx_usbotg_class = {
2545 .name = "usbotg",
2546 .sysc = &am33xx_usbhsotg_sysc,
2547 };
2549 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2550 { .name = "usbss-irq", .irq = AM33XX_IRQ_USBSS, },
2551 { .name = "musb0-irq", .irq = AM33XX_IRQ_USB0, },
2552 { .name = "musb1-irq", .irq = AM33XX_IRQ_USB1, },
2553 { .irq = -1, },
2554 };
2556 static struct omap_hwmod_ocp_if am33xx_l3_slow__usbss = {
2557 .master = &am33xx_l3slow_hwmod,
2558 .slave = &am33xx_usbss_hwmod,
2559 .addr = am33xx_usbss_addr_space,
2560 .user = OCP_USER_MPU,
2561 .flags = OCPIF_SWSUP_IDLE,
2562 };
2564 static struct omap_hwmod_ocp_if *am33xx_usbss_slaves[] = {
2565 &am33xx_l3_slow__usbss,
2566 };
2568 static struct omap_hwmod_opt_clk usbss_opt_clks[] = {
2569 { .role = "clkdcoldo", .clk = "usbotg_fck" },
2570 };
2572 static struct omap_hwmod am33xx_usbss_hwmod = {
2573 .name = "usb_otg_hs",
2574 .mpu_irqs = am33xx_usbss_mpu_irqs,
2575 .main_clk = "usbotg_ick",
2576 .clkdm_name = "l4ls_clkdm",
2577 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2578 .prcm = {
2579 .omap4 = {
2580 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2581 .modulemode = MODULEMODE_SWCTRL,
2582 },
2583 },
2584 .opt_clks = usbss_opt_clks,
2585 .opt_clks_cnt = ARRAY_SIZE(usbss_opt_clks),
2586 .slaves = am33xx_usbss_slaves,
2587 .slaves_cnt = ARRAY_SIZE(am33xx_usbss_slaves),
2588 .class = &am33xx_usbotg_class,
2589 };
2591 static __initdata struct omap_hwmod *am33xx_hwmods[] = {
2592 /* l3 class */
2593 &am33xx_l3_instr_hwmod,
2594 &am33xx_l3_main_hwmod,
2595 /* l3s class */
2596 &am33xx_l3slow_hwmod,
2597 /* l4hs class */
2598 &am33xx_l4_hs_hwmod,
2599 /* l4fw class */
2600 &am33xx_l4fw_hwmod,
2601 /* l4ls class */
2602 &am33xx_l4ls_hwmod,
2603 /* l4per class */
2604 &am33xx_l4per_hwmod,
2605 /* l4wkup class */
2606 &am33xx_l4wkup_hwmod,
2608 /* clkdiv32k class */
2609 &am33xx_clkdiv32k_hwmod,
2610 /* mpu class */
2611 &am33xx_mpu_hwmod,
2612 /* adc_tsc class */
2613 &am33xx_adc_tsc_hwmod,
2614 /* aes class */
2615 &am33xx_aes0_hwmod,
2616 /* cefuse class */
2617 &am33xx_cefuse_hwmod,
2618 /* control class */
2619 &am33xx_control_hwmod,
2620 /* dcan class */
2621 &am33xx_dcan0_hwmod,
2622 &am33xx_dcan1_hwmod,
2623 /* debugss class */
2624 &am33xx_debugss_hwmod,
2625 /* elm class */
2626 &am33xx_elm_hwmod,
2627 /* emif_fw class */
2628 &am33xx_emif_fw_hwmod,
2629 /* epwmss class */
2630 &am33xx_epwmss0_hwmod,
2631 &am33xx_epwmss1_hwmod,
2632 &am33xx_epwmss2_hwmod,
2633 /* gpio class */
2634 &am33xx_gpio0_hwmod,
2635 &am33xx_gpio1_hwmod,
2636 &am33xx_gpio2_hwmod,
2637 &am33xx_gpio3_hwmod,
2638 /* gpmc class */
2639 &am33xx_gpmc_hwmod,
2640 /* i2c class */
2641 &am33xx_i2c1_hwmod,
2642 &am33xx_i2c2_hwmod,
2643 /* icss class */
2644 &am33xx_icss_hwmod,
2645 /* ieee5000 class */
2646 &am33xx_ieee5000_hwmod,
2647 /* mailbox class */
2648 &am33xx_mailbox_hwmod,
2649 /* mcasp class */
2650 &am33xx_mcasp0_hwmod,
2651 /* mmc class */
2652 &am33xx_mmc0_hwmod,
2653 &am33xx_mmc1_hwmod,
2654 &am33xx_mmc2_hwmod,
2655 /* ocmcram class */
2656 &am33xx_ocmcram_hwmod,
2657 /* ocpwp class */
2658 &am33xx_ocpwp_hwmod,
2659 /* sha0 class */
2660 &am33xx_sha0_hwmod,
2661 /* smartreflex class */
2662 &am33xx_smartreflex0_hwmod,
2663 &am33xx_smartreflex1_hwmod,
2664 /* spi class */
2665 &am33xx_spi0_hwmod,
2666 &am33xx_spi1_hwmod,
2667 /* spinlock class */
2668 &am33xx_spinlock_hwmod,
2669 /* uart class */
2670 &am33xx_uart1_hwmod,
2671 &am33xx_uart2_hwmod,
2672 &am33xx_uart3_hwmod,
2673 &am33xx_uart4_hwmod,
2674 &am33xx_uart5_hwmod,
2675 &am33xx_uart6_hwmod,
2676 /* timer class */
2677 &am33xx_timer0_hwmod,
2678 &am33xx_timer1_hwmod,
2679 &am33xx_timer2_hwmod,
2680 &am33xx_timer3_hwmod,
2681 &am33xx_timer4_hwmod,
2682 &am33xx_timer5_hwmod,
2683 &am33xx_timer6_hwmod,
2684 &am33xx_timer7_hwmod,
2685 /* wkup_m3 class */
2686 &am33xx_wkup_m3_hwmod,
2687 /* wd_timer class */
2688 &am33xx_wd_timer1_hwmod,
2689 /* usbss hwmod */
2690 &am33xx_usbss_hwmod,
2691 /* cpgmac0 class */
2692 &am33xx_cpgmac0_hwmod,
2693 &am33xx_wdt0_hwmod, /* Secure WDT */
2694 /* tptc class */
2695 &am33xx_tptc0_hwmod,
2696 &am33xx_tptc1_hwmod,
2697 &am33xx_tptc2_hwmod,
2698 /* tpcc class */
2699 &am33xx_tpcc_hwmod,
2700 /* LCDC class */
2701 &am33xx_lcdc_hwmod,
2702 /* rtc */
2703 &am33xx_rtc_hwmod,
2704 NULL,
2705 };
2707 int __init am33xx_hwmod_init(void)
2708 {
2709 return omap_hwmod_register(am33xx_hwmods);
2710 }