1 /*
2 * Hardware modules present on the AM33XX chips
3 *
4 * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
17 #include <linux/io.h>
19 #include <plat/omap_hwmod.h>
20 #include <plat/i2c.h>
21 #include <plat/cpu.h>
22 #include <plat/gpio.h>
23 #include <plat/dma.h>
24 #include <plat/mmc.h>
25 #include <plat/mcspi.h>
27 #include "omap_hwmod_common_data.h"
28 #include "control.h"
29 #include "cm33xx.h"
30 #include "prm33xx.h"
32 /* Backward references (IPs with Bus Master capability) */
33 static struct omap_hwmod am33xx_mpu_hwmod;
34 static struct omap_hwmod am33xx_l3_main_hwmod;
35 static struct omap_hwmod am33xx_l3slow_hwmod;
36 static struct omap_hwmod am33xx_l4wkup_hwmod;
37 static struct omap_hwmod am33xx_l4per_hwmod;
38 static struct omap_hwmod am33xx_uart1_hwmod;
39 static struct omap_hwmod am33xx_uart2_hwmod;
40 static struct omap_hwmod am33xx_uart3_hwmod;
41 static struct omap_hwmod am33xx_uart4_hwmod;
42 static struct omap_hwmod am33xx_uart5_hwmod;
43 static struct omap_hwmod am33xx_uart6_hwmod;
44 static struct omap_hwmod am33xx_timer0_hwmod;
45 static struct omap_hwmod am33xx_timer1_hwmod;
46 static struct omap_hwmod am33xx_timer2_hwmod;
47 static struct omap_hwmod am33xx_timer3_hwmod;
48 static struct omap_hwmod am33xx_timer4_hwmod;
49 static struct omap_hwmod am33xx_timer5_hwmod;
50 static struct omap_hwmod am33xx_timer6_hwmod;
51 static struct omap_hwmod am33xx_timer7_hwmod;
52 static struct omap_hwmod am33xx_wd_timer1_hwmod;
53 static struct omap_hwmod am33xx_cpgmac0_hwmod;
54 static struct omap_hwmod am33xx_icss_hwmod;
55 static struct omap_hwmod am33xx_ieee5000_hwmod;
56 static struct omap_hwmod am33xx_tptc0_hwmod;
57 static struct omap_hwmod am33xx_tptc1_hwmod;
58 static struct omap_hwmod am33xx_tptc2_hwmod;
59 static struct omap_hwmod am33xx_gpio0_hwmod;
60 static struct omap_hwmod am33xx_gpio1_hwmod;
61 static struct omap_hwmod am33xx_gpio2_hwmod;
62 static struct omap_hwmod am33xx_gpio3_hwmod;
63 static struct omap_hwmod am33xx_i2c1_hwmod;
64 static struct omap_hwmod am33xx_i2c2_hwmod;
65 static struct omap_hwmod am33xx_i2c3_hwmod;
66 static struct omap_hwmod am33xx_usbss_hwmod;
67 static struct omap_hwmod am33xx_mmc0_hwmod;
68 static struct omap_hwmod am33xx_mmc1_hwmod;
69 static struct omap_hwmod am33xx_mmc2_hwmod;
70 static struct omap_hwmod am33xx_spi0_hwmod;
71 static struct omap_hwmod am33xx_spi1_hwmod;
72 static struct omap_hwmod am33xx_elm_hwmod;
73 static struct omap_hwmod am33xx_adc_tsc_hwmod;
74 static struct omap_hwmod am33xx_tpcc_hwmod;
75 static struct omap_hwmod am33xx_mcasp0_hwmod;
76 static struct omap_hwmod am33xx_mcasp1_hwmod;
77 static struct omap_hwmod am33xx_epwmss0_hwmod;
78 static struct omap_hwmod am33xx_epwmss1_hwmod;
79 static struct omap_hwmod am33xx_epwmss2_hwmod;
80 static struct omap_hwmod am33xx_gpmc_hwmod;
81 static struct omap_hwmod am33xx_lcdc_hwmod;
83 /*
84 * Interconnects hwmod structures
85 * hwmods that compose the global AM33XX OCP interconnect
86 */
88 /* MPU -> L3_SLOW Peripheral interface */
89 static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = {
90 .master = &am33xx_mpu_hwmod,
91 .slave = &am33xx_l3slow_hwmod,
92 .user = OCP_USER_MPU,
93 };
95 /* L3 SLOW -> L4_PER Peripheral interface */
96 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = {
97 .master = &am33xx_l3slow_hwmod,
98 .slave = &am33xx_l4per_hwmod,
99 .user = OCP_USER_MPU,
100 };
102 /* L3 SLOW -> L4_WKUP Peripheral interface */
103 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = {
104 .master = &am33xx_l3slow_hwmod,
105 .slave = &am33xx_l4wkup_hwmod,
106 .user = OCP_USER_MPU,
107 };
109 /* Master interfaces on the L4_WKUP interconnect */
110 static struct omap_hwmod_ocp_if *am33xx_l3_slow_masters[] = {
111 &am33xx_l3_slow__l4_per,
112 &am33xx_l3_slow__l4_wkup,
113 };
115 /* Slave interfaces on the L3_SLOW interconnect */
116 static struct omap_hwmod_ocp_if *am33xx_l3_slow_slaves[] = {
117 &am33xx_mpu__l3_slow,
118 };
120 static struct omap_hwmod am33xx_l3slow_hwmod = {
121 .name = "l3_slow",
122 .class = &l3_hwmod_class,
123 .clkdm_name = "l3s_clkdm",
124 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
125 .masters = am33xx_l3_slow_masters,
126 .masters_cnt = ARRAY_SIZE(am33xx_l3_slow_masters),
127 .slaves = am33xx_l3_slow_slaves,
128 .slaves_cnt = ARRAY_SIZE(am33xx_l3_slow_slaves),
129 };
131 /* L4 PER -> GPIO2 */
132 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
133 {
134 .pa_start = AM33XX_GPIO1_BASE,
135 .pa_end = AM33XX_GPIO1_BASE + SZ_4K - 1,
136 .flags = ADDR_TYPE_RT
137 },
138 { }
139 };
141 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
142 .master = &am33xx_l4per_hwmod,
143 .slave = &am33xx_gpio1_hwmod,
144 .clk = "l4ls_fck",
145 .addr = am33xx_gpio1_addrs,
146 .user = OCP_USER_MPU | OCP_USER_SDMA,
147 };
149 /* L4 PER -> GPIO3 */
150 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
151 {
152 .pa_start = AM33XX_GPIO2_BASE,
153 .pa_end = AM33XX_GPIO2_BASE + SZ_4K - 1,
154 .flags = ADDR_TYPE_RT
155 },
156 { }
157 };
159 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
160 .master = &am33xx_l4per_hwmod,
161 .slave = &am33xx_gpio2_hwmod,
162 .clk = "l4ls_fck",
163 .addr = am33xx_gpio2_addrs,
164 .user = OCP_USER_MPU | OCP_USER_SDMA,
165 };
167 /* L4 PER -> GPIO4 */
168 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
169 {
170 .pa_start = AM33XX_GPIO3_BASE,
171 .pa_end = AM33XX_GPIO3_BASE + SZ_4K - 1,
172 .flags = ADDR_TYPE_RT
173 },
174 { }
175 };
177 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
178 .master = &am33xx_l4per_hwmod,
179 .slave = &am33xx_gpio3_hwmod,
180 .clk = "l4ls_fck",
181 .addr = am33xx_gpio3_addrs,
182 .user = OCP_USER_MPU | OCP_USER_SDMA,
183 };
185 /* Master interfaces on the L4_PER interconnect */
186 static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = {
187 &am33xx_l4_per__gpio1,
188 &am33xx_l4_per__gpio2,
189 &am33xx_l4_per__gpio3,
190 };
191 /* Slave interfaces on the L4_PER interconnect */
192 static struct omap_hwmod_ocp_if *am33xx_l4_per_slaves[] = {
193 &am33xx_l3_slow__l4_per,
194 };
196 static struct omap_hwmod am33xx_l4per_hwmod = {
197 .name = "l4_per",
198 .class = &l4_hwmod_class,
199 .clkdm_name = "l4ls_clkdm",
200 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
201 .masters = am33xx_l4_per_masters,
202 .masters_cnt = ARRAY_SIZE(am33xx_l4_per_masters),
203 .slaves = am33xx_l4_per_slaves,
204 .slaves_cnt = ARRAY_SIZE(am33xx_l4_per_slaves),
205 };
207 /* L4 WKUP -> I2C1 */
208 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
209 {
210 .pa_start = AM33XX_I2C0_BASE,
211 .pa_end = AM33XX_I2C0_BASE + SZ_4K - 1,
212 .flags = ADDR_TYPE_RT
213 },
214 { }
215 };
217 static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = {
218 .master = &am33xx_l4wkup_hwmod,
219 .slave = &am33xx_i2c1_hwmod,
220 .addr = am33xx_i2c1_addr_space,
221 .user = OCP_USER_MPU,
222 };
224 /* L4 WKUP -> GPIO1 */
225 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
226 {
227 .pa_start = AM33XX_GPIO0_BASE,
228 .pa_end = AM33XX_GPIO0_BASE + SZ_4K - 1,
229 .flags = ADDR_TYPE_RT
230 },
231 { }
232 };
234 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
235 .master = &am33xx_l4wkup_hwmod,
236 .slave = &am33xx_gpio0_hwmod,
237 .clk = "l4ls_fck",
238 .addr = am33xx_gpio0_addrs,
239 .user = OCP_USER_MPU | OCP_USER_SDMA,
240 };
242 /* L4 WKUP -> ADC_TSC */
243 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
244 {
245 .pa_start = AM33XX_TSC_BASE,
246 .pa_end = AM33XX_TSC_BASE + SZ_8K - 1,
247 .flags = ADDR_TYPE_RT
248 },
249 { }
250 };
252 static struct omap_hwmod_ocp_if am33xx_l4_wkup_adc_tsc = {
253 .master = &am33xx_l4wkup_hwmod,
254 .slave = &am33xx_adc_tsc_hwmod,
255 .clk = "adc_tsc_ick",
256 .addr = am33xx_adc_tsc_addrs,
257 .user = OCP_USER_MPU,
258 };
260 /* Master interfaces on the L4_WKUP interconnect */
261 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = {
262 &am33xx_l4_wkup__gpio0,
263 };
264 /* Slave interfaces on the L4_WKUP interconnect */
265 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_slaves[] = {
266 &am33xx_l3_slow__l4_wkup,
267 };
269 static struct omap_hwmod am33xx_l4wkup_hwmod = {
270 .name = "l4_wkup",
271 .class = &l4_hwmod_class,
272 .clkdm_name = "l4_wkup_clkdm",
273 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
274 .masters = am33xx_l4_wkup_masters,
275 .masters_cnt = ARRAY_SIZE(am33xx_l4_wkup_masters),
276 .slaves = am33xx_l4_wkup_slaves,
277 .slaves_cnt = ARRAY_SIZE(am33xx_l4_wkup_slaves),
278 };
280 /* 'adc_tsc' class */
281 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
282 .rev_offs = 0x00,
283 .sysc_offs = 0x10,
284 .sysc_flags = SYSC_HAS_SIDLEMODE,
285 .idlemodes = (SIDLE_FORCE | SIDLE_NO |
286 SIDLE_SMART | SIDLE_SMART_WKUP),
287 .sysc_fields = &omap_hwmod_sysc_type2,
288 };
290 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
291 .name = "adc_tsc",
292 .sysc = &am33xx_adc_tsc_sysc,
293 };
295 /* adc_tsc */
296 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
297 { .irq = AM33XX_IRQ_ADC_GEN },
298 { .irq = -1 }
299 };
301 static struct omap_hwmod_ocp_if *am33xx_adc_tsc_slaves[] = {
302 &am33xx_l4_wkup_adc_tsc,
303 };
305 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
306 .name = "adc_tsc",
307 .class = &am33xx_adc_tsc_hwmod_class,
308 .mpu_irqs = am33xx_adc_tsc_irqs,
309 .main_clk = "adc_tsc_fck",
310 .clkdm_name = "l4_wkup_clkdm",
311 .prcm = {
312 .omap4 = {
313 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
314 .modulemode = MODULEMODE_SWCTRL,
315 },
316 },
317 .flags = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
318 .slaves = am33xx_adc_tsc_slaves,
319 .slaves_cnt = ARRAY_SIZE(am33xx_adc_tsc_slaves),
320 };
322 /* 'aes' class */
323 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
324 .name = "aes",
325 };
327 /* aes0 */
328 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
329 { .irq = AM33XX_IRQ_AESEIP36t0_S },
330 { .irq = -1 }
331 };
333 static struct omap_hwmod am33xx_aes0_hwmod = {
334 .name = "aes0",
335 .class = &am33xx_aes_hwmod_class,
336 .mpu_irqs = am33xx_aes0_irqs,
337 .main_clk = "aes0_fck",
338 .clkdm_name = "l3_clkdm",
339 .prcm = {
340 .omap4 = {
341 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
342 .modulemode = MODULEMODE_SWCTRL,
343 },
344 },
345 };
347 /* 'cefuse' class */
348 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
349 .name = "cefuse",
350 };
352 /* cefuse */
353 static struct omap_hwmod am33xx_cefuse_hwmod = {
354 .name = "cefuse",
355 .class = &am33xx_cefuse_hwmod_class,
356 .main_clk = "cefuse_fck",
357 .clkdm_name = "l4_cefuse_clkdm",
358 .prcm = {
359 .omap4 = {
360 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
361 .modulemode = MODULEMODE_SWCTRL,
362 },
363 },
364 };
366 /* 'clkdiv32k' class */
367 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
368 .name = "clkdiv32k",
369 };
371 /* clkdiv32k */
372 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
373 .name = "clkdiv32k",
374 .class = &am33xx_clkdiv32k_hwmod_class,
375 .main_clk = "clkdiv32k_fck",
376 .clkdm_name = "clk_24mhz_clkdm",
377 .prcm = {
378 .omap4 = {
379 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
380 .modulemode = MODULEMODE_SWCTRL,
381 },
382 },
383 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
384 };
386 /* 'control' class */
387 static struct omap_hwmod_class am33xx_control_hwmod_class = {
388 .name = "control",
389 };
391 /* control */
392 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
393 { .irq = AM33XX_IRQ_CONTROL_PLATFORM },
394 { .irq = -1 }
395 };
397 static struct omap_hwmod am33xx_control_hwmod = {
398 .name = "control",
399 .class = &am33xx_control_hwmod_class,
400 .mpu_irqs = am33xx_control_irqs,
401 .main_clk = "control_fck",
402 .clkdm_name = "l4_wkup_clkdm",
403 .prcm = {
404 .omap4 = {
405 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
406 .modulemode = MODULEMODE_SWCTRL,
407 },
408 },
409 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
410 };
412 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
413 .rev_offs = 0x0,
414 .sysc_offs = 0x8,
415 .syss_offs = 0x4,
416 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE
417 | SYSS_HAS_RESET_STATUS),
418 .idlemodes = (SIDLE_FORCE | SIDLE_NO |
419 MSTANDBY_FORCE | MSTANDBY_NO),
420 .sysc_fields = &omap_hwmod_sysc_type3,
421 };
423 /* 'cpgmac' class */
424 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
425 .name = "cpgmac0",
426 .sysc = &am33xx_cpgmac_sysc,
427 };
429 /* cpgmac0 - has 4 IRQs */
430 #if 0
431 static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
432 { .irq = AM33XX_IRQ_TPTC0 },
433 { .irq = -1 }
434 };
435 #endif
437 struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
438 {
439 .pa_start = AM33XX_CPSW_SS_BASE,
440 .pa_end = AM33XX_CPSW_SS_BASE + SZ_8K - 1,
441 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
442 },
443 { }
444 };
446 struct omap_hwmod_ocp_if am33xx_l3_main__cpgmac0 = {
447 .master = &am33xx_l3_main_hwmod,
448 .slave = &am33xx_cpgmac0_hwmod,
449 .addr = am33xx_cpgmac0_addr_space,
450 .user = OCP_USER_MPU,
451 };
453 static struct omap_hwmod_ocp_if *am33xx_cpgmac0_slaves[] = {
454 &am33xx_l3_main__cpgmac0,
455 };
457 /* cpgmac0 */
458 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
459 .name = "cpgmac0",
460 .class = &am33xx_cpgmac0_hwmod_class,
461 .main_clk = "cpgmac0_fck",
462 .clkdm_name = "cpsw_125mhz_clkdm",
463 .prcm = {
464 .omap4 = {
465 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
466 .modulemode = MODULEMODE_SWCTRL,
467 },
468 },
469 .slaves = am33xx_cpgmac0_slaves,
470 .slaves_cnt = ARRAY_SIZE(am33xx_cpgmac0_slaves),
471 };
473 /* 'dcan' class */
474 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
475 .name = "dcan",
476 };
478 /* dcan0 */
479 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
480 { .irq = AM33XX_IRQ_DCAN0_0 },
481 { .irq = -1 }
482 };
484 static struct omap_hwmod am33xx_dcan0_hwmod = {
485 .name = "dcan0",
486 .class = &am33xx_dcan_hwmod_class,
487 .mpu_irqs = am33xx_dcan0_irqs,
488 .main_clk = "dcan0_fck",
489 .clkdm_name = "l4ls_clkdm",
490 .prcm = {
491 .omap4 = {
492 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
493 .modulemode = MODULEMODE_SWCTRL,
494 },
495 },
496 };
498 /* dcan1 */
499 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
500 { .irq = AM33XX_IRQ_DCAN1_0 },
501 { .irq = -1 }
502 };
503 static struct omap_hwmod am33xx_dcan1_hwmod = {
504 .name = "dcan1",
505 .class = &am33xx_dcan_hwmod_class,
506 .mpu_irqs = am33xx_dcan1_irqs,
507 .main_clk = "dcan1_fck",
508 .clkdm_name = "l4ls_clkdm",
509 .prcm = {
510 .omap4 = {
511 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
512 .modulemode = MODULEMODE_SWCTRL,
513 },
514 },
515 };
517 /* 'debugss' class */
518 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
519 .name = "debugss",
520 };
522 /* debugss */
523 static struct omap_hwmod am33xx_debugss_hwmod = {
524 .name = "debugss",
525 .class = &am33xx_debugss_hwmod_class,
526 .main_clk = "debugss_fck",
527 .clkdm_name = "l3_aon_clkdm",
528 .prcm = {
529 .omap4 = {
530 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
531 .modulemode = MODULEMODE_SWCTRL,
532 },
533 },
534 #ifdef CONFIG_DEBUG_JTAG_ENABLE
535 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
536 #endif
537 };
539 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
540 .rev_offs = 0x0000,
541 .sysc_offs = 0x0010,
542 .syss_offs = 0x0014,
543 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
544 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
545 SYSS_HAS_RESET_STATUS),
546 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
547 .sysc_fields = &omap_hwmod_sysc_type1,
548 };
549 /* 'elm' class */
550 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
551 .name = "elm",
552 .sysc = &am33xx_elm_sysc,
553 };
555 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
556 { .irq = AM33XX_IRQ_ELM },
557 { .irq = -1 }
558 };
560 struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
561 {
562 .pa_start = AM33XX_ELM_BASE,
563 .pa_end = AM33XX_ELM_BASE + SZ_8K - 1,
564 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
565 },
566 { }
567 };
569 struct omap_hwmod_ocp_if am33xx_l4_core__elm = {
570 .master = &am33xx_l4per_hwmod,
571 .slave = &am33xx_elm_hwmod,
572 .addr = am33xx_elm_addr_space,
573 .user = OCP_USER_MPU,
574 };
576 static struct omap_hwmod_ocp_if *am33xx_elm_slaves[] = {
577 &am33xx_l4_core__elm,
578 };
580 /* elm */
581 static struct omap_hwmod am33xx_elm_hwmod = {
582 .name = "elm",
583 .class = &am33xx_elm_hwmod_class,
584 .mpu_irqs = am33xx_elm_irqs,
585 .main_clk = "elm_fck",
586 .clkdm_name = "l4ls_clkdm",
587 .slaves = am33xx_elm_slaves,
588 .slaves_cnt = ARRAY_SIZE(am33xx_elm_slaves),
589 .prcm = {
590 .omap4 = {
591 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
592 .modulemode = MODULEMODE_SWCTRL,
593 },
594 },
595 };
597 /* 'emif_fw' class */
598 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
599 .name = "emif_fw",
600 };
602 /* emif_fw */
603 static struct omap_hwmod am33xx_emif_fw_hwmod = {
604 .name = "emif_fw",
605 .class = &am33xx_emif_fw_hwmod_class,
606 .main_clk = "emif_fw_fck",
607 .clkdm_name = "l4fw_clkdm",
608 .prcm = {
609 .omap4 = {
610 .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
611 .modulemode = MODULEMODE_SWCTRL,
612 },
613 },
614 .flags = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
615 };
617 /* 'epwmss' class */
618 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
619 .rev_offs = 0x0,
620 .sysc_offs = 0x10,
621 .sysc_flags = SYSC_HAS_SIDLEMODE,
622 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
623 SIDLE_SMART_WKUP),
624 .sysc_fields = &omap_hwmod_sysc_type2,
625 };
627 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
628 .name = "epwmss",
629 .sysc = &am33xx_epwmss_sysc,
630 };
632 /* epwmss0 */
633 static struct omap_hwmod_irq_info am33xx_epwmss0_irqs[] = {
634 { .irq = AM33XX_IRQ_PWMSS0_EPWM },
635 { .irq = AM33XX_IRQ_PWMSS0 },
636 { .irq = AM33XX_IRQ_PWMSS0_ECAP },
637 { .irq = -1 }
638 };
640 struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
641 {
642 .pa_start = AM33XX_EPWMSS0_BASE,
643 .pa_end = AM33XX_EPWMSS0_BASE + SZ_4K - 1,
644 .flags = ADDR_TYPE_RT
645 },
646 { }
647 };
649 struct omap_hwmod_ocp_if am33xx_l4_core__epwmss0 = {
650 .master = &am33xx_l4per_hwmod,
651 .slave = &am33xx_epwmss0_hwmod,
652 .addr = am33xx_epwmss0_addr_space,
653 .user = OCP_USER_MPU,
654 };
656 static struct omap_hwmod_ocp_if *am33xx_epwmss0_slaves[] = {
657 &am33xx_l4_core__epwmss0,
658 };
660 static struct omap_hwmod am33xx_epwmss0_hwmod = {
661 .name = "epwmss0",
662 .mpu_irqs = am33xx_epwmss0_irqs,
663 .class = &am33xx_epwmss_hwmod_class,
664 .main_clk = "epwmss0_fck",
665 .clkdm_name = "l4ls_clkdm",
666 .prcm = {
667 .omap4 = {
668 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
669 .modulemode = MODULEMODE_SWCTRL,
670 },
671 },
672 .slaves = am33xx_epwmss0_slaves,
673 .slaves_cnt = ARRAY_SIZE(am33xx_epwmss0_slaves),
674 };
676 /* epwmss1 */
677 static struct omap_hwmod_irq_info am33xx_epwmss1_irqs[] = {
678 { .irq = AM33XX_IRQ_PWMSS1_EPWM },
679 { .irq = AM33XX_IRQ_PWMSS1 },
680 { .irq = AM33XX_IRQ_PWMSS1_ECAP },
681 { .irq = -1 }
682 };
684 struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
685 {
686 .pa_start = AM33XX_EPWMSS1_BASE,
687 .pa_end = AM33XX_EPWMSS1_BASE + SZ_4K - 1,
688 .flags = ADDR_TYPE_RT
689 },
690 { }
691 };
693 struct omap_hwmod_ocp_if am33xx_l4_core__epwmss1 = {
694 .master = &am33xx_l4per_hwmod,
695 .slave = &am33xx_epwmss1_hwmod,
696 .addr = am33xx_epwmss1_addr_space,
697 .user = OCP_USER_MPU,
698 };
700 static struct omap_hwmod_ocp_if *am33xx_epwmss1_slaves[] = {
701 &am33xx_l4_core__epwmss1,
702 };
704 static struct omap_hwmod am33xx_epwmss1_hwmod = {
705 .name = "epwmss1",
706 .mpu_irqs = am33xx_epwmss1_irqs,
707 .class = &am33xx_epwmss_hwmod_class,
708 .main_clk = "epwmss1_fck",
709 .clkdm_name = "l4ls_clkdm",
710 .prcm = {
711 .omap4 = {
712 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
713 .modulemode = MODULEMODE_SWCTRL,
714 },
715 },
716 .slaves = am33xx_epwmss1_slaves,
717 .slaves_cnt = ARRAY_SIZE(am33xx_epwmss1_slaves),
718 };
720 /* epwmss2 */
721 static struct omap_hwmod_irq_info am33xx_epwmss2_irqs[] = {
722 { .irq = AM33XX_IRQ_PWMSS2_EPWM },
723 { .irq = AM33XX_IRQ_PWMSS2 },
724 { .irq = AM33XX_IRQ_PWMSS2_ECAP },
725 { .irq = -1 }
726 };
728 struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
729 {
730 .pa_start = AM33XX_EPWMSS2_BASE,
731 .pa_end = AM33XX_EPWMSS2_BASE + SZ_4K - 1,
732 .flags = ADDR_TYPE_RT
733 },
734 { }
735 };
737 struct omap_hwmod_ocp_if am33xx_l4_core__epwmss2 = {
738 .master = &am33xx_l4per_hwmod,
739 .slave = &am33xx_epwmss2_hwmod,
740 .addr = am33xx_epwmss2_addr_space,
741 .user = OCP_USER_MPU,
742 };
744 static struct omap_hwmod_ocp_if *am33xx_epwmss2_slaves[] = {
745 &am33xx_l4_core__epwmss2,
746 };
748 static struct omap_hwmod am33xx_epwmss2_hwmod = {
749 .name = "epwmss2",
750 .mpu_irqs = am33xx_epwmss2_irqs,
751 .class = &am33xx_epwmss_hwmod_class,
752 .main_clk = "epwmss2_fck",
753 .clkdm_name = "l4ls_clkdm",
754 .prcm = {
755 .omap4 = {
756 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
757 .modulemode = MODULEMODE_SWCTRL,
758 },
759 },
760 .slaves = am33xx_epwmss2_slaves,
761 .slaves_cnt = ARRAY_SIZE(am33xx_epwmss2_slaves),
762 };
764 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
765 .rev_offs = 0x0000,
766 .sysc_offs = 0x0010,
767 .syss_offs = 0x0114,
768 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
769 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
770 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
771 SIDLE_SMART_WKUP),
772 .sysc_fields = &omap_hwmod_sysc_type1,
773 };
775 /* 'gpio' class */
776 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
777 .name = "gpio",
778 .sysc = &am33xx_gpio_sysc,
779 .rev = 2,
780 };
782 /* gpio dev_attr */
783 static struct omap_gpio_dev_attr gpio_dev_attr = {
784 .bank_width = 32,
785 .dbck_flag = true,
786 };
788 /* gpio0 */
789 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
790 { .irq = AM33XX_IRQ_GPIO0_1 },
791 { .irq = -1 }
792 };
794 /* gpio0 slave ports */
795 static struct omap_hwmod_ocp_if *am33xx_gpio0_slaves[] = {
796 &am33xx_l4_wkup__gpio0,
797 };
799 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
800 { .role = "dbclk", .clk = "gpio0_dbclk" },
801 { .role = "fclk", .clk = "gpio0_fck" },
802 };
804 /* gpio0 */
805 static struct omap_hwmod am33xx_gpio0_hwmod = {
806 .name = "gpio1",
807 .class = &am33xx_gpio_hwmod_class,
808 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
809 .mpu_irqs = am33xx_gpio0_irqs,
810 .main_clk = "gpio0_fck",
811 .clkdm_name = "l4_wkup_clkdm",
812 .prcm = {
813 .omap4 = {
814 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
815 .modulemode = MODULEMODE_SWCTRL,
816 },
817 },
818 .opt_clks = gpio0_opt_clks,
819 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
820 .dev_attr = &gpio_dev_attr,
821 .slaves = am33xx_gpio0_slaves,
822 .slaves_cnt = ARRAY_SIZE(am33xx_gpio0_slaves),
823 };
825 /* gpio1 */
826 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
827 { .irq = AM33XX_IRQ_GPIO1_1 },
828 { .irq = -1 }
829 };
831 /* gpio1 slave ports */
832 static struct omap_hwmod_ocp_if *am33xx_gpio1_slaves[] = {
833 &am33xx_l4_per__gpio1,
834 };
836 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
837 { .role = "dbclk", .clk = "gpio1_dbclk" },
838 { .role = "fclk", .clk = "gpio1_fck" },
839 };
841 static struct omap_hwmod am33xx_gpio1_hwmod = {
842 .name = "gpio2",
843 .class = &am33xx_gpio_hwmod_class,
844 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
845 .mpu_irqs = am33xx_gpio1_irqs,
846 .main_clk = "gpio1_fck",
847 .clkdm_name = "l4ls_clkdm",
848 .prcm = {
849 .omap4 = {
850 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
851 .modulemode = MODULEMODE_SWCTRL,
852 },
853 },
854 .opt_clks = gpio1_opt_clks,
855 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
856 .dev_attr = &gpio_dev_attr,
857 .slaves = am33xx_gpio1_slaves,
858 .slaves_cnt = ARRAY_SIZE(am33xx_gpio1_slaves),
859 };
861 /* gpio2 */
862 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
863 { .irq = AM33XX_IRQ_GPIO2_1 },
864 { .irq = -1 }
865 };
867 /* gpio2 slave ports */
868 static struct omap_hwmod_ocp_if *am33xx_gpio2_slaves[] = {
869 &am33xx_l4_per__gpio2,
870 };
872 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
873 { .role = "dbclk", .clk = "gpio2_dbclk" },
874 { .role = "fclk", .clk = "gpio2_fck" },
875 };
877 /* gpio2 */
878 static struct omap_hwmod am33xx_gpio2_hwmod = {
879 .name = "gpio3",
880 .class = &am33xx_gpio_hwmod_class,
881 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
882 .mpu_irqs = am33xx_gpio2_irqs,
883 .main_clk = "gpio2_fck",
884 .clkdm_name = "l4ls_clkdm",
885 .prcm = {
886 .omap4 = {
887 .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
888 .modulemode = MODULEMODE_SWCTRL,
889 },
890 },
891 .opt_clks = gpio2_opt_clks,
892 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
893 .dev_attr = &gpio_dev_attr,
894 .slaves = am33xx_gpio2_slaves,
895 .slaves_cnt = ARRAY_SIZE(am33xx_gpio2_slaves),
896 };
898 /* gpio3 */
899 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
900 { .irq = AM33XX_IRQ_GPIO3_1 },
901 { .irq = -1 }
902 };
904 /* gpio3 slave ports */
905 static struct omap_hwmod_ocp_if *am33xx_gpio3_slaves[] = {
906 &am33xx_l4_per__gpio3,
907 };
909 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
910 { .role = "dbclk", .clk = "gpio3_dbclk" },
911 { .role = "fclk", .clk = "gpio3_fck" },
912 };
914 /* gpio3 */
915 static struct omap_hwmod am33xx_gpio3_hwmod = {
916 .name = "gpio4",
917 .class = &am33xx_gpio_hwmod_class,
918 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
919 .mpu_irqs = am33xx_gpio3_irqs,
920 .main_clk = "gpio3_fck",
921 .clkdm_name = "l4ls_clkdm",
922 .prcm = {
923 .omap4 = {
924 .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
925 .modulemode = MODULEMODE_SWCTRL,
926 },
927 },
928 .opt_clks = gpio3_opt_clks,
929 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
930 .dev_attr = &gpio_dev_attr,
931 .slaves = am33xx_gpio3_slaves,
932 .slaves_cnt = ARRAY_SIZE(am33xx_gpio3_slaves),
933 };
935 /* 'gpmc' class */
936 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
937 .rev_offs = 0x0,
938 .sysc_offs = 0x10,
939 .syss_offs = 0x14,
940 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
941 SYSC_HAS_MIDLEMODE | SYSC_HAS_SOFTRESET |
942 SYSS_HAS_RESET_STATUS),
943 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
944 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
945 .sysc_fields = &omap_hwmod_sysc_type4,
946 };
948 struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
949 {
950 .pa_start = 0x50000000,
951 .pa_end = 0x50000000 + SZ_8K - 1,
952 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
953 },
954 { }
955 };
957 struct omap_hwmod_ocp_if am33xx_l3_main__gpmc = {
958 .master = &am33xx_l3_main_hwmod,
959 .slave = &am33xx_gpmc_hwmod,
960 .addr = am33xx_gpmc_addr_space,
961 .user = OCP_USER_MPU,
962 };
964 static struct omap_hwmod_ocp_if *am33xx_gpmc_slaves[] = {
965 &am33xx_l3_main__gpmc,
966 };
968 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
969 .name = "gpmc",
970 .sysc = &gpmc_sysc,
971 };
973 /* gpmc */
974 static struct omap_hwmod am33xx_gpmc_hwmod = {
975 .name = "gpmc",
976 .class = &am33xx_gpmc_hwmod_class,
977 .main_clk = "gpmc_fck",
978 .clkdm_name = "l3s_clkdm",
979 .prcm = {
980 .omap4 = {
981 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
982 .modulemode = MODULEMODE_SWCTRL,
983 },
984 },
985 .slaves = am33xx_gpmc_slaves,
986 .slaves_cnt = ARRAY_SIZE(am33xx_gpmc_slaves),
987 };
989 /* 'i2c' class */
991 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
992 .sysc_offs = 0x0010,
993 .syss_offs = 0x0090,
994 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
995 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
996 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
997 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
998 SIDLE_SMART_WKUP),
999 .sysc_fields = &omap_hwmod_sysc_type1,
1000 };
1002 static struct omap_i2c_dev_attr i2c_dev_attr = {
1003 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1004 };
1006 static struct omap_hwmod_class i2c_class = {
1007 .name = "i2c",
1008 .sysc = &am33xx_i2c_sysc,
1009 .rev = OMAP_I2C_IP_VERSION_2,
1010 .reset = &omap_i2c_reset,
1011 };
1013 /* I2C1 */
1014 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1015 { .irq = AM33XX_IRQ_MSHSI2COCP0 },
1016 { .irq = -1 }
1017 };
1019 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
1020 { .name = "tx", .dma_req = 0, },
1021 { .name = "rx", .dma_req = 0, },
1022 { .dma_req = -1 }
1023 };
1025 static struct omap_hwmod_ocp_if *am33xx_i2c1_slaves[] = {
1026 &am33xx_l4_wkup_i2c1,
1027 };
1029 static struct omap_hwmod am33xx_i2c1_hwmod = {
1030 .name = "i2c1",
1031 .mpu_irqs = i2c1_mpu_irqs,
1032 .sdma_reqs = i2c1_edma_reqs,
1033 .main_clk = "i2c1_fck",
1034 .clkdm_name = "l4_wkup_clkdm",
1035 .prcm = {
1036 .omap4 = {
1037 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
1038 .modulemode = MODULEMODE_SWCTRL,
1039 },
1040 },
1041 .flags = HWMOD_16BIT_REG,
1042 .dev_attr = &i2c_dev_attr,
1043 .slaves = am33xx_i2c1_slaves,
1044 .slaves_cnt = ARRAY_SIZE(am33xx_i2c1_slaves),
1045 .class = &i2c_class,
1046 };
1048 /* i2c2 */
1049 /* l4 per -> i2c2 */
1050 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
1051 {
1052 .pa_start = AM33XX_I2C1_BASE,
1053 .pa_end = AM33XX_I2C1_BASE + SZ_4K - 1,
1054 .flags = ADDR_TYPE_RT
1055 },
1056 { }
1057 };
1059 static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = {
1060 .master = &am33xx_l4per_hwmod,
1061 .slave = &am33xx_i2c2_hwmod,
1062 .addr = am33xx_i2c2_addr_space,
1063 .user = OCP_USER_MPU,
1064 };
1066 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1067 { .irq = AM33XX_IRQ_MSHSI2COCP1 },
1068 { .irq = -1 }
1069 };
1071 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
1072 { .name = "tx", .dma_req = 0, },
1073 { .name = "rx", .dma_req = 0, },
1074 { .dma_req = -1 }
1075 };
1077 static struct omap_hwmod_ocp_if *am33xx_i2c2_slaves[] = {
1078 &am335_l4_per_i2c2,
1079 };
1081 static struct omap_hwmod am33xx_i2c2_hwmod = {
1082 .name = "i2c2",
1083 .mpu_irqs = i2c2_mpu_irqs,
1084 .sdma_reqs = i2c2_edma_reqs,
1085 .main_clk = "i2c2_fck",
1086 .clkdm_name = "l4ls_clkdm",
1087 .prcm = {
1088 .omap4 = {
1089 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
1090 .modulemode = MODULEMODE_SWCTRL,
1091 },
1092 },
1093 .flags = HWMOD_16BIT_REG,
1094 .dev_attr = &i2c_dev_attr,
1095 .slaves = am33xx_i2c2_slaves,
1096 .slaves_cnt = ARRAY_SIZE(am33xx_i2c2_slaves),
1097 .class = &i2c_class,
1098 };
1100 /* i2c3 */
1101 /* l4 per -> i2c3 */
1102 static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
1103 {
1104 .pa_start = AM33XX_I2C2_BASE,
1105 .pa_end = AM33XX_I2C2_BASE + SZ_4K - 1,
1106 .flags = ADDR_TYPE_RT
1107 },
1108 { }
1109 };
1111 static struct omap_hwmod_ocp_if am335_l4_per_i2c3 = {
1112 .master = &am33xx_l4per_hwmod,
1113 .slave = &am33xx_i2c3_hwmod,
1114 .addr = am33xx_i2c3_addr_space,
1115 .user = OCP_USER_MPU,
1116 };
1118 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1119 { .irq = AM33XX_IRQ_MSHSI2COCP2 },
1120 { .irq = -1 }
1121 };
1123 static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
1124 { .name = "tx", .dma_req = 0, },
1125 { .name = "rx", .dma_req = 0, },
1126 { .dma_req = -1 }
1127 };
1129 static struct omap_hwmod_ocp_if *am33xx_i2c3_slaves[] = {
1130 &am335_l4_per_i2c3,
1131 };
1133 static struct omap_hwmod am33xx_i2c3_hwmod = {
1134 .name = "i2c3",
1135 .mpu_irqs = i2c3_mpu_irqs,
1136 .sdma_reqs = i2c3_edma_reqs,
1137 .main_clk = "i2c3_fck",
1138 .clkdm_name = "l4ls_clkdm",
1139 .prcm = {
1140 .omap4 = {
1141 .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
1142 .modulemode = MODULEMODE_SWCTRL,
1143 },
1144 },
1145 .flags = HWMOD_16BIT_REG,
1146 .dev_attr = &i2c_dev_attr,
1147 .slaves = am33xx_i2c3_slaves,
1148 .slaves_cnt = ARRAY_SIZE(am33xx_i2c3_slaves),
1149 .class = &i2c_class,
1150 };
1152 /* 'icss' class */
1153 static struct omap_hwmod_class am33xx_icss_hwmod_class = {
1154 .name = "icss",
1155 };
1157 /* icss */
1158 static struct omap_hwmod am33xx_icss_hwmod = {
1159 .name = "icss",
1160 .class = &am33xx_icss_hwmod_class,
1161 .main_clk = "icss_fck",
1162 .clkdm_name = "icss_ocp_clkdm",
1163 .prcm = {
1164 .omap4 = {
1165 .clkctrl_offs = AM33XX_CM_PER_ICSS_CLKCTRL_OFFSET,
1166 .modulemode = MODULEMODE_SWCTRL,
1167 },
1168 },
1169 };
1171 /* 'ieee5000' class */
1172 static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = {
1173 .name = "ieee5000",
1174 };
1176 /* ieee5000 */
1177 static struct omap_hwmod am33xx_ieee5000_hwmod = {
1178 .name = "ieee5000",
1179 .class = &am33xx_ieee5000_hwmod_class,
1180 .main_clk = "ieee5000_fck",
1181 .clkdm_name = "l3s_clkdm",
1182 .prcm = {
1183 .omap4 = {
1184 .clkctrl_offs = AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET,
1185 .modulemode = MODULEMODE_SWCTRL,
1186 },
1187 },
1188 };
1191 /* 'l3' class */
1192 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
1193 .name = "l3",
1194 };
1196 /* l4_hs */
1197 static struct omap_hwmod am33xx_l4_hs_hwmod = {
1198 .name = "l4_hs",
1199 .class = &am33xx_l3_hwmod_class,
1200 .clkdm_name = "l4hs_clkdm",
1201 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1202 .prcm = {
1203 .omap4 = {
1204 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
1205 .modulemode = MODULEMODE_SWCTRL,
1206 },
1207 },
1208 };
1210 /* l3_instr */
1211 static struct omap_hwmod am33xx_l3_instr_hwmod = {
1212 .name = "l3_instr",
1213 .class = &am33xx_l3_hwmod_class,
1214 .clkdm_name = "l3_clkdm",
1215 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1216 .prcm = {
1217 .omap4 = {
1218 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
1219 .modulemode = MODULEMODE_SWCTRL,
1220 },
1221 },
1222 };
1224 /* l3_main */
1225 static struct omap_hwmod am33xx_l3_main_hwmod = {
1226 .name = "l3_main",
1227 .class = &am33xx_l3_hwmod_class,
1228 .clkdm_name = "l3_clkdm",
1229 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1230 .prcm = {
1231 .omap4 = {
1232 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
1233 .modulemode = MODULEMODE_SWCTRL,
1234 },
1235 },
1236 };
1238 /* 'l4fw' class */
1239 static struct omap_hwmod_class am33xx_l4fw_hwmod_class = {
1240 .name = "l4fw",
1241 };
1243 /* l4fw */
1244 static struct omap_hwmod am33xx_l4fw_hwmod = {
1245 .name = "l4fw",
1246 .class = &am33xx_l4fw_hwmod_class,
1247 .clkdm_name = "l4fw_clkdm",
1248 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1249 .prcm = {
1250 .omap4 = {
1251 .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
1252 .modulemode = MODULEMODE_SWCTRL,
1253 },
1254 },
1255 };
1257 /* 'l4ls' class */
1258 static struct omap_hwmod_class am33xx_l4ls_hwmod_class = {
1259 .name = "l4ls",
1260 };
1262 /* l4ls */
1263 static struct omap_hwmod am33xx_l4ls_hwmod = {
1264 .name = "l4ls",
1265 .class = &am33xx_l4ls_hwmod_class,
1266 .main_clk = "l4ls_fck",
1267 .clkdm_name = "l4ls_clkdm",
1268 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1269 .prcm = {
1270 .omap4 = {
1271 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
1272 .modulemode = MODULEMODE_SWCTRL,
1273 },
1274 },
1275 };
1277 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
1278 .rev_offs = 0x0,
1279 .sysc_offs = 0x54,
1280 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
1281 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1282 .sysc_fields = &omap_hwmod_sysc_type2,
1283 };
1285 /* 'lcdc' class */
1286 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1287 .name = "lcdc",
1288 .sysc = &lcdc_sysc,
1289 };
1291 /* lcdc */
1292 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1293 { .irq = AM33XX_IRQ_LCD },
1294 { .irq = -1 }
1295 };
1297 struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
1298 {
1299 .pa_start = 0x4830E000,
1300 .pa_end = 0x4830E000 + SZ_8K - 1,
1301 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
1302 },
1303 { }
1304 };
1306 struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
1307 .master = &am33xx_l3_main_hwmod,
1308 .slave = &am33xx_lcdc_hwmod,
1309 .addr = am33xx_lcdc_addr_space,
1310 .user = OCP_USER_MPU,
1311 };
1313 static struct omap_hwmod_ocp_if *am33xx_lcdc_slaves[] = {
1314 &am33xx_l3_main__lcdc,
1315 };
1317 static struct omap_hwmod am33xx_lcdc_hwmod = {
1318 .name = "lcdc",
1319 .class = &am33xx_lcdc_hwmod_class,
1320 .mpu_irqs = am33xx_lcdc_irqs,
1321 .main_clk = "lcdc_fck",
1322 .clkdm_name = "lcdc_clkdm",
1323 .prcm = {
1324 .omap4 = {
1325 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1326 .modulemode = MODULEMODE_SWCTRL,
1327 },
1328 },
1329 .slaves = am33xx_lcdc_slaves,
1330 .slaves_cnt = ARRAY_SIZE(am33xx_lcdc_slaves),
1331 };
1333 /*
1334 * 'mailbox' class
1335 * mailbox module allowing communication between the on-chip processors using a
1336 * queued mailbox-interrupt mechanism.
1337 */
1339 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1340 .rev_offs = 0x0000,
1341 .sysc_offs = 0x0010,
1342 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1343 SYSC_HAS_SOFTRESET),
1344 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1345 .sysc_fields = &omap_hwmod_sysc_type2,
1346 };
1348 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1349 .name = "mailbox",
1350 .sysc = &am33xx_mailbox_sysc,
1351 };
1353 /* mailbox */
1354 static struct omap_hwmod am33xx_mailbox_hwmod;
1355 static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1356 { .irq = AM33XX_IRQ_MAILBOX },
1357 { .irq = -1 }
1358 };
1360 static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
1361 {
1362 .pa_start = AM33XX_MAILBOX0_BASE,
1363 .pa_end = AM33XX_MAILBOX0_BASE + (SZ_4K - 1),
1364 .flags = ADDR_TYPE_RT
1365 },
1366 { }
1367 };
1369 /* l4_cfg -> mailbox */
1370 static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
1371 .master = &am33xx_l4per_hwmod,
1372 .slave = &am33xx_mailbox_hwmod,
1373 .addr = am33xx_mailbox_addrs,
1374 .user = OCP_USER_MPU,
1375 };
1377 /* mailbox slave ports */
1378 static struct omap_hwmod_ocp_if *am33xx_mailbox_slaves[] = {
1379 &am33xx_l4_per__mailbox,
1380 };
1382 static struct omap_hwmod am33xx_mailbox_hwmod = {
1383 .name = "mailbox",
1384 .class = &am33xx_mailbox_hwmod_class,
1385 .clkdm_name = "l4ls_clkdm",
1386 .mpu_irqs = am33xx_mailbox_irqs,
1387 .main_clk = "mailbox0_fck",
1388 .prcm = {
1389 .omap4 = {
1390 .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1391 .modulemode = MODULEMODE_SWCTRL,
1392 },
1393 },
1394 .slaves = am33xx_mailbox_slaves,
1395 .slaves_cnt = ARRAY_SIZE(am33xx_mailbox_slaves),
1396 };
1398 /* 'mcasp' class */
1399 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1400 .name = "mcasp",
1401 };
1403 /* mcasp0 */
1404 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1405 { .name = "ax", .irq = AM33XX_IRQ_MCASP0_AX, },
1406 { .name = "ar", .irq = AM33XX_IRQ_MCASP0_AR, },
1407 { .irq = -1 }
1408 };
1410 static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
1411 {
1412 .pa_start = AM33XX_ASP0_BASE,
1413 .pa_end = AM33XX_ASP0_BASE + (SZ_1K * 12) - 1,
1414 .flags = ADDR_TYPE_RT
1415 },
1416 { }
1417 };
1419 static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp0 = {
1420 .master = &am33xx_l3slow_hwmod,
1421 .slave = &am33xx_mcasp0_hwmod,
1422 .clk = "mcasp0_ick",
1423 .addr = am33xx_mcasp0_addr_space,
1424 .user = OCP_USER_MPU,
1425 };
1427 static struct omap_hwmod_ocp_if *am33xx_mcasp0_slaves[] = {
1428 &am33xx_l3_slow__mcasp0,
1429 };
1431 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1432 .name = "mcasp0",
1433 .class = &am33xx_mcasp_hwmod_class,
1434 .mpu_irqs = am33xx_mcasp0_irqs,
1435 .main_clk = "mcasp0_fck",
1436 .clkdm_name = "l3s_clkdm",
1437 .prcm = {
1438 .omap4 = {
1439 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1440 .modulemode = MODULEMODE_SWCTRL,
1441 },
1442 },
1443 .slaves = am33xx_mcasp0_slaves,
1444 .slaves_cnt = ARRAY_SIZE(am33xx_mcasp0_slaves),
1445 };
1447 /* mcasp1 */
1448 static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
1449 { .name = "ax", .irq = AM33XX_IRQ_MCASP1_AX, },
1450 { .name = "ar", .irq = AM33XX_IRQ_MCASP1_AR, },
1451 { .irq = -1 }
1452 };
1454 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
1455 {
1456 .pa_start = AM33XX_ASP1_BASE,
1457 .pa_end = AM33XX_ASP1_BASE + (SZ_1K * 12) - 1,
1458 .flags = ADDR_TYPE_RT
1459 },
1460 { }
1461 };
1463 static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp1 = {
1464 .master = &am33xx_l3slow_hwmod,
1465 .slave = &am33xx_mcasp1_hwmod,
1466 .clk = "mcasp1_ick",
1467 .addr = am33xx_mcasp1_addr_space,
1468 .user = OCP_USER_MPU,
1469 };
1471 static struct omap_hwmod_ocp_if *am33xx_mcasp1_slaves[] = {
1472 &am33xx_l3_slow__mcasp1,
1473 };
1475 static struct omap_hwmod am33xx_mcasp1_hwmod = {
1476 .name = "mcasp1",
1477 .class = &am33xx_mcasp_hwmod_class,
1478 .mpu_irqs = am33xx_mcasp1_irqs,
1479 .main_clk = "mcasp1_fck",
1480 .clkdm_name = "l3s_clkdm",
1481 .prcm = {
1482 .omap4 = {
1483 .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
1484 .modulemode = MODULEMODE_SWCTRL,
1485 },
1486 },
1487 .slaves = am33xx_mcasp1_slaves,
1488 .slaves_cnt = ARRAY_SIZE(am33xx_mcasp1_slaves),
1489 };
1492 /* 'mmc' class */
1494 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1495 .rev_offs = 0x1fc,
1496 .sysc_offs = 0x10,
1497 .syss_offs = 0x14,
1498 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1499 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1500 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1501 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1502 .sysc_fields = &omap_hwmod_sysc_type1,
1503 };
1505 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1506 .name = "mmc",
1507 .sysc = &am33xx_mmc_sysc,
1508 };
1510 /* mmc0 */
1511 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1512 { .irq = AM33XX_IRQ_MMCHS0 },
1513 { .irq = -1 }
1514 };
1516 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1517 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS0_W, },
1518 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS0_R, },
1519 { .dma_req = -1 }
1520 };
1522 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
1523 {
1524 .pa_start = AM33XX_MMC0_BASE,
1525 .pa_end = AM33XX_MMC0_BASE + SZ_4K - 1,
1526 .flags = ADDR_TYPE_RT
1527 },
1528 { }
1529 };
1531 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc0 = {
1532 .master = &am33xx_l4ls_hwmod,
1533 .slave = &am33xx_mmc0_hwmod,
1534 .clk = "mmc0_ick",
1535 .addr = am33xx_mmc0_addr_space,
1536 .user = OCP_USER_MPU,
1537 };
1539 static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = {
1540 &am33xx_l4ls__mmc0,
1541 };
1543 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1544 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1545 };
1547 static struct omap_hwmod am33xx_mmc0_hwmod = {
1548 .name = "mmc1",
1549 .class = &am33xx_mmc_hwmod_class,
1550 .mpu_irqs = am33xx_mmc0_irqs,
1551 .sdma_reqs = am33xx_mmc0_edma_reqs,
1552 .main_clk = "mmc0_fck",
1553 .clkdm_name = "l4ls_clkdm",
1554 .prcm = {
1555 .omap4 = {
1556 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1557 .modulemode = MODULEMODE_SWCTRL,
1558 },
1559 },
1560 .dev_attr = &am33xx_mmc0_dev_attr,
1561 .slaves = am33xx_mmc0_slaves,
1562 .slaves_cnt = ARRAY_SIZE(am33xx_mmc0_slaves),
1563 };
1565 /* mmc1 */
1566 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1567 { .irq = AM33XX_IRQ_MMCHS1 },
1568 { .irq = -1 }
1569 };
1571 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1572 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS1_W, },
1573 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS1_R, },
1574 { .dma_req = -1 }
1575 };
1577 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
1578 {
1579 .pa_start = AM33XX_MMC1_BASE,
1580 .pa_end = AM33XX_MMC1_BASE + SZ_4K - 1,
1581 .flags = ADDR_TYPE_RT
1582 },
1583 { }
1584 };
1586 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc1 = {
1587 .master = &am33xx_l4ls_hwmod,
1588 .slave = &am33xx_mmc1_hwmod,
1589 .clk = "mmc1_ick",
1590 .addr = am33xx_mmc1_addr_space,
1591 .user = OCP_USER_MPU,
1592 };
1594 static struct omap_hwmod_ocp_if *am33xx_mmc1_slaves[] = {
1595 &am33xx_l4ls__mmc1,
1596 };
1598 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1599 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1600 };
1602 static struct omap_hwmod am33xx_mmc1_hwmod = {
1603 .name = "mmc2",
1604 .class = &am33xx_mmc_hwmod_class,
1605 .mpu_irqs = am33xx_mmc1_irqs,
1606 .sdma_reqs = am33xx_mmc1_edma_reqs,
1607 .main_clk = "mmc1_fck",
1608 .clkdm_name = "l4ls_clkdm",
1609 .prcm = {
1610 .omap4 = {
1611 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1612 .modulemode = MODULEMODE_SWCTRL,
1613 },
1614 },
1615 .dev_attr = &am33xx_mmc1_dev_attr,
1616 .slaves = am33xx_mmc1_slaves,
1617 .slaves_cnt = ARRAY_SIZE(am33xx_mmc1_slaves),
1618 };
1620 /* mmc2 */
1621 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1622 { .irq = AM33XX_IRQ_MMCHS2 },
1623 { .irq = -1 }
1624 };
1626 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1627 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS2_W, },
1628 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS2_R, },
1629 { .dma_req = -1 }
1630 };
1632 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
1633 {
1634 .pa_start = AM33XX_MMC2_BASE,
1635 .pa_end = AM33XX_MMC2_BASE + SZ_64K - 1,
1636 .flags = ADDR_TYPE_RT
1637 },
1638 { }
1639 };
1641 static struct omap_hwmod_ocp_if am33xx_l3_main__mmc2 = {
1642 .master = &am33xx_l3_main_hwmod,
1643 .slave = &am33xx_mmc2_hwmod,
1644 .clk = "mmc2_ick",
1645 .addr = am33xx_mmc2_addr_space,
1646 .user = OCP_USER_MPU,
1647 };
1649 static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = {
1650 &am33xx_l3_main__mmc2,
1651 };
1653 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1654 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1655 };
1656 static struct omap_hwmod am33xx_mmc2_hwmod = {
1657 .name = "mmc3",
1658 .class = &am33xx_mmc_hwmod_class,
1659 .mpu_irqs = am33xx_mmc2_irqs,
1660 .sdma_reqs = am33xx_mmc2_edma_reqs,
1661 .main_clk = "mmc2_fck",
1662 .clkdm_name = "l3s_clkdm",
1663 .prcm = {
1664 .omap4 = {
1665 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1666 .modulemode = MODULEMODE_SWCTRL,
1667 },
1668 },
1669 .dev_attr = &am33xx_mmc2_dev_attr,
1670 .slaves = am33xx_mmc2_slaves,
1671 .slaves_cnt = ARRAY_SIZE(am33xx_mmc2_slaves),
1672 };
1674 /* Master interfaces on the MPU interconnect */
1675 static struct omap_hwmod_ocp_if *am33xx_l3_mpu_masters[] = {
1676 &am33xx_mpu__l3_slow,
1677 };
1679 /* mpu */
1680 static struct omap_hwmod am33xx_mpu_hwmod = {
1681 .name = "mpu",
1682 .class = &mpu_hwmod_class,
1683 .masters = am33xx_l3_mpu_masters,
1684 .masters_cnt = ARRAY_SIZE(am33xx_l3_mpu_masters),
1685 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1686 .main_clk = "mpu_fck",
1687 .clkdm_name = "mpu_clkdm",
1688 .prcm = {
1689 .omap4 = {
1690 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1691 .modulemode = MODULEMODE_SWCTRL,
1692 },
1693 },
1694 };
1696 /* 'ocmcram' class */
1697 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
1698 .name = "ocmcram",
1699 };
1701 /* ocmcram */
1702 static struct omap_hwmod am33xx_ocmcram_hwmod = {
1703 .name = "ocmcram",
1704 .class = &am33xx_ocmcram_hwmod_class,
1705 .main_clk = "ocmcram_fck",
1706 .clkdm_name = "l3_clkdm",
1707 .prcm = {
1708 .omap4 = {
1709 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
1710 .modulemode = MODULEMODE_SWCTRL,
1711 },
1712 },
1713 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1714 };
1716 /* 'ocpwp' class */
1717 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
1718 .name = "ocpwp",
1719 };
1721 /* ocpwp */
1722 static struct omap_hwmod am33xx_ocpwp_hwmod = {
1723 .name = "ocpwp",
1724 .class = &am33xx_ocpwp_hwmod_class,
1725 .main_clk = "ocpwp_fck",
1726 .clkdm_name = "l4ls_clkdm",
1727 .prcm = {
1728 .omap4 = {
1729 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
1730 .modulemode = MODULEMODE_SWCTRL,
1731 },
1732 },
1733 };
1735 /* 'rtc' class */
1736 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1737 .name = "rtc",
1738 };
1740 /* rtc */
1741 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1742 { .irq = AM33XX_IRQ_RTC_TIMER },
1743 { .irq = -1 }
1744 };
1746 static struct omap_hwmod am33xx_rtc_hwmod = {
1747 .name = "rtc",
1748 .class = &am33xx_rtc_hwmod_class,
1749 .mpu_irqs = am33xx_rtc_irqs,
1750 .main_clk = "rtc_fck",
1751 .clkdm_name = "l4_rtc_clkdm",
1752 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), /* ??? */
1753 .prcm = {
1754 .omap4 = {
1755 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1756 .modulemode = MODULEMODE_SWCTRL,
1757 },
1758 },
1759 };
1761 /* 'sha0' class */
1762 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
1763 .name = "sha0",
1764 };
1766 /* sha0 */
1767 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
1768 { .irq = AM33XX_IRQ_SHAEIP57t0_S },
1769 { .irq = -1 }
1770 };
1772 static struct omap_hwmod am33xx_sha0_hwmod = {
1773 .name = "sha0",
1774 .class = &am33xx_sha0_hwmod_class,
1775 .mpu_irqs = am33xx_sha0_irqs,
1776 .main_clk = "sha0_fck",
1777 .clkdm_name = "l3_clkdm",
1778 .prcm = {
1779 .omap4 = {
1780 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
1781 .modulemode = MODULEMODE_SWCTRL,
1782 },
1783 },
1784 };
1786 /* 'smartreflex' class */
1787 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
1788 .name = "smartreflex",
1789 };
1791 /* smartreflex0 */
1792 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
1793 { .irq = AM33XX_IRQ_SMARTREFLEX0 },
1794 { .irq = -1 }
1795 };
1797 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
1798 .name = "smartreflex0",
1799 .class = &am33xx_smartreflex_hwmod_class,
1800 .mpu_irqs = am33xx_smartreflex0_irqs,
1801 .main_clk = "smartreflex0_fck",
1802 .clkdm_name = "l4_wkup_clkdm",
1803 .prcm = {
1804 .omap4 = {
1805 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
1806 .modulemode = MODULEMODE_SWCTRL,
1807 },
1808 },
1809 };
1811 /* smartreflex1 */
1812 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
1813 { .irq = AM33XX_IRQ_SMARTREFLEX1 },
1814 { .irq = -1 }
1815 };
1817 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
1818 .name = "smartreflex1",
1819 .class = &am33xx_smartreflex_hwmod_class,
1820 .mpu_irqs = am33xx_smartreflex1_irqs,
1821 .main_clk = "smartreflex1_fck",
1822 .clkdm_name = "l4_wkup_clkdm",
1823 .prcm = {
1824 .omap4 = {
1825 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
1826 .modulemode = MODULEMODE_SWCTRL,
1827 },
1828 },
1829 };
1831 /* 'spi' class */
1833 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1834 .rev_offs = 0x0000,
1835 .sysc_offs = 0x0110,
1836 .syss_offs = 0x0114,
1837 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1838 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1839 SYSS_HAS_RESET_STATUS),
1840 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1841 .sysc_fields = &omap_hwmod_sysc_type1,
1842 };
1844 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1845 .name = "mcspi",
1846 .sysc = &am33xx_mcspi_sysc,
1847 .rev = OMAP4_MCSPI_REV,
1848 };
1850 /* spi0 */
1851 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1852 { .irq = AM33XX_IRQ_MCSPIOCP0 },
1853 { .irq = -1 }
1854 };
1856 struct omap_hwmod_dma_info am33xx_mcspi0_sdma_reqs[] = {
1857 { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0R },
1858 { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0W },
1859 { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1R },
1860 { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1W },
1861 { .dma_req = -1 }
1862 };
1864 struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
1865 {
1866 .pa_start = AM33XX_SPI0_BASE,
1867 .pa_end = AM33XX_SPI0_BASE + SZ_1K - 1,
1868 .flags = ADDR_TYPE_RT
1869 },
1870 { }
1871 };
1873 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = {
1874 .master = &am33xx_l4per_hwmod,
1875 .slave = &am33xx_spi0_hwmod,
1876 .clk = "spi0_ick",
1877 .addr = am33xx_mcspi0_addr_space,
1878 .user = OCP_USER_MPU,
1879 };
1881 static struct omap_hwmod_ocp_if *am33xx_mcspi0_slaves[] = {
1882 &am33xx_l4_core__mcspi0,
1883 };
1885 struct omap2_mcspi_dev_attr mcspi_attrib = {
1886 .num_chipselect = 2,
1887 };
1888 static struct omap_hwmod am33xx_spi0_hwmod = {
1889 .name = "spi0",
1890 .class = &am33xx_spi_hwmod_class,
1891 .mpu_irqs = am33xx_spi0_irqs,
1892 .sdma_reqs = am33xx_mcspi0_sdma_reqs,
1893 .main_clk = "spi0_fck",
1894 .clkdm_name = "l4ls_clkdm",
1895 .prcm = {
1896 .omap4 = {
1897 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1898 .modulemode = MODULEMODE_SWCTRL,
1899 },
1900 },
1901 .dev_attr = &mcspi_attrib,
1902 .slaves = am33xx_mcspi0_slaves,
1903 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi0_slaves),
1904 };
1906 /* spi1 */
1907 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1908 { .irq = AM33XX_IRQ_SPI1 },
1909 { .irq = -1 }
1910 };
1912 struct omap_hwmod_dma_info am33xx_mcspi1_sdma_reqs[] = {
1913 { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0R },
1914 { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0W },
1915 { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1R },
1916 { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1W },
1917 { .dma_req = -1 }
1918 };
1920 struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
1921 {
1922 .pa_start = AM33XX_SPI1_BASE,
1923 .pa_end = AM33XX_SPI1_BASE + SZ_1K - 1,
1924 .flags = ADDR_TYPE_RT
1925 },
1926 { }
1927 };
1929 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = {
1930 .master = &am33xx_l4per_hwmod,
1931 .slave = &am33xx_spi1_hwmod,
1932 .clk = "spi1_ick",
1933 .addr = am33xx_mcspi1_addr_space,
1934 .user = OCP_USER_MPU,
1935 };
1937 static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = {
1938 &am33xx_l4_core__mcspi1,
1939 };
1940 static struct omap_hwmod am33xx_spi1_hwmod = {
1941 .name = "spi1",
1942 .class = &am33xx_spi_hwmod_class,
1943 .mpu_irqs = am33xx_spi1_irqs,
1944 .sdma_reqs = am33xx_mcspi1_sdma_reqs,
1945 .main_clk = "spi1_fck",
1946 .clkdm_name = "l4ls_clkdm",
1947 .prcm = {
1948 .omap4 = {
1949 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1950 .modulemode = MODULEMODE_SWCTRL,
1951 },
1952 },
1953 .dev_attr = &mcspi_attrib,
1954 .slaves = am33xx_mcspi1_slaves,
1955 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi1_slaves),
1956 };
1958 /* 'spinlock' class */
1959 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1960 .name = "spinlock",
1961 };
1963 /* spinlock */
1964 static struct omap_hwmod am33xx_spinlock_hwmod = {
1965 .name = "spinlock",
1966 .class = &am33xx_spinlock_hwmod_class,
1967 .main_clk = "spinlock_fck",
1968 .clkdm_name = "l4ls_clkdm",
1969 .prcm = {
1970 .omap4 = {
1971 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1972 .modulemode = MODULEMODE_SWCTRL,
1973 },
1974 },
1975 };
1977 /* 'timer 0 & 2-7' class */
1978 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1979 .rev_offs = 0x0000,
1980 .sysc_offs = 0x0010,
1981 .syss_offs = 0x0014,
1982 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1983 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1984 SIDLE_SMART_WKUP),
1985 .sysc_fields = &omap_hwmod_sysc_type2,
1986 };
1988 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1989 .name = "timer",
1990 .sysc = &am33xx_timer_sysc,
1991 };
1993 /* timer0 */
1994 /* l4 wkup -> timer0 interface */
1995 static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = {
1996 {
1997 .pa_start = AM33XX_TIMER0_BASE,
1998 .pa_end = AM33XX_TIMER0_BASE + SZ_1K - 1,
1999 .flags = ADDR_TYPE_RT
2000 },
2001 { }
2002 };
2004 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = {
2005 .master = &am33xx_l4wkup_hwmod,
2006 .slave = &am33xx_timer0_hwmod,
2007 .clk = "timer0_ick",
2008 .addr = am33xx_timer0_addr_space,
2009 .user = OCP_USER_MPU,
2010 };
2012 static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = {
2013 &am33xx_l4wkup__timer0,
2014 };
2016 static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = {
2017 { .irq = AM33XX_IRQ_DMTIMER0 },
2018 { .irq = -1 }
2019 };
2021 static struct omap_hwmod am33xx_timer0_hwmod = {
2022 .name = "timer0",
2023 .class = &am33xx_timer_hwmod_class,
2024 .mpu_irqs = am33xx_timer0_irqs,
2025 .main_clk = "timer0_fck",
2026 .clkdm_name = "l4_wkup_clkdm",
2027 .prcm = {
2028 .omap4 = {
2029 .clkctrl_offs = AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET,
2030 .modulemode = MODULEMODE_SWCTRL,
2031 },
2032 },
2033 .slaves = am33xx_timer0_slaves,
2034 .slaves_cnt = ARRAY_SIZE(am33xx_timer0_slaves),
2035 };
2037 /* timer1 1ms */
2038 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
2039 .rev_offs = 0x0000,
2040 .sysc_offs = 0x0010,
2041 .syss_offs = 0x0014,
2042 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2043 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
2044 SYSS_HAS_RESET_STATUS),
2045 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2046 .sysc_fields = &omap_hwmod_sysc_type1,
2047 };
2049 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
2050 .name = "timer",
2051 .sysc = &am33xx_timer1ms_sysc,
2052 };
2054 /* l4 wkup -> timer1 interface */
2055 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
2056 {
2057 .pa_start = AM33XX_TIMER1_BASE,
2058 .pa_end = AM33XX_TIMER1_BASE + SZ_1K - 1,
2059 .flags = ADDR_TYPE_RT
2060 },
2061 { }
2062 };
2064 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = {
2065 .master = &am33xx_l4wkup_hwmod,
2066 .slave = &am33xx_timer1_hwmod,
2067 .clk = "timer1_ick",
2068 .addr = am33xx_timer1_addr_space,
2069 .user = OCP_USER_MPU,
2070 };
2072 static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = {
2073 &am33xx_l4wkup__timer1,
2074 };
2076 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
2077 { .irq = AM33XX_IRQ_DMTIMER1 },
2078 { .irq = -1 }
2079 };
2081 static struct omap_hwmod am33xx_timer1_hwmod = {
2082 .name = "timer1",
2083 .class = &am33xx_timer1ms_hwmod_class,
2084 .mpu_irqs = am33xx_timer1_irqs,
2085 .main_clk = "timer1_fck",
2086 .clkdm_name = "l4_wkup_clkdm",
2087 .prcm = {
2088 .omap4 = {
2089 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2090 .modulemode = MODULEMODE_SWCTRL,
2091 },
2092 },
2093 .slaves = am33xx_timer1_slaves,
2094 .slaves_cnt = ARRAY_SIZE(am33xx_timer1_slaves),
2095 };
2097 /* timer2 */
2098 /* l4 per -> timer2 interface */
2099 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
2100 {
2101 .pa_start = AM33XX_TIMER2_BASE,
2102 .pa_end = AM33XX_TIMER2_BASE + SZ_1K - 1,
2103 .flags = ADDR_TYPE_RT
2104 },
2105 { }
2106 };
2108 static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = {
2109 .master = &am33xx_l4per_hwmod,
2110 .slave = &am33xx_timer2_hwmod,
2111 .clk = "timer2_ick",
2112 .addr = am33xx_timer2_addr_space,
2113 .user = OCP_USER_MPU,
2114 };
2116 static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = {
2117 &am33xx_l4per__timer2,
2118 };
2120 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
2121 { .irq = AM33XX_IRQ_DMTIMER2 },
2122 { .irq = -1 }
2123 };
2125 static struct omap_hwmod am33xx_timer2_hwmod = {
2126 .name = "timer2",
2127 .class = &am33xx_timer_hwmod_class,
2128 .mpu_irqs = am33xx_timer2_irqs,
2129 .main_clk = "timer2_fck",
2130 .prcm = {
2131 .omap4 = {
2132 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
2133 .modulemode = MODULEMODE_SWCTRL,
2134 },
2135 },
2136 .slaves = am33xx_timer2_slaves,
2137 .slaves_cnt = ARRAY_SIZE(am33xx_timer2_slaves),
2138 .clkdm_name = "l4ls_clkdm",
2139 };
2141 /* timer3 */
2142 /* l4 per -> timer3 interface */
2143 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
2144 {
2145 .pa_start = AM33XX_TIMER3_BASE,
2146 .pa_end = AM33XX_TIMER3_BASE + SZ_1K - 1,
2147 .flags = ADDR_TYPE_RT
2148 },
2149 { }
2150 };
2152 static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = {
2153 .master = &am33xx_l4per_hwmod,
2154 .slave = &am33xx_timer3_hwmod,
2155 .clk = "timer3_ick",
2156 .addr = am33xx_timer3_addr_space,
2157 .user = OCP_USER_MPU,
2158 };
2160 static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = {
2161 &am33xx_l4per__timer3,
2162 };
2164 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
2165 { .irq = AM33XX_IRQ_DMTIMER3 },
2166 { .irq = -1 }
2167 };
2169 static struct omap_hwmod am33xx_timer3_hwmod = {
2170 .name = "timer3",
2171 .class = &am33xx_timer_hwmod_class,
2172 .mpu_irqs = am33xx_timer3_irqs,
2173 .main_clk = "timer3_fck",
2174 .clkdm_name = "l4ls_clkdm",
2175 .prcm = {
2176 .omap4 = {
2177 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
2178 .modulemode = MODULEMODE_SWCTRL,
2179 },
2180 },
2181 .slaves = am33xx_timer3_slaves,
2182 .slaves_cnt = ARRAY_SIZE(am33xx_timer3_slaves),
2183 };
2185 /* timer4 */
2186 /* l4 per -> timer4 interface */
2187 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
2188 {
2189 .pa_start = AM33XX_TIMER4_BASE,
2190 .pa_end = AM33XX_TIMER4_BASE + SZ_1K - 1,
2191 .flags = ADDR_TYPE_RT
2192 },
2193 { }
2194 };
2196 static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = {
2197 .master = &am33xx_l4per_hwmod,
2198 .slave = &am33xx_timer4_hwmod,
2199 .clk = "timer4_ick",
2200 .addr = am33xx_timer4_addr_space,
2201 .user = OCP_USER_MPU,
2202 };
2204 static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = {
2205 &am33xx_l4per__timer4,
2206 };
2208 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
2209 { .irq = AM33XX_IRQ_DMTIMER4 },
2210 { .irq = -1 }
2211 };
2213 static struct omap_hwmod am33xx_timer4_hwmod = {
2214 .name = "timer4",
2215 .class = &am33xx_timer_hwmod_class,
2216 .mpu_irqs = am33xx_timer4_irqs,
2217 .main_clk = "timer4_fck",
2218 .prcm = {
2219 .omap4 = {
2220 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
2221 .modulemode = MODULEMODE_SWCTRL,
2222 },
2223 },
2224 .slaves = am33xx_timer4_slaves,
2225 .slaves_cnt = ARRAY_SIZE(am33xx_timer4_slaves),
2226 .clkdm_name = "l4ls_clkdm",
2227 };
2230 /* timer5 */
2231 /* l4 per -> timer5 interface */
2232 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
2233 {
2234 .pa_start = AM33XX_TIMER5_BASE,
2235 .pa_end = AM33XX_TIMER5_BASE + SZ_1K - 1,
2236 .flags = ADDR_TYPE_RT
2237 },
2238 { }
2239 };
2241 static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = {
2242 .master = &am33xx_l4per_hwmod,
2243 .slave = &am33xx_timer5_hwmod,
2244 .clk = "timer5_ick",
2245 .addr = am33xx_timer5_addr_space,
2246 .user = OCP_USER_MPU,
2247 };
2249 static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = {
2250 &am33xx_l4per__timer5,
2251 };
2253 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
2254 { .irq = AM33XX_IRQ_DMTIMER5 },
2255 { .irq = -1 }
2256 };
2258 static struct omap_hwmod am33xx_timer5_hwmod = {
2259 .name = "timer5",
2260 .class = &am33xx_timer_hwmod_class,
2261 .mpu_irqs = am33xx_timer5_irqs,
2262 .main_clk = "timer5_fck",
2263 .prcm = {
2264 .omap4 = {
2265 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
2266 .modulemode = MODULEMODE_SWCTRL,
2267 },
2268 },
2269 .slaves = am33xx_timer5_slaves,
2270 .slaves_cnt = ARRAY_SIZE(am33xx_timer5_slaves),
2271 .clkdm_name = "l4ls_clkdm",
2272 };
2274 /* timer6 */
2275 /* l4 per -> timer6 interface */
2276 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
2277 {
2278 .pa_start = AM33XX_TIMER6_BASE,
2279 .pa_end = AM33XX_TIMER6_BASE + SZ_1K - 1,
2280 .flags = ADDR_TYPE_RT
2281 },
2282 { }
2283 };
2285 static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = {
2286 .master = &am33xx_l4per_hwmod,
2287 .slave = &am33xx_timer6_hwmod,
2288 .clk = "timer6_ick",
2289 .addr = am33xx_timer6_addr_space,
2290 .user = OCP_USER_MPU,
2291 };
2293 static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = {
2294 &am33xx_l4per__timer6,
2295 };
2297 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
2298 { .irq = AM33XX_IRQ_DMTIMER6 },
2299 { .irq = -1 }
2300 };
2302 static struct omap_hwmod am33xx_timer6_hwmod = {
2303 .name = "timer6",
2304 .class = &am33xx_timer_hwmod_class,
2305 .mpu_irqs = am33xx_timer6_irqs,
2306 .main_clk = "timer6_fck",
2307 .prcm = {
2308 .omap4 = {
2309 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
2310 .modulemode = MODULEMODE_SWCTRL,
2311 },
2312 },
2313 .slaves = am33xx_timer6_slaves,
2314 .slaves_cnt = ARRAY_SIZE(am33xx_timer6_slaves),
2315 .clkdm_name = "l4ls_clkdm",
2316 };
2318 /* timer7 */
2319 /* l4 per -> timer7 interface */
2320 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
2321 {
2322 .pa_start = AM33XX_TIMER7_BASE,
2323 .pa_end = AM33XX_TIMER7_BASE + SZ_1K - 1,
2324 .flags = ADDR_TYPE_RT
2325 },
2326 { }
2327 };
2329 static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = {
2330 .master = &am33xx_l4per_hwmod,
2331 .slave = &am33xx_timer7_hwmod,
2332 .clk = "timer7_ick",
2333 .addr = am33xx_timer7_addr_space,
2334 .user = OCP_USER_MPU,
2335 };
2337 static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = {
2338 &am33xx_l4per__timer7,
2339 };
2341 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
2342 { .irq = AM33XX_IRQ_DMTIMER7 },
2343 { .irq = -1 }
2344 };
2346 static struct omap_hwmod am33xx_timer7_hwmod = {
2347 .name = "timer7",
2348 .class = &am33xx_timer_hwmod_class,
2349 .mpu_irqs = am33xx_timer7_irqs,
2350 .main_clk = "timer7_fck",
2351 .prcm = {
2352 .omap4 = {
2353 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
2354 .modulemode = MODULEMODE_SWCTRL,
2355 },
2356 },
2357 .slaves = am33xx_timer7_slaves,
2358 .slaves_cnt = ARRAY_SIZE(am33xx_timer7_slaves),
2359 .clkdm_name = "l4ls_clkdm",
2360 };
2362 /* 'tpcc' class */
2363 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
2364 .name = "tpcc",
2365 };
2367 /* tpcc */
2368 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
2369 { .name = "edma0", .irq = AM33XX_IRQ_TPCC0_INT_PO0 },
2370 { .name = "edma0_err", .irq = AM33XX_IRQ_TPCC0_ERRINT_PO },
2371 { .irq = -1 },
2372 };
2374 /* TODO move this appropriate header. */
2375 #define AM33XX_TPCC_BASE 0x49000000
2377 static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
2378 {
2379 .pa_start = AM33XX_TPCC_BASE,
2380 .pa_end = AM33XX_TPCC_BASE + SZ_32K - 1,
2381 .flags = ADDR_TYPE_RT
2382 },
2383 { }
2384 };
2386 static struct omap_hwmod_ocp_if am33xx_l3_slow__tpcc = {
2387 .master = &am33xx_l3slow_hwmod,
2388 .slave = &am33xx_tpcc_hwmod,
2389 .addr = am33xx_tpcc_addr_space,
2390 .user = OCP_USER_MPU,
2391 };
2393 static struct omap_hwmod_ocp_if *am33xx_tpcc_slaves[] = {
2394 &am33xx_l3_slow__tpcc,
2395 };
2397 static struct omap_hwmod am33xx_tpcc_hwmod = {
2398 .name = "tpcc",
2399 .class = &am33xx_tpcc_hwmod_class,
2400 .mpu_irqs = am33xx_tpcc_irqs,
2401 .main_clk = "tpcc_ick",
2402 .clkdm_name = "l3_clkdm",
2403 .prcm = {
2404 .omap4 = {
2405 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
2406 .modulemode = MODULEMODE_SWCTRL,
2407 },
2408 },
2409 .slaves = am33xx_tpcc_slaves,
2410 .slaves_cnt = ARRAY_SIZE(am33xx_tpcc_slaves),
2411 };
2413 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
2414 .rev_offs = 0x0,
2415 .sysc_offs = 0x10,
2416 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2417 SYSC_HAS_MIDLEMODE),
2418 .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
2419 .sysc_fields = &omap_hwmod_sysc_type2,
2420 };
2422 /* 'tptc' class */
2423 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
2424 .name = "tptc",
2425 .sysc = &am33xx_tptc_sysc,
2426 };
2428 /* tptc0 */
2429 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
2430 { .irq = AM33XX_IRQ_TPTC0 },
2431 { .irq = -1 }
2432 };
2434 struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
2435 {
2436 .pa_start = 0x49800000,
2437 .pa_end = 0x49800000 + SZ_8K - 1,
2438 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2439 },
2440 { }
2441 };
2443 struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
2444 .master = &am33xx_l3_main_hwmod,
2445 .slave = &am33xx_tptc0_hwmod,
2446 .addr = am33xx_tptc0_addr_space,
2447 .user = OCP_USER_MPU,
2448 };
2450 static struct omap_hwmod_ocp_if *am33xx_tptc0_slaves[] = {
2451 &am33xx_l3_main__tptc0,
2452 };
2454 static struct omap_hwmod am33xx_tptc0_hwmod = {
2455 .name = "tptc0",
2456 .class = &am33xx_tptc_hwmod_class,
2457 .mpu_irqs = am33xx_tptc0_irqs,
2458 .main_clk = "tptc0_ick",
2459 .clkdm_name = "l3_clkdm",
2460 .prcm = {
2461 .omap4 = {
2462 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
2463 .modulemode = MODULEMODE_SWCTRL,
2464 },
2465 },
2466 .slaves = am33xx_tptc0_slaves,
2467 .slaves_cnt = ARRAY_SIZE(am33xx_tptc0_slaves),
2468 };
2470 /* tptc1 */
2471 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
2472 { .irq = AM33XX_IRQ_TPTC1 },
2473 { .irq = -1 }
2474 };
2476 struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
2477 {
2478 .pa_start = 0x49900000,
2479 .pa_end = 0x49900000 + SZ_8K - 1,
2480 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2481 },
2482 { }
2483 };
2485 struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
2486 .master = &am33xx_l3_main_hwmod,
2487 .slave = &am33xx_tptc1_hwmod,
2488 .addr = am33xx_tptc1_addr_space,
2489 .user = OCP_USER_MPU,
2490 };
2492 static struct omap_hwmod_ocp_if *am33xx_tptc1_slaves[] = {
2493 &am33xx_l3_main__tptc1,
2494 };
2496 static struct omap_hwmod am33xx_tptc1_hwmod = {
2497 .name = "tptc1",
2498 .class = &am33xx_tptc_hwmod_class,
2499 .mpu_irqs = am33xx_tptc1_irqs,
2500 .main_clk = "tptc1_ick",
2501 .clkdm_name = "l3_clkdm",
2502 .prcm = {
2503 .omap4 = {
2504 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
2505 .modulemode = MODULEMODE_SWCTRL,
2506 },
2507 },
2508 .slaves = am33xx_tptc1_slaves,
2509 .slaves_cnt = ARRAY_SIZE(am33xx_tptc1_slaves),
2510 };
2512 /* tptc2 */
2513 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
2514 { .irq = AM33XX_IRQ_TPTC2 },
2515 { .irq = -1 }
2516 };
2518 struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
2519 {
2520 .pa_start = 0x49a00000,
2521 .pa_end = 0x49a00000 + SZ_8K - 1,
2522 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2523 },
2524 { }
2525 };
2527 struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
2528 .master = &am33xx_l3_main_hwmod,
2529 .slave = &am33xx_tptc2_hwmod,
2530 .addr = am33xx_tptc2_addr_space,
2531 .user = OCP_USER_MPU,
2532 };
2534 static struct omap_hwmod_ocp_if *am33xx_tptc2_slaves[] = {
2535 &am33xx_l3_main__tptc2,
2536 };
2538 static struct omap_hwmod am33xx_tptc2_hwmod = {
2539 .name = "tptc2",
2540 .class = &am33xx_tptc_hwmod_class,
2541 .mpu_irqs = am33xx_tptc2_irqs,
2542 .main_clk = "tptc2_ick",
2543 .clkdm_name = "l3_clkdm",
2544 .prcm = {
2545 .omap4 = {
2546 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
2547 .modulemode = MODULEMODE_SWCTRL,
2548 },
2549 },
2550 .slaves = am33xx_tptc2_slaves,
2551 .slaves_cnt = ARRAY_SIZE(am33xx_tptc2_slaves),
2552 };
2554 /* 'uart' class */
2555 static struct omap_hwmod_class_sysconfig uart_sysc = {
2556 .rev_offs = 0x50,
2557 .sysc_offs = 0x54,
2558 .syss_offs = 0x58,
2559 .sysc_flags = (SYSC_HAS_SIDLEMODE |
2560 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2561 SYSC_HAS_AUTOIDLE),
2562 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2563 SIDLE_SMART_WKUP),
2564 .sysc_fields = &omap_hwmod_sysc_type1,
2565 };
2567 static struct omap_hwmod_class uart_class = {
2568 .name = "uart",
2569 .sysc = &uart_sysc,
2570 };
2572 /* uart1 */
2573 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
2574 { .name = "tx", .dma_req = 26, },
2575 { .name = "rx", .dma_req = 27, },
2576 { .dma_req = -1 }
2577 };
2579 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
2580 {
2581 .pa_start = AM33XX_UART1_BASE,
2582 .pa_end = AM33XX_UART1_BASE + SZ_8K - 1,
2583 .flags = ADDR_TYPE_RT
2584 },
2585 { }
2586 };
2588 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
2589 .master = &am33xx_l4wkup_hwmod,
2590 .slave = &am33xx_uart1_hwmod,
2591 .clk = "uart1_ick",
2592 .addr = am33xx_uart1_addr_space,
2593 .user = OCP_USER_MPU,
2594 };
2596 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
2597 { .irq = AM33XX_IRQ_UART0 },
2598 { .irq = -1 }
2599 };
2601 static struct omap_hwmod_ocp_if *am33xx_uart1_slaves[] = {
2602 &am33xx_l4_wkup__uart1,
2603 };
2605 static struct omap_hwmod am33xx_uart1_hwmod = {
2606 .name = "uart1",
2607 .class = &uart_class,
2608 .mpu_irqs = am33xx_uart1_irqs,
2609 .sdma_reqs = uart1_edma_reqs,
2610 .main_clk = "uart1_fck",
2611 .clkdm_name = "l4_wkup_clkdm",
2612 .prcm = {
2613 .omap4 = {
2614 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
2615 .modulemode = MODULEMODE_SWCTRL,
2616 },
2617 },
2618 .slaves = am33xx_uart1_slaves,
2619 .slaves_cnt = ARRAY_SIZE(am33xx_uart1_slaves),
2620 };
2622 /* uart2 */
2623 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
2624 {
2625 .pa_start = AM33XX_UART2_BASE,
2626 .pa_end = AM33XX_UART2_BASE + SZ_8K - 1,
2627 .flags = ADDR_TYPE_RT
2628 },
2629 { }
2630 };
2632 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
2633 .slave = &am33xx_uart2_hwmod,
2634 .clk = "uart2_ick",
2635 .addr = am33xx_uart2_addr_space,
2636 .user = OCP_USER_MPU,
2637 };
2639 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
2640 { .irq = AM33XX_IRQ_UART1 },
2641 { .irq = -1 }
2642 };
2644 static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = {
2645 &am33xx_l4_ls__uart2,
2646 };
2648 static struct omap_hwmod am33xx_uart2_hwmod = {
2649 .name = "uart2",
2650 .class = &uart_class,
2651 .mpu_irqs = am33xx_uart2_irqs,
2652 .main_clk = "uart2_fck",
2653 .clkdm_name = "l4ls_clkdm",
2654 .sdma_reqs = uart1_edma_reqs,
2655 .prcm = {
2656 .omap4 = {
2657 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
2658 .modulemode = MODULEMODE_SWCTRL,
2659 },
2660 },
2661 .slaves = am33xx_uart2_slaves,
2662 .slaves_cnt = ARRAY_SIZE(am33xx_uart2_slaves),
2663 };
2665 /* uart3 */
2666 static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
2667 { .name = "tx", .dma_req = 30, },
2668 { .name = "rx", .dma_req = 31, },
2669 { .dma_req = -1 }
2670 };
2672 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
2673 {
2674 .pa_start = AM33XX_UART3_BASE,
2675 .pa_end = AM33XX_UART3_BASE + SZ_8K - 1,
2676 .flags = ADDR_TYPE_RT
2677 },
2678 { }
2679 };
2681 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
2682 .slave = &am33xx_uart3_hwmod,
2683 .clk = "uart3_ick",
2684 .addr = am33xx_uart3_addr_space,
2685 .user = OCP_USER_MPU,
2686 };
2688 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2689 { .irq = AM33XX_IRQ_UART2 },
2690 { .irq = -1 }
2691 };
2693 static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = {
2694 &am33xx_l4_ls__uart3,
2695 };
2697 static struct omap_hwmod am33xx_uart3_hwmod = {
2698 .name = "uart3",
2699 .class = &uart_class,
2700 .mpu_irqs = am33xx_uart3_irqs,
2701 .main_clk = "uart3_fck",
2702 .clkdm_name = "l4ls_clkdm",
2703 .sdma_reqs = uart3_edma_reqs,
2704 .prcm = {
2705 .omap4 = {
2706 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
2707 .modulemode = MODULEMODE_SWCTRL,
2708 },
2709 },
2710 .slaves = am33xx_uart3_slaves,
2711 .slaves_cnt = ARRAY_SIZE(am33xx_uart3_slaves),
2712 };
2714 /* uart4 */
2715 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
2716 {
2717 .pa_start = AM33XX_UART4_BASE,
2718 .pa_end = AM33XX_UART4_BASE + SZ_8K - 1,
2719 .flags = ADDR_TYPE_RT
2720 },
2721 { }
2722 };
2724 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
2725 .slave = &am33xx_uart4_hwmod,
2726 .clk = "uart4_ick",
2727 .addr = am33xx_uart4_addr_space,
2728 .user = OCP_USER_MPU,
2729 };
2731 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2732 { .irq = AM33XX_IRQ_UART3 },
2733 { .irq = -1 }
2734 };
2736 static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = {
2737 &am33xx_l4_ls__uart4,
2738 };
2740 static struct omap_hwmod am33xx_uart4_hwmod = {
2741 .name = "uart4",
2742 .class = &uart_class,
2743 .mpu_irqs = am33xx_uart4_irqs,
2744 .main_clk = "uart4_fck",
2745 .clkdm_name = "l4ls_clkdm",
2746 .sdma_reqs = uart1_edma_reqs,
2747 .prcm = {
2748 .omap4 = {
2749 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
2750 .modulemode = MODULEMODE_SWCTRL,
2751 },
2752 },
2753 .slaves = am33xx_uart4_slaves,
2754 .slaves_cnt = ARRAY_SIZE(am33xx_uart4_slaves),
2755 };
2757 /* uart5 */
2758 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
2759 {
2760 .pa_start = AM33XX_UART5_BASE,
2761 .pa_end = AM33XX_UART5_BASE + SZ_8K - 1,
2762 .flags = ADDR_TYPE_RT
2763 },
2764 { }
2765 };
2767 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
2768 .slave = &am33xx_uart5_hwmod,
2769 .clk = "uart5_ick",
2770 .addr = am33xx_uart5_addr_space,
2771 .user = OCP_USER_MPU,
2772 };
2774 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2775 { .irq = AM33XX_IRQ_UART4 },
2776 { .irq = -1 }
2777 };
2779 static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = {
2780 &am33xx_l4_ls__uart5,
2781 };
2783 static struct omap_hwmod am33xx_uart5_hwmod = {
2784 .name = "uart5",
2785 .class = &uart_class,
2786 .mpu_irqs = am33xx_uart5_irqs,
2787 .main_clk = "uart5_fck",
2788 .clkdm_name = "l4ls_clkdm",
2789 .sdma_reqs = uart1_edma_reqs,
2790 .prcm = {
2791 .omap4 = {
2792 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2793 .modulemode = MODULEMODE_SWCTRL,
2794 },
2795 },
2796 .slaves = am33xx_uart5_slaves,
2797 .slaves_cnt = ARRAY_SIZE(am33xx_uart5_slaves),
2798 };
2800 /* uart6 */
2801 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
2802 {
2803 .pa_start = AM33XX_UART6_BASE,
2804 .pa_end = AM33XX_UART6_BASE + SZ_8K - 1,
2805 .flags = ADDR_TYPE_RT
2806 },
2807 { }
2808 };
2810 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
2811 .slave = &am33xx_uart6_hwmod,
2812 .clk = "uart6_ick",
2813 .addr = am33xx_uart6_addr_space,
2814 .user = OCP_USER_MPU,
2815 };
2817 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2818 { .irq = AM33XX_IRQ_UART5 },
2819 { .irq = -1 }
2820 };
2822 static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = {
2823 &am33xx_l4_ls__uart6,
2824 };
2826 static struct omap_hwmod am33xx_uart6_hwmod = {
2827 .name = "uart6",
2828 .class = &uart_class,
2829 .mpu_irqs = am33xx_uart6_irqs,
2830 .main_clk = "uart6_fck",
2831 .clkdm_name = "l4ls_clkdm",
2832 .sdma_reqs = uart1_edma_reqs,
2833 .prcm = {
2834 .omap4 = {
2835 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2836 .modulemode = MODULEMODE_SWCTRL,
2837 },
2838 },
2839 .slaves = am33xx_uart6_slaves,
2840 .slaves_cnt = ARRAY_SIZE(am33xx_uart6_slaves),
2841 };
2843 /* 'wd_timer' class */
2844 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2845 .name = "wd_timer",
2846 };
2848 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
2849 {
2850 .pa_start = AM33XX_WDT1_BASE,
2851 .pa_end = AM33XX_WDT1_BASE + SZ_4K - 1,
2852 .flags = ADDR_TYPE_RT
2853 },
2854 { }
2855 };
2857 /* l4_wkup -> wd_timer1 */
2858 static struct omap_hwmod_ocp_if am33xx_l4wkup__wd_timer1 = {
2859 .master = &am33xx_l4wkup_hwmod,
2860 .slave = &am33xx_wd_timer1_hwmod,
2861 .addr = am33xx_wd_timer1_addrs,
2862 .user = OCP_USER_MPU,
2863 };
2865 /* wd_timer1 slave ports */
2866 static struct omap_hwmod_ocp_if *am33xx_wd_timer1_slaves[] = {
2867 &am33xx_l4wkup__wd_timer1,
2868 };
2870 /* wd_timer1 */
2871 /*
2872 * TODO: device.c file uses hardcoded name for watchdog
2873 timer driver "wd_timer2, so we are also using
2874 same name as of now...
2875 */
2876 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2877 .name = "wd_timer2",
2878 .class = &am33xx_wd_timer_hwmod_class,
2879 .main_clk = "wd_timer1_fck",
2880 .clkdm_name = "l4_wkup_clkdm",
2881 .prcm = {
2882 .omap4 = {
2883 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2884 .modulemode = MODULEMODE_SWCTRL,
2885 },
2886 },
2887 .slaves = am33xx_wd_timer1_slaves,
2888 .slaves_cnt = ARRAY_SIZE(am33xx_wd_timer1_slaves),
2889 };
2891 /* wdt0 */
2892 static struct omap_hwmod_irq_info am33xx_wdt0_irqs[] = {
2893 { .irq = AM33XX_IRQ_WDT0 },
2894 { .irq = -1 },
2895 };
2897 static struct omap_hwmod am33xx_wdt0_hwmod = {
2898 .name = "wdt0",
2899 .class = &am33xx_wd_timer_hwmod_class,
2900 .mpu_irqs = am33xx_wdt0_irqs,
2901 .main_clk = "wdt0_fck",
2902 .clkdm_name = "l4_wkup_clkdm",
2903 .prcm = {
2904 .omap4 = {
2905 .clkctrl_offs = AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET,
2906 .modulemode = MODULEMODE_SWCTRL,
2907 },
2908 },
2909 };
2911 /* 'wkup_m3' class */
2912 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
2913 .name = "wkup_m3",
2914 };
2916 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
2917 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
2918 };
2920 /* wkup_m3 */
2921 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
2922 .name = "wkup_m3",
2923 .class = &am33xx_wkup_m3_hwmod_class,
2924 .clkdm_name = "l4_wkup_aon_clkdm",
2925 .main_clk = "wkup_m3_fck",
2926 .rst_lines = am33xx_wkup_m3_resets,
2927 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
2928 .prcm = {
2929 .omap4 = {
2930 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
2931 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
2932 .modulemode = MODULEMODE_SWCTRL,
2933 },
2934 },
2935 .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */
2936 };
2938 /* L3 SLOW -> USBSS interface */
2939 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
2940 {
2941 .name = "usbss",
2942 .pa_start = AM33XX_USBSS_BASE,
2943 .pa_end = AM33XX_USBSS_BASE + SZ_4K - 1,
2944 .flags = ADDR_TYPE_RT
2945 },
2946 {
2947 .name = "musb0",
2948 .pa_start = AM33XX_USB0_BASE,
2949 .pa_end = AM33XX_USB0_BASE + SZ_2K - 1,
2950 .flags = ADDR_TYPE_RT
2951 },
2952 {
2953 .name = "musb1",
2954 .pa_start = AM33XX_USB1_BASE,
2955 .pa_end = AM33XX_USB1_BASE + SZ_2K - 1,
2956 .flags = ADDR_TYPE_RT
2957 },
2958 { }
2959 };
2961 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2962 .rev_offs = 0x0,
2963 .sysc_offs = 0x10,
2964 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
2965 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2966 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2967 .sysc_fields = &omap_hwmod_sysc_type4,
2968 };
2970 static struct omap_hwmod_class am33xx_usbotg_class = {
2971 .name = "usbotg",
2972 .sysc = &am33xx_usbhsotg_sysc,
2973 };
2975 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2976 { .name = "usbss-irq", .irq = AM33XX_IRQ_USBSS, },
2977 { .name = "musb0-irq", .irq = AM33XX_IRQ_USB0, },
2978 { .name = "musb1-irq", .irq = AM33XX_IRQ_USB1, },
2979 { .irq = -1, },
2980 };
2982 static struct omap_hwmod_ocp_if am33xx_l3_slow__usbss = {
2983 .master = &am33xx_l3slow_hwmod,
2984 .slave = &am33xx_usbss_hwmod,
2985 .addr = am33xx_usbss_addr_space,
2986 .user = OCP_USER_MPU,
2987 .flags = OCPIF_SWSUP_IDLE,
2988 };
2990 static struct omap_hwmod_ocp_if *am33xx_usbss_slaves[] = {
2991 &am33xx_l3_slow__usbss,
2992 };
2994 static struct omap_hwmod_opt_clk usbss_opt_clks[] = {
2995 { .role = "clkdcoldo", .clk = "usbotg_fck" },
2996 };
2998 static struct omap_hwmod am33xx_usbss_hwmod = {
2999 .name = "usb_otg_hs",