arm: omap: am33xx: update TSC hwmod data
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / omap_hwmod_33xx_data.c
1 /*
2  * Hardware modules present on the AM33XX chips
3  *
4  * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
5  *
6  * This file is automatically generated from the AM33XX hardware databases.
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation version 2.
10  *
11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12  * kind, whether express or implied; without even the implied warranty
13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  */
17 #include <linux/io.h>
19 #include <plat/omap_hwmod.h>
20 #include <plat/i2c.h>
21 #include <plat/cpu.h>
22 #include <plat/gpio.h>
23 #include <plat/dma.h>
24 #include <plat/mmc.h>
25 #include <plat/mcspi.h>
27 #include "omap_hwmod_common_data.h"
28 #include "control.h"
29 #include "cm33xx.h"
30 #include "prm33xx.h"
32 /* Backward references (IPs with Bus Master capability) */
33 static struct omap_hwmod am33xx_mpu_hwmod;
34 static struct omap_hwmod am33xx_l3_main_hwmod;
35 static struct omap_hwmod am33xx_l3slow_hwmod;
36 static struct omap_hwmod am33xx_l4wkup_hwmod;
37 static struct omap_hwmod am33xx_l4per_hwmod;
38 static struct omap_hwmod am33xx_uart1_hwmod;
39 static struct omap_hwmod am33xx_uart2_hwmod;
40 static struct omap_hwmod am33xx_uart3_hwmod;
41 static struct omap_hwmod am33xx_uart4_hwmod;
42 static struct omap_hwmod am33xx_uart5_hwmod;
43 static struct omap_hwmod am33xx_uart6_hwmod;
44 static struct omap_hwmod am33xx_timer0_hwmod;
45 static struct omap_hwmod am33xx_timer1_hwmod;
46 static struct omap_hwmod am33xx_timer2_hwmod;
47 static struct omap_hwmod am33xx_timer3_hwmod;
48 static struct omap_hwmod am33xx_timer4_hwmod;
49 static struct omap_hwmod am33xx_timer5_hwmod;
50 static struct omap_hwmod am33xx_timer6_hwmod;
51 static struct omap_hwmod am33xx_timer7_hwmod;
52 static struct omap_hwmod am33xx_wd_timer1_hwmod;
53 static struct omap_hwmod am33xx_cpgmac0_hwmod;
54 static struct omap_hwmod am33xx_icss_hwmod;
55 static struct omap_hwmod am33xx_ieee5000_hwmod;
56 static struct omap_hwmod am33xx_tptc0_hwmod;
57 static struct omap_hwmod am33xx_tptc1_hwmod;
58 static struct omap_hwmod am33xx_tptc2_hwmod;
59 static struct omap_hwmod am33xx_gpio0_hwmod;
60 static struct omap_hwmod am33xx_gpio1_hwmod;
61 static struct omap_hwmod am33xx_gpio2_hwmod;
62 static struct omap_hwmod am33xx_gpio3_hwmod;
63 static struct omap_hwmod am33xx_i2c1_hwmod;
64 static struct omap_hwmod am33xx_i2c2_hwmod;
65 static struct omap_hwmod am33xx_i2c3_hwmod;
66 static struct omap_hwmod am33xx_usbss_hwmod;
67 static struct omap_hwmod am33xx_mmc0_hwmod;
68 static struct omap_hwmod am33xx_mmc1_hwmod;
69 static struct omap_hwmod am33xx_mmc2_hwmod;
70 static struct omap_hwmod am33xx_spi0_hwmod;
71 static struct omap_hwmod am33xx_spi1_hwmod;
72 static struct omap_hwmod am33xx_elm_hwmod;
73 static struct omap_hwmod am33xx_adc_tsc_hwmod;
74 static struct omap_hwmod am33xx_tpcc_hwmod;
75 static struct omap_hwmod am33xx_mcasp0_hwmod;
76 static struct omap_hwmod am33xx_mcasp1_hwmod;
77 static struct omap_hwmod am33xx_epwmss0_hwmod;
78 static struct omap_hwmod am33xx_epwmss1_hwmod;
79 static struct omap_hwmod am33xx_epwmss2_hwmod;
80 static struct omap_hwmod am33xx_gpmc_hwmod;
81 static struct omap_hwmod am33xx_lcdc_hwmod;
83 /*
84  * Interconnects hwmod structures
85  * hwmods that compose the global AM33XX OCP interconnect
86  */
88 /* MPU -> L3_SLOW Peripheral interface */
89 static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = {
90         .master         = &am33xx_mpu_hwmod,
91         .slave          = &am33xx_l3slow_hwmod,
92         .user           = OCP_USER_MPU,
93 };
95 /* L3 SLOW -> L4_PER Peripheral interface */
96 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = {
97         .master         = &am33xx_l3slow_hwmod,
98         .slave          = &am33xx_l4per_hwmod,
99         .user           = OCP_USER_MPU,
100 };
102 /* L3 SLOW -> L4_WKUP Peripheral interface */
103 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = {
104         .master         = &am33xx_l3slow_hwmod,
105         .slave          = &am33xx_l4wkup_hwmod,
106         .user           = OCP_USER_MPU,
107 };
109 /* Master interfaces on the L4_WKUP interconnect */
110 static struct omap_hwmod_ocp_if *am33xx_l3_slow_masters[] = {
111         &am33xx_l3_slow__l4_per,
112         &am33xx_l3_slow__l4_wkup,
113 };
115 /* Slave interfaces on the L3_SLOW interconnect */
116 static struct omap_hwmod_ocp_if *am33xx_l3_slow_slaves[] = {
117         &am33xx_mpu__l3_slow,
118 };
120 static struct omap_hwmod am33xx_l3slow_hwmod = {
121         .name           = "l3_slow",
122         .class          = &l3_hwmod_class,
123         .clkdm_name     = "l3s_clkdm",
124         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
125         .masters        = am33xx_l3_slow_masters,
126         .masters_cnt    = ARRAY_SIZE(am33xx_l3_slow_masters),
127         .slaves         = am33xx_l3_slow_slaves,
128         .slaves_cnt     = ARRAY_SIZE(am33xx_l3_slow_slaves),
129 };
131 /* L4 PER -> GPIO2 */
132 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
133         {
134                 .pa_start       = AM33XX_GPIO1_BASE,
135                 .pa_end         = AM33XX_GPIO1_BASE + SZ_4K - 1,
136                 .flags          = ADDR_TYPE_RT
137         },
138         { }
139 };
141 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
142         .master         = &am33xx_l4per_hwmod,
143         .slave          = &am33xx_gpio1_hwmod,
144         .clk            = "l4ls_fck",
145         .addr           = am33xx_gpio1_addrs,
146         .user           = OCP_USER_MPU | OCP_USER_SDMA,
147 };
149 /* L4 PER -> GPIO3 */
150 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
151         {
152                 .pa_start       = AM33XX_GPIO2_BASE,
153                 .pa_end         = AM33XX_GPIO2_BASE + SZ_4K - 1,
154                 .flags          = ADDR_TYPE_RT
155         },
156         { }
157 };
159 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
160         .master         = &am33xx_l4per_hwmod,
161         .slave          = &am33xx_gpio2_hwmod,
162         .clk            = "l4ls_fck",
163         .addr           = am33xx_gpio2_addrs,
164         .user           = OCP_USER_MPU | OCP_USER_SDMA,
165 };
167 /* L4 PER -> GPIO4 */
168 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
169         {
170                 .pa_start       = AM33XX_GPIO3_BASE,
171                 .pa_end         = AM33XX_GPIO3_BASE + SZ_4K - 1,
172                 .flags          = ADDR_TYPE_RT
173         },
174         { }
175 };
177 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
178         .master         = &am33xx_l4per_hwmod,
179         .slave          = &am33xx_gpio3_hwmod,
180         .clk            = "l4ls_fck",
181         .addr           = am33xx_gpio3_addrs,
182         .user           = OCP_USER_MPU | OCP_USER_SDMA,
183 };
185 /* Master interfaces on the L4_PER interconnect */
186 static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = {
187         &am33xx_l4_per__gpio1,
188         &am33xx_l4_per__gpio2,
189         &am33xx_l4_per__gpio3,
190 };
191 /* Slave interfaces on the L4_PER interconnect */
192 static struct omap_hwmod_ocp_if *am33xx_l4_per_slaves[] = {
193         &am33xx_l3_slow__l4_per,
194 };
196 static struct omap_hwmod am33xx_l4per_hwmod = {
197         .name           = "l4_per",
198         .class          = &l4_hwmod_class,
199         .clkdm_name     = "l4ls_clkdm",
200         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
201         .masters        = am33xx_l4_per_masters,
202         .masters_cnt    = ARRAY_SIZE(am33xx_l4_per_masters),
203         .slaves         = am33xx_l4_per_slaves,
204         .slaves_cnt     = ARRAY_SIZE(am33xx_l4_per_slaves),
205 };
207 /* L4 WKUP -> I2C1 */
208 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
209         {
210                 .pa_start       = AM33XX_I2C0_BASE,
211                 .pa_end         = AM33XX_I2C0_BASE + SZ_4K - 1,
212                 .flags          = ADDR_TYPE_RT
213         },
214         { }
215 };
217 static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = {
218         .master         = &am33xx_l4wkup_hwmod,
219         .slave          = &am33xx_i2c1_hwmod,
220         .addr           = am33xx_i2c1_addr_space,
221         .user           = OCP_USER_MPU,
222 };
224 /* L4 WKUP -> GPIO1 */
225 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
226         {
227                 .pa_start       = AM33XX_GPIO0_BASE,
228                 .pa_end         = AM33XX_GPIO0_BASE + SZ_4K - 1,
229                 .flags          = ADDR_TYPE_RT
230         },
231         { }
232 };
234 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
235         .master         = &am33xx_l4wkup_hwmod,
236         .slave          = &am33xx_gpio0_hwmod,
237         .clk            = "l4ls_fck",
238         .addr           = am33xx_gpio0_addrs,
239         .user           = OCP_USER_MPU | OCP_USER_SDMA,
240 };
242 /* L4 WKUP -> ADC_TSC */
243 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
244         {
245                 .pa_start       = AM33XX_TSC_BASE,
246                 .pa_end         = AM33XX_TSC_BASE + SZ_8K - 1,
247                 .flags          = ADDR_TYPE_RT
248         },
249         { }
250 };
252 static struct omap_hwmod_ocp_if am33xx_l4_wkup_adc_tsc = {
253         .master         = &am33xx_l4wkup_hwmod,
254         .slave          = &am33xx_adc_tsc_hwmod,
255         .addr           = am33xx_adc_tsc_addrs,
256         .user           = OCP_USER_MPU,
257 };
259 /* Master interfaces on the L4_WKUP interconnect */
260 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = {
261         &am33xx_l4_wkup__gpio0,
262 };
263 /* Slave interfaces on the L4_WKUP interconnect */
264 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_slaves[] = {
265         &am33xx_l3_slow__l4_wkup,
266 };
268 static struct omap_hwmod am33xx_l4wkup_hwmod = {
269         .name           = "l4_wkup",
270         .class          = &l4_hwmod_class,
271         .clkdm_name     = "l4_wkup_clkdm",
272         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
273         .masters        = am33xx_l4_wkup_masters,
274         .masters_cnt    = ARRAY_SIZE(am33xx_l4_wkup_masters),
275         .slaves         = am33xx_l4_wkup_slaves,
276         .slaves_cnt     = ARRAY_SIZE(am33xx_l4_wkup_slaves),
277 };
279 /* 'adc_tsc' class */
280 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
281         .rev_offs       = 0x00,
282         .sysc_offs      = 0x10,
283         .sysc_flags     = SYSC_HAS_SIDLEMODE,
284         .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
285                                 SIDLE_SMART | SIDLE_SMART_WKUP),
286         .sysc_fields    = &omap_hwmod_sysc_type2,
287 };
289 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
290         .name           = "adc_tsc",
291         .sysc           = &am33xx_adc_tsc_sysc,
292 };
294 /* adc_tsc */
295 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
296         { .irq = AM33XX_IRQ_TSC },
297         { .irq = -1 }
298 };
300 static struct omap_hwmod_ocp_if *am33xx_adc_tsc_slaves[] = {
301         &am33xx_l4_wkup_adc_tsc,
302 };
304 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
305         .name           = "adc_tsc",
306         .class          = &am33xx_adc_tsc_hwmod_class,
307         .mpu_irqs       = am33xx_adc_tsc_irqs,
308         .main_clk       = "adc_tsc_fck",
309         .clkdm_name     = "l4_wkup_clkdm",
310         .prcm           = {
311                 .omap4  = {
312                         .clkctrl_offs   = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
313                         .modulemode     = MODULEMODE_SWCTRL,
314                 },
315         },
316         .flags          = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
317         .slaves         = am33xx_adc_tsc_slaves,
318         .slaves_cnt     = ARRAY_SIZE(am33xx_adc_tsc_slaves),
319 };
321 /* 'aes' class */
322 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
323         .name           = "aes",
324 };
326 /* aes0 */
327 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
328         { .irq = AM33XX_IRQ_AESEIP36t0_S },
329         { .irq = -1 }
330 };
332 static struct omap_hwmod am33xx_aes0_hwmod = {
333         .name           = "aes0",
334         .class          = &am33xx_aes_hwmod_class,
335         .mpu_irqs       = am33xx_aes0_irqs,
336         .main_clk       = "aes0_fck",
337         .clkdm_name     = "l3_clkdm",
338         .prcm           = {
339                 .omap4  = {
340                         .clkctrl_offs   = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
341                         .modulemode     = MODULEMODE_SWCTRL,
342                 },
343         },
344 };
346 /* 'cefuse' class */
347 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
348         .name           = "cefuse",
349 };
351 /* cefuse */
352 static struct omap_hwmod am33xx_cefuse_hwmod = {
353         .name           = "cefuse",
354         .class          = &am33xx_cefuse_hwmod_class,
355         .main_clk       = "cefuse_fck",
356         .clkdm_name     = "l4_cefuse_clkdm",
357         .prcm           = {
358                 .omap4  = {
359                         .clkctrl_offs   = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
360                         .modulemode     = MODULEMODE_SWCTRL,
361                 },
362         },
363 };
365 /* 'clkdiv32k' class */
366 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
367         .name           = "clkdiv32k",
368 };
370 /* clkdiv32k */
371 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
372         .name           = "clkdiv32k",
373         .class          = &am33xx_clkdiv32k_hwmod_class,
374         .main_clk       = "clkdiv32k_fck",
375         .clkdm_name     = "clk_24mhz_clkdm",
376         .prcm           = {
377                 .omap4  = {
378                         .clkctrl_offs   = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
379                         .modulemode     = MODULEMODE_SWCTRL,
380                 },
381         },
382 };
384 /* 'control' class */
385 static struct omap_hwmod_class am33xx_control_hwmod_class = {
386         .name           = "control",
387 };
389 /* control */
390 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
391         { .irq = AM33XX_IRQ_CONTROL_PLATFORM },
392         { .irq = -1 }
393 };
395 static struct omap_hwmod am33xx_control_hwmod = {
396         .name           = "control",
397         .class          = &am33xx_control_hwmod_class,
398         .mpu_irqs       = am33xx_control_irqs,
399         .main_clk       = "control_fck",
400         .clkdm_name     = "l4_wkup_clkdm",
401         .prcm           = {
402                 .omap4  = {
403                         .clkctrl_offs   = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
404                         .modulemode     = MODULEMODE_SWCTRL,
405                 },
406         },
407         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
408 };
410 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
411         .rev_offs       = 0x0,
412         .sysc_offs      = 0x8,
413         .syss_offs      = 0x4,
414         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE
415                                 | SYSS_HAS_RESET_STATUS),
416         .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
417                                 MSTANDBY_FORCE | MSTANDBY_NO),
418         .sysc_fields    = &omap_hwmod_sysc_type3,
419 };
421 /* 'cpgmac' class */
422 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
423         .name           = "cpgmac0",
424         .sysc           = &am33xx_cpgmac_sysc,
425 };
427 /* cpgmac0 - has 4 IRQs */
428 #if 0
429 static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
430         { .irq = AM33XX_IRQ_TPTC0 },
431         { .irq = -1 }
432 };
433 #endif
435 struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
436         {
437                 .pa_start       = AM33XX_CPSW_SS_BASE,
438                 .pa_end         = AM33XX_CPSW_SS_BASE + SZ_8K - 1,
439                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
440         },
441         { }
442 };
444 struct omap_hwmod_ocp_if am33xx_l3_main__cpgmac0 = {
445         .master         = &am33xx_l3_main_hwmod,
446         .slave          = &am33xx_cpgmac0_hwmod,
447         .addr           = am33xx_cpgmac0_addr_space,
448         .user           = OCP_USER_MPU,
449 };
451 static struct omap_hwmod_ocp_if *am33xx_cpgmac0_slaves[] = {
452         &am33xx_l3_main__cpgmac0,
453 };
455 /* cpgmac0 */
456 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
457         .name           = "cpgmac0",
458         .class          = &am33xx_cpgmac0_hwmod_class,
459         .main_clk       = "cpgmac0_fck",
460         .clkdm_name     = "cpsw_125mhz_clkdm",
461         .prcm           = {
462                 .omap4  = {
463                         .clkctrl_offs   = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
464                         .modulemode     = MODULEMODE_SWCTRL,
465                 },
466         },
467         .slaves         = am33xx_cpgmac0_slaves,
468         .slaves_cnt     = ARRAY_SIZE(am33xx_cpgmac0_slaves),
469 };
471 /* 'dcan' class */
472 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
473         .name           = "dcan",
474 };
476 /* dcan0 */
477 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
478         { .irq = AM33XX_IRQ_DCAN0_0 },
479         { .irq = -1 }
480 };
482 static struct omap_hwmod am33xx_dcan0_hwmod = {
483         .name           = "dcan0",
484         .class          = &am33xx_dcan_hwmod_class,
485         .mpu_irqs       = am33xx_dcan0_irqs,
486         .main_clk       = "dcan0_fck",
487         .clkdm_name     = "l4ls_clkdm",
488         .prcm           = {
489                 .omap4  = {
490                         .clkctrl_offs   = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
491                         .modulemode     = MODULEMODE_SWCTRL,
492                 },
493         },
494 };
496 /* dcan1 */
497 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
498         { .irq = AM33XX_IRQ_DCAN1_0 },
499         { .irq = -1 }
500 };
501 static struct omap_hwmod am33xx_dcan1_hwmod = {
502         .name           = "dcan1",
503         .class          = &am33xx_dcan_hwmod_class,
504         .mpu_irqs       = am33xx_dcan1_irqs,
505         .main_clk       = "dcan1_fck",
506         .clkdm_name     = "l4ls_clkdm",
507         .prcm           = {
508                 .omap4  = {
509                         .clkctrl_offs   = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
510                         .modulemode     = MODULEMODE_SWCTRL,
511                 },
512         },
513 };
515 /* 'debugss' class */
516 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
517         .name           = "debugss",
518 };
520 /* debugss */
521 static struct omap_hwmod am33xx_debugss_hwmod = {
522         .name           = "debugss",
523         .class          = &am33xx_debugss_hwmod_class,
524         .main_clk       = "debugss_fck",
525         .clkdm_name     = "l3_aon_clkdm",
526         .prcm           = {
527                 .omap4  = {
528                         .clkctrl_offs   = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
529                         .modulemode     = MODULEMODE_SWCTRL,
530                 },
531         },
532 #ifdef CONFIG_DEBUG_JTAG_ENABLE
533         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
534 #endif
535 };
537 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
538         .rev_offs       = 0x0000,
539         .sysc_offs      = 0x0010,
540         .syss_offs      = 0x0014,
541         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
542                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
543                         SYSS_HAS_RESET_STATUS),
544         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
545         .sysc_fields    = &omap_hwmod_sysc_type1,
546 };
547 /* 'elm' class */
548 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
549         .name           = "elm",
550         .sysc           = &am33xx_elm_sysc,
551 };
553 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
554         { .irq = AM33XX_IRQ_ELM },
555         { .irq = -1 }
556 };
558 struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
559         {
560                 .pa_start       = AM33XX_ELM_BASE,
561                 .pa_end         = AM33XX_ELM_BASE + SZ_8K - 1,
562                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
563         },
564         { }
565 };
567 struct omap_hwmod_ocp_if am33xx_l4_core__elm = {
568         .master         = &am33xx_l4per_hwmod,
569         .slave          = &am33xx_elm_hwmod,
570         .addr           = am33xx_elm_addr_space,
571         .user           = OCP_USER_MPU,
572 };
574 static struct omap_hwmod_ocp_if *am33xx_elm_slaves[] = {
575         &am33xx_l4_core__elm,
576 };
578 /* elm */
579 static struct omap_hwmod am33xx_elm_hwmod = {
580         .name           = "elm",
581         .class          = &am33xx_elm_hwmod_class,
582         .mpu_irqs       = am33xx_elm_irqs,
583         .main_clk       = "elm_fck",
584         .clkdm_name     = "l4ls_clkdm",
585         .slaves         = am33xx_elm_slaves,
586         .slaves_cnt     = ARRAY_SIZE(am33xx_elm_slaves),
587         .prcm           = {
588                 .omap4  = {
589                         .clkctrl_offs   = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
590                         .modulemode     = MODULEMODE_SWCTRL,
591                 },
592         },
593 };
595 /* 'emif_fw' class */
596 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
597         .name           = "emif_fw",
598 };
600 /* emif_fw */
601 static struct omap_hwmod am33xx_emif_fw_hwmod = {
602         .name           = "emif_fw",
603         .class          = &am33xx_emif_fw_hwmod_class,
604         .main_clk       = "emif_fw_fck",
605         .clkdm_name     = "l4fw_clkdm",
606         .prcm           = {
607                 .omap4  = {
608                         .clkctrl_offs   = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
609                         .modulemode     = MODULEMODE_SWCTRL,
610                 },
611         },
612         .flags          = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
613 };
615 /* 'epwmss' class */
616 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
617         .rev_offs       = 0x0,
618         .sysc_offs      = 0x10,
619         .sysc_flags     = SYSC_HAS_SIDLEMODE,
620         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
621                         SIDLE_SMART_WKUP),
622         .sysc_fields    = &omap_hwmod_sysc_type2,
623 };
625 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
626         .name           = "epwmss",
627         .sysc           = &am33xx_epwmss_sysc,
628 };
630 /* epwmss0 */
631 static struct omap_hwmod_irq_info am33xx_epwmss0_irqs[] = {
632         { .irq          = AM33XX_IRQ_PWMSS0_EPWM },
633         { .irq          = AM33XX_IRQ_PWMSS0 },
634         { .irq          = AM33XX_IRQ_PWMSS0_ECAP },
635         { .irq          = -1 }
636 };
638 struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
639         {
640                 .pa_start       = AM33XX_EPWMSS0_BASE,
641                 .pa_end         = AM33XX_EPWMSS0_BASE + SZ_4K - 1,
642                 .flags          = ADDR_TYPE_RT
643         },
644         { }
645 };
647 struct omap_hwmod_ocp_if am33xx_l4_core__epwmss0 = {
648         .master         = &am33xx_l4per_hwmod,
649         .slave          = &am33xx_epwmss0_hwmod,
650         .addr           = am33xx_epwmss0_addr_space,
651         .user           = OCP_USER_MPU,
652 };
654 static struct omap_hwmod_ocp_if *am33xx_epwmss0_slaves[] = {
655         &am33xx_l4_core__epwmss0,
656 };
658 static struct omap_hwmod am33xx_epwmss0_hwmod = {
659         .name           = "epwmss0",
660         .mpu_irqs       = am33xx_epwmss0_irqs,
661         .class          = &am33xx_epwmss_hwmod_class,
662         .main_clk       = "epwmss0_fck",
663         .clkdm_name     = "l4ls_clkdm",
664         .prcm           = {
665                 .omap4  = {
666                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
667                         .modulemode     = MODULEMODE_SWCTRL,
668                 },
669         },
670         .slaves         = am33xx_epwmss0_slaves,
671         .slaves_cnt     = ARRAY_SIZE(am33xx_epwmss0_slaves),
672 };
674 /* epwmss1 */
675 static struct omap_hwmod_irq_info am33xx_epwmss1_irqs[] = {
676         { .irq          = AM33XX_IRQ_PWMSS1_EPWM },
677         { .irq          = AM33XX_IRQ_PWMSS1 },
678         { .irq          = AM33XX_IRQ_PWMSS1_ECAP },
679         { .irq          = -1 }
680 };
682 struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
683         {
684                 .pa_start       = AM33XX_EPWMSS1_BASE,
685                 .pa_end         = AM33XX_EPWMSS1_BASE + SZ_4K - 1,
686                 .flags          = ADDR_TYPE_RT
687         },
688         { }
689 };
691 struct omap_hwmod_ocp_if am33xx_l4_core__epwmss1 = {
692         .master         = &am33xx_l4per_hwmod,
693         .slave          = &am33xx_epwmss1_hwmod,
694         .addr           = am33xx_epwmss1_addr_space,
695         .user           = OCP_USER_MPU,
696 };
698 static struct omap_hwmod_ocp_if *am33xx_epwmss1_slaves[] = {
699         &am33xx_l4_core__epwmss1,
700 };
702 static struct omap_hwmod am33xx_epwmss1_hwmod = {
703         .name           = "epwmss1",
704         .mpu_irqs       = am33xx_epwmss1_irqs,
705         .class          = &am33xx_epwmss_hwmod_class,
706         .main_clk       = "epwmss1_fck",
707         .clkdm_name     = "l4ls_clkdm",
708         .prcm           = {
709                 .omap4  = {
710                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
711                         .modulemode     = MODULEMODE_SWCTRL,
712                 },
713         },
714         .slaves         = am33xx_epwmss1_slaves,
715         .slaves_cnt     = ARRAY_SIZE(am33xx_epwmss1_slaves),
716 };
718 /* epwmss2 */
719 static struct omap_hwmod_irq_info am33xx_epwmss2_irqs[] = {
720         { .irq          = AM33XX_IRQ_PWMSS2_EPWM },
721         { .irq          = AM33XX_IRQ_PWMSS2 },
722         { .irq          = AM33XX_IRQ_PWMSS2_ECAP },
723         { .irq          = -1 }
724 };
726 struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
727         {
728                 .pa_start       = AM33XX_EPWMSS2_BASE,
729                 .pa_end         = AM33XX_EPWMSS2_BASE + SZ_4K - 1,
730                 .flags          = ADDR_TYPE_RT
731         },
732         { }
733 };
735 struct omap_hwmod_ocp_if am33xx_l4_core__epwmss2 = {
736         .master         = &am33xx_l4per_hwmod,
737         .slave          = &am33xx_epwmss2_hwmod,
738         .addr           = am33xx_epwmss2_addr_space,
739         .user           = OCP_USER_MPU,
740 };
742 static struct omap_hwmod_ocp_if *am33xx_epwmss2_slaves[] = {
743         &am33xx_l4_core__epwmss2,
744 };
746 static struct omap_hwmod am33xx_epwmss2_hwmod = {
747         .name           = "epwmss2",
748         .mpu_irqs       = am33xx_epwmss2_irqs,
749         .class          = &am33xx_epwmss_hwmod_class,
750         .main_clk       = "epwmss2_fck",
751         .clkdm_name     = "l4ls_clkdm",
752         .prcm           = {
753                 .omap4  = {
754                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
755                         .modulemode     = MODULEMODE_SWCTRL,
756                 },
757         },
758         .slaves         = am33xx_epwmss2_slaves,
759         .slaves_cnt     = ARRAY_SIZE(am33xx_epwmss2_slaves),
760 };
762 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
763         .rev_offs       = 0x0000,
764         .sysc_offs      = 0x0010,
765         .syss_offs      = 0x0114,
766         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
767                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
768         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
769                                 SIDLE_SMART_WKUP),
770         .sysc_fields    = &omap_hwmod_sysc_type1,
771 };
773 /* 'gpio' class */
774 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
775         .name           = "gpio",
776         .sysc           = &am33xx_gpio_sysc,
777         .rev            = 2,
778 };
780 /* gpio dev_attr */
781 static struct omap_gpio_dev_attr gpio_dev_attr = {
782         .bank_width     = 32,
783         .dbck_flag      = true,
784 };
786 /* gpio0 */
787 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
788         { .irq = AM33XX_IRQ_GPIO0_1 },
789         { .irq = -1 }
790 };
792 /* gpio0 slave ports */
793 static struct omap_hwmod_ocp_if *am33xx_gpio0_slaves[] = {
794         &am33xx_l4_wkup__gpio0,
795 };
797 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
798         { .role = "dbclk", .clk = "gpio0_dbclk" },
799         { .role = "fclk", .clk = "gpio0_fck" },
800 };
802 /* gpio0 */
803 static struct omap_hwmod am33xx_gpio0_hwmod = {
804         .name           = "gpio1",
805         .class          = &am33xx_gpio_hwmod_class,
806         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
807         .mpu_irqs       = am33xx_gpio0_irqs,
808         .main_clk       = "gpio0_fck",
809         .clkdm_name     = "l4_wkup_clkdm",
810         .prcm           = {
811                 .omap4  = {
812                         .clkctrl_offs   = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
813                         .modulemode     = MODULEMODE_SWCTRL,
814                 },
815         },
816         .opt_clks       = gpio0_opt_clks,
817         .opt_clks_cnt   = ARRAY_SIZE(gpio0_opt_clks),
818         .dev_attr       = &gpio_dev_attr,
819         .slaves         = am33xx_gpio0_slaves,
820         .slaves_cnt     = ARRAY_SIZE(am33xx_gpio0_slaves),
821 };
823 /* gpio1 */
824 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
825         { .irq = AM33XX_IRQ_GPIO1_1 },
826         { .irq = -1 }
827 };
829 /* gpio1 slave ports */
830 static struct omap_hwmod_ocp_if *am33xx_gpio1_slaves[] = {
831         &am33xx_l4_per__gpio1,
832 };
834 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
835         { .role = "dbclk", .clk = "gpio1_dbclk" },
836         { .role = "fclk", .clk = "gpio1_fck" },
837 };
839 static struct omap_hwmod am33xx_gpio1_hwmod = {
840         .name           = "gpio2",
841         .class          = &am33xx_gpio_hwmod_class,
842         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
843         .mpu_irqs       = am33xx_gpio1_irqs,
844         .main_clk       = "gpio1_fck",
845         .clkdm_name     = "l4ls_clkdm",
846         .prcm           = {
847                 .omap4  = {
848                         .clkctrl_offs   = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
849                         .modulemode     = MODULEMODE_SWCTRL,
850                 },
851         },
852         .opt_clks       = gpio1_opt_clks,
853         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
854         .dev_attr       = &gpio_dev_attr,
855         .slaves         = am33xx_gpio1_slaves,
856         .slaves_cnt     = ARRAY_SIZE(am33xx_gpio1_slaves),
857 };
859 /* gpio2 */
860 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
861         { .irq = AM33XX_IRQ_GPIO2_1 },
862         { .irq = -1 }
863 };
865 /* gpio2 slave ports */
866 static struct omap_hwmod_ocp_if *am33xx_gpio2_slaves[] = {
867         &am33xx_l4_per__gpio2,
868 };
870 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
871         { .role = "dbclk", .clk = "gpio2_dbclk" },
872         { .role = "fclk", .clk = "gpio2_fck" },
873 };
875 /* gpio2 */
876 static struct omap_hwmod am33xx_gpio2_hwmod = {
877         .name           = "gpio3",
878         .class          = &am33xx_gpio_hwmod_class,
879         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
880         .mpu_irqs       = am33xx_gpio2_irqs,
881         .main_clk       = "gpio2_fck",
882         .clkdm_name     = "l4ls_clkdm",
883         .prcm           = {
884                 .omap4  = {
885                         .clkctrl_offs   = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
886                         .modulemode     = MODULEMODE_SWCTRL,
887                 },
888         },
889         .opt_clks       = gpio2_opt_clks,
890         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
891         .dev_attr       = &gpio_dev_attr,
892         .slaves         = am33xx_gpio2_slaves,
893         .slaves_cnt     = ARRAY_SIZE(am33xx_gpio2_slaves),
894 };
896 /* gpio3 */
897 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
898         { .irq = AM33XX_IRQ_GPIO3_1 },
899         { .irq = -1 }
900 };
902 /* gpio3 slave ports */
903 static struct omap_hwmod_ocp_if *am33xx_gpio3_slaves[] = {
904         &am33xx_l4_per__gpio3,
905 };
907 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
908         { .role = "dbclk", .clk = "gpio3_dbclk" },
909         { .role = "fclk", .clk = "gpio3_fck" },
910 };
912 /* gpio3 */
913 static struct omap_hwmod am33xx_gpio3_hwmod = {
914         .name           = "gpio4",
915         .class          = &am33xx_gpio_hwmod_class,
916         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
917         .mpu_irqs       = am33xx_gpio3_irqs,
918         .main_clk       = "gpio3_fck",
919         .clkdm_name     = "l4ls_clkdm",
920         .prcm           = {
921                 .omap4  = {
922                         .clkctrl_offs   = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
923                         .modulemode     = MODULEMODE_SWCTRL,
924                 },
925         },
926         .opt_clks       = gpio3_opt_clks,
927         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
928         .dev_attr       = &gpio_dev_attr,
929         .slaves         = am33xx_gpio3_slaves,
930         .slaves_cnt     = ARRAY_SIZE(am33xx_gpio3_slaves),
931 };
933 /* 'gpmc' class */
934 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
935         .rev_offs       = 0x0,
936         .sysc_offs      = 0x10,
937         .syss_offs      = 0x14,
938         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
939                                 SYSC_HAS_MIDLEMODE | SYSC_HAS_SOFTRESET |
940                                 SYSS_HAS_RESET_STATUS),
941         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
942                                 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
943         .sysc_fields    = &omap_hwmod_sysc_type4,
944 };
946 struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
947         {
948                 .pa_start       = 0x50000000,
949                 .pa_end         = 0x50000000 + SZ_8K - 1,
950                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
951         },
952         { }
953 };
955 struct omap_hwmod_ocp_if am33xx_l3_main__gpmc = {
956         .master         = &am33xx_l3_main_hwmod,
957         .slave          = &am33xx_gpmc_hwmod,
958         .addr           = am33xx_gpmc_addr_space,
959         .user           = OCP_USER_MPU,
960 };
962 static struct omap_hwmod_ocp_if *am33xx_gpmc_slaves[] = {
963         &am33xx_l3_main__gpmc,
964 };
966 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
967         .name           = "gpmc",
968         .sysc           = &gpmc_sysc,
969 };
971 /* gpmc */
972 static struct omap_hwmod am33xx_gpmc_hwmod = {
973         .name           = "gpmc",
974         .class          = &am33xx_gpmc_hwmod_class,
975         .main_clk       = "gpmc_fck",
976         .clkdm_name     = "l3s_clkdm",
977         .prcm           = {
978                 .omap4  = {
979                         .clkctrl_offs   = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
980                         .modulemode     = MODULEMODE_SWCTRL,
981                 },
982         },
983         .slaves         = am33xx_gpmc_slaves,
984         .slaves_cnt     = ARRAY_SIZE(am33xx_gpmc_slaves),
985 };
987 /* 'i2c' class */
989 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
990         .sysc_offs      = 0x0010,
991         .syss_offs      = 0x0090,
992         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
993                         SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
994                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
995         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
996                         SIDLE_SMART_WKUP),
997         .sysc_fields    = &omap_hwmod_sysc_type1,
998 };
1000 static struct omap_i2c_dev_attr i2c_dev_attr = {
1001         .flags          = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1002 };
1004 static struct omap_hwmod_class i2c_class = {
1005         .name           = "i2c",
1006         .sysc           = &am33xx_i2c_sysc,
1007         .rev            = OMAP_I2C_IP_VERSION_2,
1008         .reset          = &omap_i2c_reset,
1009 };
1011 /* I2C1 */
1012 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1013         { .irq = AM33XX_IRQ_MSHSI2COCP0 },
1014         { .irq = -1 }
1015 };
1017 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
1018         { .name = "tx", .dma_req = 0, },
1019         { .name = "rx", .dma_req = 0, },
1020         { .dma_req = -1 }
1021 };
1023 static struct omap_hwmod_ocp_if *am33xx_i2c1_slaves[] = {
1024         &am33xx_l4_wkup_i2c1,
1025 };
1027 static struct omap_hwmod am33xx_i2c1_hwmod = {
1028         .name           = "i2c1",
1029         .mpu_irqs       = i2c1_mpu_irqs,
1030         .sdma_reqs      = i2c1_edma_reqs,
1031         .main_clk       = "i2c1_fck",
1032         .clkdm_name     = "l4_wkup_clkdm",
1033         .prcm           = {
1034                 .omap4  = {
1035                         .clkctrl_offs   = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
1036                         .modulemode     = MODULEMODE_SWCTRL,
1037                 },
1038         },
1039         .flags          = HWMOD_16BIT_REG,
1040         .dev_attr       = &i2c_dev_attr,
1041         .slaves         = am33xx_i2c1_slaves,
1042         .slaves_cnt     = ARRAY_SIZE(am33xx_i2c1_slaves),
1043         .class          = &i2c_class,
1044 };
1046 /* i2c2 */
1047 /* l4 per -> i2c2 */
1048 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
1049         {
1050                 .pa_start       = AM33XX_I2C1_BASE,
1051                 .pa_end         = AM33XX_I2C1_BASE + SZ_4K - 1,
1052                 .flags          = ADDR_TYPE_RT
1053         },
1054         { }
1055 };
1057 static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = {
1058         .master         = &am33xx_l4per_hwmod,
1059         .slave          = &am33xx_i2c2_hwmod,
1060         .addr           = am33xx_i2c2_addr_space,
1061         .user           = OCP_USER_MPU,
1062 };
1064 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1065         { .irq = AM33XX_IRQ_MSHSI2COCP1 },
1066         { .irq = -1 }
1067 };
1069 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
1070         { .name = "tx", .dma_req = 0, },
1071         { .name = "rx", .dma_req = 0, },
1072         { .dma_req = -1 }
1073 };
1075 static struct omap_hwmod_ocp_if *am33xx_i2c2_slaves[] = {
1076         &am335_l4_per_i2c2,
1077 };
1079 static struct omap_hwmod am33xx_i2c2_hwmod = {
1080         .name           = "i2c2",
1081         .mpu_irqs       = i2c2_mpu_irqs,
1082         .sdma_reqs      = i2c2_edma_reqs,
1083         .main_clk       = "i2c2_fck",
1084         .clkdm_name     = "l4ls_clkdm",
1085         .prcm           = {
1086                 .omap4 = {
1087                         .clkctrl_offs   = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
1088                         .modulemode     = MODULEMODE_SWCTRL,
1089                 },
1090         },
1091         .flags          = HWMOD_16BIT_REG,
1092         .dev_attr       = &i2c_dev_attr,
1093         .slaves         = am33xx_i2c2_slaves,
1094         .slaves_cnt     = ARRAY_SIZE(am33xx_i2c2_slaves),
1095         .class          = &i2c_class,
1096 };
1098 /* i2c3 */
1099 /* l4 per -> i2c3 */
1100 static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
1101         {
1102                 .pa_start       = AM33XX_I2C2_BASE,
1103                 .pa_end         = AM33XX_I2C2_BASE + SZ_4K - 1,
1104                 .flags          = ADDR_TYPE_RT
1105         },
1106         { }
1107 };
1109 static struct omap_hwmod_ocp_if am335_l4_per_i2c3 = {
1110         .master         = &am33xx_l4per_hwmod,
1111         .slave          = &am33xx_i2c3_hwmod,
1112         .addr           = am33xx_i2c3_addr_space,
1113         .user           = OCP_USER_MPU,
1114 };
1116 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1117         { .irq = AM33XX_IRQ_MSHSI2COCP2 },
1118         { .irq = -1 }
1119 };
1121 static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
1122         { .name = "tx", .dma_req = 0, },
1123         { .name = "rx", .dma_req = 0, },
1124         { .dma_req = -1 }
1125 };
1127 static struct omap_hwmod_ocp_if *am33xx_i2c3_slaves[] = {
1128         &am335_l4_per_i2c3,
1129 };
1131 static struct omap_hwmod am33xx_i2c3_hwmod = {
1132         .name           = "i2c3",
1133         .mpu_irqs       = i2c3_mpu_irqs,
1134         .sdma_reqs      = i2c3_edma_reqs,
1135         .main_clk       = "i2c3_fck",
1136         .clkdm_name     = "l4ls_clkdm",
1137         .prcm           = {
1138                 .omap4 = {
1139                         .clkctrl_offs   = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
1140                         .modulemode     = MODULEMODE_SWCTRL,
1141                 },
1142         },
1143         .flags          = HWMOD_16BIT_REG,
1144         .dev_attr       = &i2c_dev_attr,
1145         .slaves         = am33xx_i2c3_slaves,
1146         .slaves_cnt     = ARRAY_SIZE(am33xx_i2c3_slaves),
1147         .class          = &i2c_class,
1148 };
1150 /* 'icss' class */
1151 static struct omap_hwmod_class am33xx_icss_hwmod_class = {
1152         .name = "icss",
1153 };
1155 /* icss */
1156 static struct omap_hwmod am33xx_icss_hwmod = {
1157         .name           = "icss",
1158         .class          = &am33xx_icss_hwmod_class,
1159         .main_clk       = "icss_fck",
1160         .clkdm_name     = "icss_ocp_clkdm",
1161         .prcm           = {
1162                 .omap4  = {
1163                         .clkctrl_offs   = AM33XX_CM_PER_ICSS_CLKCTRL_OFFSET,
1164                         .modulemode     = MODULEMODE_SWCTRL,
1165                 },
1166         },
1167 };
1169 /* 'ieee5000' class */
1170 static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = {
1171         .name           = "ieee5000",
1172 };
1174 /* ieee5000 */
1175 static struct omap_hwmod am33xx_ieee5000_hwmod = {
1176         .name           = "ieee5000",
1177         .class          = &am33xx_ieee5000_hwmod_class,
1178         .main_clk       = "ieee5000_fck",
1179         .clkdm_name     = "l3s_clkdm",
1180         .prcm           = {
1181                 .omap4  = {
1182                         .clkctrl_offs   = AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET,
1183                         .modulemode     = MODULEMODE_SWCTRL,
1184                 },
1185         },
1186 };
1189 /* 'l3' class */
1190 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
1191         .name           = "l3",
1192 };
1194 /* l4_hs */
1195 static struct omap_hwmod am33xx_l4_hs_hwmod = {
1196         .name           = "l4_hs",
1197         .class          = &am33xx_l3_hwmod_class,
1198         .clkdm_name     = "l4hs_clkdm",
1199         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1200         .prcm           = {
1201                 .omap4  = {
1202                         .clkctrl_offs   = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
1203                         .modulemode     = MODULEMODE_SWCTRL,
1204                 },
1205         },
1206 };
1208 /* l3_instr */
1209 static struct omap_hwmod am33xx_l3_instr_hwmod = {
1210         .name           = "l3_instr",
1211         .class          = &am33xx_l3_hwmod_class,
1212         .clkdm_name     = "l3_clkdm",
1213         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1214         .prcm           = {
1215                 .omap4  = {
1216                         .clkctrl_offs   = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
1217                         .modulemode     = MODULEMODE_SWCTRL,
1218                 },
1219         },
1220 };
1222 /* l3_main */
1223 static struct omap_hwmod am33xx_l3_main_hwmod = {
1224         .name           = "l3_main",
1225         .class          = &am33xx_l3_hwmod_class,
1226         .clkdm_name     = "l3_clkdm",
1227         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1228         .prcm           = {
1229                 .omap4  = {
1230                         .clkctrl_offs   = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
1231                         .modulemode     = MODULEMODE_SWCTRL,
1232                 },
1233         },
1234 };
1236 /* 'l4fw' class */
1237 static struct omap_hwmod_class am33xx_l4fw_hwmod_class = {
1238         .name           = "l4fw",
1239 };
1241 /* l4fw */
1242 static struct omap_hwmod am33xx_l4fw_hwmod = {
1243         .name           = "l4fw",
1244         .class          = &am33xx_l4fw_hwmod_class,
1245         .clkdm_name     = "l4fw_clkdm",
1246         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1247         .prcm           = {
1248                 .omap4  = {
1249                         .clkctrl_offs   = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
1250                         .modulemode     = MODULEMODE_SWCTRL,
1251                 },
1252         },
1253 };
1255 /* 'l4ls' class */
1256 static struct omap_hwmod_class am33xx_l4ls_hwmod_class = {
1257         .name           = "l4ls",
1258 };
1260 /* l4ls */
1261 static struct omap_hwmod am33xx_l4ls_hwmod = {
1262         .name           = "l4ls",
1263         .class          = &am33xx_l4ls_hwmod_class,
1264         .main_clk       = "l4ls_fck",
1265         .clkdm_name     = "l4ls_clkdm",
1266         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1267         .prcm           = {
1268                 .omap4  = {
1269                         .clkctrl_offs   = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
1270                         .modulemode     = MODULEMODE_SWCTRL,
1271                 },
1272         },
1273 };
1275 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
1276         .rev_offs       = 0x0,
1277         .sysc_offs      = 0x54,
1278         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
1279         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1280         .sysc_fields    = &omap_hwmod_sysc_type2,
1281 };
1283 /* 'lcdc' class */
1284 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1285         .name           = "lcdc",
1286         .sysc           = &lcdc_sysc,
1287 };
1289 /* lcdc */
1290 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1291         { .irq = AM33XX_IRQ_LCD },
1292         { .irq = -1 }
1293 };
1295 struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
1296         {
1297                 .pa_start       = 0x4830E000,
1298                 .pa_end         = 0x4830E000 + SZ_8K - 1,
1299                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
1300         },
1301         { }
1302 };
1304 struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
1305         .master         = &am33xx_l3_main_hwmod,
1306         .slave          = &am33xx_lcdc_hwmod,
1307         .addr           = am33xx_lcdc_addr_space,
1308         .user           = OCP_USER_MPU,
1309 };
1311 static struct omap_hwmod_ocp_if *am33xx_lcdc_slaves[] = {
1312         &am33xx_l3_main__lcdc,
1313 };
1315 static struct omap_hwmod am33xx_lcdc_hwmod = {
1316         .name           = "lcdc",
1317         .class          = &am33xx_lcdc_hwmod_class,
1318         .mpu_irqs       = am33xx_lcdc_irqs,
1319         .main_clk       = "lcdc_fck",
1320         .clkdm_name     = "lcdc_clkdm",
1321         .prcm           = {
1322                 .omap4  = {
1323                         .clkctrl_offs   = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1324                         .modulemode     = MODULEMODE_SWCTRL,
1325                 },
1326         },
1327         .slaves         = am33xx_lcdc_slaves,
1328         .slaves_cnt     = ARRAY_SIZE(am33xx_lcdc_slaves),
1329 };
1331 /*
1332  * 'mailbox' class
1333  * mailbox module allowing communication between the on-chip processors using a
1334  * queued mailbox-interrupt mechanism.
1335  */
1337 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1338         .rev_offs       = 0x0000,
1339         .sysc_offs      = 0x0010,
1340         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1341                            SYSC_HAS_SOFTRESET),
1342         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1343         .sysc_fields    = &omap_hwmod_sysc_type2,
1344 };
1346 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1347         .name   = "mailbox",
1348         .sysc   = &am33xx_mailbox_sysc,
1349 };
1351 /* mailbox */
1352 static struct omap_hwmod am33xx_mailbox_hwmod;
1353 static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1354         { .irq = AM33XX_IRQ_MAILBOX },
1355         { .irq = -1 }
1356 };
1358 static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
1359         {
1360                 .pa_start       = AM33XX_MAILBOX0_BASE,
1361                 .pa_end         = AM33XX_MAILBOX0_BASE + (SZ_4K - 1),
1362                 .flags          = ADDR_TYPE_RT
1363         },
1364         { }
1365 };
1367 /* l4_cfg -> mailbox */
1368 static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
1369         .master         = &am33xx_l4per_hwmod,
1370         .slave          = &am33xx_mailbox_hwmod,
1371         .addr           = am33xx_mailbox_addrs,
1372         .user           = OCP_USER_MPU,
1373 };
1375 /* mailbox slave ports */
1376 static struct omap_hwmod_ocp_if *am33xx_mailbox_slaves[] = {
1377         &am33xx_l4_per__mailbox,
1378 };
1380 static struct omap_hwmod am33xx_mailbox_hwmod = {
1381         .name           = "mailbox",
1382         .class          = &am33xx_mailbox_hwmod_class,
1383         .clkdm_name     = "l4ls_clkdm",
1384         .mpu_irqs       = am33xx_mailbox_irqs,
1385         .main_clk       = "mailbox0_fck",
1386         .prcm = {
1387                 .omap4 = {
1388                         .clkctrl_offs   = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1389                         .modulemode     = MODULEMODE_SWCTRL,
1390                 },
1391         },
1392         .slaves         = am33xx_mailbox_slaves,
1393         .slaves_cnt     = ARRAY_SIZE(am33xx_mailbox_slaves),
1394 };
1396 /* 'mcasp' class */
1397 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1398         .name           = "mcasp",
1399 };
1401 /* mcasp0 */
1402 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1403         { .name = "ax", .irq = AM33XX_IRQ_MCASP0_AX, },
1404         { .name = "ar", .irq = AM33XX_IRQ_MCASP0_AR, },
1405         { .irq = -1 }
1406 };
1408 static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
1409         {
1410                 .pa_start       = AM33XX_ASP0_BASE,
1411                 .pa_end         = AM33XX_ASP0_BASE + (SZ_1K * 12) - 1,
1412                 .flags          = ADDR_TYPE_RT
1413         },
1414         { }
1415 };
1417 static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp0 = {
1418         .master         = &am33xx_l3slow_hwmod,
1419         .slave          = &am33xx_mcasp0_hwmod,
1420         .clk            = "mcasp0_ick",
1421         .addr           = am33xx_mcasp0_addr_space,
1422         .user           = OCP_USER_MPU,
1423 };
1425 static struct omap_hwmod_ocp_if *am33xx_mcasp0_slaves[] = {
1426         &am33xx_l3_slow__mcasp0,
1427 };
1429 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1430         .name           = "mcasp0",
1431         .class          = &am33xx_mcasp_hwmod_class,
1432         .mpu_irqs       = am33xx_mcasp0_irqs,
1433         .main_clk       = "mcasp0_fck",
1434         .clkdm_name     = "l3s_clkdm",
1435         .prcm           = {
1436                 .omap4  = {
1437                         .clkctrl_offs   = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1438                         .modulemode     = MODULEMODE_SWCTRL,
1439                 },
1440         },
1441         .slaves         = am33xx_mcasp0_slaves,
1442         .slaves_cnt     = ARRAY_SIZE(am33xx_mcasp0_slaves),
1443 };
1445 /* mcasp1 */
1446 static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
1447         { .name = "ax", .irq = AM33XX_IRQ_MCASP1_AX, },
1448         { .name = "ar", .irq = AM33XX_IRQ_MCASP1_AR, },
1449         { .irq = -1 }
1450 };
1452 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
1453         {
1454                 .pa_start       = AM33XX_ASP1_BASE,
1455                 .pa_end         = AM33XX_ASP1_BASE + (SZ_1K * 12) - 1,
1456                 .flags          = ADDR_TYPE_RT
1457         },
1458         { }
1459 };
1461 static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp1 = {
1462         .master         = &am33xx_l3slow_hwmod,
1463         .slave          = &am33xx_mcasp1_hwmod,
1464         .clk            = "mcasp1_ick",
1465         .addr           = am33xx_mcasp1_addr_space,
1466         .user           = OCP_USER_MPU,
1467 };
1469 static struct omap_hwmod_ocp_if *am33xx_mcasp1_slaves[] = {
1470         &am33xx_l3_slow__mcasp1,
1471 };
1473 static struct omap_hwmod am33xx_mcasp1_hwmod = {
1474         .name           = "mcasp1",
1475         .class          = &am33xx_mcasp_hwmod_class,
1476         .mpu_irqs       = am33xx_mcasp1_irqs,
1477         .main_clk       = "mcasp1_fck",
1478         .clkdm_name     = "l3s_clkdm",
1479         .prcm           = {
1480                 .omap4  = {
1481                         .clkctrl_offs   = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
1482                         .modulemode     = MODULEMODE_SWCTRL,
1483                 },
1484         },
1485         .slaves         = am33xx_mcasp1_slaves,
1486         .slaves_cnt     = ARRAY_SIZE(am33xx_mcasp1_slaves),
1487 };
1490 /* 'mmc' class */
1492 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1493         .rev_offs       = 0x1fc,
1494         .sysc_offs      = 0x10,
1495         .syss_offs      = 0x14,
1496         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1497                         SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1498                         SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1499         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1500         .sysc_fields    = &omap_hwmod_sysc_type1,
1501 };
1503 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1504         .name           = "mmc",
1505         .sysc           = &am33xx_mmc_sysc,
1506 };
1508 /* mmc0 */
1509 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1510         { .irq = AM33XX_IRQ_MMCHS0 },
1511         { .irq = -1 }
1512 };
1514 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1515         { .name = "tx", .dma_req = AM33XX_DMA_MMCHS0_W, },
1516         { .name = "rx", .dma_req = AM33XX_DMA_MMCHS0_R, },
1517         { .dma_req = -1 }
1518 };
1520 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
1521         {
1522                 .pa_start       = AM33XX_MMC0_BASE,
1523                 .pa_end         = AM33XX_MMC0_BASE + SZ_4K - 1,
1524                 .flags          = ADDR_TYPE_RT
1525         },
1526         { }
1527 };
1529 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc0 = {
1530         .master         = &am33xx_l4ls_hwmod,
1531         .slave          = &am33xx_mmc0_hwmod,
1532         .clk            = "mmc0_ick",
1533         .addr           = am33xx_mmc0_addr_space,
1534         .user           = OCP_USER_MPU,
1535 };
1537 static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = {
1538         &am33xx_l4ls__mmc0,
1539 };
1541 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1542         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1543 };
1545 static struct omap_hwmod am33xx_mmc0_hwmod = {
1546         .name           = "mmc1",
1547         .class          = &am33xx_mmc_hwmod_class,
1548         .mpu_irqs       = am33xx_mmc0_irqs,
1549         .sdma_reqs      = am33xx_mmc0_edma_reqs,
1550         .main_clk       = "mmc0_fck",
1551         .clkdm_name     = "l4ls_clkdm",
1552         .prcm           = {
1553                 .omap4  = {
1554                         .clkctrl_offs   = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1555                         .modulemode     = MODULEMODE_SWCTRL,
1556                 },
1557         },
1558         .dev_attr       = &am33xx_mmc0_dev_attr,
1559         .slaves         = am33xx_mmc0_slaves,
1560         .slaves_cnt     = ARRAY_SIZE(am33xx_mmc0_slaves),
1561 };
1563 /* mmc1 */
1564 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1565         { .irq = AM33XX_IRQ_MMCHS1 },
1566         { .irq = -1 }
1567 };
1569 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1570         { .name = "tx", .dma_req = AM33XX_DMA_MMCHS1_W, },
1571         { .name = "rx", .dma_req = AM33XX_DMA_MMCHS1_R, },
1572         { .dma_req = -1 }
1573 };
1575 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
1576         {
1577                 .pa_start       = AM33XX_MMC1_BASE,
1578                 .pa_end         = AM33XX_MMC1_BASE + SZ_4K - 1,
1579                 .flags          = ADDR_TYPE_RT
1580         },
1581         { }
1582 };
1584 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc1 = {
1585         .master         = &am33xx_l4ls_hwmod,
1586         .slave          = &am33xx_mmc1_hwmod,
1587         .clk            = "mmc1_ick",
1588         .addr           = am33xx_mmc1_addr_space,
1589         .user           = OCP_USER_MPU,
1590 };
1592 static struct omap_hwmod_ocp_if *am33xx_mmc1_slaves[] = {
1593         &am33xx_l4ls__mmc1,
1594 };
1596 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1597         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1598 };
1600 static struct omap_hwmod am33xx_mmc1_hwmod = {
1601         .name           = "mmc2",
1602         .class          = &am33xx_mmc_hwmod_class,
1603         .mpu_irqs       = am33xx_mmc1_irqs,
1604         .sdma_reqs      = am33xx_mmc1_edma_reqs,
1605         .main_clk       = "mmc1_fck",
1606         .clkdm_name     = "l4ls_clkdm",
1607         .prcm           = {
1608                 .omap4  = {
1609                         .clkctrl_offs   = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1610                         .modulemode     = MODULEMODE_SWCTRL,
1611                 },
1612         },
1613         .dev_attr       = &am33xx_mmc1_dev_attr,
1614         .slaves         = am33xx_mmc1_slaves,
1615         .slaves_cnt     = ARRAY_SIZE(am33xx_mmc1_slaves),
1616 };
1618 /* mmc2 */
1619 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1620         { .irq = AM33XX_IRQ_MMCHS2 },
1621         { .irq = -1 }
1622 };
1624 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1625         { .name = "tx", .dma_req = AM33XX_DMA_MMCHS2_W, },
1626         { .name = "rx", .dma_req = AM33XX_DMA_MMCHS2_R, },
1627         { .dma_req = -1 }
1628 };
1630 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
1631         {
1632                 .pa_start       = AM33XX_MMC2_BASE,
1633                 .pa_end         = AM33XX_MMC2_BASE + SZ_64K - 1,
1634                 .flags          = ADDR_TYPE_RT
1635         },
1636         { }
1637 };
1639 static struct omap_hwmod_ocp_if am33xx_l3_main__mmc2 = {
1640         .master         = &am33xx_l3_main_hwmod,
1641         .slave          = &am33xx_mmc2_hwmod,
1642         .clk            = "mmc2_ick",
1643         .addr           = am33xx_mmc2_addr_space,
1644         .user           = OCP_USER_MPU,
1645 };
1647 static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = {
1648         &am33xx_l3_main__mmc2,
1649 };
1651 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1652         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1653 };
1654 static struct omap_hwmod am33xx_mmc2_hwmod = {
1655         .name           = "mmc3",
1656         .class          = &am33xx_mmc_hwmod_class,
1657         .mpu_irqs       = am33xx_mmc2_irqs,
1658         .sdma_reqs      = am33xx_mmc2_edma_reqs,
1659         .main_clk       = "mmc2_fck",
1660         .clkdm_name     = "l3s_clkdm",
1661         .prcm           = {
1662                 .omap4  = {
1663                         .clkctrl_offs   = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1664                         .modulemode     = MODULEMODE_SWCTRL,
1665                 },
1666         },
1667         .dev_attr       = &am33xx_mmc2_dev_attr,
1668         .slaves         = am33xx_mmc2_slaves,
1669         .slaves_cnt     = ARRAY_SIZE(am33xx_mmc2_slaves),
1670 };
1672 /* Master interfaces on the MPU interconnect */
1673 static struct omap_hwmod_ocp_if *am33xx_l3_mpu_masters[] = {
1674         &am33xx_mpu__l3_slow,
1675 };
1677 /* mpu */
1678 static struct omap_hwmod am33xx_mpu_hwmod = {
1679         .name           = "mpu",
1680         .class          = &mpu_hwmod_class,
1681         .masters        = am33xx_l3_mpu_masters,
1682         .masters_cnt    = ARRAY_SIZE(am33xx_l3_mpu_masters),
1683         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1684         .main_clk       = "mpu_fck",
1685         .clkdm_name     = "mpu_clkdm",
1686         .prcm           = {
1687                 .omap4  = {
1688                         .clkctrl_offs   = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1689                         .modulemode     = MODULEMODE_SWCTRL,
1690                 },
1691         },
1692 };
1694 /* 'ocmcram' class */
1695 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
1696         .name = "ocmcram",
1697 };
1699 /* ocmcram */
1700 static struct omap_hwmod am33xx_ocmcram_hwmod = {
1701         .name           = "ocmcram",
1702         .class          = &am33xx_ocmcram_hwmod_class,
1703         .main_clk       = "ocmcram_fck",
1704         .clkdm_name     = "l3_clkdm",
1705         .prcm           = {
1706                 .omap4  = {
1707                         .clkctrl_offs   = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
1708                         .modulemode     = MODULEMODE_SWCTRL,
1709                 },
1710         },
1711         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1712 };
1714 /* 'ocpwp' class */
1715 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
1716         .name           = "ocpwp",
1717 };
1719 /* ocpwp */
1720 static struct omap_hwmod am33xx_ocpwp_hwmod = {
1721         .name           = "ocpwp",
1722         .class          = &am33xx_ocpwp_hwmod_class,
1723         .main_clk       = "ocpwp_fck",
1724         .clkdm_name     = "l4ls_clkdm",
1725         .prcm           = {
1726                 .omap4  = {
1727                         .clkctrl_offs   = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
1728                         .modulemode     = MODULEMODE_SWCTRL,
1729                 },
1730         },
1731 };
1733 /* 'rtc' class */
1734 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1735         .name           = "rtc",
1736 };
1738 /* rtc */
1739 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1740         { .irq = AM33XX_IRQ_RTC_TIMER },
1741         { .irq = -1 }
1742 };
1744 static struct omap_hwmod am33xx_rtc_hwmod = {
1745         .name           = "rtc",
1746         .class          = &am33xx_rtc_hwmod_class,
1747         .mpu_irqs       = am33xx_rtc_irqs,
1748         .main_clk       = "rtc_fck",
1749         .clkdm_name     = "l4_rtc_clkdm",
1750         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), /* ??? */
1751         .prcm           = {
1752                 .omap4  = {
1753                         .clkctrl_offs   = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1754                         .modulemode     = MODULEMODE_SWCTRL,
1755                 },
1756         },
1757 };
1759 /* 'sha0' class */
1760 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
1761         .name           = "sha0",
1762 };
1764 /* sha0 */
1765 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
1766         { .irq = AM33XX_IRQ_SHAEIP57t0_S },
1767         { .irq = -1 }
1768 };
1770 static struct omap_hwmod am33xx_sha0_hwmod = {
1771         .name           = "sha0",
1772         .class          = &am33xx_sha0_hwmod_class,
1773         .mpu_irqs       = am33xx_sha0_irqs,
1774         .main_clk       = "sha0_fck",
1775         .clkdm_name     = "l3_clkdm",
1776         .prcm           = {
1777                 .omap4  = {
1778                         .clkctrl_offs   = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
1779                         .modulemode     = MODULEMODE_SWCTRL,
1780                 },
1781         },
1782 };
1784 /* 'smartreflex' class */
1785 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
1786         .name           = "smartreflex",
1787 };
1789 /* smartreflex0 */
1790 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
1791         { .irq = AM33XX_IRQ_SMARTREFLEX0 },
1792         { .irq = -1 }
1793 };
1795 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
1796         .name           = "smartreflex0",
1797         .class          = &am33xx_smartreflex_hwmod_class,
1798         .mpu_irqs       = am33xx_smartreflex0_irqs,
1799         .main_clk       = "smartreflex0_fck",
1800         .clkdm_name     = "l4_wkup_clkdm",
1801         .prcm           = {
1802                 .omap4  = {
1803                         .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
1804                         .modulemode     = MODULEMODE_SWCTRL,
1805                 },
1806         },
1807 };
1809 /* smartreflex1 */
1810 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
1811         { .irq = AM33XX_IRQ_SMARTREFLEX1 },
1812         { .irq = -1 }
1813 };
1815 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
1816         .name           = "smartreflex1",
1817         .class          = &am33xx_smartreflex_hwmod_class,
1818         .mpu_irqs       = am33xx_smartreflex1_irqs,
1819         .main_clk       = "smartreflex1_fck",
1820         .clkdm_name     = "l4_wkup_clkdm",
1821         .prcm           = {
1822                 .omap4  = {
1823                         .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
1824                         .modulemode     = MODULEMODE_SWCTRL,
1825                 },
1826         },
1827 };
1829 /* 'spi' class */
1831 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1832         .rev_offs       = 0x0000,
1833         .sysc_offs      = 0x0110,
1834         .syss_offs      = 0x0114,
1835         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1836                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1837                         SYSS_HAS_RESET_STATUS),
1838         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1839         .sysc_fields    = &omap_hwmod_sysc_type1,
1840 };
1842 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1843         .name           = "mcspi",
1844         .sysc           = &am33xx_mcspi_sysc,
1845         .rev            = OMAP4_MCSPI_REV,
1846 };
1848 /* spi0 */
1849 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1850         { .irq = AM33XX_IRQ_MCSPIOCP0 },
1851         { .irq = -1 }
1852 };
1854 struct omap_hwmod_dma_info am33xx_mcspi0_sdma_reqs[] = {
1855         { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0R },
1856         { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0W },
1857         { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1R },
1858         { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1W },
1859         { .dma_req = -1 }
1860 };
1862 struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
1863         {
1864                 .pa_start       = AM33XX_SPI0_BASE,
1865                 .pa_end         = AM33XX_SPI0_BASE + SZ_1K - 1,
1866                 .flags          = ADDR_TYPE_RT
1867         },
1868         { }
1869 };
1871 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = {
1872         .master         = &am33xx_l4per_hwmod,
1873         .slave          = &am33xx_spi0_hwmod,
1874         .clk            = "spi0_ick",
1875         .addr           = am33xx_mcspi0_addr_space,
1876         .user           = OCP_USER_MPU,
1877 };
1879 static struct omap_hwmod_ocp_if *am33xx_mcspi0_slaves[] = {
1880         &am33xx_l4_core__mcspi0,
1881 };
1883 struct omap2_mcspi_dev_attr mcspi_attrib = {
1884         .num_chipselect = 2,
1885 };
1886 static struct omap_hwmod am33xx_spi0_hwmod = {
1887         .name           = "spi0",
1888         .class          = &am33xx_spi_hwmod_class,
1889         .mpu_irqs       = am33xx_spi0_irqs,
1890         .sdma_reqs      = am33xx_mcspi0_sdma_reqs,
1891         .main_clk       = "spi0_fck",
1892         .clkdm_name     = "l4ls_clkdm",
1893         .prcm           = {
1894                 .omap4  = {
1895                         .clkctrl_offs   = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1896                         .modulemode     = MODULEMODE_SWCTRL,
1897                 },
1898         },
1899         .dev_attr       = &mcspi_attrib,
1900         .slaves         = am33xx_mcspi0_slaves,
1901         .slaves_cnt     = ARRAY_SIZE(am33xx_mcspi0_slaves),
1902 };
1904 /* spi1 */
1905 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1906         { .irq = AM33XX_IRQ_SPI1 },
1907         { .irq = -1 }
1908 };
1910 struct omap_hwmod_dma_info am33xx_mcspi1_sdma_reqs[] = {
1911         { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0R },
1912         { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0W },
1913         { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1R },
1914         { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1W },
1915         { .dma_req = -1 }
1916 };
1918 struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
1919         {
1920                 .pa_start       = AM33XX_SPI1_BASE,
1921                 .pa_end         = AM33XX_SPI1_BASE + SZ_1K - 1,
1922                 .flags          = ADDR_TYPE_RT
1923         },
1924         { }
1925 };
1927 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = {
1928         .master         = &am33xx_l4per_hwmod,
1929         .slave          = &am33xx_spi1_hwmod,
1930         .clk            = "spi1_ick",
1931         .addr           = am33xx_mcspi1_addr_space,
1932         .user           = OCP_USER_MPU,
1933 };
1935 static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = {
1936         &am33xx_l4_core__mcspi1,
1937 };
1938 static struct omap_hwmod am33xx_spi1_hwmod = {
1939         .name           = "spi1",
1940         .class          = &am33xx_spi_hwmod_class,
1941         .mpu_irqs       = am33xx_spi1_irqs,
1942         .sdma_reqs      = am33xx_mcspi1_sdma_reqs,
1943         .main_clk       = "spi1_fck",
1944         .clkdm_name     = "l4ls_clkdm",
1945         .prcm           = {
1946                 .omap4  = {
1947                         .clkctrl_offs   = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1948                         .modulemode     = MODULEMODE_SWCTRL,
1949                 },
1950         },
1951         .dev_attr       = &mcspi_attrib,
1952         .slaves         = am33xx_mcspi1_slaves,
1953         .slaves_cnt     = ARRAY_SIZE(am33xx_mcspi1_slaves),
1954 };
1956 /* 'spinlock' class */
1957 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1958         .name           = "spinlock",
1959 };
1961 /* spinlock */
1962 static struct omap_hwmod am33xx_spinlock_hwmod = {
1963         .name           = "spinlock",
1964         .class          = &am33xx_spinlock_hwmod_class,
1965         .main_clk       = "spinlock_fck",
1966         .clkdm_name     = "l4ls_clkdm",
1967         .prcm           = {
1968                 .omap4  = {
1969                         .clkctrl_offs   = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1970                         .modulemode     = MODULEMODE_SWCTRL,
1971                 },
1972         },
1973 };
1975 /* 'timer 0 & 2-7' class */
1976 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1977         .rev_offs       = 0x0000,
1978         .sysc_offs      = 0x0010,
1979         .syss_offs      = 0x0014,
1980         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1981         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1982                         SIDLE_SMART_WKUP),
1983         .sysc_fields    = &omap_hwmod_sysc_type2,
1984 };
1986 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1987         .name           = "timer",
1988         .sysc           = &am33xx_timer_sysc,
1989 };
1991 /* timer0 */
1992 /* l4 wkup -> timer0 interface */
1993 static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = {
1994         {
1995                 .pa_start       = AM33XX_TIMER0_BASE,
1996                 .pa_end         = AM33XX_TIMER0_BASE + SZ_1K - 1,
1997                 .flags          = ADDR_TYPE_RT
1998         },
1999         { }
2000 };
2002 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = {
2003         .master         = &am33xx_l4wkup_hwmod,
2004         .slave          = &am33xx_timer0_hwmod,
2005         .clk            = "timer0_ick",
2006         .addr           = am33xx_timer0_addr_space,
2007         .user           = OCP_USER_MPU,
2008 };
2010 static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = {
2011         &am33xx_l4wkup__timer0,
2012 };
2014 static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = {
2015         { .irq = AM33XX_IRQ_DMTIMER0 },
2016         { .irq = -1 }
2017 };
2019 static struct omap_hwmod am33xx_timer0_hwmod = {
2020         .name           = "timer0",
2021         .class          = &am33xx_timer_hwmod_class,
2022         .mpu_irqs       = am33xx_timer0_irqs,
2023         .main_clk       = "timer0_fck",
2024         .clkdm_name     = "l4_wkup_clkdm",
2025         .prcm           = {
2026                 .omap4  = {
2027                         .clkctrl_offs   = AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET,
2028                         .modulemode     = MODULEMODE_SWCTRL,
2029                 },
2030         },
2031         .slaves         = am33xx_timer0_slaves,
2032         .slaves_cnt     = ARRAY_SIZE(am33xx_timer0_slaves),
2033 };
2035 /* timer1 1ms */
2036 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
2037         .rev_offs       = 0x0000,
2038         .sysc_offs      = 0x0010,
2039         .syss_offs      = 0x0014,
2040         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2041                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
2042                         SYSS_HAS_RESET_STATUS),
2043         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2044         .sysc_fields    = &omap_hwmod_sysc_type1,
2045 };
2047 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
2048         .name           = "timer",
2049         .sysc           = &am33xx_timer1ms_sysc,
2050 };
2052 /* l4 wkup -> timer1 interface */
2053 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
2054         {
2055                 .pa_start       = AM33XX_TIMER1_BASE,
2056                 .pa_end         = AM33XX_TIMER1_BASE + SZ_1K - 1,
2057                 .flags          = ADDR_TYPE_RT
2058         },
2059         { }
2060 };
2062 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = {
2063         .master         = &am33xx_l4wkup_hwmod,
2064         .slave          = &am33xx_timer1_hwmod,
2065         .clk            = "timer1_ick",
2066         .addr           = am33xx_timer1_addr_space,
2067         .user           = OCP_USER_MPU,
2068 };
2070 static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = {
2071         &am33xx_l4wkup__timer1,
2072 };
2074 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
2075         { .irq = AM33XX_IRQ_DMTIMER1 },
2076         { .irq = -1 }
2077 };
2079 static struct omap_hwmod am33xx_timer1_hwmod = {
2080         .name           = "timer1",
2081         .class          = &am33xx_timer1ms_hwmod_class,
2082         .mpu_irqs       = am33xx_timer1_irqs,
2083         .main_clk       = "timer1_fck",
2084         .clkdm_name     = "l4_wkup_clkdm",
2085         .prcm           = {
2086                 .omap4  = {
2087                         .clkctrl_offs   = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2088                         .modulemode     = MODULEMODE_SWCTRL,
2089                 },
2090         },
2091         .slaves         = am33xx_timer1_slaves,
2092         .slaves_cnt     = ARRAY_SIZE(am33xx_timer1_slaves),
2093 };
2095 /* timer2 */
2096 /* l4 per -> timer2 interface */
2097 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
2098         {
2099                 .pa_start       = AM33XX_TIMER2_BASE,
2100                 .pa_end         = AM33XX_TIMER2_BASE + SZ_1K - 1,
2101                 .flags          = ADDR_TYPE_RT
2102         },
2103         { }
2104 };
2106 static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = {
2107         .master         = &am33xx_l4per_hwmod,
2108         .slave          = &am33xx_timer2_hwmod,
2109         .clk            = "timer2_ick",
2110         .addr           = am33xx_timer2_addr_space,
2111         .user           = OCP_USER_MPU,
2112 };
2114 static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = {
2115         &am33xx_l4per__timer2,
2116 };
2118 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
2119         { .irq = AM33XX_IRQ_DMTIMER2 },
2120         { .irq = -1 }
2121 };
2123 static struct omap_hwmod am33xx_timer2_hwmod = {
2124         .name           = "timer2",
2125         .class          = &am33xx_timer_hwmod_class,
2126         .mpu_irqs       = am33xx_timer2_irqs,
2127         .main_clk       = "timer2_fck",
2128         .prcm           = {
2129                 .omap4  = {
2130                         .clkctrl_offs   = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
2131                         .modulemode     = MODULEMODE_SWCTRL,
2132                 },
2133         },
2134         .slaves         = am33xx_timer2_slaves,
2135         .slaves_cnt     = ARRAY_SIZE(am33xx_timer2_slaves),
2136         .clkdm_name     = "l4ls_clkdm",
2137 };
2139 /* timer3 */
2140 /* l4 per -> timer3 interface */
2141 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
2142         {
2143                 .pa_start       = AM33XX_TIMER3_BASE,
2144                 .pa_end         = AM33XX_TIMER3_BASE + SZ_1K - 1,
2145                 .flags          = ADDR_TYPE_RT
2146         },
2147         { }
2148 };
2150 static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = {
2151         .master         = &am33xx_l4per_hwmod,
2152         .slave          = &am33xx_timer3_hwmod,
2153         .clk            = "timer3_ick",
2154         .addr           = am33xx_timer3_addr_space,
2155         .user           = OCP_USER_MPU,
2156 };
2158 static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = {
2159         &am33xx_l4per__timer3,
2160 };
2162 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
2163         { .irq = AM33XX_IRQ_DMTIMER3 },
2164         { .irq = -1 }
2165 };
2167 static struct omap_hwmod am33xx_timer3_hwmod = {
2168         .name           = "timer3",
2169         .class          = &am33xx_timer_hwmod_class,
2170         .mpu_irqs       = am33xx_timer3_irqs,
2171         .main_clk       = "timer3_fck",
2172         .clkdm_name     = "l4ls_clkdm",
2173         .prcm           = {
2174                 .omap4  = {
2175                         .clkctrl_offs   = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
2176                         .modulemode     = MODULEMODE_SWCTRL,
2177                 },
2178         },
2179         .slaves         = am33xx_timer3_slaves,
2180         .slaves_cnt     = ARRAY_SIZE(am33xx_timer3_slaves),
2181 };
2183 /* timer4 */
2184 /* l4 per -> timer4 interface */
2185 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
2186         {
2187                 .pa_start       = AM33XX_TIMER4_BASE,
2188                 .pa_end         = AM33XX_TIMER4_BASE + SZ_1K - 1,
2189                 .flags          = ADDR_TYPE_RT
2190         },
2191         { }
2192 };
2194 static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = {
2195         .master         = &am33xx_l4per_hwmod,
2196         .slave          = &am33xx_timer4_hwmod,
2197         .clk            = "timer4_ick",
2198         .addr           = am33xx_timer4_addr_space,
2199         .user           = OCP_USER_MPU,
2200 };
2202 static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = {
2203         &am33xx_l4per__timer4,
2204 };
2206 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
2207         { .irq = AM33XX_IRQ_DMTIMER4 },
2208         { .irq = -1 }
2209 };
2211 static struct omap_hwmod am33xx_timer4_hwmod = {
2212         .name           = "timer4",
2213         .class          = &am33xx_timer_hwmod_class,
2214         .mpu_irqs       = am33xx_timer4_irqs,
2215         .main_clk       = "timer4_fck",
2216         .prcm           = {
2217                 .omap4  = {
2218                         .clkctrl_offs   = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
2219                         .modulemode     = MODULEMODE_SWCTRL,
2220                 },
2221         },
2222         .slaves         = am33xx_timer4_slaves,
2223         .slaves_cnt     = ARRAY_SIZE(am33xx_timer4_slaves),
2224         .clkdm_name     = "l4ls_clkdm",
2225 };
2228 /* timer5 */
2229 /* l4 per -> timer5 interface */
2230 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
2231         {
2232                 .pa_start       = AM33XX_TIMER5_BASE,
2233                 .pa_end         = AM33XX_TIMER5_BASE + SZ_1K - 1,
2234                 .flags          = ADDR_TYPE_RT
2235         },
2236         { }
2237 };
2239 static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = {
2240         .master         = &am33xx_l4per_hwmod,
2241         .slave          = &am33xx_timer5_hwmod,
2242         .clk            = "timer5_ick",
2243         .addr           = am33xx_timer5_addr_space,
2244         .user           = OCP_USER_MPU,
2245 };
2247 static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = {
2248         &am33xx_l4per__timer5,
2249 };
2251 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
2252         { .irq = AM33XX_IRQ_DMTIMER5 },
2253         { .irq = -1 }
2254 };
2256 static struct omap_hwmod am33xx_timer5_hwmod = {
2257         .name           = "timer5",
2258         .class          = &am33xx_timer_hwmod_class,
2259         .mpu_irqs       = am33xx_timer5_irqs,
2260         .main_clk       = "timer5_fck",
2261         .prcm           = {
2262                 .omap4  = {
2263                         .clkctrl_offs   = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
2264                         .modulemode     = MODULEMODE_SWCTRL,
2265                 },
2266         },
2267         .slaves         = am33xx_timer5_slaves,
2268         .slaves_cnt     = ARRAY_SIZE(am33xx_timer5_slaves),
2269         .clkdm_name     = "l4ls_clkdm",
2270 };
2272 /* timer6 */
2273 /* l4 per -> timer6 interface */
2274 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
2275         {
2276                 .pa_start       = AM33XX_TIMER6_BASE,
2277                 .pa_end         = AM33XX_TIMER6_BASE + SZ_1K - 1,
2278                 .flags          = ADDR_TYPE_RT
2279         },
2280         { }
2281 };
2283 static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = {
2284         .master         = &am33xx_l4per_hwmod,
2285         .slave          = &am33xx_timer6_hwmod,
2286         .clk            = "timer6_ick",
2287         .addr           = am33xx_timer6_addr_space,
2288         .user           = OCP_USER_MPU,
2289 };
2291 static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = {
2292         &am33xx_l4per__timer6,
2293 };
2295 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
2296         { .irq = AM33XX_IRQ_DMTIMER6 },
2297         { .irq = -1 }
2298 };
2300 static struct omap_hwmod am33xx_timer6_hwmod = {
2301         .name           = "timer6",
2302         .class          = &am33xx_timer_hwmod_class,
2303         .mpu_irqs       = am33xx_timer6_irqs,
2304         .main_clk       = "timer6_fck",
2305         .prcm           = {
2306                 .omap4  = {
2307                         .clkctrl_offs   = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
2308                         .modulemode     = MODULEMODE_SWCTRL,
2309                 },
2310         },
2311         .slaves         = am33xx_timer6_slaves,
2312         .slaves_cnt     = ARRAY_SIZE(am33xx_timer6_slaves),
2313         .clkdm_name     = "l4ls_clkdm",
2314 };
2316 /* timer7 */
2317 /* l4 per -> timer7 interface */
2318 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
2319         {
2320                 .pa_start       = AM33XX_TIMER7_BASE,
2321                 .pa_end         = AM33XX_TIMER7_BASE + SZ_1K - 1,
2322                 .flags          = ADDR_TYPE_RT
2323         },
2324         { }
2325 };
2327 static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = {
2328         .master         = &am33xx_l4per_hwmod,
2329         .slave          = &am33xx_timer7_hwmod,
2330         .clk            = "timer7_ick",
2331         .addr           = am33xx_timer7_addr_space,
2332         .user           = OCP_USER_MPU,
2333 };
2335 static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = {
2336         &am33xx_l4per__timer7,
2337 };
2339 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
2340         { .irq = AM33XX_IRQ_DMTIMER7 },
2341         { .irq = -1 }
2342 };
2344 static struct omap_hwmod am33xx_timer7_hwmod = {
2345         .name           = "timer7",
2346         .class          = &am33xx_timer_hwmod_class,
2347         .mpu_irqs       = am33xx_timer7_irqs,
2348         .main_clk       = "timer7_fck",
2349         .prcm           = {
2350                 .omap4  = {
2351                         .clkctrl_offs   = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
2352                         .modulemode     = MODULEMODE_SWCTRL,
2353                 },
2354         },
2355         .slaves         = am33xx_timer7_slaves,
2356         .slaves_cnt     = ARRAY_SIZE(am33xx_timer7_slaves),
2357         .clkdm_name     = "l4ls_clkdm",
2358 };
2360 /* 'tpcc' class */
2361 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
2362         .name           = "tpcc",
2363 };
2365 /* tpcc */
2366 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
2367         { .name = "edma0", .irq = AM33XX_IRQ_TPCC0_INT_PO0 },
2368         { .name = "edma0_err", .irq = AM33XX_IRQ_TPCC0_ERRINT_PO },
2369         { .irq = -1 },
2370 };
2372 /* TODO move this appropriate header. */
2373 #define AM33XX_TPCC_BASE                0x49000000
2375 static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
2376         {
2377                 .pa_start       = AM33XX_TPCC_BASE,
2378                 .pa_end         = AM33XX_TPCC_BASE + SZ_32K - 1,
2379                 .flags          = ADDR_TYPE_RT
2380         },
2381         { }
2382 };
2384 static struct omap_hwmod_ocp_if am33xx_l3_slow__tpcc = {
2385         .master         = &am33xx_l3slow_hwmod,
2386         .slave          = &am33xx_tpcc_hwmod,
2387         .addr           = am33xx_tpcc_addr_space,
2388         .user           = OCP_USER_MPU,
2389 };
2391 static struct omap_hwmod_ocp_if *am33xx_tpcc_slaves[] = {
2392         &am33xx_l3_slow__tpcc,
2393 };
2395 static struct omap_hwmod am33xx_tpcc_hwmod = {
2396         .name           = "tpcc",
2397         .class          = &am33xx_tpcc_hwmod_class,
2398         .mpu_irqs       = am33xx_tpcc_irqs,
2399         .main_clk       = "tpcc_ick",
2400         .clkdm_name     = "l3_clkdm",
2401         .prcm           = {
2402                 .omap4  = {
2403                         .clkctrl_offs   = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
2404                         .modulemode     = MODULEMODE_SWCTRL,
2405                 },
2406         },
2407         .slaves         = am33xx_tpcc_slaves,
2408         .slaves_cnt     = ARRAY_SIZE(am33xx_tpcc_slaves),
2409 };
2411 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
2412         .rev_offs       = 0x0,
2413         .sysc_offs      = 0x10,
2414         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2415                                 SYSC_HAS_MIDLEMODE),
2416         .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
2417         .sysc_fields    = &omap_hwmod_sysc_type2,
2418 };
2420 /* 'tptc' class */
2421 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
2422         .name           = "tptc",
2423         .sysc           = &am33xx_tptc_sysc,
2424 };
2426 /* tptc0 */
2427 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
2428         { .irq = AM33XX_IRQ_TPTC0 },
2429         { .irq = -1 }
2430 };
2432 struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
2433         {
2434                 .pa_start       = 0x49800000,
2435                 .pa_end         = 0x49800000 + SZ_8K - 1,
2436                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2437         },
2438         { }
2439 };
2441 struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
2442         .master         = &am33xx_l3_main_hwmod,
2443         .slave          = &am33xx_tptc0_hwmod,
2444         .addr           = am33xx_tptc0_addr_space,
2445         .user           = OCP_USER_MPU,
2446 };
2448 static struct omap_hwmod_ocp_if *am33xx_tptc0_slaves[] = {
2449         &am33xx_l3_main__tptc0,
2450 };
2452 static struct omap_hwmod am33xx_tptc0_hwmod = {
2453         .name           = "tptc0",
2454         .class          = &am33xx_tptc_hwmod_class,
2455         .mpu_irqs       = am33xx_tptc0_irqs,
2456         .main_clk       = "tptc0_ick",
2457         .clkdm_name     = "l3_clkdm",
2458         .prcm           = {
2459                 .omap4  = {
2460                         .clkctrl_offs   = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
2461                         .modulemode     = MODULEMODE_SWCTRL,
2462                 },
2463         },
2464         .slaves         = am33xx_tptc0_slaves,
2465         .slaves_cnt     = ARRAY_SIZE(am33xx_tptc0_slaves),
2466 };
2468 /* tptc1 */
2469 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
2470         { .irq = AM33XX_IRQ_TPTC1 },
2471         { .irq = -1 }
2472 };
2474 struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
2475         {
2476                 .pa_start       = 0x49900000,
2477                 .pa_end         = 0x49900000 + SZ_8K - 1,
2478                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2479         },
2480         { }
2481 };
2483 struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
2484         .master         = &am33xx_l3_main_hwmod,
2485         .slave          = &am33xx_tptc1_hwmod,
2486         .addr           = am33xx_tptc1_addr_space,
2487         .user           = OCP_USER_MPU,
2488 };
2490 static struct omap_hwmod_ocp_if *am33xx_tptc1_slaves[] = {
2491         &am33xx_l3_main__tptc1,
2492 };
2494 static struct omap_hwmod am33xx_tptc1_hwmod = {
2495         .name           = "tptc1",
2496         .class          = &am33xx_tptc_hwmod_class,
2497         .mpu_irqs       = am33xx_tptc1_irqs,
2498         .main_clk       = "tptc1_ick",
2499         .clkdm_name     = "l3_clkdm",
2500         .prcm           = {
2501                 .omap4  = {
2502                         .clkctrl_offs   = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
2503                         .modulemode     = MODULEMODE_SWCTRL,
2504                 },
2505         },
2506         .slaves         = am33xx_tptc1_slaves,
2507         .slaves_cnt     = ARRAY_SIZE(am33xx_tptc1_slaves),
2508 };
2510 /* tptc2 */
2511 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
2512         { .irq = AM33XX_IRQ_TPTC2 },
2513         { .irq = -1 }
2514 };
2516 struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
2517         {
2518                 .pa_start       = 0x49a00000,
2519                 .pa_end         = 0x49a00000 + SZ_8K - 1,
2520                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2521         },
2522         { }
2523 };
2525 struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
2526         .master         = &am33xx_l3_main_hwmod,
2527         .slave          = &am33xx_tptc2_hwmod,
2528         .addr           = am33xx_tptc2_addr_space,
2529         .user           = OCP_USER_MPU,
2530 };
2532 static struct omap_hwmod_ocp_if *am33xx_tptc2_slaves[] = {
2533         &am33xx_l3_main__tptc2,
2534 };
2536 static struct omap_hwmod am33xx_tptc2_hwmod = {
2537         .name           = "tptc2",
2538         .class          = &am33xx_tptc_hwmod_class,
2539         .mpu_irqs       = am33xx_tptc2_irqs,
2540         .main_clk       = "tptc2_ick",
2541         .clkdm_name     = "l3_clkdm",
2542         .prcm           = {
2543                 .omap4  = {
2544                         .clkctrl_offs   = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
2545                         .modulemode     = MODULEMODE_SWCTRL,
2546                 },
2547         },
2548         .slaves         = am33xx_tptc2_slaves,
2549         .slaves_cnt     = ARRAY_SIZE(am33xx_tptc2_slaves),
2550 };
2552 /* 'uart' class */
2553 static struct omap_hwmod_class_sysconfig uart_sysc = {
2554         .rev_offs       = 0x50,
2555         .sysc_offs      = 0x54,
2556         .syss_offs      = 0x58,
2557         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
2558                         SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2559                         SYSC_HAS_AUTOIDLE),
2560         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2561                         SIDLE_SMART_WKUP),
2562         .sysc_fields    = &omap_hwmod_sysc_type1,
2563 };
2565 static struct omap_hwmod_class uart_class = {
2566         .name           = "uart",
2567         .sysc           = &uart_sysc,
2568 };
2570 /* uart1 */
2571 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
2572         { .name = "tx", .dma_req = 26, },
2573         { .name = "rx", .dma_req = 27, },
2574         { .dma_req = -1 }
2575 };
2577 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
2578         {
2579                 .pa_start       = AM33XX_UART1_BASE,
2580                 .pa_end         = AM33XX_UART1_BASE + SZ_8K - 1,
2581                 .flags          = ADDR_TYPE_RT
2582         },
2583         { }
2584 };
2586 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
2587         .master         = &am33xx_l4wkup_hwmod,
2588         .slave          = &am33xx_uart1_hwmod,
2589         .clk            = "uart1_ick",
2590         .addr           = am33xx_uart1_addr_space,
2591         .user           = OCP_USER_MPU,
2592 };
2594 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
2595         { .irq = AM33XX_IRQ_UART0 },
2596         { .irq = -1 }
2597 };
2599 static struct omap_hwmod_ocp_if *am33xx_uart1_slaves[] = {
2600         &am33xx_l4_wkup__uart1,
2601 };
2603 static struct omap_hwmod am33xx_uart1_hwmod = {
2604         .name           = "uart1",
2605         .class          = &uart_class,
2606         .mpu_irqs       = am33xx_uart1_irqs,
2607         .sdma_reqs      = uart1_edma_reqs,
2608         .main_clk       = "uart1_fck",
2609         .clkdm_name     = "l4_wkup_clkdm",
2610         .prcm           = {
2611                 .omap4  = {
2612                         .clkctrl_offs   = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
2613                         .modulemode     = MODULEMODE_SWCTRL,
2614                 },
2615         },
2616         .slaves         = am33xx_uart1_slaves,
2617         .slaves_cnt     = ARRAY_SIZE(am33xx_uart1_slaves),
2618 };
2620 /* uart2 */
2621 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
2622         {
2623                 .pa_start       = AM33XX_UART2_BASE,
2624                 .pa_end         = AM33XX_UART2_BASE + SZ_8K - 1,
2625                 .flags          = ADDR_TYPE_RT
2626         },
2627         { }
2628 };
2630 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
2631         .slave          = &am33xx_uart2_hwmod,
2632         .clk            = "uart2_ick",
2633         .addr           = am33xx_uart2_addr_space,
2634         .user           = OCP_USER_MPU,
2635 };
2637 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
2638         { .irq = AM33XX_IRQ_UART1 },
2639         { .irq = -1 }
2640 };
2642 static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = {
2643         &am33xx_l4_ls__uart2,
2644 };
2646 static struct omap_hwmod am33xx_uart2_hwmod = {
2647         .name           = "uart2",
2648         .class          = &uart_class,
2649         .mpu_irqs       = am33xx_uart2_irqs,
2650         .main_clk       = "uart2_fck",
2651         .clkdm_name     = "l4ls_clkdm",
2652         .sdma_reqs      = uart1_edma_reqs,
2653         .prcm           = {
2654                 .omap4  = {
2655                         .clkctrl_offs   = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
2656                         .modulemode     = MODULEMODE_SWCTRL,
2657                 },
2658         },
2659         .slaves         = am33xx_uart2_slaves,
2660         .slaves_cnt     = ARRAY_SIZE(am33xx_uart2_slaves),
2661 };
2663 /* uart3 */
2664 static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
2665         { .name = "tx", .dma_req = 30, },
2666         { .name = "rx", .dma_req = 31, },
2667         { .dma_req = -1 }
2668 };
2670 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
2671         {
2672                 .pa_start       = AM33XX_UART3_BASE,
2673                 .pa_end         = AM33XX_UART3_BASE + SZ_8K - 1,
2674                 .flags          = ADDR_TYPE_RT
2675         },
2676         { }
2677 };
2679 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
2680         .slave          = &am33xx_uart3_hwmod,
2681         .clk            = "uart3_ick",
2682         .addr           = am33xx_uart3_addr_space,
2683         .user           = OCP_USER_MPU,
2684 };
2686 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2687         { .irq = AM33XX_IRQ_UART2 },
2688         { .irq = -1 }
2689 };
2691 static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = {
2692         &am33xx_l4_ls__uart3,
2693 };
2695 static struct omap_hwmod am33xx_uart3_hwmod = {
2696         .name           = "uart3",
2697         .class          = &uart_class,
2698         .mpu_irqs       = am33xx_uart3_irqs,
2699         .main_clk       = "uart3_fck",
2700         .clkdm_name     = "l4ls_clkdm",
2701         .sdma_reqs      = uart3_edma_reqs,
2702         .prcm           = {
2703                 .omap4  = {
2704                         .clkctrl_offs   = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
2705                         .modulemode     = MODULEMODE_SWCTRL,
2706                 },
2707         },
2708         .slaves         = am33xx_uart3_slaves,
2709         .slaves_cnt     = ARRAY_SIZE(am33xx_uart3_slaves),
2710 };
2712 /* uart4 */
2713 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
2714         {
2715                 .pa_start       = AM33XX_UART4_BASE,
2716                 .pa_end         = AM33XX_UART4_BASE + SZ_8K - 1,
2717                 .flags          = ADDR_TYPE_RT
2718         },
2719         { }
2720 };
2722 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
2723         .slave          = &am33xx_uart4_hwmod,
2724         .clk            = "uart4_ick",
2725         .addr           = am33xx_uart4_addr_space,
2726         .user           = OCP_USER_MPU,
2727 };
2729 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2730         { .irq = AM33XX_IRQ_UART3 },
2731         { .irq = -1 }
2732 };
2734 static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = {
2735         &am33xx_l4_ls__uart4,
2736 };
2738 static struct omap_hwmod am33xx_uart4_hwmod = {
2739         .name           = "uart4",
2740         .class          = &uart_class,
2741         .mpu_irqs       = am33xx_uart4_irqs,
2742         .main_clk       = "uart4_fck",
2743         .clkdm_name     = "l4ls_clkdm",
2744         .sdma_reqs      = uart1_edma_reqs,
2745         .prcm           = {
2746                 .omap4  = {
2747                         .clkctrl_offs   = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
2748                         .modulemode     = MODULEMODE_SWCTRL,
2749                 },
2750         },
2751         .slaves         = am33xx_uart4_slaves,
2752         .slaves_cnt     = ARRAY_SIZE(am33xx_uart4_slaves),
2753 };
2755 /* uart5 */
2756 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
2757         {
2758                 .pa_start       = AM33XX_UART5_BASE,
2759                 .pa_end         = AM33XX_UART5_BASE + SZ_8K - 1,
2760                 .flags          = ADDR_TYPE_RT
2761         },
2762         { }
2763 };
2765 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
2766         .slave          = &am33xx_uart5_hwmod,
2767         .clk            = "uart5_ick",
2768         .addr           = am33xx_uart5_addr_space,
2769         .user           = OCP_USER_MPU,
2770 };
2772 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2773         { .irq = AM33XX_IRQ_UART4 },
2774         { .irq = -1 }
2775 };
2777 static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = {
2778         &am33xx_l4_ls__uart5,
2779 };
2781 static struct omap_hwmod am33xx_uart5_hwmod = {
2782         .name           = "uart5",
2783         .class          = &uart_class,
2784         .mpu_irqs       = am33xx_uart5_irqs,
2785         .main_clk       = "uart5_fck",
2786         .clkdm_name     = "l4ls_clkdm",
2787         .sdma_reqs      = uart1_edma_reqs,
2788         .prcm           = {
2789                 .omap4  = {
2790                         .clkctrl_offs   = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2791                         .modulemode     = MODULEMODE_SWCTRL,
2792                 },
2793         },
2794         .slaves         = am33xx_uart5_slaves,
2795         .slaves_cnt     = ARRAY_SIZE(am33xx_uart5_slaves),
2796 };
2798 /* uart6 */
2799 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
2800         {
2801                 .pa_start       = AM33XX_UART6_BASE,
2802                 .pa_end         = AM33XX_UART6_BASE + SZ_8K - 1,
2803                 .flags          = ADDR_TYPE_RT
2804         },
2805         { }
2806 };
2808 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
2809         .slave          = &am33xx_uart6_hwmod,
2810         .clk            = "uart6_ick",
2811         .addr           = am33xx_uart6_addr_space,
2812         .user           = OCP_USER_MPU,
2813 };
2815 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2816         { .irq = AM33XX_IRQ_UART5 },
2817         { .irq = -1 }
2818 };
2820 static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = {
2821         &am33xx_l4_ls__uart6,
2822 };
2824 static struct omap_hwmod am33xx_uart6_hwmod = {
2825         .name           = "uart6",
2826         .class          = &uart_class,
2827         .mpu_irqs       = am33xx_uart6_irqs,
2828         .main_clk       = "uart6_fck",
2829         .clkdm_name     = "l4ls_clkdm",
2830         .sdma_reqs      = uart1_edma_reqs,
2831         .prcm           = {
2832                 .omap4  = {
2833                         .clkctrl_offs   = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2834                         .modulemode     = MODULEMODE_SWCTRL,
2835                 },
2836         },
2837         .slaves         = am33xx_uart6_slaves,
2838         .slaves_cnt     = ARRAY_SIZE(am33xx_uart6_slaves),
2839 };
2841 /* 'wd_timer' class */
2842 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2843         .name           = "wd_timer",
2844 };
2846 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
2847         {
2848                 .pa_start       = AM33XX_WDT1_BASE,
2849                 .pa_end         = AM33XX_WDT1_BASE + SZ_4K - 1,
2850                 .flags          = ADDR_TYPE_RT
2851         },
2852         { }
2853 };
2855 /* l4_wkup -> wd_timer1 */
2856 static struct omap_hwmod_ocp_if am33xx_l4wkup__wd_timer1 = {
2857         .master         = &am33xx_l4wkup_hwmod,
2858         .slave          = &am33xx_wd_timer1_hwmod,
2859         .addr           = am33xx_wd_timer1_addrs,
2860         .user           = OCP_USER_MPU,
2861 };
2863 /* wd_timer1 slave ports */
2864 static struct omap_hwmod_ocp_if *am33xx_wd_timer1_slaves[] = {
2865         &am33xx_l4wkup__wd_timer1,
2866 };
2868 /* wd_timer1 */
2869 /*
2870  * TODO: device.c file uses hardcoded name for watchdog
2871          timer driver "wd_timer2, so we are also using
2872          same name as of now...
2873  */
2874 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2875         .name           = "wd_timer2",
2876         .class          = &am33xx_wd_timer_hwmod_class,
2877         .main_clk       = "wd_timer1_fck",
2878         .clkdm_name     = "l4_wkup_clkdm",
2879         .prcm           = {
2880                 .omap4  = {
2881                         .clkctrl_offs   = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2882                         .modulemode     = MODULEMODE_SWCTRL,
2883                 },
2884         },
2885         .slaves         = am33xx_wd_timer1_slaves,
2886         .slaves_cnt     = ARRAY_SIZE(am33xx_wd_timer1_slaves),
2887 };
2889 /* wdt0 */
2890 static struct omap_hwmod_irq_info am33xx_wdt0_irqs[] = {
2891         { .irq = AM33XX_IRQ_WDT0 },
2892         { .irq = -1 },
2893 };
2895 static struct omap_hwmod am33xx_wdt0_hwmod = {
2896         .name           = "wdt0",
2897         .class          = &am33xx_wd_timer_hwmod_class,
2898         .mpu_irqs       = am33xx_wdt0_irqs,
2899         .main_clk       = "wdt0_fck",
2900         .clkdm_name     = "l4_wkup_clkdm",
2901         .prcm           = {
2902                 .omap4  = {
2903                         .clkctrl_offs   = AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET,
2904                         .modulemode     = MODULEMODE_SWCTRL,
2905                 },
2906         },
2907 };
2909 /* 'wkup_m3' class */
2910 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
2911         .name           = "wkup_m3",
2912 };
2914 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
2915         { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
2916 };
2918 /* wkup_m3 */
2919 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
2920         .name           = "wkup_m3",
2921         .class          = &am33xx_wkup_m3_hwmod_class,
2922         .clkdm_name     = "l4_wkup_aon_clkdm",
2923         .main_clk       = "wkup_m3_fck",
2924         .rst_lines      = am33xx_wkup_m3_resets,
2925         .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
2926         .prcm           = {
2927                 .omap4  = {
2928                         .clkctrl_offs   = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
2929                         .rstctrl_offs   = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
2930                         .modulemode     = MODULEMODE_SWCTRL,
2931                 },
2932         },
2933         .flags          = HWMOD_INIT_NO_RESET,  /* Keep hardreset asserted */
2934 };
2936 /* L3 SLOW -> USBSS interface */
2937 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
2938         {
2939                 .name           = "usbss",
2940                 .pa_start       = AM33XX_USBSS_BASE,
2941                 .pa_end         = AM33XX_USBSS_BASE + SZ_4K - 1,
2942                 .flags          = ADDR_TYPE_RT
2943         },
2944         {
2945                 .name           = "musb0",
2946                 .pa_start       = AM33XX_USB0_BASE,
2947                 .pa_end         = AM33XX_USB0_BASE + SZ_2K - 1,
2948                 .flags          = ADDR_TYPE_RT
2949         },
2950         {
2951                 .name           = "musb1",
2952                 .pa_start       = AM33XX_USB1_BASE,
2953                 .pa_end         = AM33XX_USB1_BASE + SZ_2K - 1,
2954                 .flags          = ADDR_TYPE_RT
2955         },
2956         { }
2957 };
2959 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2960         .rev_offs       = 0x0,
2961         .sysc_offs      = 0x10,
2962         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
2963         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2964                                 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2965         .sysc_fields    = &omap_hwmod_sysc_type4,
2966 };
2968 static struct omap_hwmod_class am33xx_usbotg_class = {
2969         .name           = "usbotg",
2970         .sysc           = &am33xx_usbhsotg_sysc,
2971 };
2973 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2974         { .name = "usbss-irq", .irq = AM33XX_IRQ_USBSS, },
2975         { .name = "musb0-irq", .irq = AM33XX_IRQ_USB0, },
2976         { .name = "musb1-irq", .irq = AM33XX_IRQ_USB1, },
2977         { .irq = -1, },
2978 };
2980 static struct omap_hwmod_ocp_if am33xx_l3_slow__usbss = {
2981         .master         = &am33xx_l3slow_hwmod,
2982         .slave          = &am33xx_usbss_hwmod,
2983         .addr           = am33xx_usbss_addr_space,
2984         .user           = OCP_USER_MPU,
2985         .flags          = OCPIF_SWSUP_IDLE,
2986 };
2988 static struct omap_hwmod_ocp_if *am33xx_usbss_slaves[] = {
2989         &am33xx_l3_slow__usbss,
2990 };
2992 static struct omap_hwmod_opt_clk usbss_opt_clks[] = {
2993         { .role = "clkdcoldo", .clk = "usbotg_fck" },
2994 };
2996 static struct omap_hwmod am33xx_usbss_hwmod = {
2997         .name           = "usb_otg_hs",
2998         .mpu_irqs       = am33xx_usbss_mpu_irqs,
2999         .main_clk       = "usbotg_ick",