7dc0f51404baf80f690834411a18d1a87c4bac75
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / omap_hwmod_33xx_data.c
1 /*
2  * Hardware modules present on the AM33XX chips
3  *
4  * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
5  *
6  * This file is automatically generated from the AM33XX hardware databases.
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation version 2.
10  *
11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12  * kind, whether express or implied; without even the implied warranty
13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  */
17 #include <linux/io.h>
19 #include <plat/omap_hwmod.h>
20 #include <plat/cpu.h>
21 #include <plat/gpio.h>
22 #include <plat/dma.h>
23 #include <plat/mmc.h>
24 #include <plat/mcspi.h>
26 #include "omap_hwmod_common_data.h"
27 #include "control.h"
28 #include "cm33xx.h"
29 #include "prm33xx.h"
31 /* Backward references (IPs with Bus Master capability) */
32 static struct omap_hwmod am33xx_mpu_hwmod;
33 static struct omap_hwmod am33xx_l3slow_hwmod;
34 static struct omap_hwmod am33xx_l4wkup_hwmod;
35 static struct omap_hwmod am33xx_l4per_hwmod;
36 static struct omap_hwmod am33xx_uart1_hwmod;
37 static struct omap_hwmod am33xx_uart2_hwmod;
38 static struct omap_hwmod am33xx_uart3_hwmod;
39 static struct omap_hwmod am33xx_uart4_hwmod;
40 static struct omap_hwmod am33xx_uart5_hwmod;
41 static struct omap_hwmod am33xx_uart6_hwmod;
42 static struct omap_hwmod am33xx_timer0_hwmod;
43 static struct omap_hwmod am33xx_timer1_hwmod;
44 static struct omap_hwmod am33xx_timer2_hwmod;
45 static struct omap_hwmod am33xx_timer3_hwmod;
46 static struct omap_hwmod am33xx_timer4_hwmod;
47 static struct omap_hwmod am33xx_timer5_hwmod;
48 static struct omap_hwmod am33xx_timer6_hwmod;
49 static struct omap_hwmod am33xx_timer7_hwmod;
50 static struct omap_hwmod am33xx_wd_timer1_hwmod;
51 static struct omap_hwmod am33xx_cpgmac0_hwmod;
52 static struct omap_hwmod am33xx_icss_hwmod;
53 static struct omap_hwmod am33xx_ieee5000_hwmod;
54 static struct omap_hwmod am33xx_tptc0_hwmod;
55 static struct omap_hwmod am33xx_tptc1_hwmod;
56 static struct omap_hwmod am33xx_tptc2_hwmod;
57 static struct omap_hwmod am33xx_gpio0_hwmod;
58 static struct omap_hwmod am33xx_gpio1_hwmod;
59 static struct omap_hwmod am33xx_gpio2_hwmod;
60 static struct omap_hwmod am33xx_gpio3_hwmod;
61 static struct omap_hwmod am33xx_i2c1_hwmod;
62 static struct omap_hwmod am33xx_i2c2_hwmod;
63 static struct omap_hwmod am33xx_usbss_hwmod;
64 static struct omap_hwmod am33xx_mmc0_hwmod;
65 static struct omap_hwmod am33xx_mmc1_hwmod;
66 static struct omap_hwmod am33xx_mmc2_hwmod;
67 static struct omap_hwmod am33xx_spi0_hwmod;
68 static struct omap_hwmod am33xx_spi1_hwmod;
69 static struct omap_hwmod am33xx_elm_hwmod;
70 static struct omap_hwmod am33xx_adc_tsc_hwmod;
71 static struct omap_hwmod am33xx_tpcc_hwmod;
72 static struct omap_hwmod am33xx_mcasp0_hwmod;
73 static struct omap_hwmod am33xx_mcasp1_hwmod;
74 static struct omap_hwmod am33xx_epwmss0_hwmod;
75 static struct omap_hwmod am33xx_epwmss1_hwmod;
76 static struct omap_hwmod am33xx_epwmss2_hwmod;
78 /*
79  * Interconnects hwmod structures
80  * hwmods that compose the global AM33XX OCP interconnect
81  */
83 /* MPU -> L3_SLOW Peripheral interface */
84 static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = {
85         .master         = &am33xx_mpu_hwmod,
86         .slave          = &am33xx_l3slow_hwmod,
87         .user           = OCP_USER_MPU,
88 };
90 /* L3 SLOW -> L4_PER Peripheral interface */
91 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = {
92         .master         = &am33xx_l3slow_hwmod,
93         .slave          = &am33xx_l4per_hwmod,
94         .user           = OCP_USER_MPU,
95 };
97 /* L3 SLOW -> L4_WKUP Peripheral interface */
98 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = {
99         .master         = &am33xx_l3slow_hwmod,
100         .slave          = &am33xx_l4wkup_hwmod,
101         .user           = OCP_USER_MPU,
102 };
104 /* Master interfaces on the L4_WKUP interconnect */
105 static struct omap_hwmod_ocp_if *am33xx_l3_slow_masters[] = {
106         &am33xx_l3_slow__l4_per,
107         &am33xx_l3_slow__l4_wkup,
108 };
110 /* Slave interfaces on the L3_SLOW interconnect */
111 static struct omap_hwmod_ocp_if *am33xx_l3_slow_slaves[] = {
112         &am33xx_mpu__l3_slow,
113 };
115 static struct omap_hwmod am33xx_l3slow_hwmod = {
116         .name           = "l3_slow",
117         .class          = &l3_hwmod_class,
118         .clkdm_name     = "l3s_clkdm",
119         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
120         .masters        = am33xx_l3_slow_masters,
121         .masters_cnt    = ARRAY_SIZE(am33xx_l3_slow_masters),
122         .slaves         = am33xx_l3_slow_slaves,
123         .slaves_cnt     = ARRAY_SIZE(am33xx_l3_slow_slaves),
124 };
126 /* L4 PER -> GPIO2 */
127 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
128         {
129                 .pa_start       = AM33XX_GPIO1_BASE,
130                 .pa_end         = AM33XX_GPIO1_BASE + SZ_4K - 1,
131                 .flags          = ADDR_TYPE_RT
132         },
133         { }
134 };
136 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
137         .master         = &am33xx_l4per_hwmod,
138         .slave          = &am33xx_gpio1_hwmod,
139         .clk            = "l4ls_fck",
140         .addr           = am33xx_gpio1_addrs,
141         .user           = OCP_USER_MPU | OCP_USER_SDMA,
142 };
144 /* L4 PER -> GPIO3 */
145 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
146         {
147                 .pa_start       = AM33XX_GPIO2_BASE,
148                 .pa_end         = AM33XX_GPIO2_BASE + SZ_4K - 1,
149                 .flags          = ADDR_TYPE_RT
150         },
151         { }
152 };
154 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
155         .master         = &am33xx_l4per_hwmod,
156         .slave          = &am33xx_gpio2_hwmod,
157         .clk            = "l4ls_fck",
158         .addr           = am33xx_gpio2_addrs,
159         .user           = OCP_USER_MPU | OCP_USER_SDMA,
160 };
162 /* L4 PER -> GPIO4 */
163 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
164         {
165                 .pa_start       = AM33XX_GPIO3_BASE,
166                 .pa_end         = AM33XX_GPIO3_BASE + SZ_4K - 1,
167                 .flags          = ADDR_TYPE_RT
168         },
169         { }
170 };
172 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
173         .master         = &am33xx_l4per_hwmod,
174         .slave          = &am33xx_gpio3_hwmod,
175         .clk            = "l4ls_fck",
176         .addr           = am33xx_gpio3_addrs,
177         .user           = OCP_USER_MPU | OCP_USER_SDMA,
178 };
180 /* Master interfaces on the L4_PER interconnect */
181 static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = {
182         &am33xx_l4_per__gpio1,
183         &am33xx_l4_per__gpio2,
184         &am33xx_l4_per__gpio3,
185 };
186 /* Slave interfaces on the L4_PER interconnect */
187 static struct omap_hwmod_ocp_if *am33xx_l4_per_slaves[] = {
188         &am33xx_l3_slow__l4_per,
189 };
191 static struct omap_hwmod am33xx_l4per_hwmod = {
192         .name           = "l4_per",
193         .class          = &l4_hwmod_class,
194         .clkdm_name     = "l4ls_clkdm",
195         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
196         .masters        = am33xx_l4_per_masters,
197         .masters_cnt    = ARRAY_SIZE(am33xx_l4_per_masters),
198         .slaves         = am33xx_l4_per_slaves,
199         .slaves_cnt     = ARRAY_SIZE(am33xx_l4_per_slaves),
200 };
202 /* L4 WKUP -> I2C1 */
203 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
204         {
205                 .pa_start       = AM33XX_I2C0_BASE,
206                 .pa_end         = AM33XX_I2C0_BASE + SZ_4K - 1,
207                 .flags          = ADDR_TYPE_RT
208         },
209         { }
210 };
212 static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = {
213         .master         = &am33xx_l4wkup_hwmod,
214         .slave          = &am33xx_i2c1_hwmod,
215         .addr           = am33xx_i2c1_addr_space,
216         .user           = OCP_USER_MPU,
217 };
219 /* L4 WKUP -> GPIO1 */
220 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
221         {
222                 .pa_start       = AM33XX_GPIO0_BASE,
223                 .pa_end         = AM33XX_GPIO0_BASE + SZ_4K - 1,
224                 .flags          = ADDR_TYPE_RT
225         },
226         { }
227 };
229 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
230         .master         = &am33xx_l4wkup_hwmod,
231         .slave          = &am33xx_gpio0_hwmod,
232         .clk            = "l4ls_fck",
233         .addr           = am33xx_gpio0_addrs,
234         .user           = OCP_USER_MPU | OCP_USER_SDMA,
235 };
237 /* L4 WKUP -> ADC_TSC */
238 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
239         {
240                 .pa_start       = AM33XX_TSC_BASE,
241                 .pa_end         = AM33XX_TSC_BASE + SZ_8K - 1,
242                 .flags          = ADDR_TYPE_RT
243         },
244         { }
245 };
247 static struct omap_hwmod_ocp_if am33xx_l4_wkup_adc_tsc = {
248         .master         = &am33xx_l4wkup_hwmod,
249         .slave          = &am33xx_adc_tsc_hwmod,
250         .addr           = am33xx_adc_tsc_addrs,
251         .user           = OCP_USER_MPU,
252 };
254 /* Master interfaces on the L4_WKUP interconnect */
255 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = {
256         &am33xx_l4_wkup__gpio0,
257 };
258 /* Slave interfaces on the L4_WKUP interconnect */
259 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_slaves[] = {
260         &am33xx_l3_slow__l4_wkup,
261 };
263 static struct omap_hwmod am33xx_l4wkup_hwmod = {
264         .name           = "l4_wkup",
265         .class          = &l4_hwmod_class,
266         .clkdm_name     = "l4_wkup_clkdm",
267         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
268         .masters        = am33xx_l4_wkup_masters,
269         .masters_cnt    = ARRAY_SIZE(am33xx_l4_wkup_masters),
270         .slaves         = am33xx_l4_wkup_slaves,
271         .slaves_cnt     = ARRAY_SIZE(am33xx_l4_wkup_slaves),
272 };
274 /* 'adc_tsc' class */
275 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
276         .name           = "adc_tsc",
277 };
279 /* adc_tsc */
280 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
281         { .irq = AM33XX_IRQ_TSC },
282         { .irq = -1 }
283 };
285 static struct omap_hwmod_ocp_if *am33xx_adc_tsc_slaves[] = {
286         &am33xx_l4_wkup_adc_tsc,
287 };
289 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
290         .name           = "adc_tsc",
291         .class          = &am33xx_adc_tsc_hwmod_class,
292         .mpu_irqs       = am33xx_adc_tsc_irqs,
293         .main_clk       = "adc_tsc_fck",
294         .clkdm_name     = "l4_wkup_clkdm",
295         .prcm           = {
296                 .omap4  = {
297                         .clkctrl_offs   = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
298                         .modulemode     = MODULEMODE_SWCTRL,
299                 },
300         },
301         .flags          = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
302         .slaves         = am33xx_adc_tsc_slaves,
303         .slaves_cnt     = ARRAY_SIZE(am33xx_adc_tsc_slaves),
304 };
306 /* 'aes' class */
307 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
308         .name           = "aes",
309 };
311 /* aes0 */
312 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
313         { .irq = AM33XX_IRQ_AESEIP36t0_S },
314         { .irq = -1 }
315 };
317 static struct omap_hwmod am33xx_aes0_hwmod = {
318         .name           = "aes0",
319         .class          = &am33xx_aes_hwmod_class,
320         .mpu_irqs       = am33xx_aes0_irqs,
321         .main_clk       = "aes0_fck",
322         .clkdm_name     = "l3_clkdm",
323         .prcm           = {
324                 .omap4  = {
325                         .clkctrl_offs   = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
326                         .modulemode     = MODULEMODE_SWCTRL,
327                 },
328         },
329 };
331 /* 'cefuse' class */
332 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
333         .name           = "cefuse",
334 };
336 /* cefuse */
337 static struct omap_hwmod am33xx_cefuse_hwmod = {
338         .name           = "cefuse",
339         .class          = &am33xx_cefuse_hwmod_class,
340         .main_clk       = "cefuse_fck",
341         .clkdm_name     = "l4_cefuse_clkdm",
342         .prcm           = {
343                 .omap4  = {
344                         .clkctrl_offs   = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
345                         .modulemode     = MODULEMODE_SWCTRL,
346                 },
347         },
348 };
350 /* 'clkdiv32k' class */
351 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
352         .name           = "clkdiv32k",
353 };
355 /* clkdiv32k */
356 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
357         .name           = "clkdiv32k",
358         .class          = &am33xx_clkdiv32k_hwmod_class,
359         .main_clk       = "clkdiv32k_fck",
360         .clkdm_name     = "clk_24mhz_clkdm",
361         .prcm           = {
362                 .omap4  = {
363                         .clkctrl_offs   = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
364                         .modulemode     = MODULEMODE_SWCTRL,
365                 },
366         },
367         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
368 };
370 /* 'control' class */
371 static struct omap_hwmod_class am33xx_control_hwmod_class = {
372         .name           = "control",
373 };
375 /* control */
376 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
377         { .irq = AM33XX_IRQ_CONTROL_PLATFORM },
378         { .irq = -1 }
379 };
381 static struct omap_hwmod am33xx_control_hwmod = {
382         .name           = "control",
383         .class          = &am33xx_control_hwmod_class,
384         .mpu_irqs       = am33xx_control_irqs,
385         .main_clk       = "control_fck",
386         .clkdm_name     = "l4_wkup_clkdm",
387         .prcm           = {
388                 .omap4  = {
389                         .clkctrl_offs   = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
390                         .modulemode     = MODULEMODE_SWCTRL,
391                 },
392         },
393         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
394 };
396 /* 'cpgmac0' class */
397 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
398         .name           = "cpgmac0",
399 };
401 /* cpgmac0 */
402 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
403         .name           = "cpgmac0",
404         .class          = &am33xx_cpgmac0_hwmod_class,
405         .main_clk       = "cpgmac0_fck",
406         .clkdm_name     = "cpsw_125mhz_clkdm",
407         .prcm           = {
408                 .omap4  = {
409                         .clkctrl_offs   = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
410                         .modulemode     = MODULEMODE_SWCTRL,
411                 },
412         },
413 };
415 /* 'dcan' class */
416 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
417         .name           = "dcan",
418 };
420 /* dcan0 */
421 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
422         { .irq = AM33XX_IRQ_DCAN0_0 },
423         { .irq = -1 }
424 };
426 static struct omap_hwmod am33xx_dcan0_hwmod = {
427         .name           = "dcan0",
428         .class          = &am33xx_dcan_hwmod_class,
429         .mpu_irqs       = am33xx_dcan0_irqs,
430         .main_clk       = "dcan0_fck",
431         .clkdm_name     = "l4ls_clkdm",
432         .prcm           = {
433                 .omap4  = {
434                         .clkctrl_offs   = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
435                         .modulemode     = MODULEMODE_SWCTRL,
436                 },
437         },
438 };
440 /* dcan1 */
441 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
442         { .irq = AM33XX_IRQ_DCAN1_0 },
443         { .irq = -1 }
444 };
445 static struct omap_hwmod am33xx_dcan1_hwmod = {
446         .name           = "dcan1",
447         .class          = &am33xx_dcan_hwmod_class,
448         .mpu_irqs       = am33xx_dcan1_irqs,
449         .main_clk       = "dcan1_fck",
450         .clkdm_name     = "l4ls_clkdm",
451         .prcm           = {
452                 .omap4  = {
453                         .clkctrl_offs   = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
454                         .modulemode     = MODULEMODE_SWCTRL,
455                 },
456         },
457 };
459 /* 'debugss' class */
460 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
461         .name           = "debugss",
462 };
464 /* debugss */
465 static struct omap_hwmod am33xx_debugss_hwmod = {
466         .name           = "debugss",
467         .class          = &am33xx_debugss_hwmod_class,
468         .main_clk       = "debugss_fck",
469         .clkdm_name     = "l3_aon_clkdm",
470         .prcm           = {
471                 .omap4  = {
472                         .clkctrl_offs   = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
473                         .modulemode     = MODULEMODE_SWCTRL,
474                 },
475         },
476 #ifdef CONFIG_DEBUG_JTAG_ENABLE
477         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
478 #endif
479 };
481 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
482         .rev_offs       = 0x0000,
483         .sysc_offs      = 0x0010,
484         .syss_offs      = 0x0014,
485         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
486                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
487                         SYSS_HAS_RESET_STATUS),
488         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
489         .sysc_fields    = &omap_hwmod_sysc_type1,
490 };
491 /* 'elm' class */
492 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
493         .name           = "elm",
494         .sysc           = &am33xx_elm_sysc,
495 };
497 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
498         { .irq = AM33XX_IRQ_ELM },
499         { .irq = -1 }
500 };
502 struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
503         {
504                 .pa_start       = AM33XX_ELM_BASE,
505                 .pa_end         = AM33XX_ELM_BASE + SZ_8K - 1,
506                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
507         },
508         { }
509 };
511 struct omap_hwmod_ocp_if am33xx_l4_core__elm = {
512         .master         = &am33xx_l4per_hwmod,
513         .slave          = &am33xx_elm_hwmod,
514         .addr           = am33xx_elm_addr_space,
515         .user           = OCP_USER_MPU,
516 };
518 static struct omap_hwmod_ocp_if *am33xx_elm_slaves[] = {
519         &am33xx_l4_core__elm,
520 };
522 /* elm */
523 static struct omap_hwmod am33xx_elm_hwmod = {
524         .name           = "elm",
525         .class          = &am33xx_elm_hwmod_class,
526         .mpu_irqs       = am33xx_elm_irqs,
527         .main_clk       = "elm_fck",
528         .clkdm_name     = "l4ls_clkdm",
529         .slaves         = am33xx_elm_slaves,
530         .slaves_cnt     = ARRAY_SIZE(am33xx_elm_slaves),
531         .prcm           = {
532                 .omap4  = {
533                         .clkctrl_offs   = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
534                         .modulemode     = MODULEMODE_SWCTRL,
535                 },
536         },
537 };
539 /* 'emif_fw' class */
540 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
541         .name           = "emif_fw",
542 };
544 /* emif_fw */
545 static struct omap_hwmod am33xx_emif_fw_hwmod = {
546         .name           = "emif_fw",
547         .class          = &am33xx_emif_fw_hwmod_class,
548         .main_clk       = "emif_fw_fck",
549         .clkdm_name     = "l4fw_clkdm",
550         .prcm           = {
551                 .omap4  = {
552                         .clkctrl_offs   = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
553                         .modulemode     = MODULEMODE_SWCTRL,
554                 },
555         },
556         .flags          = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
557 };
559 /* 'epwmss' class */
560 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
561         .rev_offs       = 0x0,
562         .sysc_offs      = 0x10,
563         .sysc_flags     = SYSC_HAS_SIDLEMODE,
564         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
565                         SIDLE_SMART_WKUP),
566         .sysc_fields    = &omap_hwmod_sysc_type2,
567 };
569 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
570         .name           = "epwmss",
571         .sysc           = &am33xx_epwmss_sysc,
572 };
574 /* epwmss0 */
575 static struct omap_hwmod_irq_info am33xx_epwmss0_irqs[] = {
576         { .irq          = AM33XX_IRQ_PWMSS0_EPWM },
577         { .irq          = AM33XX_IRQ_PWMSS0 },
578         { .irq          = AM33XX_IRQ_PWMSS0_ECAP },
579         { .irq          = -1 }
580 };
582 struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
583         {
584                 .pa_start       = AM33XX_EPWMSS0_BASE,
585                 .pa_end         = AM33XX_EPWMSS0_BASE + SZ_4K - 1,
586                 .flags          = ADDR_TYPE_RT
587         },
588         { }
589 };
591 struct omap_hwmod_ocp_if am33xx_l4_core__epwmss0 = {
592         .master         = &am33xx_l4per_hwmod,
593         .slave          = &am33xx_epwmss0_hwmod,
594         .addr           = am33xx_epwmss0_addr_space,
595         .user           = OCP_USER_MPU,
596 };
598 static struct omap_hwmod_ocp_if *am33xx_epwmss0_slaves[] = {
599         &am33xx_l4_core__epwmss0,
600 };
602 static struct omap_hwmod am33xx_epwmss0_hwmod = {
603         .name           = "epwmss0",
604         .mpu_irqs       = am33xx_epwmss0_irqs,
605         .class          = &am33xx_epwmss_hwmod_class,
606         .main_clk       = "epwmss0_fck",
607         .clkdm_name     = "l4ls_clkdm",
608         .prcm           = {
609                 .omap4  = {
610                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
611                         .modulemode     = MODULEMODE_SWCTRL,
612                 },
613         },
614         .slaves         = am33xx_epwmss0_slaves,
615         .slaves_cnt     = ARRAY_SIZE(am33xx_epwmss0_slaves),
616 };
618 /* epwmss1 */
619 static struct omap_hwmod_irq_info am33xx_epwmss1_irqs[] = {
620         { .irq          = AM33XX_IRQ_PWMSS1_EPWM },
621         { .irq          = AM33XX_IRQ_PWMSS1 },
622         { .irq          = AM33XX_IRQ_PWMSS1_ECAP },
623         { .irq          = -1 }
624 };
626 struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
627         {
628                 .pa_start       = AM33XX_EPWMSS1_BASE,
629                 .pa_end         = AM33XX_EPWMSS1_BASE + SZ_4K - 1,
630                 .flags          = ADDR_TYPE_RT
631         },
632         { }
633 };
635 struct omap_hwmod_ocp_if am33xx_l4_core__epwmss1 = {
636         .master         = &am33xx_l4per_hwmod,
637         .slave          = &am33xx_epwmss1_hwmod,
638         .addr           = am33xx_epwmss1_addr_space,
639         .user           = OCP_USER_MPU,
640 };
642 static struct omap_hwmod_ocp_if *am33xx_epwmss1_slaves[] = {
643         &am33xx_l4_core__epwmss1,
644 };
646 static struct omap_hwmod am33xx_epwmss1_hwmod = {
647         .name           = "epwmss1",
648         .mpu_irqs       = am33xx_epwmss1_irqs,
649         .class          = &am33xx_epwmss_hwmod_class,
650         .main_clk       = "epwmss1_fck",
651         .clkdm_name     = "l4ls_clkdm",
652         .prcm           = {
653                 .omap4  = {
654                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
655                         .modulemode     = MODULEMODE_SWCTRL,
656                 },
657         },
658         .slaves         = am33xx_epwmss1_slaves,
659         .slaves_cnt     = ARRAY_SIZE(am33xx_epwmss1_slaves),
660 };
662 /* epwmss2 */
663 static struct omap_hwmod_irq_info am33xx_epwmss2_irqs[] = {
664         { .irq          = AM33XX_IRQ_PWMSS2_EPWM },
665         { .irq          = AM33XX_IRQ_PWMSS2 },
666         { .irq          = AM33XX_IRQ_PWMSS2_ECAP },
667         { .irq          = -1 }
668 };
670 struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
671         {
672                 .pa_start       = AM33XX_EPWMSS2_BASE,
673                 .pa_end         = AM33XX_EPWMSS2_BASE + SZ_4K - 1,
674                 .flags          = ADDR_TYPE_RT
675         },
676         { }
677 };
679 struct omap_hwmod_ocp_if am33xx_l4_core__epwmss2 = {
680         .master         = &am33xx_l4per_hwmod,
681         .slave          = &am33xx_epwmss2_hwmod,
682         .addr           = am33xx_epwmss2_addr_space,
683         .user           = OCP_USER_MPU,
684 };
686 static struct omap_hwmod_ocp_if *am33xx_epwmss2_slaves[] = {
687         &am33xx_l4_core__epwmss2,
688 };
690 static struct omap_hwmod am33xx_epwmss2_hwmod = {
691         .name           = "epwmss2",
692         .mpu_irqs       = am33xx_epwmss2_irqs,
693         .class          = &am33xx_epwmss_hwmod_class,
694         .main_clk       = "epwmss2_fck",
695         .clkdm_name     = "l4ls_clkdm",
696         .prcm           = {
697                 .omap4  = {
698                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
699                         .modulemode     = MODULEMODE_SWCTRL,
700                 },
701         },
702         .slaves         = am33xx_epwmss2_slaves,
703         .slaves_cnt     = ARRAY_SIZE(am33xx_epwmss2_slaves),
704 };
706 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
707         .rev_offs       = 0x0000,
708         .sysc_offs      = 0x0010,
709         .syss_offs      = 0x0114,
710         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
711                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
712         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
713                                 SIDLE_SMART_WKUP),
714         .sysc_fields    = &omap_hwmod_sysc_type1,
715 };
717 /* 'gpio' class */
718 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
719         .name           = "gpio",
720         .sysc           = &am33xx_gpio_sysc,
721         .rev            = 2,
722 };
724 /* gpio dev_attr */
725 static struct omap_gpio_dev_attr gpio_dev_attr = {
726         .bank_width     = 32,
727         .dbck_flag      = true,
728 };
730 /* gpio0 */
731 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
732         { .irq = AM33XX_IRQ_GPIO0_1 },
733         { .irq = -1 }
734 };
736 /* gpio0 slave ports */
737 static struct omap_hwmod_ocp_if *am33xx_gpio0_slaves[] = {
738         &am33xx_l4_wkup__gpio0,
739 };
741 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
742         { .role = "dbclk", .clk = "gpio0_dbclk" },
743         { .role = "fclk", .clk = "gpio0_fck" },
744 };
746 /* gpio0 */
747 static struct omap_hwmod am33xx_gpio0_hwmod = {
748         .name           = "gpio1",
749         .class          = &am33xx_gpio_hwmod_class,
750         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
751         .mpu_irqs       = am33xx_gpio0_irqs,
752         .main_clk       = "gpio0_fck",
753         .clkdm_name     = "l4_wkup_clkdm",
754         .prcm           = {
755                 .omap4  = {
756                         .clkctrl_offs   = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
757                         .modulemode     = MODULEMODE_SWCTRL,
758                 },
759         },
760         .opt_clks       = gpio0_opt_clks,
761         .opt_clks_cnt   = ARRAY_SIZE(gpio0_opt_clks),
762         .dev_attr       = &gpio_dev_attr,
763         .slaves         = am33xx_gpio0_slaves,
764         .slaves_cnt     = ARRAY_SIZE(am33xx_gpio0_slaves),
765 };
767 /* gpio1 */
768 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
769         { .irq = AM33XX_IRQ_GPIO1_1 },
770         { .irq = -1 }
771 };
773 /* gpio1 slave ports */
774 static struct omap_hwmod_ocp_if *am33xx_gpio1_slaves[] = {
775         &am33xx_l4_per__gpio1,
776 };
778 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
779         { .role = "dbclk", .clk = "gpio1_dbclk" },
780         { .role = "fclk", .clk = "gpio1_fck" },
781 };
783 static struct omap_hwmod am33xx_gpio1_hwmod = {
784         .name           = "gpio2",
785         .class          = &am33xx_gpio_hwmod_class,
786         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
787         .mpu_irqs       = am33xx_gpio1_irqs,
788         .main_clk       = "gpio1_fck",
789         .clkdm_name     = "l4ls_clkdm",
790         .prcm           = {
791                 .omap4  = {
792                         .clkctrl_offs   = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
793                         .modulemode     = MODULEMODE_SWCTRL,
794                 },
795         },
796         .opt_clks       = gpio1_opt_clks,
797         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
798         .dev_attr       = &gpio_dev_attr,
799         .slaves         = am33xx_gpio1_slaves,
800         .slaves_cnt     = ARRAY_SIZE(am33xx_gpio1_slaves),
801 };
803 /* gpio2 */
804 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
805         { .irq = AM33XX_IRQ_GPIO2_1 },
806         { .irq = -1 }
807 };
809 /* gpio2 slave ports */
810 static struct omap_hwmod_ocp_if *am33xx_gpio2_slaves[] = {
811         &am33xx_l4_per__gpio2,
812 };
814 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
815         { .role = "dbclk", .clk = "gpio2_dbclk" },
816         { .role = "fclk", .clk = "gpio2_fck" },
817 };
819 /* gpio2 */
820 static struct omap_hwmod am33xx_gpio2_hwmod = {
821         .name           = "gpio3",
822         .class          = &am33xx_gpio_hwmod_class,
823         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
824         .mpu_irqs       = am33xx_gpio2_irqs,
825         .main_clk       = "gpio2_fck",
826         .clkdm_name     = "l4ls_clkdm",
827         .prcm           = {
828                 .omap4  = {
829                         .clkctrl_offs   = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
830                         .modulemode     = MODULEMODE_SWCTRL,
831                 },
832         },
833         .opt_clks       = gpio2_opt_clks,
834         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
835         .dev_attr       = &gpio_dev_attr,
836         .slaves         = am33xx_gpio2_slaves,
837         .slaves_cnt     = ARRAY_SIZE(am33xx_gpio2_slaves),
838 };
840 /* gpio3 */
841 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
842         { .irq = AM33XX_IRQ_GPIO3_1 },
843         { .irq = -1 }
844 };
846 /* gpio3 slave ports */
847 static struct omap_hwmod_ocp_if *am33xx_gpio3_slaves[] = {
848         &am33xx_l4_per__gpio3,
849 };
851 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
852         { .role = "dbclk", .clk = "gpio3_dbclk" },
853         { .role = "fclk", .clk = "gpio3_fck" },
854 };
856 /* gpio3 */
857 static struct omap_hwmod am33xx_gpio3_hwmod = {
858         .name           = "gpio4",
859         .class          = &am33xx_gpio_hwmod_class,
860         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
861         .mpu_irqs       = am33xx_gpio3_irqs,
862         .main_clk       = "gpio3_fck",
863         .clkdm_name     = "l4ls_clkdm",
864         .prcm           = {
865                 .omap4  = {
866                         .clkctrl_offs   = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
867                         .modulemode     = MODULEMODE_SWCTRL,
868                 },
869         },
870         .opt_clks       = gpio3_opt_clks,
871         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
872         .dev_attr       = &gpio_dev_attr,
873         .slaves         = am33xx_gpio3_slaves,
874         .slaves_cnt     = ARRAY_SIZE(am33xx_gpio3_slaves),
875 };
877 /* 'gpmc' class */
879 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
880         .name           = "gpmc",
881 };
883 /* gpmc */
884 static struct omap_hwmod am33xx_gpmc_hwmod = {
885         .name           = "gpmc",
886         .class          = &am33xx_gpmc_hwmod_class,
887         .main_clk       = "gpmc_fck",
888         .clkdm_name     = "l3s_clkdm",
889         .prcm           = {
890                 .omap4  = {
891                         .clkctrl_offs   = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
892                         .modulemode     = MODULEMODE_SWCTRL,
893                 },
894         },
895 };
897 /* 'i2c' class */
899 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
900         .sysc_offs      = 0x0010,
901         .syss_offs      = 0x0090,
902         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
903                         SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
904                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
905         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
906                         SIDLE_SMART_WKUP),
907         .sysc_fields    = &omap_hwmod_sysc_type1,
908 };
910 static struct omap_i2c_dev_attr i2c_dev_attr = {
911         .flags          = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
912 };
914 static struct omap_hwmod_class i2c_class = {
915         .name           = "i2c",
916         .sysc           = &am33xx_i2c_sysc,
917         .rev            = OMAP_I2C_IP_VERSION_2,
918         .reset          = &omap_i2c_reset,
919 };
921 /* I2C1 */
922 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
923         { .irq = AM33XX_IRQ_MSHSI2COCP0 },
924         { .irq = -1 }
925 };
927 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
928         { .name = "tx", .dma_req = 0, },
929         { .name = "rx", .dma_req = 0, },
930         { .dma_req = -1 }
931 };
933 static struct omap_hwmod_ocp_if *am33xx_i2c1_slaves[] = {
934         &am33xx_l4_wkup_i2c1,
935 };
937 static struct omap_hwmod am33xx_i2c1_hwmod = {
938         .name           = "i2c1",
939         .mpu_irqs       = i2c1_mpu_irqs,
940         .sdma_reqs      = i2c1_edma_reqs,
941         .main_clk       = "i2c1_fck",
942         .clkdm_name     = "l4_wkup_clkdm",
943         .prcm           = {
944                 .omap4  = {
945                         .clkctrl_offs   = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
946                         .modulemode     = MODULEMODE_SWCTRL,
947                 },
948         },
949         .flags          = HWMOD_16BIT_REG,
950         .dev_attr       = &i2c_dev_attr,
951         .slaves         = am33xx_i2c1_slaves,
952         .slaves_cnt     = ARRAY_SIZE(am33xx_i2c1_slaves),
953         .class          = &i2c_class,
954 };
956 /* i2c2 */
957 /* l4 per -> i2c2 */
958 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
959         {
960                 .pa_start       = AM33XX_I2C1_BASE,
961                 .pa_end         = AM33XX_I2C1_BASE + SZ_4K - 1,
962                 .flags          = ADDR_TYPE_RT
963         },
964         { }
965 };
967 static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = {
968         .master         = &am33xx_l4per_hwmod,
969         .slave          = &am33xx_i2c2_hwmod,
970         .addr           = am33xx_i2c2_addr_space,
971         .user           = OCP_USER_MPU,
972 };
974 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
975         { .irq = AM33XX_IRQ_MSHSI2COCP1 },
976         { .irq = -1 }
977 };
979 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
980         { .name = "tx", .dma_req = 0, },
981         { .name = "rx", .dma_req = 0, },
982         { .dma_req = -1 }
983 };
985 static struct omap_hwmod_ocp_if *am33xx_i2c2_slaves[] = {
986         &am335_l4_per_i2c2,
987 };
989 static struct omap_hwmod am33xx_i2c2_hwmod = {
990         .name           = "i2c2",
991         .mpu_irqs       = i2c2_mpu_irqs,
992         .sdma_reqs      = i2c2_edma_reqs,
993         .main_clk       = "i2c2_fck",
994         .clkdm_name     = "l4ls_clkdm",
995         .prcm           = {
996                 .omap4 = {
997                         .clkctrl_offs   = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
998                         .modulemode     = MODULEMODE_SWCTRL,
999                 },
1000         },
1001         .flags          = HWMOD_16BIT_REG,
1002         .dev_attr       = &i2c_dev_attr,
1003         .slaves         = am33xx_i2c2_slaves,
1004         .slaves_cnt     = ARRAY_SIZE(am33xx_i2c2_slaves),
1005         .class          = &i2c_class,
1006 };
1008 /* 'icss' class */
1009 static struct omap_hwmod_class am33xx_icss_hwmod_class = {
1010         .name = "icss",
1011 };
1013 /* icss */
1014 static struct omap_hwmod am33xx_icss_hwmod = {
1015         .name           = "icss",
1016         .class          = &am33xx_icss_hwmod_class,
1017         .main_clk       = "icss_fck",
1018         .clkdm_name     = "icss_ocp_clkdm",
1019         .prcm           = {
1020                 .omap4  = {
1021                         .clkctrl_offs   = AM33XX_CM_PER_ICSS_CLKCTRL_OFFSET,
1022                         .modulemode     = MODULEMODE_SWCTRL,
1023                 },
1024         },
1025 };
1027 /* 'ieee5000' class */
1028 static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = {
1029         .name           = "ieee5000",
1030 };
1032 /* ieee5000 */
1033 static struct omap_hwmod am33xx_ieee5000_hwmod = {
1034         .name           = "ieee5000",
1035         .class          = &am33xx_ieee5000_hwmod_class,
1036         .main_clk       = "ieee5000_fck",
1037         .clkdm_name     = "l3s_clkdm",
1038         .prcm           = {
1039                 .omap4  = {
1040                         .clkctrl_offs   = AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET,
1041                         .modulemode     = MODULEMODE_SWCTRL,
1042                 },
1043         },
1044 };
1047 /* 'l3' class */
1048 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
1049         .name           = "l3",
1050 };
1052 /* l4_hs */
1053 static struct omap_hwmod am33xx_l4_hs_hwmod = {
1054         .name           = "l4_hs",
1055         .class          = &am33xx_l3_hwmod_class,
1056         .clkdm_name     = "l4hs_clkdm",
1057         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1058         .prcm           = {
1059                 .omap4  = {
1060                         .clkctrl_offs   = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
1061                         .modulemode     = MODULEMODE_SWCTRL,
1062                 },
1063         },
1064 };
1066 /* l3_instr */
1067 static struct omap_hwmod am33xx_l3_instr_hwmod = {
1068         .name           = "l3_instr",
1069         .class          = &am33xx_l3_hwmod_class,
1070         .clkdm_name     = "l3_clkdm",
1071         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1072         .prcm           = {
1073                 .omap4  = {
1074                         .clkctrl_offs   = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
1075                         .modulemode     = MODULEMODE_SWCTRL,
1076                 },
1077         },
1078 };
1080 /* l3_main */
1081 static struct omap_hwmod am33xx_l3_main_hwmod = {
1082         .name           = "l3_main",
1083         .class          = &am33xx_l3_hwmod_class,
1084         .clkdm_name     = "l3_clkdm",
1085         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1086         .prcm           = {
1087                 .omap4  = {
1088                         .clkctrl_offs   = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
1089                         .modulemode     = MODULEMODE_SWCTRL,
1090                 },
1091         },
1092 };
1094 /* 'l4fw' class */
1095 static struct omap_hwmod_class am33xx_l4fw_hwmod_class = {
1096         .name           = "l4fw",
1097 };
1099 /* l4fw */
1100 static struct omap_hwmod am33xx_l4fw_hwmod = {
1101         .name           = "l4fw",
1102         .class          = &am33xx_l4fw_hwmod_class,
1103         .clkdm_name     = "l4fw_clkdm",
1104         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1105         .prcm           = {
1106                 .omap4  = {
1107                         .clkctrl_offs   = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
1108                         .modulemode     = MODULEMODE_SWCTRL,
1109                 },
1110         },
1111 };
1113 /* 'l4ls' class */
1114 static struct omap_hwmod_class am33xx_l4ls_hwmod_class = {
1115         .name           = "l4ls",
1116 };
1118 /* l4ls */
1119 static struct omap_hwmod am33xx_l4ls_hwmod = {
1120         .name           = "l4ls",
1121         .class          = &am33xx_l4ls_hwmod_class,
1122         .main_clk       = "l4ls_fck",
1123         .clkdm_name     = "l4ls_clkdm",
1124         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1125         .prcm           = {
1126                 .omap4  = {
1127                         .clkctrl_offs   = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
1128                         .modulemode     = MODULEMODE_SWCTRL,
1129                 },
1130         },
1131 };
1133 /* 'lcdc' class */
1134 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1135         .name           = "lcdc",
1136 };
1138 /* lcdc */
1139 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1140         { .irq = AM33XX_IRQ_LCD },
1141         { .irq = -1 }
1142 };
1144 static struct omap_hwmod am33xx_lcdc_hwmod = {
1145         .name           = "lcdc",
1146         .class          = &am33xx_lcdc_hwmod_class,
1147         .mpu_irqs       = am33xx_lcdc_irqs,
1148         .main_clk       = "lcdc_fck",
1149         .clkdm_name     = "lcdc_clkdm",
1150         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1151         .prcm           = {
1152                 .omap4  = {
1153                         .clkctrl_offs   = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1154                         .modulemode     = MODULEMODE_SWCTRL,
1155                 },
1156         },
1157 };
1159 /*
1160  * 'mailbox' class
1161  * mailbox module allowing communication between the on-chip processors using a
1162  * queued mailbox-interrupt mechanism.
1163  */
1165 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1166         .rev_offs       = 0x0000,
1167         .sysc_offs      = 0x0010,
1168         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1169                            SYSC_HAS_SOFTRESET),
1170         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1171         .sysc_fields    = &omap_hwmod_sysc_type2,
1172 };
1174 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1175         .name   = "mailbox",
1176         .sysc   = &am33xx_mailbox_sysc,
1177 };
1179 /* mailbox */
1180 static struct omap_hwmod am33xx_mailbox_hwmod;
1181 static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1182         { .irq = AM33XX_IRQ_MAILBOX },
1183         { .irq = -1 }
1184 };
1186 static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
1187         {
1188                 .pa_start       = AM33XX_MAILBOX0_BASE,
1189                 .pa_end         = AM33XX_MAILBOX0_BASE + (SZ_4K - 1),
1190                 .flags          = ADDR_TYPE_RT
1191         },
1192         { }
1193 };
1195 /* l4_cfg -> mailbox */
1196 static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
1197         .master         = &am33xx_l4per_hwmod,
1198         .slave          = &am33xx_mailbox_hwmod,
1199         .addr           = am33xx_mailbox_addrs,
1200         .user           = OCP_USER_MPU,
1201 };
1203 /* mailbox slave ports */
1204 static struct omap_hwmod_ocp_if *am33xx_mailbox_slaves[] = {
1205         &am33xx_l4_per__mailbox,
1206 };
1208 static struct omap_hwmod am33xx_mailbox_hwmod = {
1209         .name           = "mailbox",
1210         .class          = &am33xx_mailbox_hwmod_class,
1211         .clkdm_name     = "l4ls_clkdm",
1212         .mpu_irqs       = am33xx_mailbox_irqs,
1213         .main_clk       = "mailbox0_fck",
1214         .prcm = {
1215                 .omap4 = {
1216                         .clkctrl_offs   = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1217                         .modulemode     = MODULEMODE_SWCTRL,
1218                 },
1219         },
1220         .slaves         = am33xx_mailbox_slaves,
1221         .slaves_cnt     = ARRAY_SIZE(am33xx_mailbox_slaves),
1222 };
1224 /* 'mcasp' class */
1225 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1226         .name           = "mcasp",
1227 };
1229 /* mcasp0 */
1230 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1231         { .name = "ax", .irq = AM33XX_IRQ_MCASP0_AX, },
1232         { .name = "ar", .irq = AM33XX_IRQ_MCASP0_AR, },
1233         { .irq = -1 }
1234 };
1236 static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
1237         {
1238                 .pa_start       = AM33XX_ASP0_BASE,
1239                 .pa_end         = AM33XX_ASP0_BASE + (SZ_1K * 12) - 1,
1240                 .flags          = ADDR_TYPE_RT
1241         },
1242         { }
1243 };
1245 static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp0 = {
1246         .master         = &am33xx_l3slow_hwmod,
1247         .slave          = &am33xx_mcasp0_hwmod,
1248         .clk            = "mcasp0_ick",
1249         .addr           = am33xx_mcasp0_addr_space,
1250         .user           = OCP_USER_MPU,
1251 };
1253 static struct omap_hwmod_ocp_if *am33xx_mcasp0_slaves[] = {
1254         &am33xx_l3_slow__mcasp0,
1255 };
1257 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1258         .name           = "mcasp0",
1259         .class          = &am33xx_mcasp_hwmod_class,
1260         .mpu_irqs       = am33xx_mcasp0_irqs,
1261         .main_clk       = "mcasp0_fck",
1262         .clkdm_name     = "l3s_clkdm",
1263         .prcm           = {
1264                 .omap4  = {
1265                         .clkctrl_offs   = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1266                         .modulemode     = MODULEMODE_SWCTRL,
1267                 },
1268         },
1269         .slaves         = am33xx_mcasp0_slaves,
1270         .slaves_cnt     = ARRAY_SIZE(am33xx_mcasp0_slaves),
1271 };
1273 /* mcasp1 */
1274 static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
1275         { .name = "ax", .irq = AM33XX_IRQ_MCASP1_AX, },
1276         { .name = "ar", .irq = AM33XX_IRQ_MCASP1_AR, },
1277         { .irq = -1 }
1278 };
1280 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
1281         {
1282                 .pa_start       = AM33XX_ASP1_BASE,
1283                 .pa_end         = AM33XX_ASP1_BASE + (SZ_1K * 12) - 1,
1284                 .flags          = ADDR_TYPE_RT
1285         },
1286         { }
1287 };
1289 static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp1 = {
1290         .master         = &am33xx_l3slow_hwmod,
1291         .slave          = &am33xx_mcasp1_hwmod,
1292         .clk            = "mcasp1_ick",
1293         .addr           = am33xx_mcasp1_addr_space,
1294         .user           = OCP_USER_MPU,
1295 };
1297 static struct omap_hwmod_ocp_if *am33xx_mcasp1_slaves[] = {
1298         &am33xx_l3_slow__mcasp1,
1299 };
1301 static struct omap_hwmod am33xx_mcasp1_hwmod = {
1302         .name           = "mcasp1",
1303         .class          = &am33xx_mcasp_hwmod_class,
1304         .mpu_irqs       = am33xx_mcasp1_irqs,
1305         .main_clk       = "mcasp1_fck",
1306         .clkdm_name     = "l3s_clkdm",
1307         .prcm           = {
1308                 .omap4  = {
1309                         .clkctrl_offs   = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
1310                         .modulemode     = MODULEMODE_SWCTRL,
1311                 },
1312         },
1313         .slaves         = am33xx_mcasp1_slaves,
1314         .slaves_cnt     = ARRAY_SIZE(am33xx_mcasp1_slaves),
1315 };
1318 /* 'mmc' class */
1320 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1321         .rev_offs       = 0x1fc,
1322         .sysc_offs      = 0x10,
1323         .syss_offs      = 0x14,
1324         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1325                         SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1326                         SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1327         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1328         .sysc_fields    = &omap_hwmod_sysc_type1,
1329 };
1331 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1332         .name           = "mmc",
1333         .sysc           = &am33xx_mmc_sysc,
1334 };
1336 /* mmc0 */
1337 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1338         { .irq = AM33XX_IRQ_MMCHS0 },
1339         { .irq = -1 }
1340 };
1342 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1343         { .name = "tx", .dma_req = AM33XX_DMA_MMCHS0_W, },
1344         { .name = "rx", .dma_req = AM33XX_DMA_MMCHS0_R, },
1345         { .dma_req = -1 }
1346 };
1348 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
1349         {
1350                 .pa_start       = AM33XX_MMC0_BASE,
1351                 .pa_end         = AM33XX_MMC0_BASE + SZ_4K - 1,
1352                 .flags          = ADDR_TYPE_RT
1353         },
1354         { }
1355 };
1357 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc0 = {
1358         .master         = &am33xx_l4ls_hwmod,
1359         .slave          = &am33xx_mmc0_hwmod,
1360         .clk            = "mmc0_ick",
1361         .addr           = am33xx_mmc0_addr_space,
1362         .user           = OCP_USER_MPU,
1363 };
1365 static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = {
1366         &am33xx_l4ls__mmc0,
1367 };
1369 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1370         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1371 };
1373 static struct omap_hwmod am33xx_mmc0_hwmod = {
1374         .name           = "mmc1",
1375         .class          = &am33xx_mmc_hwmod_class,
1376         .mpu_irqs       = am33xx_mmc0_irqs,
1377         .sdma_reqs      = am33xx_mmc0_edma_reqs,
1378         .main_clk       = "mmc0_fck",
1379         .clkdm_name     = "l4ls_clkdm",
1380         .prcm           = {
1381                 .omap4  = {
1382                         .clkctrl_offs   = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1383                         .modulemode     = MODULEMODE_SWCTRL,
1384                 },
1385         },
1386         .dev_attr       = &am33xx_mmc0_dev_attr,
1387         .slaves         = am33xx_mmc0_slaves,
1388         .slaves_cnt     = ARRAY_SIZE(am33xx_mmc0_slaves),
1389 };
1391 /* mmc1 */
1392 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1393         { .irq = AM33XX_IRQ_MMCHS1 },
1394         { .irq = -1 }
1395 };
1397 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1398         { .name = "tx", .dma_req = AM33XX_DMA_MMCHS1_W, },
1399         { .name = "rx", .dma_req = AM33XX_DMA_MMCHS1_R, },
1400         { .dma_req = -1 }
1401 };
1403 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
1404         {
1405                 .pa_start       = AM33XX_MMC1_BASE,
1406                 .pa_end         = AM33XX_MMC1_BASE + SZ_4K - 1,
1407                 .flags          = ADDR_TYPE_RT
1408         },
1409         { }
1410 };
1412 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc1 = {
1413         .master         = &am33xx_l4ls_hwmod,
1414         .slave          = &am33xx_mmc1_hwmod,
1415         .clk            = "mmc1_ick",
1416         .addr           = am33xx_mmc1_addr_space,
1417         .user           = OCP_USER_MPU,
1418 };
1420 static struct omap_hwmod_ocp_if *am33xx_mmc1_slaves[] = {
1421         &am33xx_l4ls__mmc1,
1422 };
1424 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1425         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1426 };
1428 static struct omap_hwmod am33xx_mmc1_hwmod = {
1429         .name           = "mmc2",
1430         .class          = &am33xx_mmc_hwmod_class,
1431         .mpu_irqs       = am33xx_mmc1_irqs,
1432         .sdma_reqs      = am33xx_mmc1_edma_reqs,
1433         .main_clk       = "mmc1_fck",
1434         .clkdm_name     = "l4ls_clkdm",
1435         .prcm           = {
1436                 .omap4  = {
1437                         .clkctrl_offs   = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1438                         .modulemode     = MODULEMODE_SWCTRL,
1439                 },
1440         },
1441         .dev_attr       = &am33xx_mmc1_dev_attr,
1442         .slaves         = am33xx_mmc1_slaves,
1443         .slaves_cnt     = ARRAY_SIZE(am33xx_mmc1_slaves),
1444 };
1446 /* mmc2 */
1447 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1448         { .irq = AM33XX_IRQ_MMCHS2 },
1449         { .irq = -1 }
1450 };
1452 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1453         { .name = "tx", .dma_req = AM33XX_DMA_MMCHS2_W, },
1454         { .name = "rx", .dma_req = AM33XX_DMA_MMCHS2_R, },
1455         { .dma_req = -1 }
1456 };
1458 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
1459         {
1460                 .pa_start       = AM33XX_MMC2_BASE,
1461                 .pa_end         = AM33XX_MMC2_BASE + SZ_64K - 1,
1462                 .flags          = ADDR_TYPE_RT
1463         },
1464         { }
1465 };
1467 static struct omap_hwmod_ocp_if am33xx_l3_main__mmc2 = {
1468         .master         = &am33xx_l3_main_hwmod,
1469         .slave          = &am33xx_mmc2_hwmod,
1470         .clk            = "mmc2_ick",
1471         .addr           = am33xx_mmc2_addr_space,
1472         .user           = OCP_USER_MPU,
1473 };
1475 static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = {
1476         &am33xx_l3_main__mmc2,
1477 };
1479 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1480         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1481 };
1482 static struct omap_hwmod am33xx_mmc2_hwmod = {
1483         .name           = "mmc3",
1484         .class          = &am33xx_mmc_hwmod_class,
1485         .mpu_irqs       = am33xx_mmc2_irqs,
1486         .sdma_reqs      = am33xx_mmc2_edma_reqs,
1487         .main_clk       = "mmc2_fck",
1488         .clkdm_name     = "l3s_clkdm",
1489         .prcm           = {
1490                 .omap4  = {
1491                         .clkctrl_offs   = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1492                         .modulemode     = MODULEMODE_SWCTRL,
1493                 },
1494         },
1495         .dev_attr       = &am33xx_mmc2_dev_attr,
1496         .slaves         = am33xx_mmc2_slaves,
1497         .slaves_cnt     = ARRAY_SIZE(am33xx_mmc2_slaves),
1498 };
1500 /* Master interfaces on the MPU interconnect */
1501 static struct omap_hwmod_ocp_if *am33xx_l3_mpu_masters[] = {
1502         &am33xx_mpu__l3_slow,
1503 };
1505 /* mpu */
1506 static struct omap_hwmod am33xx_mpu_hwmod = {
1507         .name           = "mpu",
1508         .class          = &mpu_hwmod_class,
1509         .masters        = am33xx_l3_mpu_masters,
1510         .masters_cnt    = ARRAY_SIZE(am33xx_l3_mpu_masters),
1511         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1512         .main_clk       = "mpu_fck",
1513         .clkdm_name     = "mpu_clkdm",
1514         .prcm           = {
1515                 .omap4  = {
1516                         .clkctrl_offs   = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1517                         .modulemode     = MODULEMODE_SWCTRL,
1518                 },
1519         },
1520 };
1522 /* 'ocmcram' class */
1523 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
1524         .name = "ocmcram",
1525 };
1527 /* ocmcram */
1528 static struct omap_hwmod am33xx_ocmcram_hwmod = {
1529         .name           = "ocmcram",
1530         .class          = &am33xx_ocmcram_hwmod_class,
1531         .main_clk       = "ocmcram_fck",
1532         .clkdm_name     = "l3_clkdm",
1533         .prcm           = {
1534                 .omap4  = {
1535                         .clkctrl_offs   = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
1536                         .modulemode     = MODULEMODE_SWCTRL,
1537                 },
1538         },
1539         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1540 };
1542 /* 'ocpwp' class */
1543 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
1544         .name           = "ocpwp",
1545 };
1547 /* ocpwp */
1548 static struct omap_hwmod am33xx_ocpwp_hwmod = {
1549         .name           = "ocpwp",
1550         .class          = &am33xx_ocpwp_hwmod_class,
1551         .main_clk       = "ocpwp_fck",
1552         .clkdm_name     = "l4ls_clkdm",
1553         .prcm           = {
1554                 .omap4  = {
1555                         .clkctrl_offs   = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
1556                         .modulemode     = MODULEMODE_SWCTRL,
1557                 },
1558         },
1559 };
1561 /* 'rtc' class */
1562 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1563         .name           = "rtc",
1564 };
1566 /* rtc */
1567 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1568         { .irq = AM33XX_IRQ_RTC_TIMER },
1569         { .irq = -1 }
1570 };
1572 static struct omap_hwmod am33xx_rtc_hwmod = {
1573         .name           = "rtc",
1574         .class          = &am33xx_rtc_hwmod_class,
1575         .mpu_irqs       = am33xx_rtc_irqs,
1576         .main_clk       = "rtc_fck",
1577         .clkdm_name     = "l4_rtc_clkdm",
1578         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1579         .prcm           = {
1580                 .omap4  = {
1581                         .clkctrl_offs   = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1582                         .modulemode     = MODULEMODE_SWCTRL,
1583                 },
1584         },
1585 };
1587 /* 'sha0' class */
1588 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
1589         .name           = "sha0",
1590 };
1592 /* sha0 */
1593 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
1594         { .irq = AM33XX_IRQ_SHAEIP57t0_S },
1595         { .irq = -1 }
1596 };
1598 static struct omap_hwmod am33xx_sha0_hwmod = {
1599         .name           = "sha0",
1600         .class          = &am33xx_sha0_hwmod_class,
1601         .mpu_irqs       = am33xx_sha0_irqs,
1602         .main_clk       = "sha0_fck",
1603         .clkdm_name     = "l3_clkdm",
1604         .prcm           = {
1605                 .omap4  = {
1606                         .clkctrl_offs   = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
1607                         .modulemode     = MODULEMODE_SWCTRL,
1608                 },
1609         },
1610 };
1612 /* 'smartreflex' class */
1613 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
1614         .name           = "smartreflex",
1615 };
1617 /* smartreflex0 */
1618 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
1619         { .irq = AM33XX_IRQ_SMARTREFLEX0 },
1620         { .irq = -1 }
1621 };
1623 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
1624         .name           = "smartreflex0",
1625         .class          = &am33xx_smartreflex_hwmod_class,
1626         .mpu_irqs       = am33xx_smartreflex0_irqs,
1627         .main_clk       = "smartreflex0_fck",
1628         .clkdm_name     = "l4_wkup_clkdm",
1629         .prcm           = {
1630                 .omap4  = {
1631                         .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
1632                         .modulemode     = MODULEMODE_SWCTRL,
1633                 },
1634         },
1635 };
1637 /* smartreflex1 */
1638 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
1639         { .irq = AM33XX_IRQ_SMARTREFLEX1 },
1640         { .irq = -1 }
1641 };
1643 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
1644         .name           = "smartreflex1",
1645         .class          = &am33xx_smartreflex_hwmod_class,
1646         .mpu_irqs       = am33xx_smartreflex1_irqs,
1647         .main_clk       = "smartreflex1_fck",
1648         .clkdm_name     = "l4_wkup_clkdm",
1649         .prcm           = {
1650                 .omap4  = {
1651                         .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
1652                         .modulemode     = MODULEMODE_SWCTRL,
1653                 },
1654         },
1655 };
1657 /* 'spi' class */
1659 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1660         .rev_offs       = 0x0000,
1661         .sysc_offs      = 0x0110,
1662         .syss_offs      = 0x0114,
1663         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1664                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1665                         SYSS_HAS_RESET_STATUS),
1666         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1667         .sysc_fields    = &omap_hwmod_sysc_type1,
1668 };
1670 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1671         .name           = "mcspi",
1672         .sysc           = &am33xx_mcspi_sysc,
1673         .rev            = OMAP4_MCSPI_REV,
1674 };
1676 /* spi0 */
1677 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1678         { .irq = AM33XX_IRQ_MCSPIOCP0 },
1679         { .irq = -1 }
1680 };
1682 struct omap_hwmod_dma_info am33xx_mcspi0_sdma_reqs[] = {
1683         { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0R },
1684         { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0W },
1685         { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1R },
1686         { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1W },
1687         { .dma_req = -1 }
1688 };
1690 struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
1691         {
1692                 .pa_start       = AM33XX_SPI0_BASE,
1693                 .pa_end         = AM33XX_SPI0_BASE + SZ_1K - 1,
1694                 .flags          = ADDR_TYPE_RT
1695         },
1696         { }
1697 };
1699 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = {
1700         .master         = &am33xx_l4per_hwmod,
1701         .slave          = &am33xx_spi0_hwmod,
1702         .clk            = "spi0_ick",
1703         .addr           = am33xx_mcspi0_addr_space,
1704         .user           = OCP_USER_MPU,
1705 };
1707 static struct omap_hwmod_ocp_if *am33xx_mcspi0_slaves[] = {
1708         &am33xx_l4_core__mcspi0,
1709 };
1711 struct omap2_mcspi_dev_attr mcspi_attrib = {
1712         .num_chipselect = 2,
1713 };
1714 static struct omap_hwmod am33xx_spi0_hwmod = {
1715         .name           = "spi0",
1716         .class          = &am33xx_spi_hwmod_class,
1717         .mpu_irqs       = am33xx_spi0_irqs,
1718         .sdma_reqs      = am33xx_mcspi0_sdma_reqs,
1719         .main_clk       = "spi0_fck",
1720         .clkdm_name     = "l4ls_clkdm",
1721         .prcm           = {
1722                 .omap4  = {
1723                         .clkctrl_offs   = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1724                         .modulemode     = MODULEMODE_SWCTRL,
1725                 },
1726         },
1727         .dev_attr       = &mcspi_attrib,
1728         .slaves         = am33xx_mcspi0_slaves,
1729         .slaves_cnt     = ARRAY_SIZE(am33xx_mcspi0_slaves),
1730 };
1732 /* spi1 */
1733 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1734         { .irq = AM33XX_IRQ_SPI1 },
1735         { .irq = -1 }
1736 };
1738 struct omap_hwmod_dma_info am33xx_mcspi1_sdma_reqs[] = {
1739         { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0R },
1740         { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0W },
1741         { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1R },
1742         { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1W },
1743         { .dma_req = -1 }
1744 };
1746 struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
1747         {
1748                 .pa_start       = AM33XX_SPI1_BASE,
1749                 .pa_end         = AM33XX_SPI1_BASE + SZ_1K - 1,
1750                 .flags          = ADDR_TYPE_RT
1751         },
1752         { }
1753 };
1755 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = {
1756         .master         = &am33xx_l4per_hwmod,
1757         .slave          = &am33xx_spi1_hwmod,
1758         .clk            = "spi1_ick",
1759         .addr           = am33xx_mcspi1_addr_space,
1760         .user           = OCP_USER_MPU,
1761 };
1763 static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = {
1764         &am33xx_l4_core__mcspi1,
1765 };
1766 static struct omap_hwmod am33xx_spi1_hwmod = {
1767         .name           = "spi1",
1768         .class          = &am33xx_spi_hwmod_class,
1769         .mpu_irqs       = am33xx_spi1_irqs,
1770         .sdma_reqs      = am33xx_mcspi1_sdma_reqs,
1771         .main_clk       = "spi1_fck",
1772         .clkdm_name     = "l4ls_clkdm",
1773         .prcm           = {
1774                 .omap4  = {
1775                         .clkctrl_offs   = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1776                         .modulemode     = MODULEMODE_SWCTRL,
1777                 },
1778         },
1779         .dev_attr       = &mcspi_attrib,
1780         .slaves         = am33xx_mcspi1_slaves,
1781         .slaves_cnt     = ARRAY_SIZE(am33xx_mcspi1_slaves),
1782 };
1784 /* 'spinlock' class */
1785 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1786         .name           = "spinlock",
1787 };
1789 /* spinlock */
1790 static struct omap_hwmod am33xx_spinlock_hwmod = {
1791         .name           = "spinlock",
1792         .class          = &am33xx_spinlock_hwmod_class,
1793         .main_clk       = "spinlock_fck",
1794         .clkdm_name     = "l4ls_clkdm",
1795         .prcm           = {
1796                 .omap4  = {
1797                         .clkctrl_offs   = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1798                         .modulemode     = MODULEMODE_SWCTRL,
1799                 },
1800         },
1801 };
1803 /* 'timer 0 & 2-7' class */
1804 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1805         .rev_offs       = 0x0000,
1806         .sysc_offs      = 0x0010,
1807         .syss_offs      = 0x0014,
1808         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1809         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1810                         SIDLE_SMART_WKUP),
1811         .sysc_fields    = &omap_hwmod_sysc_type2,
1812 };
1814 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1815         .name           = "timer",
1816         .sysc           = &am33xx_timer_sysc,
1817 };
1819 /* timer0 */
1820 /* l4 wkup -> timer0 interface */
1821 static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = {
1822         {
1823                 .pa_start       = AM33XX_TIMER0_BASE,
1824                 .pa_end         = AM33XX_TIMER0_BASE + SZ_1K - 1,
1825                 .flags          = ADDR_TYPE_RT
1826         },
1827         { }
1828 };
1830 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = {
1831         .master         = &am33xx_l4wkup_hwmod,
1832         .slave          = &am33xx_timer0_hwmod,
1833         .clk            = "timer0_ick",
1834         .addr           = am33xx_timer0_addr_space,
1835         .user           = OCP_USER_MPU,
1836 };
1838 static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = {
1839         &am33xx_l4wkup__timer0,
1840 };
1842 static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = {
1843         { .irq = AM33XX_IRQ_DMTIMER0 },
1844         { .irq = -1 }
1845 };
1847 static struct omap_hwmod am33xx_timer0_hwmod = {
1848         .name           = "timer0",
1849         .class          = &am33xx_timer_hwmod_class,
1850         .mpu_irqs       = am33xx_timer0_irqs,
1851         .main_clk       = "timer0_fck",
1852         .clkdm_name     = "l4_wkup_clkdm",
1853         .prcm           = {
1854                 .omap4  = {
1855                         .clkctrl_offs   = AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET,
1856                         .modulemode     = MODULEMODE_SWCTRL,
1857                 },
1858         },
1859         .slaves         = am33xx_timer0_slaves,
1860         .slaves_cnt     = ARRAY_SIZE(am33xx_timer0_slaves),
1861 };
1863 /* timer1 1ms */
1864 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1865         .rev_offs       = 0x0000,
1866         .sysc_offs      = 0x0010,
1867         .syss_offs      = 0x0014,
1868         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1869                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1870                         SYSS_HAS_RESET_STATUS),
1871         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1872         .sysc_fields    = &omap_hwmod_sysc_type1,
1873 };
1875 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1876         .name           = "timer",
1877         .sysc           = &am33xx_timer1ms_sysc,
1878 };
1880 /* l4 wkup -> timer1 interface */
1881 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
1882         {
1883                 .pa_start       = AM33XX_TIMER1_BASE,
1884                 .pa_end         = AM33XX_TIMER1_BASE + SZ_1K - 1,
1885                 .flags          = ADDR_TYPE_RT
1886         },
1887         { }
1888 };
1890 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = {
1891         .master         = &am33xx_l4wkup_hwmod,
1892         .slave          = &am33xx_timer1_hwmod,
1893         .clk            = "timer1_ick",
1894         .addr           = am33xx_timer1_addr_space,
1895         .user           = OCP_USER_MPU,
1896 };
1898 static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = {
1899         &am33xx_l4wkup__timer1,
1900 };
1902 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
1903         { .irq = AM33XX_IRQ_DMTIMER1 },
1904         { .irq = -1 }
1905 };
1907 static struct omap_hwmod am33xx_timer1_hwmod = {
1908         .name           = "timer1",
1909         .class          = &am33xx_timer1ms_hwmod_class,
1910         .mpu_irqs       = am33xx_timer1_irqs,
1911         .main_clk       = "timer1_fck",
1912         .clkdm_name     = "l4_wkup_clkdm",
1913         .prcm           = {
1914                 .omap4  = {
1915                         .clkctrl_offs   = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1916                         .modulemode     = MODULEMODE_SWCTRL,
1917                 },
1918         },
1919         .slaves         = am33xx_timer1_slaves,
1920         .slaves_cnt     = ARRAY_SIZE(am33xx_timer1_slaves),
1921 };
1923 /* timer2 */
1924 /* l4 per -> timer2 interface */
1925 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
1926         {
1927                 .pa_start       = AM33XX_TIMER2_BASE,
1928                 .pa_end         = AM33XX_TIMER2_BASE + SZ_1K - 1,
1929                 .flags          = ADDR_TYPE_RT
1930         },
1931         { }
1932 };
1934 static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = {
1935         .master         = &am33xx_l4per_hwmod,
1936         .slave          = &am33xx_timer2_hwmod,
1937         .clk            = "timer2_ick",
1938         .addr           = am33xx_timer2_addr_space,
1939         .user           = OCP_USER_MPU,
1940 };
1942 static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = {
1943         &am33xx_l4per__timer2,
1944 };
1946 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
1947         { .irq = AM33XX_IRQ_DMTIMER2 },
1948         { .irq = -1 }
1949 };
1951 static struct omap_hwmod am33xx_timer2_hwmod = {
1952         .name           = "timer2",
1953         .class          = &am33xx_timer_hwmod_class,
1954         .mpu_irqs       = am33xx_timer2_irqs,
1955         .main_clk       = "timer2_fck",
1956         .prcm           = {
1957                 .omap4  = {
1958                         .clkctrl_offs   = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1959                         .modulemode     = MODULEMODE_SWCTRL,
1960                 },
1961         },
1962         .slaves         = am33xx_timer2_slaves,
1963         .slaves_cnt     = ARRAY_SIZE(am33xx_timer2_slaves),
1964         .clkdm_name     = "l4ls_clkdm",
1965 };
1967 /* timer3 */
1968 /* l4 per -> timer3 interface */
1969 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
1970         {
1971                 .pa_start       = AM33XX_TIMER3_BASE,
1972                 .pa_end         = AM33XX_TIMER3_BASE + SZ_1K - 1,
1973                 .flags          = ADDR_TYPE_RT
1974         },
1975         { }
1976 };
1978 static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = {
1979         .master         = &am33xx_l4per_hwmod,
1980         .slave          = &am33xx_timer3_hwmod,
1981         .clk            = "timer3_ick",
1982         .addr           = am33xx_timer3_addr_space,
1983         .user           = OCP_USER_MPU,
1984 };
1986 static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = {
1987         &am33xx_l4per__timer3,
1988 };
1990 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
1991         { .irq = AM33XX_IRQ_DMTIMER3 },
1992         { .irq = -1 }
1993 };
1995 static struct omap_hwmod am33xx_timer3_hwmod = {
1996         .name           = "timer3",
1997         .class          = &am33xx_timer_hwmod_class,
1998         .mpu_irqs       = am33xx_timer3_irqs,
1999         .main_clk       = "timer3_fck",
2000         .clkdm_name     = "l4ls_clkdm",
2001         .prcm           = {
2002                 .omap4  = {
2003                         .clkctrl_offs   = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
2004                         .modulemode     = MODULEMODE_SWCTRL,
2005                 },
2006         },
2007         .slaves         = am33xx_timer3_slaves,
2008         .slaves_cnt     = ARRAY_SIZE(am33xx_timer3_slaves),
2009 };
2011 /* timer4 */
2012 /* l4 per -> timer4 interface */
2013 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
2014         {
2015                 .pa_start       = AM33XX_TIMER4_BASE,
2016                 .pa_end         = AM33XX_TIMER4_BASE + SZ_1K - 1,
2017                 .flags          = ADDR_TYPE_RT
2018         },
2019         { }
2020 };
2022 static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = {
2023         .master         = &am33xx_l4per_hwmod,
2024         .slave          = &am33xx_timer4_hwmod,
2025         .clk            = "timer4_ick",
2026         .addr           = am33xx_timer4_addr_space,
2027         .user           = OCP_USER_MPU,
2028 };
2030 static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = {
2031         &am33xx_l4per__timer4,
2032 };
2034 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
2035         { .irq = AM33XX_IRQ_DMTIMER4 },
2036         { .irq = -1 }
2037 };
2039 static struct omap_hwmod am33xx_timer4_hwmod = {
2040         .name           = "timer4",
2041         .class          = &am33xx_timer_hwmod_class,
2042         .mpu_irqs       = am33xx_timer4_irqs,
2043         .main_clk       = "timer4_fck",
2044         .prcm           = {
2045                 .omap4  = {
2046                         .clkctrl_offs   = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
2047                         .modulemode     = MODULEMODE_SWCTRL,
2048                 },
2049         },
2050         .slaves         = am33xx_timer4_slaves,
2051         .slaves_cnt     = ARRAY_SIZE(am33xx_timer4_slaves),
2052         .clkdm_name     = "l4ls_clkdm",
2053 };
2056 /* timer5 */
2057 /* l4 per -> timer5 interface */
2058 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
2059         {
2060                 .pa_start       = AM33XX_TIMER5_BASE,
2061                 .pa_end         = AM33XX_TIMER5_BASE + SZ_1K - 1,
2062                 .flags          = ADDR_TYPE_RT
2063         },
2064         { }
2065 };
2067 static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = {
2068         .master         = &am33xx_l4per_hwmod,
2069         .slave          = &am33xx_timer5_hwmod,
2070         .clk            = "timer5_ick",
2071         .addr           = am33xx_timer5_addr_space,
2072         .user           = OCP_USER_MPU,
2073 };
2075 static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = {
2076         &am33xx_l4per__timer5,
2077 };
2079 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
2080         { .irq = AM33XX_IRQ_DMTIMER5 },
2081         { .irq = -1 }
2082 };
2084 static struct omap_hwmod am33xx_timer5_hwmod = {
2085         .name           = "timer5",
2086         .class          = &am33xx_timer_hwmod_class,
2087         .mpu_irqs       = am33xx_timer5_irqs,
2088         .main_clk       = "timer5_fck",
2089         .prcm           = {
2090                 .omap4  = {
2091                         .clkctrl_offs   = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
2092                         .modulemode     = MODULEMODE_SWCTRL,
2093                 },
2094         },
2095         .slaves         = am33xx_timer5_slaves,
2096         .slaves_cnt     = ARRAY_SIZE(am33xx_timer5_slaves),
2097         .clkdm_name     = "l4ls_clkdm",
2098 };
2100 /* timer6 */
2101 /* l4 per -> timer6 interface */
2102 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
2103         {
2104                 .pa_start       = AM33XX_TIMER6_BASE,
2105                 .pa_end         = AM33XX_TIMER6_BASE + SZ_1K - 1,
2106                 .flags          = ADDR_TYPE_RT
2107         },
2108         { }
2109 };
2111 static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = {
2112         .master         = &am33xx_l4per_hwmod,
2113         .slave          = &am33xx_timer6_hwmod,
2114         .clk            = "timer6_ick",
2115         .addr           = am33xx_timer6_addr_space,
2116         .user           = OCP_USER_MPU,
2117 };
2119 static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = {
2120         &am33xx_l4per__timer6,
2121 };
2123 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
2124         { .irq = AM33XX_IRQ_DMTIMER6 },
2125         { .irq = -1 }
2126 };
2128 static struct omap_hwmod am33xx_timer6_hwmod = {
2129         .name           = "timer6",
2130         .class          = &am33xx_timer_hwmod_class,
2131         .mpu_irqs       = am33xx_timer6_irqs,
2132         .main_clk       = "timer6_fck",
2133         .prcm           = {
2134                 .omap4  = {
2135                         .clkctrl_offs   = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
2136                         .modulemode     = MODULEMODE_SWCTRL,
2137                 },
2138         },
2139         .slaves         = am33xx_timer6_slaves,
2140         .slaves_cnt     = ARRAY_SIZE(am33xx_timer6_slaves),
2141         .clkdm_name     = "l4ls_clkdm",
2142 };
2144 /* timer7 */
2145 /* l4 per -> timer7 interface */
2146 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
2147         {
2148                 .pa_start       = AM33XX_TIMER7_BASE,
2149                 .pa_end         = AM33XX_TIMER7_BASE + SZ_1K - 1,
2150                 .flags          = ADDR_TYPE_RT
2151         },
2152         { }
2153 };
2155 static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = {
2156         .master         = &am33xx_l4per_hwmod,
2157         .slave          = &am33xx_timer7_hwmod,
2158         .clk            = "timer7_ick",
2159         .addr           = am33xx_timer7_addr_space,
2160         .user           = OCP_USER_MPU,
2161 };
2163 static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = {
2164         &am33xx_l4per__timer7,
2165 };
2167 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
2168         { .irq = AM33XX_IRQ_DMTIMER7 },
2169         { .irq = -1 }
2170 };
2172 static struct omap_hwmod am33xx_timer7_hwmod = {
2173         .name           = "timer7",
2174         .class          = &am33xx_timer_hwmod_class,
2175         .mpu_irqs       = am33xx_timer7_irqs,
2176         .main_clk       = "timer7_fck",
2177         .prcm           = {
2178                 .omap4  = {
2179                         .clkctrl_offs   = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
2180                         .modulemode     = MODULEMODE_SWCTRL,
2181                 },
2182         },
2183         .slaves         = am33xx_timer7_slaves,
2184         .slaves_cnt     = ARRAY_SIZE(am33xx_timer7_slaves),
2185         .clkdm_name     = "l4ls_clkdm",
2186 };
2188 /* 'tpcc' class */
2189 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
2190         .name           = "tpcc",
2191 };
2193 /* tpcc */
2194 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
2195         { .name = "edma0", .irq = AM33XX_IRQ_TPCC0_INT_PO0 },
2196         { .name = "edma0_err", .irq = AM33XX_IRQ_TPCC0_ERRINT_PO },
2197         { .irq = -1 },
2198 };
2200 /* TODO move this appropriate header. */
2201 #define AM33XX_TPCC_BASE                0x49000000
2203 static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
2204         {
2205                 .pa_start       = AM33XX_TPCC_BASE,
2206                 .pa_end         = AM33XX_TPCC_BASE + SZ_32K - 1,
2207                 .flags          = ADDR_TYPE_RT
2208         },
2209         { }
2210 };
2212 static struct omap_hwmod_ocp_if am33xx_l3_slow__tpcc = {
2213         .master         = &am33xx_l3slow_hwmod,
2214         .slave          = &am33xx_tpcc_hwmod,
2215         .addr           = am33xx_tpcc_addr_space,
2216         .user           = OCP_USER_MPU,
2217 };
2219 static struct omap_hwmod_ocp_if *am33xx_tpcc_slaves[] = {
2220         &am33xx_l3_slow__tpcc,
2221 };
2223 static struct omap_hwmod am33xx_tpcc_hwmod = {
2224         .name           = "tpcc",
2225         .class          = &am33xx_tpcc_hwmod_class,
2226         .mpu_irqs       = am33xx_tpcc_irqs,
2227         .main_clk       = "tpcc_ick",
2228         .clkdm_name     = "l3_clkdm",
2229         .prcm           = {
2230                 .omap4  = {
2231                         .clkctrl_offs   = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
2232                         .modulemode     = MODULEMODE_SWCTRL,
2233                 },
2234         },
2235         .slaves         = am33xx_tpcc_slaves,
2236         .slaves_cnt     = ARRAY_SIZE(am33xx_tpcc_slaves),
2237 };
2239 /* 'tptc' class */
2240 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
2241         .name           = "tptc",
2242 };
2244 /* tptc0 */
2245 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
2246         { .irq = AM33XX_IRQ_TPTC0 },
2247         { .irq = -1 }
2248 };
2250 static struct omap_hwmod am33xx_tptc0_hwmod = {
2251         .name           = "tptc0",
2252         .class          = &am33xx_tptc_hwmod_class,
2253         .mpu_irqs       = am33xx_tptc0_irqs,
2254         .main_clk       = "tptc0_ick",
2255         .clkdm_name     = "l3_clkdm",
2256         .prcm           = {
2257                 .omap4  = {
2258                         .clkctrl_offs   = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
2259                         .modulemode     = MODULEMODE_SWCTRL,
2260                 },
2261         },
2262 };
2264 /* tptc1 */
2265 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
2266         { .irq = AM33XX_IRQ_TPTC1 },
2267         { .irq = -1 }
2268 };
2270 static struct omap_hwmod am33xx_tptc1_hwmod = {
2271         .name           = "tptc1",
2272         .class          = &am33xx_tptc_hwmod_class,
2273         .mpu_irqs       = am33xx_tptc1_irqs,
2274         .main_clk       = "tptc1_ick",
2275         .clkdm_name     = "l3_clkdm",
2276         .prcm           = {
2277                 .omap4  = {
2278                         .clkctrl_offs   = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
2279                         .modulemode     = MODULEMODE_SWCTRL,
2280                 },
2281         },
2282 };
2284 /* tptc2 */
2285 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
2286         { .irq = AM33XX_IRQ_TPTC2 },
2287         { .irq = -1 }
2288 };
2290 static struct omap_hwmod am33xx_tptc2_hwmod = {
2291         .name           = "tptc2",
2292         .class          = &am33xx_tptc_hwmod_class,
2293         .mpu_irqs       = am33xx_tptc2_irqs,
2294         .main_clk       = "tptc2_ick",
2295         .clkdm_name     = "l3_clkdm",
2296         .prcm           = {
2297                 .omap4  = {
2298                         .clkctrl_offs   = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
2299                         .modulemode     = MODULEMODE_SWCTRL,
2300                 },
2301         },
2302 };
2304 /* 'uart' class */
2305 static struct omap_hwmod_class_sysconfig uart_sysc = {
2306         .rev_offs       = 0x50,
2307         .sysc_offs      = 0x54,
2308         .syss_offs      = 0x58,
2309         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
2310                         SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2311                         SYSC_HAS_AUTOIDLE),
2312         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2313         .sysc_fields    = &omap_hwmod_sysc_type1,
2314 };
2316 static struct omap_hwmod_class uart_class = {
2317         .name           = "uart",
2318         .sysc           = &uart_sysc,
2319 };
2321 /* uart1 */
2322 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
2323         { .name = "tx", .dma_req = 26, },
2324         { .name = "rx", .dma_req = 27, },
2325         { .dma_req = -1 }
2326 };
2328 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
2329         {
2330                 .pa_start       = AM33XX_UART1_BASE,
2331                 .pa_end         = AM33XX_UART1_BASE + SZ_8K - 1,
2332                 .flags          = ADDR_TYPE_RT
2333         },
2334         { }
2335 };
2337 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
2338         .master         = &am33xx_l4wkup_hwmod,
2339         .slave          = &am33xx_uart1_hwmod,
2340         .clk            = "uart1_ick",
2341         .addr           = am33xx_uart1_addr_space,
2342         .user           = OCP_USER_MPU,
2343 };
2345 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
2346         { .irq = AM33XX_IRQ_UART0 },
2347         { .irq = -1 }
2348 };
2350 static struct omap_hwmod_ocp_if *am33xx_uart1_slaves[] = {
2351         &am33xx_l4_wkup__uart1,
2352 };
2354 static struct omap_hwmod am33xx_uart1_hwmod = {
2355         .name           = "uart1",
2356         .class          = &uart_class,
2357         .mpu_irqs       = am33xx_uart1_irqs,
2358         .sdma_reqs      = uart1_edma_reqs,
2359         .main_clk       = "uart1_fck",
2360         .clkdm_name     = "l4_wkup_clkdm",
2361         .prcm           = {
2362                 .omap4  = {
2363                         .clkctrl_offs   = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
2364                         .modulemode     = MODULEMODE_SWCTRL,
2365                 },
2366         },
2367         .slaves         = am33xx_uart1_slaves,
2368         .slaves_cnt     = ARRAY_SIZE(am33xx_uart1_slaves),
2369 };
2371 /* uart2 */
2372 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
2373         {
2374                 .pa_start       = AM33XX_UART2_BASE,
2375                 .pa_end         = AM33XX_UART2_BASE + SZ_8K - 1,
2376                 .flags          = ADDR_TYPE_RT
2377         },
2378         { }
2379 };
2381 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
2382         .slave          = &am33xx_uart2_hwmod,
2383         .clk            = "uart2_ick",
2384         .addr           = am33xx_uart2_addr_space,
2385         .user           = OCP_USER_MPU,
2386 };
2388 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
2389         { .irq = AM33XX_IRQ_UART1 },
2390         { .irq = -1 }
2391 };
2393 static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = {
2394         &am33xx_l4_ls__uart2,
2395 };
2397 static struct omap_hwmod am33xx_uart2_hwmod = {
2398         .name           = "uart2",
2399         .class          = &uart_class,
2400         .mpu_irqs       = am33xx_uart2_irqs,
2401         .main_clk       = "uart2_fck",
2402         .clkdm_name     = "l4ls_clkdm",
2403         .sdma_reqs      = uart1_edma_reqs,
2404         .prcm           = {
2405                 .omap4  = {
2406                         .clkctrl_offs   = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
2407                         .modulemode     = MODULEMODE_SWCTRL,
2408                 },
2409         },
2410         .slaves         = am33xx_uart2_slaves,
2411         .slaves_cnt     = ARRAY_SIZE(am33xx_uart2_slaves),
2412 };
2414 /* uart3 */
2415 static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
2416         { .name = "tx", .dma_req = 30, },
2417         { .name = "rx", .dma_req = 31, },
2418         { .dma_req = -1 }
2419 };
2421 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
2422         {
2423                 .pa_start       = AM33XX_UART3_BASE,
2424                 .pa_end         = AM33XX_UART3_BASE + SZ_8K - 1,
2425                 .flags          = ADDR_TYPE_RT
2426         },
2427         { }
2428 };
2430 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
2431         .slave          = &am33xx_uart3_hwmod,
2432         .clk            = "uart3_ick",
2433         .addr           = am33xx_uart3_addr_space,
2434         .user           = OCP_USER_MPU,
2435 };
2437 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2438         { .irq = AM33XX_IRQ_UART2 },
2439         { .irq = -1 }
2440 };
2442 static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = {
2443         &am33xx_l4_ls__uart3,
2444 };
2446 static struct omap_hwmod am33xx_uart3_hwmod = {
2447         .name           = "uart3",
2448         .class          = &uart_class,
2449         .mpu_irqs       = am33xx_uart3_irqs,
2450         .main_clk       = "uart3_fck",
2451         .clkdm_name     = "l4ls_clkdm",
2452         .sdma_reqs      = uart3_edma_reqs,
2453         .prcm           = {
2454                 .omap4  = {
2455                         .clkctrl_offs   = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
2456                         .modulemode     = MODULEMODE_SWCTRL,
2457                 },
2458         },
2459         .slaves         = am33xx_uart3_slaves,
2460         .slaves_cnt     = ARRAY_SIZE(am33xx_uart3_slaves),
2461 };
2463 /* uart4 */
2464 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
2465         {
2466                 .pa_start       = AM33XX_UART4_BASE,
2467                 .pa_end         = AM33XX_UART4_BASE + SZ_8K - 1,
2468                 .flags          = ADDR_TYPE_RT
2469         },
2470         { }
2471 };
2473 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
2474         .slave          = &am33xx_uart4_hwmod,
2475         .clk            = "uart4_ick",
2476         .addr           = am33xx_uart4_addr_space,
2477         .user           = OCP_USER_MPU,
2478 };
2480 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2481         { .irq = AM33XX_IRQ_UART3 },
2482         { .irq = -1 }
2483 };
2485 static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = {
2486         &am33xx_l4_ls__uart4,
2487 };
2489 static struct omap_hwmod am33xx_uart4_hwmod = {
2490         .name           = "uart4",
2491         .class          = &uart_class,
2492         .mpu_irqs       = am33xx_uart4_irqs,
2493         .main_clk       = "uart4_fck",
2494         .clkdm_name     = "l4ls_clkdm",
2495         .sdma_reqs      = uart1_edma_reqs,
2496         .prcm           = {
2497                 .omap4  = {
2498                         .clkctrl_offs   = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
2499                         .modulemode     = MODULEMODE_SWCTRL,
2500                 },
2501         },
2502         .slaves         = am33xx_uart4_slaves,
2503         .slaves_cnt     = ARRAY_SIZE(am33xx_uart4_slaves),
2504 };
2506 /* uart5 */
2507 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
2508         {
2509                 .pa_start       = AM33XX_UART5_BASE,
2510                 .pa_end         = AM33XX_UART5_BASE + SZ_8K - 1,
2511                 .flags          = ADDR_TYPE_RT
2512         },
2513         { }
2514 };
2516 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
2517         .slave          = &am33xx_uart5_hwmod,
2518         .clk            = "uart5_ick",
2519         .addr           = am33xx_uart5_addr_space,
2520         .user           = OCP_USER_MPU,
2521 };
2523 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2524         { .irq = AM33XX_IRQ_UART4 },
2525         { .irq = -1 }
2526 };
2528 static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = {
2529         &am33xx_l4_ls__uart5,
2530 };
2532 static struct omap_hwmod am33xx_uart5_hwmod = {
2533         .name           = "uart5",
2534         .class          = &uart_class,
2535         .mpu_irqs       = am33xx_uart5_irqs,
2536         .main_clk       = "uart5_fck",
2537         .clkdm_name     = "l4ls_clkdm",
2538         .sdma_reqs      = uart1_edma_reqs,
2539         .prcm           = {
2540                 .omap4  = {
2541                         .clkctrl_offs   = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2542                         .modulemode     = MODULEMODE_SWCTRL,
2543                 },
2544         },
2545         .slaves         = am33xx_uart5_slaves,
2546         .slaves_cnt     = ARRAY_SIZE(am33xx_uart5_slaves),
2547 };
2549 /* uart6 */
2550 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
2551         {
2552                 .pa_start       = AM33XX_UART6_BASE,
2553                 .pa_end         = AM33XX_UART6_BASE + SZ_8K - 1,
2554                 .flags          = ADDR_TYPE_RT
2555         },
2556         { }
2557 };
2559 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
2560         .slave          = &am33xx_uart6_hwmod,
2561         .clk            = "uart6_ick",
2562         .addr           = am33xx_uart6_addr_space,
2563         .user           = OCP_USER_MPU,
2564 };
2566 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2567         { .irq = AM33XX_IRQ_UART5 },
2568         { .irq = -1 }
2569 };
2571 static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = {
2572         &am33xx_l4_ls__uart6,
2573 };
2575 static struct omap_hwmod am33xx_uart6_hwmod = {
2576         .name           = "uart6",
2577         .class          = &uart_class,
2578         .mpu_irqs       = am33xx_uart6_irqs,
2579         .main_clk       = "uart6_fck",
2580         .clkdm_name     = "l4ls_clkdm",
2581         .sdma_reqs      = uart1_edma_reqs,
2582         .prcm           = {
2583                 .omap4  = {
2584                         .clkctrl_offs   = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2585                         .modulemode     = MODULEMODE_SWCTRL,
2586                 },
2587         },
2588         .slaves         = am33xx_uart6_slaves,
2589         .slaves_cnt     = ARRAY_SIZE(am33xx_uart6_slaves),
2590 };
2592 /* 'wd_timer' class */
2593 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2594         .name           = "wd_timer",
2595 };
2597 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
2598         {
2599                 .pa_start       = AM33XX_WDT1_BASE,
2600                 .pa_end         = AM33XX_WDT1_BASE + SZ_4K - 1,
2601                 .flags          = ADDR_TYPE_RT
2602         },
2603         { }
2604 };
2606 /* l4_wkup -> wd_timer1 */
2607 static struct omap_hwmod_ocp_if am33xx_l4wkup__wd_timer1 = {
2608         .master         = &am33xx_l4wkup_hwmod,
2609         .slave          = &am33xx_wd_timer1_hwmod,
2610         .addr           = am33xx_wd_timer1_addrs,
2611         .user           = OCP_USER_MPU,
2612 };
2614 /* wd_timer1 slave ports */
2615 static struct omap_hwmod_ocp_if *am33xx_wd_timer1_slaves[] = {
2616         &am33xx_l4wkup__wd_timer1,
2617 };
2619 /* wd_timer1 */
2620 /*
2621  * TODO: device.c file uses hardcoded name for watchdog
2622          timer driver "wd_timer2, so we are also using
2623          same name as of now...
2624  */
2625 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2626         .name           = "wd_timer2",
2627         .class          = &am33xx_wd_timer_hwmod_class,
2628         .main_clk       = "wd_timer1_fck",
2629         .clkdm_name     = "l4_wkup_clkdm",
2630         .prcm           = {
2631                 .omap4  = {
2632                         .clkctrl_offs   = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2633                         .modulemode     = MODULEMODE_SWCTRL,
2634                 },
2635         },
2636         .slaves         = am33xx_wd_timer1_slaves,
2637         .slaves_cnt     = ARRAY_SIZE(am33xx_wd_timer1_slaves),
2638 };
2640 /* wdt0 */
2641 static struct omap_hwmod_irq_info am33xx_wdt0_irqs[] = {
2642         { .irq = AM33XX_IRQ_WDT0 },
2643         { .irq = -1 },
2644 };
2646 static struct omap_hwmod am33xx_wdt0_hwmod = {
2647         .name           = "wdt0",
2648         .class          = &am33xx_wd_timer_hwmod_class,
2649         .mpu_irqs       = am33xx_wdt0_irqs,
2650         .main_clk       = "wdt0_fck",
2651         .clkdm_name     = "l4_wkup_clkdm",
2652         .prcm           = {
2653                 .omap4  = {
2654                         .clkctrl_offs   = AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET,
2655                         .modulemode     = MODULEMODE_SWCTRL,
2656                 },
2657         },
2658 };
2660 /* 'wkup_m3' class */
2661 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
2662         .name           = "wkup_m3",
2663 };
2665 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
2666         { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
2667 };
2669 /* wkup_m3 */
2670 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
2671         .name           = "wkup_m3",
2672         .class          = &am33xx_wkup_m3_hwmod_class,
2673         .clkdm_name     = "l4_wkup_aon_clkdm",
2674         .main_clk       = "wkup_m3_fck",
2675         .rst_lines      = am33xx_wkup_m3_resets,
2676         .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
2677         .prcm           = {
2678                 .omap4  = {
2679                         .clkctrl_offs   = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
2680                         .rstctrl_offs   = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
2681                         .modulemode     = MODULEMODE_SWCTRL,
2682                 },
2683         },
2684         .flags          = HWMOD_INIT_NO_RESET,  /* Keep hardreset asserted */
2685 };
2687 /* L3 SLOW -> USBSS interface */
2688 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
2689         {
2690                 .name           = "usbss",
2691                 .pa_start       = AM33XX_USBSS_BASE,
2692                 .pa_end         = AM33XX_USBSS_BASE + SZ_4K - 1,
2693                 .flags          = ADDR_TYPE_RT
2694         },
2695         {
2696                 .name           = "musb0",
2697                 .pa_start       = AM33XX_USB0_BASE,
2698                 .pa_end         = AM33XX_USB0_BASE + SZ_2K - 1,
2699                 .flags          = ADDR_TYPE_RT
2700         },
2701         {
2702                 .name           = "musb1",
2703                 .pa_start       = AM33XX_USB1_BASE,
2704                 .pa_end         = AM33XX_USB1_BASE + SZ_2K - 1,
2705                 .flags          = ADDR_TYPE_RT
2706         },
2707         { }
2708 };
2710 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2711         .rev_offs       = 0x0,
2712         .sysc_offs      = 0x10,
2713         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2714         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2715         .sysc_fields    = &omap_hwmod_sysc_type1,
2716 };
2718 static struct omap_hwmod_class am33xx_usbotg_class = {
2719         .name           = "usbotg",
2720         .sysc           = &am33xx_usbhsotg_sysc,
2721 };
2723 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2724         { .name = "usbss-irq", .irq = AM33XX_IRQ_USBSS, },
2725         { .name = "musb0-irq", .irq = AM33XX_IRQ_USB0, },
2726         { .name = "musb1-irq", .irq = AM33XX_IRQ_USB1, },
2727         { .irq = -1, },
2728 };
2730 static struct omap_hwmod_ocp_if am33xx_l3_slow__usbss = {
2731         .master         = &am33xx_l3slow_hwmod,
2732         .slave          = &am33xx_usbss_hwmod,
2733         .addr           = am33xx_usbss_addr_space,
2734         .user           = OCP_USER_MPU,
2735         .flags          = OCPIF_SWSUP_IDLE,
2736 };
2738 static struct omap_hwmod_ocp_if *am33xx_usbss_slaves[] = {
2739         &am33xx_l3_slow__usbss,
2740 };
2742 static struct omap_hwmod_opt_clk usbss_opt_clks[] = {
2743         { .role = "clkdcoldo", .clk = "usbotg_fck" },
2744 };
2746 static struct omap_hwmod am33xx_usbss_hwmod = {
2747         .name           = "usb_otg_hs",
2748         .mpu_irqs       = am33xx_usbss_mpu_irqs,
2749         .main_clk       = "usbotg_ick",
2750         .clkdm_name     = "l4ls_clkdm",
2751         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2752         .prcm           = {
2753                 .omap4  = {
2754                         .clkctrl_offs   = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2755                         .modulemode     = MODULEMODE_SWCTRL,
2756                 },
2757         },
2758         .opt_clks       = usbss_opt_clks,
2759         .opt_clks_cnt   = ARRAY_SIZE(usbss_opt_clks),
2760         .slaves         = am33xx_usbss_slaves,
2761         .slaves_cnt     = ARRAY_SIZE(am33xx_usbss_slaves),
2762         .class          = &am33xx_usbotg_class,
2763 };
2765 static __initdata struct omap_hwmod *am33xx_hwmods[] = {
2766         /* l3 class */
2767         &am33xx_l3_instr_hwmod,
2768         &am33xx_l3_main_hwmod,
2769         /* l3s class */
2770         &am33xx_l3slow_hwmod,
2771         /* l4hs class */
2772         &am33xx_l4_hs_hwmod,
2773         /* l4fw class */
2774         &am33xx_l4fw_hwmod,
2775         /* l4ls class */
2776         &am33xx_l4ls_hwmod,
2777         /* l4per class */
2778         &am33xx_l4per_hwmod,
2779         /* l4wkup class */
2780         &am33xx_l4wkup_hwmod,
2782         /* clkdiv32k class */
2783         &am33xx_clkdiv32k_hwmod,
2784         /* mpu class */
2785         &am33xx_mpu_hwmod,
2786         /* adc_tsc class */
2787         &am33xx_adc_tsc_hwmod,
2788         /* aes class */
2789         &am33xx_aes0_hwmod,
2790         /* cefuse class */
2791         &am33xx_cefuse_hwmod,
2792         /* control class */
2793         &am33xx_control_hwmod,
2794         /* dcan class */
2795         &am33xx_dcan0_hwmod,
2796         &am33xx_dcan1_hwmod,
2797         /* debugss class */
2798         &am33xx_debugss_hwmod,
2799         /* elm class */
2800         &am33xx_elm_hwmod,
2801         /* emif_fw class */
2802         &am33xx_emif_fw_hwmod,
2803         /* epwmss class */
2804         &am33xx_epwmss0_hwmod,
2805         &am33xx_epwmss1_hwmod,
2806         &am33xx_epwmss2_hwmod,
2807         /* gpio class */
2808         &am33xx_gpio0_hwmod,
2809         &am33xx_gpio1_hwmod,
2810         &am33xx_gpio2_hwmod,
2811         &am33xx_gpio3_hwmod,
2812         /* gpmc class */
2813         &am33xx_gpmc_hwmod,
2814         /* i2c class */
2815         &am33xx_i2c1_hwmod,
2816         &am33xx_i2c2_hwmod,
2817         /* icss class */
2818         &am33xx_icss_hwmod,
2819         /* ieee5000 class */
2820         &am33xx_ieee5000_hwmod,
2821         /* mailbox class */
2822         &am33xx_mailbox_hwmod,
2823         /* mcasp class */
2824         &am33xx_mcasp0_hwmod,
2825         &am33xx_mcasp1_hwmod,
2826         /* mmc class */
2827         &am33xx_mmc0_hwmod,
2828         &am33xx_mmc1_hwmod,
2829         &am33xx_mmc2_hwmod,
2830         /* ocmcram class */
2831         &am33xx_ocmcram_hwmod,
2832         /* ocpwp class */
2833         &am33xx_ocpwp_hwmod,
2834         /* sha0 class */
2835         &am33xx_sha0_hwmod,
2836         /* smartreflex class */
2837         &am33xx_smartreflex0_hwmod,
2838         &am33xx_smartreflex1_hwmod,
2839         /* spi class */
2840         &am33xx_spi0_hwmod,
2841         &am33xx_spi1_hwmod,
2842         /* spinlock class */
2843         &am33xx_spinlock_hwmod,
2844         /* uart class */
2845         &am33xx_uart1_hwmod,
2846         &am33xx_uart2_hwmod,
2847         &am33xx_uart3_hwmod,
2848         &am33xx_uart4_hwmod,
2849         &am33xx_uart5_hwmod,
2850         &am33xx_uart6_hwmod,
2851         /* timer class */
2852         &am33xx_timer0_hwmod,
2853         &am33xx_timer1_hwmod,
2854         &am33xx_timer2_hwmod,
2855         &am33xx_timer3_hwmod,
2856         &am33xx_timer4_hwmod,
2857         &am33xx_timer5_hwmod,
2858         &am33xx_timer6_hwmod,
2859         &am33xx_timer7_hwmod,
2860         /* wkup_m3 class */
2861         &am33xx_wkup_m3_hwmod,
2862         /* wd_timer class */
2863         &am33xx_wd_timer1_hwmod,
2864         /* usbss hwmod */
2865         &am33xx_usbss_hwmod,
2866         /* cpgmac0 class */
2867         &am33xx_cpgmac0_hwmod,
2868         &am33xx_wdt0_hwmod, /* Secure WDT */
2869         /* tptc class */
2870         &am33xx_tptc0_hwmod,
2871         &am33xx_tptc1_hwmod,
2872         &am33xx_tptc2_hwmod,
2873         /* tpcc class */
2874         &am33xx_tpcc_hwmod,
2875         /* LCDC class */
2876         &am33xx_lcdc_hwmod,
2877         /* rtc */
2878         &am33xx_rtc_hwmod,
2879         NULL,
2880 };
2882 int __init am33xx_hwmod_init(void)
2884         return omap_hwmod_register(am33xx_hwmods);