1 /*
2 * Hardware modules present on the AM33XX chips
3 *
4 * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
17 #include <linux/io.h>
19 #include <plat/omap_hwmod.h>
20 #include <plat/cpu.h>
21 #include <plat/gpio.h>
22 #include <plat/dma.h>
23 #include <plat/mmc.h>
24 #include <plat/mcspi.h>
26 #include "omap_hwmod_common_data.h"
27 #include "control.h"
28 #include "cm33xx.h"
29 #include "prm33xx.h"
31 /* Backward references (IPs with Bus Master capability) */
32 static struct omap_hwmod am33xx_mpu_hwmod;
33 static struct omap_hwmod am33xx_l3slow_hwmod;
34 static struct omap_hwmod am33xx_l4wkup_hwmod;
35 static struct omap_hwmod am33xx_l4per_hwmod;
36 static struct omap_hwmod am33xx_uart1_hwmod;
37 static struct omap_hwmod am33xx_uart2_hwmod;
38 static struct omap_hwmod am33xx_uart3_hwmod;
39 static struct omap_hwmod am33xx_uart4_hwmod;
40 static struct omap_hwmod am33xx_uart5_hwmod;
41 static struct omap_hwmod am33xx_uart6_hwmod;
42 static struct omap_hwmod am33xx_timer0_hwmod;
43 static struct omap_hwmod am33xx_timer1_hwmod;
44 static struct omap_hwmod am33xx_timer2_hwmod;
45 static struct omap_hwmod am33xx_timer3_hwmod;
46 static struct omap_hwmod am33xx_timer4_hwmod;
47 static struct omap_hwmod am33xx_timer5_hwmod;
48 static struct omap_hwmod am33xx_timer6_hwmod;
49 static struct omap_hwmod am33xx_timer7_hwmod;
50 static struct omap_hwmod am33xx_wd_timer1_hwmod;
51 static struct omap_hwmod am33xx_cpgmac0_hwmod;
52 static struct omap_hwmod am33xx_icss_hwmod;
53 static struct omap_hwmod am33xx_ieee5000_hwmod;
54 static struct omap_hwmod am33xx_tptc0_hwmod;
55 static struct omap_hwmod am33xx_tptc1_hwmod;
56 static struct omap_hwmod am33xx_tptc2_hwmod;
57 static struct omap_hwmod am33xx_gpio0_hwmod;
58 static struct omap_hwmod am33xx_gpio1_hwmod;
59 static struct omap_hwmod am33xx_gpio2_hwmod;
60 static struct omap_hwmod am33xx_gpio3_hwmod;
61 static struct omap_hwmod am33xx_i2c1_hwmod;
62 static struct omap_hwmod am33xx_i2c2_hwmod;
63 static struct omap_hwmod am33xx_usbss_hwmod;
64 static struct omap_hwmod am33xx_mmc0_hwmod;
65 static struct omap_hwmod am33xx_mmc1_hwmod;
66 static struct omap_hwmod am33xx_mmc2_hwmod;
67 static struct omap_hwmod am33xx_spi0_hwmod;
68 static struct omap_hwmod am33xx_spi1_hwmod;
69 static struct omap_hwmod am33xx_elm_hwmod;
71 /*
72 * Interconnects hwmod structures
73 * hwmods that compose the global AM33XX OCP interconnect
74 */
76 /* MPU -> L3_SLOW Peripheral interface */
77 static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = {
78 .master = &am33xx_mpu_hwmod,
79 .slave = &am33xx_l3slow_hwmod,
80 .user = OCP_USER_MPU,
81 };
83 /* L3 SLOW -> L4_PER Peripheral interface */
84 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = {
85 .master = &am33xx_l3slow_hwmod,
86 .slave = &am33xx_l4per_hwmod,
87 .user = OCP_USER_MPU,
88 };
90 /* L3 SLOW -> L4_WKUP Peripheral interface */
91 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = {
92 .master = &am33xx_l3slow_hwmod,
93 .slave = &am33xx_l4wkup_hwmod,
94 .user = OCP_USER_MPU,
95 };
97 /* Master interfaces on the L4_WKUP interconnect */
98 static struct omap_hwmod_ocp_if *am33xx_l3_slow_masters[] = {
99 &am33xx_l3_slow__l4_per,
100 &am33xx_l3_slow__l4_wkup,
101 };
103 /* Slave interfaces on the L3_SLOW interconnect */
104 static struct omap_hwmod_ocp_if *am33xx_l3_slow_slaves[] = {
105 &am33xx_mpu__l3_slow,
106 };
108 static struct omap_hwmod am33xx_l3slow_hwmod = {
109 .name = "l3_slow",
110 .class = &l3_hwmod_class,
111 .clkdm_name = "l3s_clkdm",
112 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
113 .masters = am33xx_l3_slow_masters,
114 .masters_cnt = ARRAY_SIZE(am33xx_l3_slow_masters),
115 .slaves = am33xx_l3_slow_slaves,
116 .slaves_cnt = ARRAY_SIZE(am33xx_l3_slow_slaves),
117 };
119 /* L4 PER -> GPIO2 */
120 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
121 {
122 .pa_start = AM33XX_GPIO1_BASE,
123 .pa_end = AM33XX_GPIO1_BASE + SZ_4K - 1,
124 .flags = ADDR_TYPE_RT
125 },
126 { }
127 };
129 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
130 .master = &am33xx_l4per_hwmod,
131 .slave = &am33xx_gpio1_hwmod,
132 .clk = "l4ls_fck",
133 .addr = am33xx_gpio1_addrs,
134 .user = OCP_USER_MPU | OCP_USER_SDMA,
135 };
137 /* L4 PER -> GPIO3 */
138 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
139 {
140 .pa_start = AM33XX_GPIO2_BASE,
141 .pa_end = AM33XX_GPIO2_BASE + SZ_4K - 1,
142 .flags = ADDR_TYPE_RT
143 },
144 { }
145 };
147 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
148 .master = &am33xx_l4per_hwmod,
149 .slave = &am33xx_gpio2_hwmod,
150 .clk = "l4ls_fck",
151 .addr = am33xx_gpio2_addrs,
152 .user = OCP_USER_MPU | OCP_USER_SDMA,
153 };
155 /* L4 PER -> GPIO4 */
156 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
157 {
158 .pa_start = AM33XX_GPIO3_BASE,
159 .pa_end = AM33XX_GPIO3_BASE + SZ_4K - 1,
160 .flags = ADDR_TYPE_RT
161 },
162 { }
163 };
165 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
166 .master = &am33xx_l4per_hwmod,
167 .slave = &am33xx_gpio3_hwmod,
168 .clk = "l4ls_fck",
169 .addr = am33xx_gpio3_addrs,
170 .user = OCP_USER_MPU | OCP_USER_SDMA,
171 };
173 /* Master interfaces on the L4_PER interconnect */
174 static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = {
175 &am33xx_l4_per__gpio1,
176 &am33xx_l4_per__gpio2,
177 &am33xx_l4_per__gpio3,
178 };
179 /* Slave interfaces on the L4_PER interconnect */
180 static struct omap_hwmod_ocp_if *am33xx_l4_per_slaves[] = {
181 &am33xx_l3_slow__l4_per,
182 };
184 static struct omap_hwmod am33xx_l4per_hwmod = {
185 .name = "l4_per",
186 .class = &l4_hwmod_class,
187 .clkdm_name = "l4ls_clkdm",
188 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
189 .masters = am33xx_l4_per_masters,
190 .masters_cnt = ARRAY_SIZE(am33xx_l4_per_masters),
191 .slaves = am33xx_l4_per_slaves,
192 .slaves_cnt = ARRAY_SIZE(am33xx_l4_per_slaves),
193 };
195 /* L4 WKUP -> I2C1 */
196 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
197 {
198 .pa_start = AM33XX_I2C0_BASE,
199 .pa_end = AM33XX_I2C0_BASE + SZ_4K - 1,
200 .flags = ADDR_TYPE_RT
201 },
202 { }
203 };
205 static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = {
206 .master = &am33xx_l4wkup_hwmod,
207 .slave = &am33xx_i2c1_hwmod,
208 .addr = am33xx_i2c1_addr_space,
209 .user = OCP_USER_MPU,
210 };
212 /* L4 WKUP -> GPIO1 */
213 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
214 {
215 .pa_start = AM33XX_GPIO0_BASE,
216 .pa_end = AM33XX_GPIO0_BASE + SZ_4K - 1,
217 .flags = ADDR_TYPE_RT
218 },
219 { }
220 };
222 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
223 .master = &am33xx_l4wkup_hwmod,
224 .slave = &am33xx_gpio0_hwmod,
225 .clk = "l4ls_fck",
226 .addr = am33xx_gpio0_addrs,
227 .user = OCP_USER_MPU | OCP_USER_SDMA,
228 };
230 /* Master interfaces on the L4_WKUP interconnect */
231 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = {
232 &am33xx_l4_wkup__gpio0,
233 };
234 /* Slave interfaces on the L4_WKUP interconnect */
235 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_slaves[] = {
236 &am33xx_l3_slow__l4_wkup,
237 };
239 static struct omap_hwmod am33xx_l4wkup_hwmod = {
240 .name = "l4_wkup",
241 .class = &l4_hwmod_class,
242 .clkdm_name = "l4_wkup_clkdm",
243 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
244 .masters = am33xx_l4_wkup_masters,
245 .masters_cnt = ARRAY_SIZE(am33xx_l4_wkup_masters),
246 .slaves = am33xx_l4_wkup_slaves,
247 .slaves_cnt = ARRAY_SIZE(am33xx_l4_wkup_slaves),
248 };
250 /* 'adc_tsc' class */
251 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
252 .name = "adc_tsc",
253 };
255 /* adc_tsc */
256 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
257 { .irq = AM33XX_IRQ_TSC },
258 { .irq = -1 }
259 };
261 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
262 .name = "adc_tsc",
263 .class = &am33xx_adc_tsc_hwmod_class,
264 .mpu_irqs = am33xx_adc_tsc_irqs,
265 .main_clk = "adc_tsc_fck",
266 .clkdm_name = "l4_wkup_clkdm",
267 .prcm = {
268 .omap4 = {
269 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
270 .modulemode = MODULEMODE_SWCTRL,
271 },
272 },
273 };
275 /* 'aes' class */
276 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
277 .name = "aes",
278 };
280 /* aes0 */
281 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
282 { .irq = AM33XX_IRQ_AESEIP36t0_S },
283 { .irq = -1 }
284 };
286 static struct omap_hwmod am33xx_aes0_hwmod = {
287 .name = "aes0",
288 .class = &am33xx_aes_hwmod_class,
289 .mpu_irqs = am33xx_aes0_irqs,
290 .main_clk = "aes0_fck",
291 .clkdm_name = "l3_clkdm",
292 .prcm = {
293 .omap4 = {
294 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
295 .modulemode = MODULEMODE_SWCTRL,
296 },
297 },
298 };
300 /* 'cefuse' class */
301 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
302 .name = "cefuse",
303 };
305 /* cefuse */
306 static struct omap_hwmod am33xx_cefuse_hwmod = {
307 .name = "cefuse",
308 .class = &am33xx_cefuse_hwmod_class,
309 .main_clk = "cefuse_fck",
310 .clkdm_name = "l4_cefuse_clkdm",
311 .prcm = {
312 .omap4 = {
313 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
314 .modulemode = MODULEMODE_SWCTRL,
315 },
316 },
317 };
319 /* 'clkdiv32k' class */
320 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
321 .name = "clkdiv32k",
322 };
324 /* clkdiv32k */
325 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
326 .name = "clkdiv32k",
327 .class = &am33xx_clkdiv32k_hwmod_class,
328 .main_clk = "clkdiv32k_fck",
329 .clkdm_name = "clk_24mhz_clkdm",
330 .prcm = {
331 .omap4 = {
332 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
333 .modulemode = MODULEMODE_SWCTRL,
334 },
335 },
336 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
337 };
339 /* 'control' class */
340 static struct omap_hwmod_class am33xx_control_hwmod_class = {
341 .name = "control",
342 };
344 /* control */
345 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
346 { .irq = AM33XX_IRQ_CONTROL_PLATFORM },
347 { .irq = -1 }
348 };
350 static struct omap_hwmod am33xx_control_hwmod = {
351 .name = "control",
352 .class = &am33xx_control_hwmod_class,
353 .mpu_irqs = am33xx_control_irqs,
354 .main_clk = "control_fck",
355 .clkdm_name = "l4_wkup_clkdm",
356 .prcm = {
357 .omap4 = {
358 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
359 .modulemode = MODULEMODE_SWCTRL,
360 },
361 },
362 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
363 };
365 /* 'cpgmac0' class */
366 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
367 .name = "cpgmac0",
368 };
370 /* cpgmac0 */
371 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
372 .name = "cpgmac0",
373 .class = &am33xx_cpgmac0_hwmod_class,
374 .main_clk = "cpgmac0_fck",
375 .clkdm_name = "cpsw_125mhz_clkdm",
376 .prcm = {
377 .omap4 = {
378 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
379 .modulemode = MODULEMODE_SWCTRL,
380 },
381 },
382 };
384 /* 'dcan' class */
385 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
386 .name = "dcan",
387 };
389 /* dcan0 */
390 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
391 { .irq = AM33XX_IRQ_DCAN0_0 },
392 { .irq = -1 }
393 };
395 static struct omap_hwmod am33xx_dcan0_hwmod = {
396 .name = "dcan0",
397 .class = &am33xx_dcan_hwmod_class,
398 .mpu_irqs = am33xx_dcan0_irqs,
399 .main_clk = "dcan0_fck",
400 .clkdm_name = "l4ls_clkdm",
401 .prcm = {
402 .omap4 = {
403 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
404 .modulemode = MODULEMODE_SWCTRL,
405 },
406 },
407 };
409 /* dcan1 */
410 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
411 { .irq = AM33XX_IRQ_DCAN1_0 },
412 { .irq = -1 }
413 };
414 static struct omap_hwmod am33xx_dcan1_hwmod = {
415 .name = "dcan1",
416 .class = &am33xx_dcan_hwmod_class,
417 .mpu_irqs = am33xx_dcan1_irqs,
418 .main_clk = "dcan1_fck",
419 .clkdm_name = "l4ls_clkdm",
420 .prcm = {
421 .omap4 = {
422 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
423 .modulemode = MODULEMODE_SWCTRL,
424 },
425 },
426 };
428 /* 'debugss' class */
429 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
430 .name = "debugss",
431 };
433 /* debugss */
434 static struct omap_hwmod am33xx_debugss_hwmod = {
435 .name = "debugss",
436 .class = &am33xx_debugss_hwmod_class,
437 .main_clk = "debugss_fck",
438 .clkdm_name = "l3_aon_clkdm",
439 .prcm = {
440 .omap4 = {
441 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
442 .modulemode = MODULEMODE_SWCTRL,
443 },
444 },
445 #ifdef CONFIG_DEBUG_JTAG_ENABLE
446 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
447 #endif
448 };
450 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
451 .rev_offs = 0x0000,
452 .sysc_offs = 0x0010,
453 .syss_offs = 0x0014,
454 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
455 SYSC_HAS_SOFTRESET |
456 SYSS_HAS_RESET_STATUS),
457 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
458 .sysc_fields = &omap_hwmod_sysc_type1,
459 };
460 /* 'elm' class */
461 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
462 .name = "elm",
463 .sysc = &am33xx_elm_sysc,
464 };
466 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
467 { .irq = AM33XX_IRQ_ELM },
468 { .irq = -1 }
469 };
471 struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
472 {
473 .pa_start = AM33XX_ELM_BASE,
474 .pa_end = AM33XX_ELM_BASE + SZ_8K - 1,
475 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
476 },
477 { }
478 };
480 struct omap_hwmod_ocp_if am33xx_l4_core__elm = {
481 .master = &am33xx_l4per_hwmod,
482 .slave = &am33xx_elm_hwmod,
483 .addr = am33xx_elm_addr_space,
484 .user = OCP_USER_MPU,
485 };
487 static struct omap_hwmod_ocp_if *am33xx_elm_slaves[] = {
488 &am33xx_l4_core__elm,
489 };
491 /* elm */
492 static struct omap_hwmod am33xx_elm_hwmod = {
493 .name = "elm",
494 .class = &am33xx_elm_hwmod_class,
495 .mpu_irqs = am33xx_elm_irqs,
496 .main_clk = "elm_fck",
497 .clkdm_name = "l4ls_clkdm",
498 .slaves = am33xx_elm_slaves,
499 .slaves_cnt = ARRAY_SIZE(am33xx_elm_slaves),
500 .prcm = {
501 .omap4 = {
502 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
503 .modulemode = MODULEMODE_SWCTRL,
504 },
505 },
506 };
508 /* 'emif_fw' class */
509 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
510 .name = "emif_fw",
511 };
513 /* emif_fw */
514 static struct omap_hwmod am33xx_emif_fw_hwmod = {
515 .name = "emif_fw",
516 .class = &am33xx_emif_fw_hwmod_class,
517 .main_clk = "emif_fw_fck",
518 .clkdm_name = "l4fw_clkdm",
519 .prcm = {
520 .omap4 = {
521 .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
522 .modulemode = MODULEMODE_SWCTRL,
523 },
524 },
525 .flags = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
526 };
528 /* 'epwmss' class */
529 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
530 .name = "epwmss",
531 };
533 /* epwmss0 */
534 static struct omap_hwmod am33xx_epwmss0_hwmod = {
535 .name = "epwmss0",
536 .class = &am33xx_epwmss_hwmod_class,
537 .main_clk = "epwmss0_fck",
538 .clkdm_name = "l4ls_clkdm",
539 .prcm = {
540 .omap4 = {
541 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
542 .modulemode = MODULEMODE_SWCTRL,
543 },
544 },
545 };
547 /* epwmss1 */
548 static struct omap_hwmod am33xx_epwmss1_hwmod = {
549 .name = "epwmss1",
550 .class = &am33xx_epwmss_hwmod_class,
551 .main_clk = "epwmss1_fck",
552 .clkdm_name = "l4ls_clkdm",
553 .prcm = {
554 .omap4 = {
555 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
556 .modulemode = MODULEMODE_SWCTRL,
557 },
558 },
559 };
561 /* epwmss2 */
562 static struct omap_hwmod am33xx_epwmss2_hwmod = {
563 .name = "epwmss2",
564 .class = &am33xx_epwmss_hwmod_class,
565 .main_clk = "epwmss2_fck",
566 .clkdm_name = "l4ls_clkdm",
567 .prcm = {
568 .omap4 = {
569 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
570 .modulemode = MODULEMODE_SWCTRL,
571 },
572 },
573 };
575 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
576 .rev_offs = 0x0000,
577 .sysc_offs = 0x0010,
578 .syss_offs = 0x0114,
579 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
580 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
581 SYSS_HAS_RESET_STATUS),
582 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
583 SIDLE_SMART_WKUP),
584 .sysc_fields = &omap_hwmod_sysc_type1,
585 };
587 /* 'gpio' class */
588 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
589 .name = "gpio",
590 .sysc = &am33xx_gpio_sysc,
591 .rev = 2,
592 };
594 /* gpio dev_attr */
595 static struct omap_gpio_dev_attr gpio_dev_attr = {
596 .bank_width = 32,
597 .dbck_flag = true,
598 };
600 /* gpio0 */
601 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
602 { .irq = AM33XX_IRQ_GPIO0_1 },
603 { .irq = -1 }
604 };
606 /* gpio0 slave ports */
607 static struct omap_hwmod_ocp_if *am33xx_gpio0_slaves[] = {
608 &am33xx_l4_wkup__gpio0,
609 };
611 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
612 { .role = "dbclk", .clk = "gpio0_dbclk" },
613 };
615 /* gpio0 */
616 static struct omap_hwmod am33xx_gpio0_hwmod = {
617 .name = "gpio1",
618 .class = &am33xx_gpio_hwmod_class,
619 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
620 .mpu_irqs = am33xx_gpio0_irqs,
621 .main_clk = "gpio0_fck",
622 .clkdm_name = "l4_wkup_clkdm",
623 .prcm = {
624 .omap4 = {
625 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
626 .modulemode = MODULEMODE_SWCTRL,
627 },
628 },
629 .opt_clks = gpio0_opt_clks,
630 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
631 .dev_attr = &gpio_dev_attr,
632 .slaves = am33xx_gpio0_slaves,
633 .slaves_cnt = ARRAY_SIZE(am33xx_gpio0_slaves),
634 };
636 /* gpio1 */
637 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
638 { .irq = AM33XX_IRQ_GPIO1_1 },
639 { .irq = -1 }
640 };
642 /* gpio1 slave ports */
643 static struct omap_hwmod_ocp_if *am33xx_gpio1_slaves[] = {
644 &am33xx_l4_per__gpio1,
645 };
647 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
648 { .role = "dbclk", .clk = "gpio1_dbclk" },
649 };
651 static struct omap_hwmod am33xx_gpio1_hwmod = {
652 .name = "gpio2",
653 .class = &am33xx_gpio_hwmod_class,
654 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
655 .mpu_irqs = am33xx_gpio1_irqs,
656 .main_clk = "gpio1_fck",
657 .clkdm_name = "l4ls_clkdm",
658 .prcm = {
659 .omap4 = {
660 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
661 .modulemode = MODULEMODE_SWCTRL,
662 },
663 },
664 .opt_clks = gpio1_opt_clks,
665 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
666 .dev_attr = &gpio_dev_attr,
667 .slaves = am33xx_gpio1_slaves,
668 .slaves_cnt = ARRAY_SIZE(am33xx_gpio1_slaves),
669 };
671 /* gpio2 */
672 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
673 { .irq = AM33XX_IRQ_GPIO2_1 },
674 { .irq = -1 }
675 };
677 /* gpio2 slave ports */
678 static struct omap_hwmod_ocp_if *am33xx_gpio2_slaves[] = {
679 &am33xx_l4_per__gpio2,
680 };
682 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
683 { .role = "dbclk", .clk = "gpio2_dbclk" },
684 };
686 /* gpio2 */
687 static struct omap_hwmod am33xx_gpio2_hwmod = {
688 .name = "gpio3",
689 .class = &am33xx_gpio_hwmod_class,
690 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
691 .mpu_irqs = am33xx_gpio2_irqs,
692 .main_clk = "gpio2_fck",
693 .clkdm_name = "l4ls_clkdm",
694 .prcm = {
695 .omap4 = {
696 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
697 .modulemode = MODULEMODE_SWCTRL,
698 },
699 },
700 .opt_clks = gpio2_opt_clks,
701 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
702 .dev_attr = &gpio_dev_attr,
703 .slaves = am33xx_gpio2_slaves,
704 .slaves_cnt = ARRAY_SIZE(am33xx_gpio2_slaves),
705 };
707 /* gpio3 */
708 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
709 { .irq = AM33XX_IRQ_GPIO3_1 },
710 { .irq = -1 }
711 };
713 /* gpio3 slave ports */
714 static struct omap_hwmod_ocp_if *am33xx_gpio3_slaves[] = {
715 &am33xx_l4_per__gpio3,
716 };
718 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
719 { .role = "dbclk", .clk = "gpio3_dbclk" },
720 };
722 /* gpio3 */
723 static struct omap_hwmod am33xx_gpio3_hwmod = {
724 .name = "gpio4",
725 .class = &am33xx_gpio_hwmod_class,
726 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
727 .mpu_irqs = am33xx_gpio3_irqs,
728 .main_clk = "gpio3_fck",
729 .clkdm_name = "l4ls_clkdm",
730 .prcm = {
731 .omap4 = {
732 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
733 .modulemode = MODULEMODE_SWCTRL,
734 },
735 },
736 .opt_clks = gpio3_opt_clks,
737 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
738 .dev_attr = &gpio_dev_attr,
739 .slaves = am33xx_gpio3_slaves,
740 .slaves_cnt = ARRAY_SIZE(am33xx_gpio3_slaves),
741 };
743 /* 'gpmc' class */
745 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
746 .name = "gpmc",
747 };
749 /* gpmc */
750 static struct omap_hwmod am33xx_gpmc_hwmod = {
751 .name = "gpmc",
752 .class = &am33xx_gpmc_hwmod_class,
753 .main_clk = "gpmc_fck",
754 .clkdm_name = "l3s_clkdm",
755 .prcm = {
756 .omap4 = {
757 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
758 .modulemode = MODULEMODE_SWCTRL,
759 },
760 },
761 };
763 /* 'i2c' class */
765 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
766 .sysc_offs = 0x0010,
767 .syss_offs = 0x0090,
768 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
769 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
770 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
771 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
772 SIDLE_SMART_WKUP),
773 .sysc_fields = &omap_hwmod_sysc_type1,
774 };
776 static struct omap_i2c_dev_attr i2c_dev_attr = {
777 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
778 };
780 static struct omap_hwmod_class i2c_class = {
781 .name = "i2c",
782 .sysc = &am33xx_i2c_sysc,
783 .rev = OMAP_I2C_IP_VERSION_2,
784 .reset = &omap_i2c_reset,
785 };
787 /* I2C1 */
788 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
789 { .irq = AM33XX_IRQ_MSHSI2COCP0 },
790 { .irq = -1 }
791 };
793 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
794 { .name = "tx", .dma_req = 0, },
795 { .name = "rx", .dma_req = 0, },
796 { .dma_req = -1 }
797 };
799 static struct omap_hwmod_ocp_if *am33xx_i2c1_slaves[] = {
800 &am33xx_l4_wkup_i2c1,
801 };
803 static struct omap_hwmod am33xx_i2c1_hwmod = {
804 .name = "i2c1",
805 .mpu_irqs = i2c1_mpu_irqs,
806 .sdma_reqs = i2c1_edma_reqs,
807 .main_clk = "i2c1_fck",
808 .clkdm_name = "l4_wkup_clkdm",
809 .prcm = {
810 .omap4 = {
811 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
812 .modulemode = MODULEMODE_SWCTRL,
813 },
814 },
815 .flags = HWMOD_16BIT_REG,
816 .dev_attr = &i2c_dev_attr,
817 .slaves = am33xx_i2c1_slaves,
818 .slaves_cnt = ARRAY_SIZE(am33xx_i2c1_slaves),
819 .class = &i2c_class,
820 };
822 /* i2c2 */
823 /* l4 per -> i2c2 */
824 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
825 {
826 .pa_start = AM33XX_I2C1_BASE,
827 .pa_end = AM33XX_I2C1_BASE + SZ_4K - 1,
828 .flags = ADDR_TYPE_RT
829 },
830 { }
831 };
833 static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = {
834 .master = &am33xx_l4per_hwmod,
835 .slave = &am33xx_i2c2_hwmod,
836 .addr = am33xx_i2c2_addr_space,
837 .user = OCP_USER_MPU,
838 };
840 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
841 { .irq = AM33XX_IRQ_MSHSI2COCP1 },
842 { .irq = -1 }
843 };
845 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
846 { .name = "tx", .dma_req = 0, },
847 { .name = "rx", .dma_req = 0, },
848 { .dma_req = -1 }
849 };
851 static struct omap_hwmod_ocp_if *am33xx_i2c2_slaves[] = {
852 &am335_l4_per_i2c2,
853 };
855 static struct omap_hwmod am33xx_i2c2_hwmod = {
856 .name = "i2c2",
857 .mpu_irqs = i2c2_mpu_irqs,
858 .sdma_reqs = i2c2_edma_reqs,
859 .main_clk = "i2c2_fck",
860 .clkdm_name = "l4ls_clkdm",
861 .prcm = {
862 .omap4 = {
863 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
864 .modulemode = MODULEMODE_SWCTRL,
865 },
866 },
867 .flags = HWMOD_16BIT_REG,
868 .dev_attr = &i2c_dev_attr,
869 .slaves = am33xx_i2c2_slaves,
870 .slaves_cnt = ARRAY_SIZE(am33xx_i2c2_slaves),
871 .class = &i2c_class,
872 };
874 /* 'icss' class */
875 static struct omap_hwmod_class am33xx_icss_hwmod_class = {
876 .name = "icss",
877 };
879 /* icss */
880 static struct omap_hwmod am33xx_icss_hwmod = {
881 .name = "icss",
882 .class = &am33xx_icss_hwmod_class,
883 .main_clk = "icss_fck",
884 .clkdm_name = "icss_ocp_clkdm",
885 .prcm = {
886 .omap4 = {
887 .clkctrl_offs = AM33XX_CM_PER_ICSS_CLKCTRL_OFFSET,
888 .modulemode = MODULEMODE_SWCTRL,
889 },
890 },
891 };
893 /* 'ieee5000' class */
894 static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = {
895 .name = "ieee5000",
896 };
898 /* ieee5000 */
899 static struct omap_hwmod am33xx_ieee5000_hwmod = {
900 .name = "ieee5000",
901 .class = &am33xx_ieee5000_hwmod_class,
902 .main_clk = "ieee5000_fck",
903 .clkdm_name = "l3s_clkdm",
904 .prcm = {
905 .omap4 = {
906 .clkctrl_offs = AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET,
907 .modulemode = MODULEMODE_SWCTRL,
908 },
909 },
910 };
913 /* 'l3' class */
914 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
915 .name = "l3",
916 };
918 /* l4_hs */
919 static struct omap_hwmod am33xx_l4_hs_hwmod = {
920 .name = "l4_hs",
921 .class = &am33xx_l3_hwmod_class,
922 .clkdm_name = "l4hs_clkdm",
923 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
924 .prcm = {
925 .omap4 = {
926 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
927 .modulemode = MODULEMODE_SWCTRL,
928 },
929 },
930 };
932 /* l3_instr */
933 static struct omap_hwmod am33xx_l3_instr_hwmod = {
934 .name = "l3_instr",
935 .class = &am33xx_l3_hwmod_class,
936 .clkdm_name = "l3_clkdm",
937 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
938 .prcm = {
939 .omap4 = {
940 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
941 .modulemode = MODULEMODE_SWCTRL,
942 },
943 },
944 };
946 /* l3_main */
947 static struct omap_hwmod am33xx_l3_main_hwmod = {
948 .name = "l3_main",
949 .class = &am33xx_l3_hwmod_class,
950 .clkdm_name = "l3_clkdm",
951 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
952 .prcm = {
953 .omap4 = {
954 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
955 .modulemode = MODULEMODE_SWCTRL,
956 },
957 },
958 };
960 /* 'l4fw' class */
961 static struct omap_hwmod_class am33xx_l4fw_hwmod_class = {
962 .name = "l4fw",
963 };
965 /* l4fw */
966 static struct omap_hwmod am33xx_l4fw_hwmod = {
967 .name = "l4fw",
968 .class = &am33xx_l4fw_hwmod_class,
969 .clkdm_name = "l4fw_clkdm",
970 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
971 .prcm = {
972 .omap4 = {
973 .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
974 .modulemode = MODULEMODE_SWCTRL,
975 },
976 },
977 };
979 /* 'l4ls' class */
980 static struct omap_hwmod_class am33xx_l4ls_hwmod_class = {
981 .name = "l4ls",
982 };
984 /* l4ls */
985 static struct omap_hwmod am33xx_l4ls_hwmod = {
986 .name = "l4ls",
987 .class = &am33xx_l4ls_hwmod_class,
988 .main_clk = "l4ls_fck",
989 .clkdm_name = "l4ls_clkdm",
990 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
991 .prcm = {
992 .omap4 = {
993 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
994 .modulemode = MODULEMODE_SWCTRL,
995 },
996 },
997 };
999 /* 'lcdc' class */
1000 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1001 .name = "lcdc",
1002 };
1004 /* lcdc */
1005 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1006 { .irq = AM33XX_IRQ_LCD },
1007 { .irq = -1 }
1008 };
1010 static struct omap_hwmod am33xx_lcdc_hwmod = {
1011 .name = "lcdc",
1012 .class = &am33xx_lcdc_hwmod_class,
1013 .mpu_irqs = am33xx_lcdc_irqs,
1014 .main_clk = "lcdc_fck",
1015 .clkdm_name = "lcdc_clkdm",
1016 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1017 .prcm = {
1018 .omap4 = {
1019 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1020 .modulemode = MODULEMODE_SWCTRL,
1021 },
1022 },
1023 };
1025 /*
1026 * 'mailbox' class
1027 * mailbox module allowing communication between the on-chip processors using a
1028 * queued mailbox-interrupt mechanism.
1029 */
1031 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1032 .rev_offs = 0x0000,
1033 .sysc_offs = 0x0010,
1034 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1035 SYSC_HAS_SOFTRESET),
1036 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1037 .sysc_fields = &omap_hwmod_sysc_type2,
1038 };
1040 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1041 .name = "mailbox",
1042 .sysc = &am33xx_mailbox_sysc,
1043 };
1045 /* mailbox */
1046 static struct omap_hwmod am33xx_mailbox_hwmod;
1047 static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1048 { .irq = AM33XX_IRQ_MAILBOX },
1049 { .irq = -1 }
1050 };
1052 static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
1053 {
1054 .pa_start = AM33XX_MAILBOX0_BASE,
1055 .pa_end = AM33XX_MAILBOX0_BASE + (SZ_4K - 1),
1056 .flags = ADDR_TYPE_RT
1057 },
1058 { }
1059 };
1061 /* l4_cfg -> mailbox */
1062 static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
1063 .master = &am33xx_l4per_hwmod,
1064 .slave = &am33xx_mailbox_hwmod,
1065 .addr = am33xx_mailbox_addrs,
1066 .user = OCP_USER_MPU,
1067 };
1069 /* mailbox slave ports */
1070 static struct omap_hwmod_ocp_if *am33xx_mailbox_slaves[] = {
1071 &am33xx_l4_per__mailbox,
1072 };
1074 static struct omap_hwmod am33xx_mailbox_hwmod = {
1075 .name = "mailbox",
1076 .class = &am33xx_mailbox_hwmod_class,
1077 .clkdm_name = "l4ls_clkdm",
1078 .mpu_irqs = am33xx_mailbox_irqs,
1079 .main_clk = "mailbox0_fck",
1080 .prcm = {
1081 .omap4 = {
1082 .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1083 .modulemode = MODULEMODE_SWCTRL,
1084 },
1085 },
1086 .slaves = am33xx_mailbox_slaves,
1087 .slaves_cnt = ARRAY_SIZE(am33xx_mailbox_slaves),
1088 };
1090 /* 'mcasp' class */
1091 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1092 .name = "mcasp",
1093 };
1095 /* mcasp0 */
1096 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1097 { .irq = 80 },
1098 { .irq = -1 }
1099 };
1101 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1102 .name = "mcasp0",
1103 .class = &am33xx_mcasp_hwmod_class,
1104 .mpu_irqs = am33xx_mcasp0_irqs,
1105 .main_clk = "mcasp0_fck",
1106 .clkdm_name = "l3s_clkdm",
1107 .prcm = {
1108 .omap4 = {
1109 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1110 .modulemode = MODULEMODE_SWCTRL,
1111 },
1112 },
1113 };
1115 /* 'mmc' class */
1117 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1118 .rev_offs = 0x1fc,
1119 .sysc_offs = 0x10,
1120 .syss_offs = 0x14,
1121 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1122 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1123 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1124 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1125 .sysc_fields = &omap_hwmod_sysc_type1,
1126 };
1128 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1129 .name = "mmc",
1130 .sysc = &am33xx_mmc_sysc,
1131 };
1133 /* mmc0 */
1134 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1135 { .irq = AM33XX_IRQ_MMCHS0 },
1136 { .irq = -1 }
1137 };
1139 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1140 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS0_W, },
1141 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS0_R, },
1142 { .dma_req = -1 }
1143 };
1145 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
1146 {
1147 .pa_start = AM33XX_MMC0_BASE,
1148 .pa_end = AM33XX_MMC0_BASE + SZ_4K - 1,
1149 .flags = ADDR_TYPE_RT
1150 },
1151 { }
1152 };
1154 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc0 = {
1155 .master = &am33xx_l4ls_hwmod,
1156 .slave = &am33xx_mmc0_hwmod,
1157 .clk = "mmc0_ick",
1158 .addr = am33xx_mmc0_addr_space,
1159 .user = OCP_USER_MPU,
1160 };
1162 static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = {
1163 &am33xx_l4ls__mmc0,
1164 };
1166 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1167 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1168 };
1170 static struct omap_hwmod am33xx_mmc0_hwmod = {
1171 .name = "mmc1",
1172 .class = &am33xx_mmc_hwmod_class,
1173 .mpu_irqs = am33xx_mmc0_irqs,
1174 .sdma_reqs = am33xx_mmc0_edma_reqs,
1175 .main_clk = "mmc0_fck",
1176 .clkdm_name = "l4ls_clkdm",
1177 .prcm = {
1178 .omap4 = {
1179 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1180 .modulemode = MODULEMODE_SWCTRL,
1181 },
1182 },
1183 .dev_attr = &am33xx_mmc0_dev_attr,
1184 .slaves = am33xx_mmc0_slaves,
1185 .slaves_cnt = ARRAY_SIZE(am33xx_mmc0_slaves),
1186 };
1188 /* mmc1 */
1189 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1190 { .irq = AM33XX_IRQ_MMCHS1 },
1191 { .irq = -1 }
1192 };
1194 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1195 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS1_W, },
1196 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS1_R, },
1197 { .dma_req = -1 }
1198 };
1200 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
1201 {
1202 .pa_start = AM33XX_MMC1_BASE,
1203 .pa_end = AM33XX_MMC1_BASE + SZ_4K - 1,
1204 .flags = ADDR_TYPE_RT
1205 },
1206 { }
1207 };
1209 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc1 = {
1210 .master = &am33xx_l4ls_hwmod,
1211 .slave = &am33xx_mmc1_hwmod,
1212 .clk = "mmc1_ick",
1213 .addr = am33xx_mmc1_addr_space,
1214 .user = OCP_USER_MPU,
1215 };
1217 static struct omap_hwmod_ocp_if *am33xx_mmc1_slaves[] = {
1218 &am33xx_l4ls__mmc1,
1219 };
1221 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1222 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1223 };
1225 static struct omap_hwmod am33xx_mmc1_hwmod = {
1226 .name = "mmc2",
1227 .class = &am33xx_mmc_hwmod_class,
1228 .mpu_irqs = am33xx_mmc1_irqs,
1229 .sdma_reqs = am33xx_mmc1_edma_reqs,
1230 .main_clk = "mmc1_fck",
1231 .clkdm_name = "l4ls_clkdm",
1232 .prcm = {
1233 .omap4 = {
1234 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1235 .modulemode = MODULEMODE_SWCTRL,
1236 },
1237 },
1238 .dev_attr = &am33xx_mmc1_dev_attr,
1239 .slaves = am33xx_mmc1_slaves,
1240 .slaves_cnt = ARRAY_SIZE(am33xx_mmc1_slaves),
1241 };
1243 /* mmc2 */
1244 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1245 { .irq = AM33XX_IRQ_MMCHS2 },
1246 { .irq = -1 }
1247 };
1249 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1250 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS2_W, },
1251 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS2_R, },
1252 { .dma_req = -1 }
1253 };
1255 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
1256 {
1257 .pa_start = AM33XX_MMC2_BASE,
1258 .pa_end = AM33XX_MMC2_BASE + SZ_64K - 1,
1259 .flags = ADDR_TYPE_RT
1260 },
1261 { }
1262 };
1264 static struct omap_hwmod_ocp_if am33xx_l3_main__mmc2 = {
1265 .master = &am33xx_l3_main_hwmod,
1266 .slave = &am33xx_mmc2_hwmod,
1267 .clk = "mmc2_ick",
1268 .addr = am33xx_mmc2_addr_space,
1269 .user = OCP_USER_MPU,
1270 };
1272 static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = {
1273 &am33xx_l3_main__mmc2,
1274 };
1276 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1277 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1278 };
1279 static struct omap_hwmod am33xx_mmc2_hwmod = {
1280 .name = "mmc3",
1281 .class = &am33xx_mmc_hwmod_class,
1282 .mpu_irqs = am33xx_mmc2_irqs,
1283 .sdma_reqs = am33xx_mmc2_edma_reqs,
1284 .main_clk = "mmc2_fck",
1285 .clkdm_name = "l3s_clkdm",
1286 .prcm = {
1287 .omap4 = {
1288 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1289 .modulemode = MODULEMODE_SWCTRL,
1290 },
1291 },
1292 .dev_attr = &am33xx_mmc2_dev_attr,
1293 .slaves = am33xx_mmc2_slaves,
1294 .slaves_cnt = ARRAY_SIZE(am33xx_mmc2_slaves),
1295 };
1297 /* Master interfaces on the MPU interconnect */
1298 static struct omap_hwmod_ocp_if *am33xx_l3_mpu_masters[] = {
1299 &am33xx_mpu__l3_slow,
1300 };
1302 /* mpu */
1303 static struct omap_hwmod am33xx_mpu_hwmod = {
1304 .name = "mpu",
1305 .class = &mpu_hwmod_class,
1306 .masters = am33xx_l3_mpu_masters,
1307 .masters_cnt = ARRAY_SIZE(am33xx_l3_mpu_masters),
1308 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1309 .main_clk = "mpu_fck",
1310 .clkdm_name = "mpu_clkdm",
1311 .prcm = {
1312 .omap4 = {
1313 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1314 .modulemode = MODULEMODE_SWCTRL,
1315 },
1316 },
1317 };
1319 /* 'ocmcram' class */
1320 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
1321 .name = "ocmcram",
1322 };
1324 /* ocmcram */
1325 static struct omap_hwmod am33xx_ocmcram_hwmod = {
1326 .name = "ocmcram",
1327 .class = &am33xx_ocmcram_hwmod_class,
1328 .main_clk = "ocmcram_fck",
1329 .clkdm_name = "l3_clkdm",
1330 .prcm = {
1331 .omap4 = {
1332 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
1333 .modulemode = MODULEMODE_SWCTRL,
1334 },
1335 },
1336 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1337 };
1339 /* 'ocpwp' class */
1340 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
1341 .name = "ocpwp",
1342 };
1344 /* ocpwp */
1345 static struct omap_hwmod am33xx_ocpwp_hwmod = {
1346 .name = "ocpwp",
1347 .class = &am33xx_ocpwp_hwmod_class,
1348 .main_clk = "ocpwp_fck",
1349 .clkdm_name = "l4ls_clkdm",
1350 .prcm = {
1351 .omap4 = {
1352 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
1353 .modulemode = MODULEMODE_SWCTRL,
1354 },
1355 },
1356 };
1358 /* 'rtc' class */
1359 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1360 .name = "rtc",
1361 };
1363 /* rtc */
1364 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1365 { .irq = AM33XX_IRQ_RTC_TIMER },
1366 { .irq = -1 }
1367 };
1369 static struct omap_hwmod am33xx_rtc_hwmod = {
1370 .name = "rtc",
1371 .class = &am33xx_rtc_hwmod_class,
1372 .mpu_irqs = am33xx_rtc_irqs,
1373 .main_clk = "rtc_fck",
1374 .clkdm_name = "l4_rtc_clkdm",
1375 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1376 .prcm = {
1377 .omap4 = {
1378 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1379 .modulemode = MODULEMODE_SWCTRL,
1380 },
1381 },
1382 };
1384 /* 'sha0' class */
1385 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
1386 .name = "sha0",
1387 };
1389 /* sha0 */
1390 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
1391 { .irq = AM33XX_IRQ_SHAEIP57t0_S },
1392 { .irq = -1 }
1393 };
1395 static struct omap_hwmod am33xx_sha0_hwmod = {
1396 .name = "sha0",
1397 .class = &am33xx_sha0_hwmod_class,
1398 .mpu_irqs = am33xx_sha0_irqs,
1399 .main_clk = "sha0_fck",
1400 .clkdm_name = "l3_clkdm",
1401 .prcm = {
1402 .omap4 = {
1403 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
1404 .modulemode = MODULEMODE_SWCTRL,
1405 },
1406 },
1407 };
1409 /* 'smartreflex' class */
1410 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
1411 .name = "smartreflex",
1412 };
1414 /* smartreflex0 */
1415 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
1416 { .irq = AM33XX_IRQ_SMARTREFLEX0 },
1417 { .irq = -1 }
1418 };
1420 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
1421 .name = "smartreflex0",
1422 .class = &am33xx_smartreflex_hwmod_class,
1423 .mpu_irqs = am33xx_smartreflex0_irqs,
1424 .main_clk = "smartreflex0_fck",
1425 .clkdm_name = "l4_wkup_clkdm",
1426 .prcm = {
1427 .omap4 = {
1428 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
1429 .modulemode = MODULEMODE_SWCTRL,
1430 },
1431 },
1432 };
1434 /* smartreflex1 */
1435 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
1436 { .irq = AM33XX_IRQ_SMARTREFLEX1 },
1437 { .irq = -1 }
1438 };
1440 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
1441 .name = "smartreflex1",
1442 .class = &am33xx_smartreflex_hwmod_class,
1443 .mpu_irqs = am33xx_smartreflex1_irqs,
1444 .main_clk = "smartreflex1_fck",
1445 .clkdm_name = "l4_wkup_clkdm",
1446 .prcm = {
1447 .omap4 = {
1448 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
1449 .modulemode = MODULEMODE_SWCTRL,
1450 },
1451 },
1452 };
1454 /* 'spi' class */
1456 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1457 .rev_offs = 0x0000,
1458 .sysc_offs = 0x0110,
1459 .syss_offs = 0x0114,
1460 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1461 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1462 SYSS_HAS_RESET_STATUS),
1463 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1464 .sysc_fields = &omap_hwmod_sysc_type1,
1465 };
1467 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1468 .name = "mcspi",
1469 .sysc = &am33xx_mcspi_sysc,
1470 .rev = OMAP4_MCSPI_REV,
1471 };
1473 /* spi0 */
1474 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1475 { .irq = AM33XX_IRQ_MCSPIOCP0 },
1476 { .irq = -1 }
1477 };
1479 struct omap_hwmod_dma_info am33xx_mcspi0_sdma_reqs[] = {
1480 { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0R },
1481 { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0W },
1482 { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1R },
1483 { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1W },
1484 { .dma_req = -1 }
1485 };
1487 struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
1488 {
1489 .pa_start = AM33XX_SPI0_BASE,
1490 .pa_end = AM33XX_SPI0_BASE + SZ_1K - 1,
1491 .flags = ADDR_TYPE_RT
1492 },
1493 { }
1494 };
1496 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = {
1497 .master = &am33xx_l4per_hwmod,
1498 .slave = &am33xx_spi0_hwmod,
1499 .clk = "spi0_ick",
1500 .addr = am33xx_mcspi0_addr_space,
1501 .user = OCP_USER_MPU,
1502 };
1504 static struct omap_hwmod_ocp_if *am33xx_mcspi0_slaves[] = {
1505 &am33xx_l4_core__mcspi0,
1506 };
1508 struct omap2_mcspi_dev_attr mcspi_attrib = {
1509 .num_chipselect = 2,
1510 };
1511 static struct omap_hwmod am33xx_spi0_hwmod = {
1512 .name = "spi0",
1513 .class = &am33xx_spi_hwmod_class,
1514 .mpu_irqs = am33xx_spi0_irqs,
1515 .sdma_reqs = am33xx_mcspi0_sdma_reqs,
1516 .main_clk = "spi0_fck",
1517 .clkdm_name = "l4ls_clkdm",
1518 .prcm = {
1519 .omap4 = {
1520 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1521 .modulemode = MODULEMODE_SWCTRL,
1522 },
1523 },
1524 .dev_attr = &mcspi_attrib,
1525 .slaves = am33xx_mcspi0_slaves,
1526 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi0_slaves),
1527 };
1529 /* spi1 */
1530 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1531 { .irq = AM33XX_IRQ_SPI1 },
1532 { .irq = -1 }
1533 };
1535 struct omap_hwmod_dma_info am33xx_mcspi1_sdma_reqs[] = {
1536 { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0R },
1537 { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0W },
1538 { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1R },
1539 { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1W },
1540 { .dma_req = -1 }
1541 };
1543 struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
1544 {
1545 .pa_start = AM33XX_SPI1_BASE,
1546 .pa_end = AM33XX_SPI1_BASE + SZ_1K - 1,
1547 .flags = ADDR_TYPE_RT
1548 },
1549 { }
1550 };
1552 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = {
1553 .master = &am33xx_l4per_hwmod,
1554 .slave = &am33xx_spi1_hwmod,
1555 .clk = "spi1_ick",
1556 .addr = am33xx_mcspi1_addr_space,
1557 .user = OCP_USER_MPU,
1558 };
1560 static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = {
1561 &am33xx_l4_core__mcspi1,
1562 };
1563 static struct omap_hwmod am33xx_spi1_hwmod = {
1564 .name = "spi1",
1565 .class = &am33xx_spi_hwmod_class,
1566 .mpu_irqs = am33xx_spi1_irqs,
1567 .sdma_reqs = am33xx_mcspi1_sdma_reqs,
1568 .main_clk = "spi1_fck",
1569 .clkdm_name = "l4ls_clkdm",
1570 .prcm = {
1571 .omap4 = {
1572 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1573 .modulemode = MODULEMODE_SWCTRL,
1574 },
1575 },
1576 .dev_attr = &mcspi_attrib,
1577 .slaves = am33xx_mcspi1_slaves,
1578 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi1_slaves),
1579 };
1581 /* 'spinlock' class */
1582 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1583 .name = "spinlock",
1584 };
1586 /* spinlock */
1587 static struct omap_hwmod am33xx_spinlock_hwmod = {
1588 .name = "spinlock",
1589 .class = &am33xx_spinlock_hwmod_class,
1590 .main_clk = "spinlock_fck",
1591 .clkdm_name = "l4ls_clkdm",
1592 .prcm = {
1593 .omap4 = {
1594 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1595 .modulemode = MODULEMODE_SWCTRL,
1596 },
1597 },
1598 };
1600 /* 'timer 0 & 2-7' class */
1601 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1602 .rev_offs = 0x0000,
1603 .sysc_offs = 0x0010,
1604 .syss_offs = 0x0014,
1605 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1606 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1607 SIDLE_SMART_WKUP),
1608 .sysc_fields = &omap_hwmod_sysc_type2,
1609 };
1611 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1612 .name = "timer",
1613 .sysc = &am33xx_timer_sysc,
1614 };
1616 /* timer0 */
1617 /* l4 wkup -> timer0 interface */
1618 static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = {
1619 {
1620 .pa_start = AM33XX_TIMER0_BASE,
1621 .pa_end = AM33XX_TIMER0_BASE + SZ_1K - 1,
1622 .flags = ADDR_TYPE_RT
1623 },
1624 { }
1625 };
1627 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = {
1628 .master = &am33xx_l4wkup_hwmod,
1629 .slave = &am33xx_timer0_hwmod,
1630 .clk = "timer0_ick",
1631 .addr = am33xx_timer0_addr_space,
1632 .user = OCP_USER_MPU,
1633 };
1635 static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = {
1636 &am33xx_l4wkup__timer0,
1637 };
1639 static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = {
1640 { .irq = AM33XX_IRQ_DMTIMER0 },
1641 { .irq = -1 }
1642 };
1644 static struct omap_hwmod am33xx_timer0_hwmod = {
1645 .name = "timer0",
1646 .class = &am33xx_timer_hwmod_class,
1647 .mpu_irqs = am33xx_timer0_irqs,
1648 .main_clk = "timer0_fck",
1649 .clkdm_name = "l4_wkup_clkdm",
1650 .prcm = {
1651 .omap4 = {
1652 .clkctrl_offs = AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET,
1653 .modulemode = MODULEMODE_SWCTRL,
1654 },
1655 },
1656 .slaves = am33xx_timer0_slaves,
1657 .slaves_cnt = ARRAY_SIZE(am33xx_timer0_slaves),
1658 };
1660 /* timer1 1ms */
1661 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1662 .rev_offs = 0x0000,
1663 .sysc_offs = 0x0010,
1664 .syss_offs = 0x0014,
1665 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1666 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1667 SYSS_HAS_RESET_STATUS),
1668 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1669 .sysc_fields = &omap_hwmod_sysc_type1,
1670 };
1672 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1673 .name = "timer",
1674 .sysc = &am33xx_timer1ms_sysc,
1675 };
1677 /* l4 wkup -> timer1 interface */
1678 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
1679 {
1680 .pa_start = AM33XX_TIMER1_BASE,
1681 .pa_end = AM33XX_TIMER1_BASE + SZ_1K - 1,
1682 .flags = ADDR_TYPE_RT
1683 },
1684 { }
1685 };
1687 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = {
1688 .master = &am33xx_l4wkup_hwmod,
1689 .slave = &am33xx_timer1_hwmod,
1690 .clk = "timer1_ick",
1691 .addr = am33xx_timer1_addr_space,
1692 .user = OCP_USER_MPU,
1693 };
1695 static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = {
1696 &am33xx_l4wkup__timer1,
1697 };
1699 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
1700 { .irq = AM33XX_IRQ_DMTIMER1 },
1701 { .irq = -1 }
1702 };
1704 static struct omap_hwmod am33xx_timer1_hwmod = {
1705 .name = "timer1",
1706 .class = &am33xx_timer1ms_hwmod_class,
1707 .mpu_irqs = am33xx_timer1_irqs,
1708 .main_clk = "timer1_fck",
1709 .clkdm_name = "l4_wkup_clkdm",
1710 .prcm = {
1711 .omap4 = {
1712 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1713 .modulemode = MODULEMODE_SWCTRL,
1714 },
1715 },
1716 .slaves = am33xx_timer1_slaves,
1717 .slaves_cnt = ARRAY_SIZE(am33xx_timer1_slaves),
1718 };
1720 /* timer2 */
1721 /* l4 per -> timer2 interface */
1722 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
1723 {
1724 .pa_start = AM33XX_TIMER2_BASE,
1725 .pa_end = AM33XX_TIMER2_BASE + SZ_1K - 1,
1726 .flags = ADDR_TYPE_RT
1727 },
1728 { }
1729 };
1731 static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = {
1732 .master = &am33xx_l4per_hwmod,
1733 .slave = &am33xx_timer2_hwmod,
1734 .clk = "timer2_ick",
1735 .addr = am33xx_timer2_addr_space,
1736 .user = OCP_USER_MPU,
1737 };
1739 static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = {
1740 &am33xx_l4per__timer2,
1741 };
1743 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
1744 { .irq = AM33XX_IRQ_DMTIMER2 },
1745 { .irq = -1 }
1746 };
1748 static struct omap_hwmod am33xx_timer2_hwmod = {
1749 .name = "timer2",
1750 .class = &am33xx_timer_hwmod_class,
1751 .mpu_irqs = am33xx_timer2_irqs,
1752 .main_clk = "timer2_fck",
1753 .prcm = {
1754 .omap4 = {
1755 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1756 .modulemode = MODULEMODE_SWCTRL,
1757 },
1758 },
1759 .slaves = am33xx_timer2_slaves,
1760 .slaves_cnt = ARRAY_SIZE(am33xx_timer2_slaves),
1761 .clkdm_name = "l4ls_clkdm",
1762 };
1764 /* timer3 */
1765 /* l4 per -> timer3 interface */
1766 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
1767 {
1768 .pa_start = AM33XX_TIMER3_BASE,
1769 .pa_end = AM33XX_TIMER3_BASE + SZ_1K - 1,
1770 .flags = ADDR_TYPE_RT
1771 },
1772 { }
1773 };
1775 static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = {
1776 .master = &am33xx_l4per_hwmod,
1777 .slave = &am33xx_timer3_hwmod,
1778 .clk = "timer3_ick",
1779 .addr = am33xx_timer3_addr_space,
1780 .user = OCP_USER_MPU,
1781 };
1783 static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = {
1784 &am33xx_l4per__timer3,
1785 };
1787 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
1788 { .irq = AM33XX_IRQ_DMTIMER3 },
1789 { .irq = -1 }
1790 };
1792 static struct omap_hwmod am33xx_timer3_hwmod = {
1793 .name = "timer3",
1794 .class = &am33xx_timer_hwmod_class,
1795 .mpu_irqs = am33xx_timer3_irqs,
1796 .main_clk = "timer3_fck",
1797 .clkdm_name = "l4ls_clkdm",
1798 .prcm = {
1799 .omap4 = {
1800 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1801 .modulemode = MODULEMODE_SWCTRL,
1802 },
1803 },
1804 .slaves = am33xx_timer3_slaves,
1805 .slaves_cnt = ARRAY_SIZE(am33xx_timer3_slaves),
1806 };
1808 /* timer4 */
1809 /* l4 per -> timer4 interface */
1810 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
1811 {
1812 .pa_start = AM33XX_TIMER4_BASE,
1813 .pa_end = AM33XX_TIMER4_BASE + SZ_1K - 1,
1814 .flags = ADDR_TYPE_RT
1815 },
1816 { }
1817 };
1819 static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = {
1820 .master = &am33xx_l4per_hwmod,
1821 .slave = &am33xx_timer4_hwmod,
1822 .clk = "timer4_ick",
1823 .addr = am33xx_timer4_addr_space,
1824 .user = OCP_USER_MPU,
1825 };
1827 static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = {
1828 &am33xx_l4per__timer4,
1829 };
1831 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
1832 { .irq = AM33XX_IRQ_DMTIMER4 },
1833 { .irq = -1 }
1834 };
1836 static struct omap_hwmod am33xx_timer4_hwmod = {
1837 .name = "timer4",
1838 .class = &am33xx_timer_hwmod_class,
1839 .mpu_irqs = am33xx_timer4_irqs,
1840 .main_clk = "timer4_fck",
1841 .prcm = {
1842 .omap4 = {
1843 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1844 .modulemode = MODULEMODE_SWCTRL,
1845 },
1846 },
1847 .slaves = am33xx_timer4_slaves,
1848 .slaves_cnt = ARRAY_SIZE(am33xx_timer4_slaves),
1849 .clkdm_name = "l4ls_clkdm",
1850 };
1853 /* timer5 */
1854 /* l4 per -> timer5 interface */
1855 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
1856 {
1857 .pa_start = AM33XX_TIMER5_BASE,
1858 .pa_end = AM33XX_TIMER5_BASE + SZ_1K - 1,
1859 .flags = ADDR_TYPE_RT
1860 },
1861 { }
1862 };
1864 static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = {
1865 .master = &am33xx_l4per_hwmod,
1866 .slave = &am33xx_timer5_hwmod,
1867 .clk = "timer5_ick",
1868 .addr = am33xx_timer5_addr_space,
1869 .user = OCP_USER_MPU,
1870 };
1872 static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = {
1873 &am33xx_l4per__timer5,
1874 };
1876 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
1877 { .irq = AM33XX_IRQ_DMTIMER5 },
1878 { .irq = -1 }
1879 };
1881 static struct omap_hwmod am33xx_timer5_hwmod = {
1882 .name = "timer5",
1883 .class = &am33xx_timer_hwmod_class,
1884 .mpu_irqs = am33xx_timer5_irqs,
1885 .main_clk = "timer5_fck",
1886 .prcm = {
1887 .omap4 = {
1888 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1889 .modulemode = MODULEMODE_SWCTRL,
1890 },
1891 },
1892 .slaves = am33xx_timer5_slaves,
1893 .slaves_cnt = ARRAY_SIZE(am33xx_timer5_slaves),
1894 .clkdm_name = "l4ls_clkdm",
1895 };
1897 /* timer6 */
1898 /* l4 per -> timer6 interface */
1899 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
1900 {
1901 .pa_start = AM33XX_TIMER6_BASE,
1902 .pa_end = AM33XX_TIMER6_BASE + SZ_1K - 1,
1903 .flags = ADDR_TYPE_RT
1904 },
1905 { }
1906 };
1908 static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = {
1909 .master = &am33xx_l4per_hwmod,
1910 .slave = &am33xx_timer6_hwmod,
1911 .clk = "timer6_ick",
1912 .addr = am33xx_timer6_addr_space,
1913 .user = OCP_USER_MPU,
1914 };
1916 static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = {
1917 &am33xx_l4per__timer6,
1918 };
1920 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
1921 { .irq = AM33XX_IRQ_DMTIMER6 },
1922 { .irq = -1 }
1923 };
1925 static struct omap_hwmod am33xx_timer6_hwmod = {
1926 .name = "timer6",
1927 .class = &am33xx_timer_hwmod_class,
1928 .mpu_irqs = am33xx_timer6_irqs,
1929 .main_clk = "timer6_fck",
1930 .prcm = {
1931 .omap4 = {
1932 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
1933 .modulemode = MODULEMODE_SWCTRL,
1934 },
1935 },
1936 .slaves = am33xx_timer6_slaves,
1937 .slaves_cnt = ARRAY_SIZE(am33xx_timer6_slaves),
1938 .clkdm_name = "l4ls_clkdm",
1939 };
1941 /* timer7 */
1942 /* l4 per -> timer7 interface */
1943 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
1944 {
1945 .pa_start = AM33XX_TIMER7_BASE,
1946 .pa_end = AM33XX_TIMER7_BASE + SZ_1K - 1,
1947 .flags = ADDR_TYPE_RT
1948 },
1949 { }
1950 };
1952 static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = {
1953 .master = &am33xx_l4per_hwmod,
1954 .slave = &am33xx_timer7_hwmod,
1955 .clk = "timer7_ick",
1956 .addr = am33xx_timer7_addr_space,
1957 .user = OCP_USER_MPU,
1958 };
1960 static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = {
1961 &am33xx_l4per__timer7,
1962 };
1964 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
1965 { .irq = AM33XX_IRQ_DMTIMER7 },
1966 { .irq = -1 }
1967 };
1969 static struct omap_hwmod am33xx_timer7_hwmod = {
1970 .name = "timer7",
1971 .class = &am33xx_timer_hwmod_class,
1972 .mpu_irqs = am33xx_timer7_irqs,
1973 .main_clk = "timer7_fck",
1974 .prcm = {
1975 .omap4 = {
1976 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
1977 .modulemode = MODULEMODE_SWCTRL,
1978 },
1979 },
1980 .slaves = am33xx_timer7_slaves,
1981 .slaves_cnt = ARRAY_SIZE(am33xx_timer7_slaves),
1982 .clkdm_name = "l4ls_clkdm",
1983 };
1985 /* 'tpcc' class */
1986 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1987 .name = "tpcc",
1988 };
1990 /* tpcc */
1991 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
1992 { .irq = AM33XX_IRQ_TPCC0_INT_PO0 },
1993 { .irq = -1 },
1994 };
1996 static struct omap_hwmod am33xx_tpcc_hwmod = {
1997 .name = "tpcc",
1998 .class = &am33xx_tpcc_hwmod_class,
1999 .mpu_irqs = am33xx_tpcc_irqs,
2000 .main_clk = "tpcc_ick",
2001 .clkdm_name = "l3_clkdm",
2002 .prcm = {
2003 .omap4 = {
2004 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
2005 .modulemode = MODULEMODE_SWCTRL,
2006 },
2007 },
2008 };
2010 /* 'tptc' class */
2011 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
2012 .name = "tptc",
2013 };
2015 /* tptc0 */
2016 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
2017 { .irq = AM33XX_IRQ_TPTC0 },
2018 { .irq = -1 }
2019 };
2021 static struct omap_hwmod am33xx_tptc0_hwmod = {
2022 .name = "tptc0",
2023 .class = &am33xx_tptc_hwmod_class,
2024 .mpu_irqs = am33xx_tptc0_irqs,
2025 .main_clk = "tptc0_ick",
2026 .clkdm_name = "l3_clkdm",
2027 .prcm = {
2028 .omap4 = {
2029 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
2030 .modulemode = MODULEMODE_SWCTRL,
2031 },
2032 },
2033 };
2035 /* tptc1 */
2036 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
2037 { .irq = AM33XX_IRQ_TPTC1 },
2038 { .irq = -1 }
2039 };
2041 static struct omap_hwmod am33xx_tptc1_hwmod = {
2042 .name = "tptc1",
2043 .class = &am33xx_tptc_hwmod_class,
2044 .mpu_irqs = am33xx_tptc1_irqs,
2045 .main_clk = "tptc1_ick",
2046 .clkdm_name = "l3_clkdm",
2047 .prcm = {
2048 .omap4 = {
2049 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
2050 .modulemode = MODULEMODE_SWCTRL,
2051 },
2052 },
2053 };
2055 /* tptc2 */
2056 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
2057 { .irq = AM33XX_IRQ_TPTC2 },
2058 { .irq = -1 }
2059 };
2061 static struct omap_hwmod am33xx_tptc2_hwmod = {
2062 .name = "tptc2",
2063 .class = &am33xx_tptc_hwmod_class,
2064 .mpu_irqs = am33xx_tptc2_irqs,
2065 .main_clk = "tptc2_ick",
2066 .clkdm_name = "l3_clkdm",
2067 .prcm = {
2068 .omap4 = {
2069 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
2070 .modulemode = MODULEMODE_SWCTRL,
2071 },
2072 },
2073 };
2075 /* 'uart' class */
2076 static struct omap_hwmod_class_sysconfig uart_sysc = {
2077 .rev_offs = 0x50,
2078 .sysc_offs = 0x54,
2079 .syss_offs = 0x58,
2080 .sysc_flags = (SYSC_HAS_SIDLEMODE |
2081 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2082 SYSC_HAS_AUTOIDLE),
2083 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2084 .sysc_fields = &omap_hwmod_sysc_type1,
2085 };
2087 static struct omap_hwmod_class uart_class = {
2088 .name = "uart",
2089 .sysc = &uart_sysc,
2090 };
2092 /* uart1 */
2093 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
2094 { .name = "tx", .dma_req = 26, },
2095 { .name = "rx", .dma_req = 27, },
2096 { .dma_req = -1 }
2097 };
2099 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
2100 {
2101 .pa_start = AM33XX_UART1_BASE,
2102 .pa_end = AM33XX_UART1_BASE + SZ_8K - 1,
2103 .flags = ADDR_TYPE_RT
2104 },
2105 { }
2106 };
2108 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
2109 .master = &am33xx_l4wkup_hwmod,
2110 .slave = &am33xx_uart1_hwmod,
2111 .clk = "uart1_ick",
2112 .addr = am33xx_uart1_addr_space,
2113 .user = OCP_USER_MPU,
2114 };
2116 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
2117 { .irq = AM33XX_IRQ_UART0 },
2118 { .irq = -1 }
2119 };
2121 static struct omap_hwmod_ocp_if *am33xx_uart1_slaves[] = {
2122 &am33xx_l4_wkup__uart1,
2123 };
2125 static struct omap_hwmod am33xx_uart1_hwmod = {
2126 .name = "uart1",
2127 .class = &uart_class,
2128 .mpu_irqs = am33xx_uart1_irqs,
2129 .sdma_reqs = uart1_edma_reqs,
2130 .main_clk = "uart1_fck",
2131 .clkdm_name = "l4_wkup_clkdm",
2132 .prcm = {
2133 .omap4 = {
2134 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
2135 .modulemode = MODULEMODE_SWCTRL,
2136 },
2137 },
2138 .slaves = am33xx_uart1_slaves,
2139 .slaves_cnt = ARRAY_SIZE(am33xx_uart1_slaves),
2140 };
2142 /* uart2 */
2143 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
2144 {
2145 .pa_start = AM33XX_UART2_BASE,
2146 .pa_end = AM33XX_UART2_BASE + SZ_8K - 1,
2147 .flags = ADDR_TYPE_RT
2148 },
2149 { }
2150 };
2152 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
2153 .slave = &am33xx_uart2_hwmod,
2154 .clk = "uart2_ick",
2155 .addr = am33xx_uart2_addr_space,
2156 .user = OCP_USER_MPU,
2157 };
2159 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
2160 { .irq = AM33XX_IRQ_UART1 },
2161 { .irq = -1 }
2162 };
2164 static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = {
2165 &am33xx_l4_ls__uart2,
2166 };
2168 static struct omap_hwmod am33xx_uart2_hwmod = {
2169 .name = "uart2",
2170 .class = &uart_class,
2171 .mpu_irqs = am33xx_uart2_irqs,
2172 .main_clk = "uart2_fck",
2173 .clkdm_name = "l4ls_clkdm",
2174 .sdma_reqs = uart1_edma_reqs,
2175 .prcm = {
2176 .omap4 = {
2177 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
2178 .modulemode = MODULEMODE_SWCTRL,
2179 },
2180 },
2181 .slaves = am33xx_uart2_slaves,
2182 .slaves_cnt = ARRAY_SIZE(am33xx_uart2_slaves),
2183 };
2185 /* uart3 */
2186 static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
2187 { .name = "tx", .dma_req = 30, },
2188 { .name = "rx", .dma_req = 31, },
2189 { .dma_req = -1 }
2190 };
2192 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
2193 {
2194 .pa_start = AM33XX_UART3_BASE,
2195 .pa_end = AM33XX_UART3_BASE + SZ_8K - 1,
2196 .flags = ADDR_TYPE_RT
2197 },
2198 { }
2199 };
2201 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
2202 .slave = &am33xx_uart3_hwmod,
2203 .clk = "uart3_ick",
2204 .addr = am33xx_uart3_addr_space,
2205 .user = OCP_USER_MPU,
2206 };
2208 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2209 { .irq = AM33XX_IRQ_UART2 },
2210 { .irq = -1 }
2211 };
2213 static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = {
2214 &am33xx_l4_ls__uart3,
2215 };
2217 static struct omap_hwmod am33xx_uart3_hwmod = {
2218 .name = "uart3",
2219 .class = &uart_class,
2220 .mpu_irqs = am33xx_uart3_irqs,
2221 .main_clk = "uart3_fck",
2222 .clkdm_name = "l4ls_clkdm",
2223 .sdma_reqs = uart3_edma_reqs,
2224 .prcm = {
2225 .omap4 = {
2226 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
2227 .modulemode = MODULEMODE_SWCTRL,
2228 },
2229 },
2230 .slaves = am33xx_uart3_slaves,
2231 .slaves_cnt = ARRAY_SIZE(am33xx_uart3_slaves),
2232 };
2234 /* uart4 */
2235 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
2236 {
2237 .pa_start = AM33XX_UART4_BASE,
2238 .pa_end = AM33XX_UART4_BASE + SZ_8K - 1,
2239 .flags = ADDR_TYPE_RT
2240 },
2241 { }
2242 };
2244 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
2245 .slave = &am33xx_uart4_hwmod,
2246 .clk = "uart4_ick",
2247 .addr = am33xx_uart4_addr_space,
2248 .user = OCP_USER_MPU,
2249 };
2251 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2252 { .irq = AM33XX_IRQ_UART3 },
2253 { .irq = -1 }
2254 };
2256 static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = {
2257 &am33xx_l4_ls__uart4,
2258 };
2260 static struct omap_hwmod am33xx_uart4_hwmod = {
2261 .name = "uart4",
2262 .class = &uart_class,
2263 .mpu_irqs = am33xx_uart4_irqs,
2264 .main_clk = "uart4_fck",
2265 .clkdm_name = "l4ls_clkdm",
2266 .sdma_reqs = uart1_edma_reqs,
2267 .prcm = {
2268 .omap4 = {
2269 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
2270 .modulemode = MODULEMODE_SWCTRL,
2271 },
2272 },
2273 .slaves = am33xx_uart4_slaves,
2274 .slaves_cnt = ARRAY_SIZE(am33xx_uart4_slaves),
2275 };
2277 /* uart5 */
2278 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
2279 {
2280 .pa_start = AM33XX_UART5_BASE,
2281 .pa_end = AM33XX_UART5_BASE + SZ_8K - 1,
2282 .flags = ADDR_TYPE_RT
2283 },
2284 { }
2285 };
2287 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
2288 .slave = &am33xx_uart5_hwmod,
2289 .clk = "uart5_ick",
2290 .addr = am33xx_uart5_addr_space,
2291 .user = OCP_USER_MPU,
2292 };
2294 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2295 { .irq = AM33XX_IRQ_UART4 },
2296 { .irq = -1 }
2297 };
2299 static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = {
2300 &am33xx_l4_ls__uart5,
2301 };
2303 static struct omap_hwmod am33xx_uart5_hwmod = {
2304 .name = "uart5",
2305 .class = &uart_class,
2306 .mpu_irqs = am33xx_uart5_irqs,
2307 .main_clk = "uart5_fck",
2308 .clkdm_name = "l4ls_clkdm",
2309 .sdma_reqs = uart1_edma_reqs,
2310 .prcm = {
2311 .omap4 = {
2312 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2313 .modulemode = MODULEMODE_SWCTRL,
2314 },
2315 },
2316 .slaves = am33xx_uart5_slaves,
2317 .slaves_cnt = ARRAY_SIZE(am33xx_uart5_slaves),
2318 };
2320 /* uart6 */
2321 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
2322 {
2323 .pa_start = AM33XX_UART6_BASE,
2324 .pa_end = AM33XX_UART6_BASE + SZ_8K - 1,
2325 .flags = ADDR_TYPE_RT
2326 },
2327 { }
2328 };
2330 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
2331 .slave = &am33xx_uart6_hwmod,
2332 .clk = "uart6_ick",
2333 .addr = am33xx_uart6_addr_space,
2334 .user = OCP_USER_MPU,
2335 };
2337 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2338 { .irq = AM33XX_IRQ_UART5 },
2339 { .irq = -1 }
2340 };
2342 static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = {
2343 &am33xx_l4_ls__uart6,
2344 };
2346 static struct omap_hwmod am33xx_uart6_hwmod = {
2347 .name = "uart6",
2348 .class = &uart_class,
2349 .mpu_irqs = am33xx_uart6_irqs,
2350 .main_clk = "uart6_fck",
2351 .clkdm_name = "l4ls_clkdm",
2352 .sdma_reqs = uart1_edma_reqs,
2353 .prcm = {
2354 .omap4 = {
2355 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2356 .modulemode = MODULEMODE_SWCTRL,
2357 },
2358 },
2359 .slaves = am33xx_uart6_slaves,
2360 .slaves_cnt = ARRAY_SIZE(am33xx_uart6_slaves),
2361 };
2363 /* 'wd_timer' class */
2364 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2365 .name = "wd_timer",
2366 };
2368 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
2369 {
2370 .pa_start = AM33XX_WDT1_BASE,
2371 .pa_end = AM33XX_WDT1_BASE + SZ_4K - 1,
2372 .flags = ADDR_TYPE_RT
2373 },
2374 { }
2375 };
2377 /* l4_wkup -> wd_timer1 */
2378 static struct omap_hwmod_ocp_if am33xx_l4wkup__wd_timer1 = {
2379 .master = &am33xx_l4wkup_hwmod,
2380 .slave = &am33xx_wd_timer1_hwmod,
2381 .addr = am33xx_wd_timer1_addrs,
2382 .user = OCP_USER_MPU,
2383 };
2385 /* wd_timer1 slave ports */
2386 static struct omap_hwmod_ocp_if *am33xx_wd_timer1_slaves[] = {
2387 &am33xx_l4wkup__wd_timer1,
2388 };
2390 /* wd_timer1 */
2391 /*
2392 * TODO: device.c file uses hardcoded name for watchdog
2393 timer driver "wd_timer2, so we are also using
2394 same name as of now...
2395 */
2396 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2397 .name = "wd_timer2",
2398 .class = &am33xx_wd_timer_hwmod_class,
2399 .main_clk = "wd_timer1_fck",
2400 .clkdm_name = "l4_wkup_clkdm",
2401 .prcm = {
2402 .omap4 = {
2403 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2404 .modulemode = MODULEMODE_SWCTRL,
2405 },
2406 },
2407 .slaves = am33xx_wd_timer1_slaves,
2408 .slaves_cnt = ARRAY_SIZE(am33xx_wd_timer1_slaves),
2409 };
2411 /* wdt0 */
2412 static struct omap_hwmod_irq_info am33xx_wdt0_irqs[] = {
2413 { .irq = AM33XX_IRQ_WDT0 },
2414 { .irq = -1 },
2415 };
2417 static struct omap_hwmod am33xx_wdt0_hwmod = {
2418 .name = "wdt0",
2419 .class = &am33xx_wd_timer_hwmod_class,
2420 .mpu_irqs = am33xx_wdt0_irqs,
2421 .main_clk = "wdt0_fck",
2422 .clkdm_name = "l4_wkup_clkdm",
2423 .prcm = {
2424 .omap4 = {
2425 .clkctrl_offs = AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET,
2426 .modulemode = MODULEMODE_SWCTRL,
2427 },
2428 },
2429 };
2431 /* 'wkup_m3' class */
2432 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
2433 .name = "wkup_m3",
2434 };
2436 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
2437 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
2438 };
2440 /* wkup_m3 */
2441 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
2442 .name = "wkup_m3",
2443 .class = &am33xx_wkup_m3_hwmod_class,
2444 .clkdm_name = "l4_wkup_aon_clkdm",
2445 .main_clk = "wkup_m3_fck",
2446 .rst_lines = am33xx_wkup_m3_resets,
2447 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
2448 .prcm = {
2449 .omap4 = {
2450 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
2451 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
2452 .modulemode = MODULEMODE_SWCTRL,
2453 },
2454 },
2455 .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */
2456 };
2458 /* L3 SLOW -> USBSS interface */
2459 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
2460 {
2461 .name = "usbss",
2462 .pa_start = AM33XX_USBSS_BASE,
2463 .pa_end = AM33XX_USBSS_BASE + SZ_4K - 1,
2464 .flags = ADDR_TYPE_RT
2465 },
2466 {
2467 .name = "musb0",
2468 .pa_start = AM33XX_USB0_BASE,
2469 .pa_end = AM33XX_USB0_BASE + SZ_2K - 1,
2470 .flags = ADDR_TYPE_RT
2471 },
2472 {
2473 .name = "musb1",
2474 .pa_start = AM33XX_USB1_BASE,
2475 .pa_end = AM33XX_USB1_BASE + SZ_2K - 1,
2476 .flags = ADDR_TYPE_RT
2477 },
2478 { }
2479 };
2481 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2482 .rev_offs = 0x0,
2483 .sysc_offs = 0x10,
2484 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2485 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2486 .sysc_fields = &omap_hwmod_sysc_type1,
2487 };
2489 static struct omap_hwmod_class am33xx_usbotg_class = {
2490 .name = "usbotg",
2491 .sysc = &am33xx_usbhsotg_sysc,
2492 };
2494 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2495 { .name = "usbss-irq", .irq = AM33XX_IRQ_USBSS, },
2496 { .name = "musb0-irq", .irq = AM33XX_IRQ_USB0, },
2497 { .name = "musb1-irq", .irq = AM33XX_IRQ_USB1, },
2498 { .irq = -1, },
2499 };
2501 static struct omap_hwmod_ocp_if am33xx_l3_slow__usbss = {
2502 .master = &am33xx_l3slow_hwmod,
2503 .slave = &am33xx_usbss_hwmod,
2504 .addr = am33xx_usbss_addr_space,
2505 .user = OCP_USER_MPU,
2506 .flags = OCPIF_SWSUP_IDLE,
2507 };
2509 static struct omap_hwmod_ocp_if *am33xx_usbss_slaves[] = {
2510 &am33xx_l3_slow__usbss,
2511 };
2513 static struct omap_hwmod_opt_clk usbss_opt_clks[] = {
2514 { .role = "clkdcoldo", .clk = "usbotg_fck" },
2515 };
2517 static struct omap_hwmod am33xx_usbss_hwmod = {
2518 .name = "usb_otg_hs",
2519 .mpu_irqs = am33xx_usbss_mpu_irqs,
2520 .main_clk = "usbotg_ick",
2521 .clkdm_name = "l4ls_clkdm",
2522 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2523 .prcm = {
2524 .omap4 = {
2525 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2526 .modulemode = MODULEMODE_SWCTRL,
2527 },
2528 },
2529 .opt_clks = usbss_opt_clks,
2530 .opt_clks_cnt = ARRAY_SIZE(usbss_opt_clks),
2531 .slaves = am33xx_usbss_slaves,
2532 .slaves_cnt = ARRAY_SIZE(am33xx_usbss_slaves),
2533 .class = &am33xx_usbotg_class,
2534 };
2536 static __initdata struct omap_hwmod *am33xx_hwmods[] = {
2537 /* l3 class */
2538 &am33xx_l3_instr_hwmod,
2539 &am33xx_l3_main_hwmod,
2540 /* l3s class */
2541 &am33xx_l3slow_hwmod,
2542 /* l4hs class */
2543 &am33xx_l4_hs_hwmod,
2544 /* l4fw class */
2545 &am33xx_l4fw_hwmod,
2546 /* l4ls class */
2547 &am33xx_l4ls_hwmod,
2548 /* l4per class */
2549 &am33xx_l4per_hwmod,
2550 /* l4wkup class */
2551 &am33xx_l4wkup_hwmod,
2553 /* clkdiv32k class */
2554 &am33xx_clkdiv32k_hwmod,
2555 /* mpu class */
2556 &am33xx_mpu_hwmod,
2557 /* adc_tsc class */
2558 &am33xx_adc_tsc_hwmod,
2559 /* aes class */
2560 &am33xx_aes0_hwmod,
2561 /* cefuse class */
2562 &am33xx_cefuse_hwmod,
2563 /* control class */
2564 &am33xx_control_hwmod,
2565 /* dcan class */
2566 &am33xx_dcan0_hwmod,
2567 &am33xx_dcan1_hwmod,
2568 /* debugss class */
2569 &am33xx_debugss_hwmod,
2570 /* elm class */
2571 &am33xx_elm_hwmod,
2572 /* emif_fw class */
2573 &am33xx_emif_fw_hwmod,
2574 /* epwmss class */
2575 &am33xx_epwmss0_hwmod,
2576 &am33xx_epwmss1_hwmod,
2577 &am33xx_epwmss2_hwmod,
2578 /* gpio class */
2579 &am33xx_gpio0_hwmod,
2580 &am33xx_gpio1_hwmod,
2581 &am33xx_gpio2_hwmod,
2582 &am33xx_gpio3_hwmod,
2583 /* gpmc class */
2584 &am33xx_gpmc_hwmod,
2585 /* i2c class */
2586 &am33xx_i2c1_hwmod,
2587 &am33xx_i2c2_hwmod,
2588 /* icss class */
2589 &am33xx_icss_hwmod,
2590 /* ieee5000 class */
2591 &am33xx_ieee5000_hwmod,
2592 /* mailbox class */
2593 &am33xx_mailbox_hwmod,
2594 /* mcasp class */
2595 &am33xx_mcasp0_hwmod,
2596 /* mmc class */
2597 &am33xx_mmc0_hwmod,
2598 &am33xx_mmc1_hwmod,
2599 &am33xx_mmc2_hwmod,
2600 /* ocmcram class */
2601 &am33xx_ocmcram_hwmod,
2602 /* ocpwp class */
2603 &am33xx_ocpwp_hwmod,
2604 /* sha0 class */
2605 &am33xx_sha0_hwmod,
2606 /* smartreflex class */
2607 &am33xx_smartreflex0_hwmod,
2608 &am33xx_smartreflex1_hwmod,
2609 /* spi class */
2610 &am33xx_spi0_hwmod,
2611 &am33xx_spi1_hwmod,
2612 /* spinlock class */
2613 &am33xx_spinlock_hwmod,
2614 /* uart class */
2615 &am33xx_uart1_hwmod,
2616 &am33xx_uart2_hwmod,
2617 &am33xx_uart3_hwmod,
2618 &am33xx_uart4_hwmod,
2619 &am33xx_uart5_hwmod,
2620 &am33xx_uart6_hwmod,
2621 /* timer class */
2622 &am33xx_timer0_hwmod,
2623 &am33xx_timer1_hwmod,
2624 &am33xx_timer2_hwmod,
2625 &am33xx_timer3_hwmod,
2626 &am33xx_timer4_hwmod,
2627 &am33xx_timer5_hwmod,
2628 &am33xx_timer6_hwmod,
2629 &am33xx_timer7_hwmod,
2630 /* wkup_m3 class */
2631 &am33xx_wkup_m3_hwmod,
2632 /* wd_timer class */
2633 &am33xx_wd_timer1_hwmod,
2634 /* usbss hwmod */
2635 &am33xx_usbss_hwmod,
2636 /* cpgmac0 class */
2637 &am33xx_cpgmac0_hwmod,
2638 &am33xx_wdt0_hwmod, /* Secure WDT */
2639 /* tptc class */
2640 &am33xx_tptc0_hwmod,
2641 &am33xx_tptc1_hwmod,
2642 &am33xx_tptc2_hwmod,
2643 /* tpcc class */
2644 &am33xx_tpcc_hwmod,
2645 /* LCDC class */
2646 &am33xx_lcdc_hwmod,
2647 /* rtc */
2648 &am33xx_rtc_hwmod,
2649 NULL,
2650 };
2652 int __init am33xx_hwmod_init(void)
2653 {
2654 return omap_hwmod_register(am33xx_hwmods);
2655 }