arm:debug: Add a config option for enabling JTAG clock
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / omap_hwmod_33xx_data.c
1 /*
2  * Hardware modules present on the AM33XX chips
3  *
4  * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
5  *
6  * This file is automatically generated from the AM33XX hardware databases.
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation version 2.
10  *
11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12  * kind, whether express or implied; without even the implied warranty
13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  */
17 #include <linux/io.h>
19 #include <plat/omap_hwmod.h>
20 #include <plat/cpu.h>
21 #include <plat/gpio.h>
22 #include <plat/dma.h>
23 #include <plat/mmc.h>
24 #include <plat/mcspi.h>
26 #include "omap_hwmod_common_data.h"
27 #include "control.h"
28 #include "cm33xx.h"
30 /* Backward references (IPs with Bus Master capability) */
31 static struct omap_hwmod am33xx_mpu_hwmod;
32 static struct omap_hwmod am33xx_l3slow_hwmod;
33 static struct omap_hwmod am33xx_l4wkup_hwmod;
34 static struct omap_hwmod am33xx_l4per_hwmod;
35 static struct omap_hwmod am33xx_uart1_hwmod;
36 static struct omap_hwmod am33xx_uart2_hwmod;
37 static struct omap_hwmod am33xx_uart3_hwmod;
38 static struct omap_hwmod am33xx_uart4_hwmod;
39 static struct omap_hwmod am33xx_uart5_hwmod;
40 static struct omap_hwmod am33xx_uart6_hwmod;
41 static struct omap_hwmod am33xx_timer0_hwmod;
42 static struct omap_hwmod am33xx_timer1_hwmod;
43 static struct omap_hwmod am33xx_timer2_hwmod;
44 static struct omap_hwmod am33xx_timer3_hwmod;
45 static struct omap_hwmod am33xx_timer4_hwmod;
46 static struct omap_hwmod am33xx_timer5_hwmod;
47 static struct omap_hwmod am33xx_timer6_hwmod;
48 static struct omap_hwmod am33xx_timer7_hwmod;
49 static struct omap_hwmod am33xx_wd_timer1_hwmod;
50 static struct omap_hwmod am33xx_cpgmac0_hwmod;
51 static struct omap_hwmod am33xx_icss_hwmod;
52 static struct omap_hwmod am33xx_ieee5000_hwmod;
53 static struct omap_hwmod am33xx_tptc0_hwmod;
54 static struct omap_hwmod am33xx_tptc1_hwmod;
55 static struct omap_hwmod am33xx_tptc2_hwmod;
56 static struct omap_hwmod am33xx_gpio0_hwmod;
57 static struct omap_hwmod am33xx_gpio1_hwmod;
58 static struct omap_hwmod am33xx_gpio2_hwmod;
59 static struct omap_hwmod am33xx_gpio3_hwmod;
60 static struct omap_hwmod am33xx_i2c1_hwmod;
61 static struct omap_hwmod am33xx_i2c2_hwmod;
62 static struct omap_hwmod am33xx_usbss_hwmod;
63 static struct omap_hwmod am33xx_mmc0_hwmod;
64 static struct omap_hwmod am33xx_mmc1_hwmod;
65 static struct omap_hwmod am33xx_mmc2_hwmod;
66 static struct omap_hwmod am33xx_spi0_hwmod;
67 static struct omap_hwmod am33xx_spi1_hwmod;
68 static struct omap_hwmod am33xx_elm_hwmod;
70 /*
71  * Interconnects hwmod structures
72  * hwmods that compose the global AM33XX OCP interconnect
73  */
75 /* MPU -> L3_SLOW Peripheral interface */
76 static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = {
77         .master         = &am33xx_mpu_hwmod,
78         .slave          = &am33xx_l3slow_hwmod,
79         .user           = OCP_USER_MPU,
80 };
82 /* L3 SLOW -> L4_PER Peripheral interface */
83 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = {
84         .master         = &am33xx_l3slow_hwmod,
85         .slave          = &am33xx_l4per_hwmod,
86         .user           = OCP_USER_MPU,
87 };
89 /* L3 SLOW -> L4_WKUP Peripheral interface */
90 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = {
91         .master         = &am33xx_l3slow_hwmod,
92         .slave          = &am33xx_l4wkup_hwmod,
93         .user           = OCP_USER_MPU,
94 };
96 /* Master interfaces on the L4_WKUP interconnect */
97 static struct omap_hwmod_ocp_if *am33xx_l3_slow_masters[] = {
98         &am33xx_l3_slow__l4_per,
99         &am33xx_l3_slow__l4_wkup,
100 };
102 /* Slave interfaces on the L3_SLOW interconnect */
103 static struct omap_hwmod_ocp_if *am33xx_l3_slow_slaves[] = {
104         &am33xx_mpu__l3_slow,
105 };
107 static struct omap_hwmod am33xx_l3slow_hwmod = {
108         .name           = "l3_slow",
109         .class          = &l3_hwmod_class,
110         .clkdm_name     = "l3s_clkdm",
111         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
112         .masters        = am33xx_l3_slow_masters,
113         .masters_cnt    = ARRAY_SIZE(am33xx_l3_slow_masters),
114         .slaves         = am33xx_l3_slow_slaves,
115         .slaves_cnt     = ARRAY_SIZE(am33xx_l3_slow_slaves),
116 };
118 /* L4 PER -> GPIO2 */
119 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
120         {
121                 .pa_start       = AM33XX_GPIO1_BASE,
122                 .pa_end         = AM33XX_GPIO1_BASE + SZ_4K - 1,
123                 .flags          = ADDR_TYPE_RT
124         },
125         { }
126 };
128 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
129         .master         = &am33xx_l4per_hwmod,
130         .slave          = &am33xx_gpio1_hwmod,
131         .clk            = "l4ls_fck",
132         .addr           = am33xx_gpio1_addrs,
133         .user           = OCP_USER_MPU | OCP_USER_SDMA,
134 };
136 /* L4 PER -> GPIO3 */
137 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
138         {
139                 .pa_start       = AM33XX_GPIO2_BASE,
140                 .pa_end         = AM33XX_GPIO2_BASE + SZ_4K - 1,
141                 .flags          = ADDR_TYPE_RT
142         },
143         { }
144 };
146 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
147         .master         = &am33xx_l4per_hwmod,
148         .slave          = &am33xx_gpio2_hwmod,
149         .clk            = "l4ls_fck",
150         .addr           = am33xx_gpio2_addrs,
151         .user           = OCP_USER_MPU | OCP_USER_SDMA,
152 };
154 /* L4 PER -> GPIO4 */
155 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
156         {
157                 .pa_start       = AM33XX_GPIO3_BASE,
158                 .pa_end         = AM33XX_GPIO3_BASE + SZ_4K - 1,
159                 .flags          = ADDR_TYPE_RT
160         },
161         { }
162 };
164 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
165         .master         = &am33xx_l4per_hwmod,
166         .slave          = &am33xx_gpio3_hwmod,
167         .clk            = "l4ls_fck",
168         .addr           = am33xx_gpio3_addrs,
169         .user           = OCP_USER_MPU | OCP_USER_SDMA,
170 };
172 /* Master interfaces on the L4_PER interconnect */
173 static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = {
174         &am33xx_l4_per__gpio1,
175         &am33xx_l4_per__gpio2,
176         &am33xx_l4_per__gpio3,
177 };
178 /* Slave interfaces on the L4_PER interconnect */
179 static struct omap_hwmod_ocp_if *am33xx_l4_per_slaves[] = {
180         &am33xx_l3_slow__l4_per,
181 };
183 static struct omap_hwmod am33xx_l4per_hwmod = {
184         .name           = "l4_per",
185         .class          = &l4_hwmod_class,
186         .clkdm_name     = "l4ls_clkdm",
187         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
188         .masters        = am33xx_l4_per_masters,
189         .masters_cnt    = ARRAY_SIZE(am33xx_l4_per_masters),
190         .slaves         = am33xx_l4_per_slaves,
191         .slaves_cnt     = ARRAY_SIZE(am33xx_l4_per_slaves),
192 };
194 /* L4 WKUP -> I2C1 */
195 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
196         {
197                 .pa_start       = AM33XX_I2C0_BASE,
198                 .pa_end         = AM33XX_I2C0_BASE + SZ_4K - 1,
199                 .flags          = ADDR_TYPE_RT
200         },
201         { }
202 };
204 static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = {
205         .master         = &am33xx_l4wkup_hwmod,
206         .slave          = &am33xx_i2c1_hwmod,
207         .addr           = am33xx_i2c1_addr_space,
208         .user           = OCP_USER_MPU,
209 };
211 /* L4 WKUP -> GPIO1 */
212 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
213         {
214                 .pa_start       = AM33XX_GPIO0_BASE,
215                 .pa_end         = AM33XX_GPIO0_BASE + SZ_4K - 1,
216                 .flags          = ADDR_TYPE_RT
217         },
218         { }
219 };
221 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
222         .master         = &am33xx_l4wkup_hwmod,
223         .slave          = &am33xx_gpio0_hwmod,
224         .clk            = "l4ls_fck",
225         .addr           = am33xx_gpio0_addrs,
226         .user           = OCP_USER_MPU | OCP_USER_SDMA,
227 };
229 /* Master interfaces on the L4_WKUP interconnect */
230 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = {
231         &am33xx_l4_wkup__gpio0,
232 };
233 /* Slave interfaces on the L4_WKUP interconnect */
234 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_slaves[] = {
235         &am33xx_l3_slow__l4_wkup,
236 };
238 static struct omap_hwmod am33xx_l4wkup_hwmod = {
239         .name           = "l4_wkup",
240         .class          = &l4_hwmod_class,
241         .clkdm_name     = "l4_wkup_clkdm",
242         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
243         .masters        = am33xx_l4_wkup_masters,
244         .masters_cnt    = ARRAY_SIZE(am33xx_l4_wkup_masters),
245         .slaves         = am33xx_l4_wkup_slaves,
246         .slaves_cnt     = ARRAY_SIZE(am33xx_l4_wkup_slaves),
247 };
249 /* 'adc_tsc' class */
250 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
251         .name           = "adc_tsc",
252 };
254 /* adc_tsc */
255 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
256         { .irq = AM33XX_IRQ_TSC },
257         { .irq = -1 }
258 };
260 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
261         .name           = "adc_tsc",
262         .class          = &am33xx_adc_tsc_hwmod_class,
263         .mpu_irqs       = am33xx_adc_tsc_irqs,
264         .main_clk       = "adc_tsc_fck",
265         .clkdm_name     = "l4_wkup_clkdm",
266         .prcm           = {
267                 .omap4  = {
268                         .clkctrl_offs   = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
269                         .modulemode     = MODULEMODE_SWCTRL,
270                 },
271         },
272 };
274 /* 'aes' class */
275 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
276         .name           = "aes",
277 };
279 /* aes0 */
280 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
281         { .irq = AM33XX_IRQ_AESEIP36t0_S },
282         { .irq = -1 }
283 };
285 static struct omap_hwmod am33xx_aes0_hwmod = {
286         .name           = "aes0",
287         .class          = &am33xx_aes_hwmod_class,
288         .mpu_irqs       = am33xx_aes0_irqs,
289         .main_clk       = "aes0_fck",
290         .clkdm_name     = "l3_clkdm",
291         .prcm           = {
292                 .omap4  = {
293                         .clkctrl_offs   = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
294                         .modulemode     = MODULEMODE_SWCTRL,
295                 },
296         },
297 };
299 /* 'cefuse' class */
300 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
301         .name           = "cefuse",
302 };
304 /* cefuse */
305 static struct omap_hwmod am33xx_cefuse_hwmod = {
306         .name           = "cefuse",
307         .class          = &am33xx_cefuse_hwmod_class,
308         .main_clk       = "cefuse_fck",
309         .clkdm_name     = "l4_cefuse_clkdm",
310         .prcm           = {
311                 .omap4  = {
312                         .clkctrl_offs   = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
313                         .modulemode     = MODULEMODE_SWCTRL,
314                 },
315         },
316 };
318 /* 'clkdiv32k' class */
319 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
320         .name           = "clkdiv32k",
321 };
323 /* clkdiv32k */
324 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
325         .name           = "clkdiv32k",
326         .class          = &am33xx_clkdiv32k_hwmod_class,
327         .main_clk       = "clkdiv32k_fck",
328         .clkdm_name     = "clk_24mhz_clkdm",
329         .prcm           = {
330                 .omap4  = {
331                         .clkctrl_offs   = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
332                         .modulemode     = MODULEMODE_SWCTRL,
333                 },
334         },
335         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
336 };
338 /* 'control' class */
339 static struct omap_hwmod_class am33xx_control_hwmod_class = {
340         .name           = "control",
341 };
343 /* control */
344 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
345         { .irq = AM33XX_IRQ_CONTROL_PLATFORM },
346         { .irq = -1 }
347 };
349 static struct omap_hwmod am33xx_control_hwmod = {
350         .name           = "control",
351         .class          = &am33xx_control_hwmod_class,
352         .mpu_irqs       = am33xx_control_irqs,
353         .main_clk       = "control_fck",
354         .clkdm_name     = "l4_wkup_clkdm",
355         .prcm           = {
356                 .omap4  = {
357                         .clkctrl_offs   = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
358                         .modulemode     = MODULEMODE_SWCTRL,
359                 },
360         },
361         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
362 };
364 /* 'cpgmac0' class */
365 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
366         .name           = "cpgmac0",
367 };
369 /* cpgmac0 */
370 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
371         .name           = "cpgmac0",
372         .class          = &am33xx_cpgmac0_hwmod_class,
373         .main_clk       = "cpgmac0_fck",
374         .clkdm_name     = "cpsw_125mhz_clkdm",
375         .prcm           = {
376                 .omap4  = {
377                         .clkctrl_offs   = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
378                         .modulemode     = MODULEMODE_SWCTRL,
379                 },
380         },
381 };
383 /* 'dcan' class */
384 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
385         .name           = "dcan",
386 };
388 /* dcan0 */
389 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
390         { .irq = AM33XX_IRQ_DCAN0_0 },
391         { .irq = -1 }
392 };
394 static struct omap_hwmod am33xx_dcan0_hwmod = {
395         .name           = "dcan0",
396         .class          = &am33xx_dcan_hwmod_class,
397         .mpu_irqs       = am33xx_dcan0_irqs,
398         .main_clk       = "dcan0_fck",
399         .clkdm_name     = "l4ls_clkdm",
400         .prcm           = {
401                 .omap4  = {
402                         .clkctrl_offs   = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
403                         .modulemode     = MODULEMODE_SWCTRL,
404                 },
405         },
406 };
408 /* dcan1 */
409 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
410         { .irq = AM33XX_IRQ_DCAN1_0 },
411         { .irq = -1 }
412 };
413 static struct omap_hwmod am33xx_dcan1_hwmod = {
414         .name           = "dcan1",
415         .class          = &am33xx_dcan_hwmod_class,
416         .mpu_irqs       = am33xx_dcan1_irqs,
417         .main_clk       = "dcan1_fck",
418         .clkdm_name     = "l4ls_clkdm",
419         .prcm           = {
420                 .omap4  = {
421                         .clkctrl_offs   = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
422                         .modulemode     = MODULEMODE_SWCTRL,
423                 },
424         },
425 };
427 /* 'debugss' class */
428 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
429         .name           = "debugss",
430 };
432 /* debugss */
433 static struct omap_hwmod am33xx_debugss_hwmod = {
434         .name           = "debugss",
435         .class          = &am33xx_debugss_hwmod_class,
436         .main_clk       = "debugss_fck",
437         .clkdm_name     = "l3_aon_clkdm",
438         .prcm           = {
439                 .omap4  = {
440                         .clkctrl_offs   = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
441                         .modulemode     = MODULEMODE_SWCTRL,
442                 },
443         },
444 };
446 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
447         .rev_offs       = 0x0000,
448         .sysc_offs      = 0x0010,
449         .syss_offs      = 0x0014,
450         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
451                                 SYSC_HAS_SOFTRESET |
452                                 SYSS_HAS_RESET_STATUS),
453         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
454         .sysc_fields    = &omap_hwmod_sysc_type1,
455 };
456 /* 'elm' class */
457 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
458         .name           = "elm",
459         .sysc           = &am33xx_elm_sysc,
460 };
462 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
463         { .irq = AM33XX_IRQ_ELM },
464         { .irq = -1 }
465 };
467 struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
468         {
469                 .pa_start       = AM33XX_ELM_BASE,
470                 .pa_end         = AM33XX_ELM_BASE + SZ_8K - 1,
471                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
472         },
473         { }
474 };
476 struct omap_hwmod_ocp_if am33xx_l4_core__elm = {
477         .master         = &am33xx_l4per_hwmod,
478         .slave          = &am33xx_elm_hwmod,
479         .addr           = am33xx_elm_addr_space,
480         .user           = OCP_USER_MPU,
481 };
483 static struct omap_hwmod_ocp_if *am33xx_elm_slaves[] = {
484         &am33xx_l4_core__elm,
485 };
487 /* elm */
488 static struct omap_hwmod am33xx_elm_hwmod = {
489         .name           = "elm",
490         .class          = &am33xx_elm_hwmod_class,
491         .mpu_irqs       = am33xx_elm_irqs,
492         .main_clk       = "elm_fck",
493         .clkdm_name     = "l4ls_clkdm",
494         .slaves         = am33xx_elm_slaves,
495         .slaves_cnt     = ARRAY_SIZE(am33xx_elm_slaves),
496         .prcm           = {
497                 .omap4  = {
498                         .clkctrl_offs   = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
499                         .modulemode     = MODULEMODE_SWCTRL,
500                 },
501         },
502 };
504 /* 'emif_fw' class */
505 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
506         .name           = "emif_fw",
507 };
509 /* emif_fw */
510 static struct omap_hwmod am33xx_emif_fw_hwmod = {
511         .name           = "emif_fw",
512         .class          = &am33xx_emif_fw_hwmod_class,
513         .main_clk       = "emif_fw_fck",
514         .clkdm_name     = "l4fw_clkdm",
515         .prcm           = {
516                 .omap4  = {
517                         .clkctrl_offs   = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
518                         .modulemode     = MODULEMODE_SWCTRL,
519                 },
520         },
521         .flags          = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
522 };
524 /* 'epwmss' class */
525 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
526         .name           = "epwmss",
527 };
529 /* epwmss0 */
530 static struct omap_hwmod am33xx_epwmss0_hwmod = {
531         .name           = "epwmss0",
532         .class          = &am33xx_epwmss_hwmod_class,
533         .main_clk       = "epwmss0_fck",
534         .clkdm_name     = "l4ls_clkdm",
535         .prcm           = {
536                 .omap4  = {
537                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
538                         .modulemode     = MODULEMODE_SWCTRL,
539                 },
540         },
541 };
543 /* epwmss1 */
544 static struct omap_hwmod am33xx_epwmss1_hwmod = {
545         .name           = "epwmss1",
546         .class          = &am33xx_epwmss_hwmod_class,
547         .main_clk       = "epwmss1_fck",
548         .clkdm_name     = "l4ls_clkdm",
549         .prcm           = {
550                 .omap4  = {
551                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
552                         .modulemode     = MODULEMODE_SWCTRL,
553                 },
554         },
555 };
557 /* epwmss2 */
558 static struct omap_hwmod am33xx_epwmss2_hwmod = {
559         .name           = "epwmss2",
560         .class          = &am33xx_epwmss_hwmod_class,
561         .main_clk       = "epwmss2_fck",
562         .clkdm_name     = "l4ls_clkdm",
563         .prcm           = {
564                 .omap4  = {
565                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
566                         .modulemode     = MODULEMODE_SWCTRL,
567                 },
568         },
569 };
571 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
572         .rev_offs       = 0x0000,
573         .sysc_offs      = 0x0010,
574         .syss_offs      = 0x0114,
575         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
576                         SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
577                         SYSS_HAS_RESET_STATUS),
578         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
579                         SIDLE_SMART_WKUP),
580         .sysc_fields    = &omap_hwmod_sysc_type1,
581 };
583 /* 'gpio' class */
584 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
585         .name           = "gpio",
586         .sysc           = &am33xx_gpio_sysc,
587         .rev            = 2,
588 };
590 /* gpio dev_attr */
591 static struct omap_gpio_dev_attr gpio_dev_attr = {
592         .bank_width     = 32,
593         .dbck_flag      = true,
594 };
596 /* gpio0 */
597 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
598         { .irq = AM33XX_IRQ_GPIO0_1 },
599         { .irq = -1 }
600 };
602 /* gpio0 slave ports */
603 static struct omap_hwmod_ocp_if *am33xx_gpio0_slaves[] = {
604         &am33xx_l4_wkup__gpio0,
605 };
607 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
608         { .role = "dbclk", .clk = "gpio0_dbclk" },
609 };
611 /* gpio0 */
612 static struct omap_hwmod am33xx_gpio0_hwmod = {
613         .name           = "gpio1",
614         .class          = &am33xx_gpio_hwmod_class,
615         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
616         .mpu_irqs       = am33xx_gpio0_irqs,
617         .main_clk       = "gpio0_fck",
618         .clkdm_name     = "l4_wkup_clkdm",
619         .prcm           = {
620                 .omap4  = {
621                         .clkctrl_offs   = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
622                         .modulemode     = MODULEMODE_SWCTRL,
623                 },
624         },
625         .opt_clks       = gpio0_opt_clks,
626         .opt_clks_cnt   = ARRAY_SIZE(gpio0_opt_clks),
627         .dev_attr       = &gpio_dev_attr,
628         .slaves         = am33xx_gpio0_slaves,
629         .slaves_cnt     = ARRAY_SIZE(am33xx_gpio0_slaves),
630 };
632 /* gpio1 */
633 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
634         { .irq = AM33XX_IRQ_GPIO1_1 },
635         { .irq = -1 }
636 };
638 /* gpio1 slave ports */
639 static struct omap_hwmod_ocp_if *am33xx_gpio1_slaves[] = {
640         &am33xx_l4_per__gpio1,
641 };
643 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
644         { .role = "dbclk", .clk = "gpio1_dbclk" },
645 };
647 static struct omap_hwmod am33xx_gpio1_hwmod = {
648         .name           = "gpio2",
649         .class          = &am33xx_gpio_hwmod_class,
650         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
651         .mpu_irqs       = am33xx_gpio1_irqs,
652         .main_clk       = "gpio1_fck",
653         .clkdm_name     = "l4ls_clkdm",
654         .prcm           = {
655                 .omap4  = {
656                         .clkctrl_offs   = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
657                         .modulemode     = MODULEMODE_SWCTRL,
658                 },
659         },
660         .opt_clks       = gpio1_opt_clks,
661         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
662         .dev_attr       = &gpio_dev_attr,
663         .slaves         = am33xx_gpio1_slaves,
664         .slaves_cnt     = ARRAY_SIZE(am33xx_gpio1_slaves),
665 };
667 /* gpio2 */
668 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
669         { .irq = AM33XX_IRQ_GPIO2_1 },
670         { .irq = -1 }
671 };
673 /* gpio2 slave ports */
674 static struct omap_hwmod_ocp_if *am33xx_gpio2_slaves[] = {
675         &am33xx_l4_per__gpio2,
676 };
678 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
679         { .role = "dbclk", .clk = "gpio2_dbclk" },
680 };
682 /* gpio2 */
683 static struct omap_hwmod am33xx_gpio2_hwmod = {
684         .name           = "gpio3",
685         .class          = &am33xx_gpio_hwmod_class,
686         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
687         .mpu_irqs       = am33xx_gpio2_irqs,
688         .main_clk       = "gpio2_fck",
689         .clkdm_name     = "l4ls_clkdm",
690         .prcm           = {
691                 .omap4  = {
692                         .clkctrl_offs   = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
693                         .modulemode     = MODULEMODE_SWCTRL,
694                 },
695         },
696         .opt_clks       = gpio2_opt_clks,
697         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
698         .dev_attr       = &gpio_dev_attr,
699         .slaves         = am33xx_gpio2_slaves,
700         .slaves_cnt     = ARRAY_SIZE(am33xx_gpio2_slaves),
701 };
703 /* gpio3 */
704 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
705         { .irq = AM33XX_IRQ_GPIO3_1 },
706         { .irq = -1 }
707 };
709 /* gpio3 slave ports */
710 static struct omap_hwmod_ocp_if *am33xx_gpio3_slaves[] = {
711         &am33xx_l4_per__gpio3,
712 };
714 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
715         { .role = "dbclk", .clk = "gpio3_dbclk" },
716 };
718 /* gpio3 */
719 static struct omap_hwmod am33xx_gpio3_hwmod = {
720         .name           = "gpio4",
721         .class          = &am33xx_gpio_hwmod_class,
722         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
723         .mpu_irqs       = am33xx_gpio3_irqs,
724         .main_clk       = "gpio3_fck",
725         .clkdm_name     = "l4ls_clkdm",
726         .prcm           = {
727                 .omap4  = {
728                         .clkctrl_offs   = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
729                         .modulemode     = MODULEMODE_SWCTRL,
730                 },
731         },
732         .opt_clks       = gpio3_opt_clks,
733         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
734         .dev_attr       = &gpio_dev_attr,
735         .slaves         = am33xx_gpio3_slaves,
736         .slaves_cnt     = ARRAY_SIZE(am33xx_gpio3_slaves),
737 };
739 /* 'gpmc' class */
741 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
742         .name           = "gpmc",
743 };
745 /* gpmc */
746 static struct omap_hwmod am33xx_gpmc_hwmod = {
747         .name           = "gpmc",
748         .class          = &am33xx_gpmc_hwmod_class,
749         .main_clk       = "gpmc_fck",
750         .clkdm_name     = "l3s_clkdm",
751         .prcm           = {
752                 .omap4  = {
753                         .clkctrl_offs   = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
754                         .modulemode     = MODULEMODE_SWCTRL,
755                 },
756         },
757 };
759 /* 'i2c' class */
761 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
762         .sysc_offs      = 0x0010,
763         .syss_offs      = 0x0090,
764         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
765                         SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
766                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
767         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
768                         SIDLE_SMART_WKUP),
769         .sysc_fields    = &omap_hwmod_sysc_type1,
770 };
772 static struct omap_i2c_dev_attr i2c_dev_attr = {
773         .flags          = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
774 };
776 static struct omap_hwmod_class i2c_class = {
777         .name           = "i2c",
778         .sysc           = &am33xx_i2c_sysc,
779         .rev            = OMAP_I2C_IP_VERSION_2,
780         .reset          = &omap_i2c_reset,
781 };
783 /* I2C1 */
784 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
785         { .irq = AM33XX_IRQ_MSHSI2COCP0 },
786         { .irq = -1 }
787 };
789 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
790         { .name = "tx", .dma_req = 0, },
791         { .name = "rx", .dma_req = 0, },
792         { .dma_req = -1 }
793 };
795 static struct omap_hwmod_ocp_if *am33xx_i2c1_slaves[] = {
796         &am33xx_l4_wkup_i2c1,
797 };
799 static struct omap_hwmod am33xx_i2c1_hwmod = {
800         .name           = "i2c1",
801         .mpu_irqs       = i2c1_mpu_irqs,
802         .sdma_reqs      = i2c1_edma_reqs,
803         .main_clk       = "i2c1_fck",
804         .clkdm_name     = "l4_wkup_clkdm",
805         .prcm           = {
806                 .omap4  = {
807                         .clkctrl_offs   = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
808                         .modulemode     = MODULEMODE_SWCTRL,
809                 },
810         },
811         .flags          = HWMOD_16BIT_REG,
812         .dev_attr       = &i2c_dev_attr,
813         .slaves         = am33xx_i2c1_slaves,
814         .slaves_cnt     = ARRAY_SIZE(am33xx_i2c1_slaves),
815         .class          = &i2c_class,
816 };
818 /* i2c2 */
819 /* l4 per -> i2c2 */
820 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
821         {
822                 .pa_start       = AM33XX_I2C1_BASE,
823                 .pa_end         = AM33XX_I2C1_BASE + SZ_4K - 1,
824                 .flags          = ADDR_TYPE_RT
825         },
826         { }
827 };
829 static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = {
830         .master         = &am33xx_l4per_hwmod,
831         .slave          = &am33xx_i2c2_hwmod,
832         .addr           = am33xx_i2c2_addr_space,
833         .user           = OCP_USER_MPU,
834 };
836 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
837         { .irq = AM33XX_IRQ_MSHSI2COCP1 },
838         { .irq = -1 }
839 };
841 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
842         { .name = "tx", .dma_req = 0, },
843         { .name = "rx", .dma_req = 0, },
844         { .dma_req = -1 }
845 };
847 static struct omap_hwmod_ocp_if *am33xx_i2c2_slaves[] = {
848         &am335_l4_per_i2c2,
849 };
851 static struct omap_hwmod am33xx_i2c2_hwmod = {
852         .name           = "i2c2",
853         .mpu_irqs       = i2c2_mpu_irqs,
854         .sdma_reqs      = i2c2_edma_reqs,
855         .main_clk       = "i2c2_fck",
856         .clkdm_name     = "l4ls_clkdm",
857         .prcm           = {
858                 .omap4 = {
859                         .clkctrl_offs   = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
860                         .modulemode     = MODULEMODE_SWCTRL,
861                 },
862         },
863         .flags          = HWMOD_16BIT_REG,
864         .dev_attr       = &i2c_dev_attr,
865         .slaves         = am33xx_i2c2_slaves,
866         .slaves_cnt     = ARRAY_SIZE(am33xx_i2c2_slaves),
867         .class          = &i2c_class,
868 };
870 /* 'icss' class */
871 static struct omap_hwmod_class am33xx_icss_hwmod_class = {
872         .name = "icss",
873 };
875 /* icss */
876 static struct omap_hwmod am33xx_icss_hwmod = {
877         .name           = "icss",
878         .class          = &am33xx_icss_hwmod_class,
879         .main_clk       = "icss_fck",
880         .clkdm_name     = "icss_ocp_clkdm",
881         .prcm           = {
882                 .omap4  = {
883                         .clkctrl_offs   = AM33XX_CM_PER_ICSS_CLKCTRL_OFFSET,
884                         .modulemode     = MODULEMODE_SWCTRL,
885                 },
886         },
887 };
889 /* 'ieee5000' class */
890 static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = {
891         .name           = "ieee5000",
892 };
894 /* ieee5000 */
895 static struct omap_hwmod am33xx_ieee5000_hwmod = {
896         .name           = "ieee5000",
897         .class          = &am33xx_ieee5000_hwmod_class,
898         .main_clk       = "ieee5000_fck",
899         .clkdm_name     = "l3s_clkdm",
900         .prcm           = {
901                 .omap4  = {
902                         .clkctrl_offs   = AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET,
903                         .modulemode     = MODULEMODE_SWCTRL,
904                 },
905         },
906 };
909 /* 'l3' class */
910 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
911         .name           = "l3",
912 };
914 /* l4_hs */
915 static struct omap_hwmod am33xx_l4_hs_hwmod = {
916         .name           = "l4_hs",
917         .class          = &am33xx_l3_hwmod_class,
918         .clkdm_name     = "l4hs_clkdm",
919         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
920         .prcm           = {
921                 .omap4  = {
922                         .clkctrl_offs   = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
923                         .modulemode     = MODULEMODE_SWCTRL,
924                 },
925         },
926 };
928 /* l3_instr */
929 static struct omap_hwmod am33xx_l3_instr_hwmod = {
930         .name           = "l3_instr",
931         .class          = &am33xx_l3_hwmod_class,
932         .clkdm_name     = "l3_clkdm",
933         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
934         .prcm           = {
935                 .omap4  = {
936                         .clkctrl_offs   = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
937                         .modulemode     = MODULEMODE_SWCTRL,
938                 },
939         },
940 };
942 /* l3_main */
943 static struct omap_hwmod am33xx_l3_main_hwmod = {
944         .name           = "l3_main",
945         .class          = &am33xx_l3_hwmod_class,
946         .clkdm_name     = "l3_clkdm",
947         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
948         .prcm           = {
949                 .omap4  = {
950                         .clkctrl_offs   = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
951                         .modulemode     = MODULEMODE_SWCTRL,
952                 },
953         },
954 };
956 /* 'l4fw' class */
957 static struct omap_hwmod_class am33xx_l4fw_hwmod_class = {
958         .name           = "l4fw",
959 };
961 /* l4fw */
962 static struct omap_hwmod am33xx_l4fw_hwmod = {
963         .name           = "l4fw",
964         .class          = &am33xx_l4fw_hwmod_class,
965         .clkdm_name     = "l4fw_clkdm",
966         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
967         .prcm           = {
968                 .omap4  = {
969                         .clkctrl_offs   = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
970                         .modulemode     = MODULEMODE_SWCTRL,
971                 },
972         },
973 };
975 /* 'l4ls' class */
976 static struct omap_hwmod_class am33xx_l4ls_hwmod_class = {
977         .name           = "l4ls",
978 };
980 /* l4ls */
981 static struct omap_hwmod am33xx_l4ls_hwmod = {
982         .name           = "l4ls",
983         .class          = &am33xx_l4ls_hwmod_class,
984         .main_clk       = "l4ls_fck",
985         .clkdm_name     = "l4ls_clkdm",
986         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
987         .prcm           = {
988                 .omap4  = {
989                         .clkctrl_offs   = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
990                         .modulemode     = MODULEMODE_SWCTRL,
991                 },
992         },
993 };
995 /* 'lcdc' class */
996 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
997         .name           = "lcdc",
998 };
1000 /* lcdc */
1001 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1002         { .irq = AM33XX_IRQ_LCD },
1003         { .irq = -1 }
1004 };
1006 static struct omap_hwmod am33xx_lcdc_hwmod = {
1007         .name           = "lcdc",
1008         .class          = &am33xx_lcdc_hwmod_class,
1009         .mpu_irqs       = am33xx_lcdc_irqs,
1010         .main_clk       = "lcdc_fck",
1011         .clkdm_name     = "lcdc_clkdm",
1012         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1013         .prcm           = {
1014                 .omap4  = {
1015                         .clkctrl_offs   = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1016                         .modulemode     = MODULEMODE_SWCTRL,
1017                 },
1018         },
1019 };
1021 /* 'mcasp' class */
1022 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1023         .name           = "mcasp",
1024 };
1026 /* mcasp0 */
1027 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1028         { .irq = 80 },
1029         { .irq = -1 }
1030 };
1032 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1033         .name           = "mcasp0",
1034         .class          = &am33xx_mcasp_hwmod_class,
1035         .mpu_irqs       = am33xx_mcasp0_irqs,
1036         .main_clk       = "mcasp0_fck",
1037         .clkdm_name     = "l3s_clkdm",
1038         .prcm           = {
1039                 .omap4  = {
1040                         .clkctrl_offs   = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1041                         .modulemode     = MODULEMODE_SWCTRL,
1042                 },
1043         },
1044 };
1046 /* 'mmc' class */
1048 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1049         .rev_offs       = 0x1fc,
1050         .sysc_offs      = 0x10,
1051         .syss_offs      = 0x14,
1052         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1053                         SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1054                         SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1055         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1056         .sysc_fields    = &omap_hwmod_sysc_type1,
1057 };
1059 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1060         .name           = "mmc",
1061         .sysc           = &am33xx_mmc_sysc,
1062 };
1064 /* mmc0 */
1065 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1066         { .irq = AM33XX_IRQ_MMCHS0 },
1067         { .irq = -1 }
1068 };
1070 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1071         { .name = "tx", .dma_req = AM33XX_DMA_MMCHS0_W, },
1072         { .name = "rx", .dma_req = AM33XX_DMA_MMCHS0_R, },
1073         { .dma_req = -1 }
1074 };
1076 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
1077         {
1078                 .pa_start       = AM33XX_MMC0_BASE,
1079                 .pa_end         = AM33XX_MMC0_BASE + SZ_4K - 1,
1080                 .flags          = ADDR_TYPE_RT
1081         },
1082         { }
1083 };
1085 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc0 = {
1086         .master         = &am33xx_l4ls_hwmod,
1087         .slave          = &am33xx_mmc0_hwmod,
1088         .clk            = "mmc0_ick",
1089         .addr           = am33xx_mmc0_addr_space,
1090         .user           = OCP_USER_MPU,
1091 };
1093 static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = {
1094         &am33xx_l4ls__mmc0,
1095 };
1097 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1098         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1099 };
1101 static struct omap_hwmod am33xx_mmc0_hwmod = {
1102         .name           = "mmc1",
1103         .class          = &am33xx_mmc_hwmod_class,
1104         .mpu_irqs       = am33xx_mmc0_irqs,
1105         .sdma_reqs      = am33xx_mmc0_edma_reqs,
1106         .main_clk       = "mmc0_fck",
1107         .clkdm_name     = "l4ls_clkdm",
1108         .prcm           = {
1109                 .omap4  = {
1110                         .clkctrl_offs   = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1111                         .modulemode     = MODULEMODE_SWCTRL,
1112                 },
1113         },
1114         .dev_attr       = &am33xx_mmc0_dev_attr,
1115         .slaves         = am33xx_mmc0_slaves,
1116         .slaves_cnt     = ARRAY_SIZE(am33xx_mmc0_slaves),
1117 };
1119 /* mmc1 */
1120 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1121         { .irq = AM33XX_IRQ_MMCHS1 },
1122         { .irq = -1 }
1123 };
1125 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1126         { .name = "tx", .dma_req = AM33XX_DMA_MMCHS1_W, },
1127         { .name = "rx", .dma_req = AM33XX_DMA_MMCHS1_R, },
1128         { .dma_req = -1 }
1129 };
1131 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
1132         {
1133                 .pa_start       = AM33XX_MMC1_BASE,
1134                 .pa_end         = AM33XX_MMC1_BASE + SZ_4K - 1,
1135                 .flags          = ADDR_TYPE_RT
1136         },
1137         { }
1138 };
1140 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc1 = {
1141         .master         = &am33xx_l4ls_hwmod,
1142         .slave          = &am33xx_mmc1_hwmod,
1143         .clk            = "mmc1_ick",
1144         .addr           = am33xx_mmc1_addr_space,
1145         .user           = OCP_USER_MPU,
1146 };
1148 static struct omap_hwmod_ocp_if *am33xx_mmc1_slaves[] = {
1149         &am33xx_l4ls__mmc1,
1150 };
1152 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1153         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1154 };
1156 static struct omap_hwmod am33xx_mmc1_hwmod = {
1157         .name           = "mmc2",
1158         .class          = &am33xx_mmc_hwmod_class,
1159         .mpu_irqs       = am33xx_mmc1_irqs,
1160         .sdma_reqs      = am33xx_mmc1_edma_reqs,
1161         .main_clk       = "mmc1_fck",
1162         .clkdm_name     = "l4ls_clkdm",
1163         .prcm           = {
1164                 .omap4  = {
1165                         .clkctrl_offs   = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1166                         .modulemode     = MODULEMODE_SWCTRL,
1167                 },
1168         },
1169         .dev_attr       = &am33xx_mmc1_dev_attr,
1170         .slaves         = am33xx_mmc1_slaves,
1171         .slaves_cnt     = ARRAY_SIZE(am33xx_mmc1_slaves),
1172 };
1174 /* mmc2 */
1175 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1176         { .irq = AM33XX_IRQ_MMCHS2 },
1177         { .irq = -1 }
1178 };
1180 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1181         { .name = "tx", .dma_req = AM33XX_DMA_MMCHS2_W, },
1182         { .name = "rx", .dma_req = AM33XX_DMA_MMCHS2_R, },
1183         { .dma_req = -1 }
1184 };
1186 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1187         { .name = "tx", .dma_req = AM33XX_DMA_MMCHS2_W, },
1188         { .name = "rx", .dma_req = AM33XX_DMA_MMCHS2_R, },
1189         { .dma_req = -1 }
1190 };
1192 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
1193         {
1194                 .pa_start       = AM33XX_MMC2_BASE,
1195                 .pa_end         = AM33XX_MMC2_BASE + SZ_64K - 1,
1196                 .flags          = ADDR_TYPE_RT
1197         },
1198         { }
1199 };
1201 static struct omap_hwmod_ocp_if am33xx_l3_main__mmc2 = {
1202         .master         = &am33xx_l3_main_hwmod,
1203         .slave          = &am33xx_mmc2_hwmod,
1204         .clk            = "mmc2_ick",
1205         .addr           = am33xx_mmc2_addr_space,
1206         .user           = OCP_USER_MPU,
1207 };
1209 static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = {
1210         &am33xx_l3_main__mmc2,
1211 };
1213 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1214         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1215 };
1216 static struct omap_hwmod am33xx_mmc2_hwmod = {
1217         .name           = "mmc3",
1218         .class          = &am33xx_mmc_hwmod_class,
1219         .mpu_irqs       = am33xx_mmc2_irqs,
1220         .sdma_reqs      = am33xx_mmc2_edma_reqs,
1221         .main_clk       = "mmc2_fck",
1222         .clkdm_name     = "l3s_clkdm",
1223         .prcm           = {
1224                 .omap4  = {
1225                         .clkctrl_offs   = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1226                         .modulemode     = MODULEMODE_SWCTRL,
1227                 },
1228         },
1229         .dev_attr       = &am33xx_mmc2_dev_attr,
1230         .slaves         = am33xx_mmc2_slaves,
1231         .slaves_cnt     = ARRAY_SIZE(am33xx_mmc2_slaves),
1232 };
1234 /* Master interfaces on the MPU interconnect */
1235 static struct omap_hwmod_ocp_if *am33xx_l3_mpu_masters[] = {
1236         &am33xx_mpu__l3_slow,
1237 };
1239 /* mpu */
1240 static struct omap_hwmod am33xx_mpu_hwmod = {
1241         .name           = "mpu",
1242         .class          = &mpu_hwmod_class,
1243         .masters        = am33xx_l3_mpu_masters,
1244         .masters_cnt    = ARRAY_SIZE(am33xx_l3_mpu_masters),
1245         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1246         .main_clk       = "mpu_fck",
1247         .clkdm_name     = "mpu_clkdm",
1248         .prcm           = {
1249                 .omap4  = {
1250                         .clkctrl_offs   = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1251                         .modulemode     = MODULEMODE_SWCTRL,
1252                 },
1253         },
1254 };
1256 /* 'ocmcram' class */
1257 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
1258         .name = "ocmcram",
1259 };
1261 /* ocmcram */
1262 static struct omap_hwmod am33xx_ocmcram_hwmod = {
1263         .name           = "ocmcram",
1264         .class          = &am33xx_ocmcram_hwmod_class,
1265         .main_clk       = "ocmcram_fck",
1266         .clkdm_name     = "l3_clkdm",
1267         .prcm           = {
1268                 .omap4  = {
1269                         .clkctrl_offs   = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
1270                         .modulemode     = MODULEMODE_SWCTRL,
1271                 },
1272         },
1273 };
1275 /* 'ocpwp' class */
1276 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
1277         .name           = "ocpwp",
1278 };
1280 /* ocpwp */
1281 static struct omap_hwmod am33xx_ocpwp_hwmod = {
1282         .name           = "ocpwp",
1283         .class          = &am33xx_ocpwp_hwmod_class,
1284         .main_clk       = "ocpwp_fck",
1285         .clkdm_name     = "l4ls_clkdm",
1286         .prcm           = {
1287                 .omap4  = {
1288                         .clkctrl_offs   = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
1289                         .modulemode     = MODULEMODE_SWCTRL,
1290                 },
1291         },
1292 };
1294 /* 'rtc' class */
1295 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1296         .name           = "rtc",
1297 };
1299 /* rtc */
1300 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1301         { .irq = AM33XX_IRQ_RTC_TIMER },
1302         { .irq = -1 }
1303 };
1305 static struct omap_hwmod am33xx_rtc_hwmod = {
1306         .name           = "rtc",
1307         .class          = &am33xx_rtc_hwmod_class,
1308         .mpu_irqs       = am33xx_rtc_irqs,
1309         .main_clk       = "rtc_fck",
1310         .clkdm_name     = "l4_rtc_clkdm",
1311         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1312         .prcm           = {
1313                 .omap4  = {
1314                         .clkctrl_offs   = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1315                         .modulemode     = MODULEMODE_SWCTRL,
1316                 },
1317         },
1318 };
1320 /* 'sha0' class */
1321 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
1322         .name           = "sha0",
1323 };
1325 /* sha0 */
1326 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
1327         { .irq = AM33XX_IRQ_SHAEIP57t0_S },
1328         { .irq = -1 }
1329 };
1331 static struct omap_hwmod am33xx_sha0_hwmod = {
1332         .name           = "sha0",
1333         .class          = &am33xx_sha0_hwmod_class,
1334         .mpu_irqs       = am33xx_sha0_irqs,
1335         .main_clk       = "sha0_fck",
1336         .clkdm_name     = "l3_clkdm",
1337         .prcm           = {
1338                 .omap4  = {
1339                         .clkctrl_offs   = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
1340                         .modulemode     = MODULEMODE_SWCTRL,
1341                 },
1342         },
1343 };
1345 /* 'smartreflex' class */
1346 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
1347         .name           = "smartreflex",
1348 };
1350 /* smartreflex0 */
1351 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
1352         { .irq = AM33XX_IRQ_SMARTREFLEX0 },
1353         { .irq = -1 }
1354 };
1356 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
1357         .name           = "smartreflex0",
1358         .class          = &am33xx_smartreflex_hwmod_class,
1359         .mpu_irqs       = am33xx_smartreflex0_irqs,
1360         .main_clk       = "smartreflex0_fck",
1361         .clkdm_name     = "l4_wkup_clkdm",
1362         .prcm           = {
1363                 .omap4  = {
1364                         .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
1365                         .modulemode     = MODULEMODE_SWCTRL,
1366                 },
1367         },
1368 };
1370 /* smartreflex1 */
1371 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
1372         { .irq = AM33XX_IRQ_SMARTREFLEX1 },
1373         { .irq = -1 }
1374 };
1376 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
1377         .name           = "smartreflex1",
1378         .class          = &am33xx_smartreflex_hwmod_class,
1379         .mpu_irqs       = am33xx_smartreflex1_irqs,
1380         .main_clk       = "smartreflex1_fck",
1381         .clkdm_name     = "l4_wkup_clkdm",
1382         .prcm           = {
1383                 .omap4  = {
1384                         .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
1385                         .modulemode     = MODULEMODE_SWCTRL,
1386                 },
1387         },
1388 };
1390 /* 'spi' class */
1392 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1393         .rev_offs       = 0x0000,
1394         .sysc_offs      = 0x0110,
1395         .syss_offs      = 0x0114,
1396         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1397                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1398                         SYSS_HAS_RESET_STATUS),
1399         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1400         .sysc_fields    = &omap_hwmod_sysc_type1,
1401 };
1403 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1404         .name           = "mcspi",
1405         .sysc           = &am33xx_mcspi_sysc,
1406         .rev            = OMAP4_MCSPI_REV,
1407 };
1409 /* spi0 */
1410 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1411         { .irq = AM33XX_IRQ_MCSPIOCP0 },
1412         { .irq = -1 }
1413 };
1415 struct omap_hwmod_dma_info am33xx_mcspi0_sdma_reqs[] = {
1416         { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0R },
1417         { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0W },
1418         { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1R },
1419         { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1W },
1420         { .dma_req = -1 }
1421 };
1423 struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
1424         {
1425                 .pa_start       = AM33XX_SPI0_BASE,
1426                 .pa_end         = AM33XX_SPI0_BASE + SZ_1K - 1,
1427                 .flags          = ADDR_TYPE_RT
1428         },
1429         { }
1430 };
1432 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = {
1433         .master         = &am33xx_l4per_hwmod,
1434         .slave          = &am33xx_spi0_hwmod,
1435         .clk            = "spi0_ick",
1436         .addr           = am33xx_mcspi0_addr_space,
1437         .user           = OCP_USER_MPU,
1438 };
1440 static struct omap_hwmod_ocp_if *am33xx_mcspi0_slaves[] = {
1441         &am33xx_l4_core__mcspi0,
1442 };
1444 struct omap2_mcspi_dev_attr mcspi_attrib = {
1445         .num_chipselect = 2,
1446 };
1447 static struct omap_hwmod am33xx_spi0_hwmod = {
1448         .name           = "spi0",
1449         .class          = &am33xx_spi_hwmod_class,
1450         .mpu_irqs       = am33xx_spi0_irqs,
1451         .sdma_reqs      = am33xx_mcspi0_sdma_reqs,
1452         .main_clk       = "spi0_fck",
1453         .clkdm_name     = "l4ls_clkdm",
1454         .prcm           = {
1455                 .omap4  = {
1456                         .clkctrl_offs   = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1457                         .modulemode     = MODULEMODE_SWCTRL,
1458                 },
1459         },
1460         .dev_attr       = &mcspi_attrib,
1461         .slaves         = am33xx_mcspi0_slaves,
1462         .slaves_cnt     = ARRAY_SIZE(am33xx_mcspi0_slaves),
1463 };
1465 /* spi1 */
1466 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1467         { .irq = AM33XX_IRQ_SPI1 },
1468         { .irq = -1 }
1469 };
1471 struct omap_hwmod_dma_info am33xx_mcspi1_sdma_reqs[] = {
1472         { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0R },
1473         { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0W },
1474         { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1R },
1475         { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1W },
1476         { .dma_req = -1 }
1477 };
1479 struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
1480         {
1481                 .pa_start       = AM33XX_SPI1_BASE,
1482                 .pa_end         = AM33XX_SPI1_BASE + SZ_1K - 1,
1483                 .flags          = ADDR_TYPE_RT
1484         },
1485         { }
1486 };
1488 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = {
1489         .master         = &am33xx_l4per_hwmod,
1490         .slave          = &am33xx_spi1_hwmod,
1491         .clk            = "spi1_ick",
1492         .addr           = am33xx_mcspi1_addr_space,
1493         .user           = OCP_USER_MPU,
1494 };
1496 static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = {
1497         &am33xx_l4_core__mcspi1,
1498 };
1499 static struct omap_hwmod am33xx_spi1_hwmod = {
1500         .name           = "spi1",
1501         .class          = &am33xx_spi_hwmod_class,
1502         .mpu_irqs       = am33xx_spi1_irqs,
1503         .sdma_reqs      = am33xx_mcspi1_sdma_reqs,
1504         .main_clk       = "spi1_fck",
1505         .clkdm_name     = "l4ls_clkdm",
1506         .prcm           = {
1507                 .omap4  = {
1508                         .clkctrl_offs   = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1509                         .modulemode     = MODULEMODE_SWCTRL,
1510                 },
1511         },
1512         .dev_attr       = &mcspi_attrib,
1513         .slaves         = am33xx_mcspi1_slaves,
1514         .slaves_cnt     = ARRAY_SIZE(am33xx_mcspi1_slaves),
1515 };
1517 /* 'spinlock' class */
1518 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1519         .name           = "spinlock",
1520 };
1522 /* spinlock */
1523 static struct omap_hwmod am33xx_spinlock_hwmod = {
1524         .name           = "spinlock",
1525         .class          = &am33xx_spinlock_hwmod_class,
1526         .main_clk       = "spinlock_fck",
1527         .clkdm_name     = "l4ls_clkdm",
1528         .prcm           = {
1529                 .omap4  = {
1530                         .clkctrl_offs   = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1531                         .modulemode     = MODULEMODE_SWCTRL,
1532                 },
1533         },
1534 };
1536 /* 'timer 0 & 2-7' class */
1537 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1538         .rev_offs       = 0x0000,
1539         .sysc_offs      = 0x0010,
1540         .syss_offs      = 0x0014,
1541         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1542         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1543                         SIDLE_SMART_WKUP),
1544         .sysc_fields    = &omap_hwmod_sysc_type2,
1545 };
1547 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1548         .name           = "timer",
1549         .sysc           = &am33xx_timer_sysc,
1550 };
1552 /* timer0 */
1553 /* l4 wkup -> timer0 interface */
1554 static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = {
1555         {
1556                 .pa_start       = AM33XX_TIMER0_BASE,
1557                 .pa_end         = AM33XX_TIMER0_BASE + SZ_1K - 1,
1558                 .flags          = ADDR_TYPE_RT
1559         },
1560         { }
1561 };
1563 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = {
1564         .master         = &am33xx_l4wkup_hwmod,
1565         .slave          = &am33xx_timer0_hwmod,
1566         .clk            = "timer0_ick",
1567         .addr           = am33xx_timer0_addr_space,
1568         .user           = OCP_USER_MPU,
1569 };
1571 static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = {
1572         &am33xx_l4wkup__timer0,
1573 };
1575 static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = {
1576         { .irq = AM33XX_IRQ_DMTIMER0 },
1577         { .irq = -1 }
1578 };
1580 static struct omap_hwmod am33xx_timer0_hwmod = {
1581         .name           = "timer0",
1582         .class          = &am33xx_timer_hwmod_class,
1583         .mpu_irqs       = am33xx_timer0_irqs,
1584         .main_clk       = "timer0_fck",
1585         .clkdm_name     = "l4_wkup_clkdm",
1586         .prcm           = {
1587                 .omap4  = {
1588                         .clkctrl_offs   = AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET,
1589                         .modulemode     = MODULEMODE_SWCTRL,
1590                 },
1591         },
1592         .slaves         = am33xx_timer0_slaves,
1593         .slaves_cnt     = ARRAY_SIZE(am33xx_timer0_slaves),
1594 };
1596 /* timer1 1ms */
1597 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1598         .rev_offs       = 0x0000,
1599         .sysc_offs      = 0x0010,
1600         .syss_offs      = 0x0014,
1601         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1602                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1603                         SYSS_HAS_RESET_STATUS),
1604         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1605         .sysc_fields    = &omap_hwmod_sysc_type1,
1606 };
1608 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1609         .name           = "timer",
1610         .sysc           = &am33xx_timer1ms_sysc,
1611 };
1613 /* l4 wkup -> timer1 interface */
1614 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
1615         {
1616                 .pa_start       = AM33XX_TIMER1_BASE,
1617                 .pa_end         = AM33XX_TIMER1_BASE + SZ_1K - 1,
1618                 .flags          = ADDR_TYPE_RT
1619         },
1620         { }
1621 };
1623 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = {
1624         .master         = &am33xx_l4wkup_hwmod,
1625         .slave          = &am33xx_timer1_hwmod,
1626         .clk            = "timer1_ick",
1627         .addr           = am33xx_timer1_addr_space,
1628         .user           = OCP_USER_MPU,
1629 };
1631 static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = {
1632         &am33xx_l4wkup__timer1,
1633 };
1635 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
1636         { .irq = AM33XX_IRQ_DMTIMER1 },
1637         { .irq = -1 }
1638 };
1640 static struct omap_hwmod am33xx_timer1_hwmod = {
1641         .name           = "timer1",
1642         .class          = &am33xx_timer1ms_hwmod_class,
1643         .mpu_irqs       = am33xx_timer1_irqs,
1644         .main_clk       = "timer1_fck",
1645         .clkdm_name     = "l4_wkup_clkdm",
1646         .prcm           = {
1647                 .omap4  = {
1648                         .clkctrl_offs   = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1649                         .modulemode     = MODULEMODE_SWCTRL,
1650                 },
1651         },
1652         .slaves         = am33xx_timer1_slaves,
1653         .slaves_cnt     = ARRAY_SIZE(am33xx_timer1_slaves),
1654 };
1656 /* timer2 */
1657 /* l4 per -> timer2 interface */
1658 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
1659         {
1660                 .pa_start       = AM33XX_TIMER2_BASE,
1661                 .pa_end         = AM33XX_TIMER2_BASE + SZ_1K - 1,
1662                 .flags          = ADDR_TYPE_RT
1663         },
1664         { }
1665 };
1667 static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = {
1668         .master         = &am33xx_l4per_hwmod,
1669         .slave          = &am33xx_timer2_hwmod,
1670         .clk            = "timer2_ick",
1671         .addr           = am33xx_timer2_addr_space,
1672         .user           = OCP_USER_MPU,
1673 };
1675 static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = {
1676         &am33xx_l4per__timer2,
1677 };
1679 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
1680         { .irq = AM33XX_IRQ_DMTIMER2 },
1681         { .irq = -1 }
1682 };
1684 static struct omap_hwmod am33xx_timer2_hwmod = {
1685         .name           = "timer2",
1686         .class          = &am33xx_timer_hwmod_class,
1687         .mpu_irqs       = am33xx_timer2_irqs,
1688         .main_clk       = "timer2_fck",
1689         .prcm           = {
1690                 .omap4  = {
1691                         .clkctrl_offs   = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1692                         .modulemode     = MODULEMODE_SWCTRL,
1693                 },
1694         },
1695         .slaves         = am33xx_timer2_slaves,
1696         .slaves_cnt     = ARRAY_SIZE(am33xx_timer2_slaves),
1697         .clkdm_name     = "l4ls_clkdm",
1698 };
1700 /* timer3 */
1701 /* l4 per -> timer3 interface */
1702 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
1703         {
1704                 .pa_start       = AM33XX_TIMER3_BASE,
1705                 .pa_end         = AM33XX_TIMER3_BASE + SZ_1K - 1,
1706                 .flags          = ADDR_TYPE_RT
1707         },
1708         { }
1709 };
1711 static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = {
1712         .master         = &am33xx_l4per_hwmod,
1713         .slave          = &am33xx_timer3_hwmod,
1714         .clk            = "timer3_ick",
1715         .addr           = am33xx_timer3_addr_space,
1716         .user           = OCP_USER_MPU,
1717 };
1719 static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = {
1720         &am33xx_l4per__timer3,
1721 };
1723 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
1724         { .irq = AM33XX_IRQ_DMTIMER3 },
1725         { .irq = -1 }
1726 };
1728 static struct omap_hwmod am33xx_timer3_hwmod = {
1729         .name           = "timer3",
1730         .class          = &am33xx_timer_hwmod_class,
1731         .mpu_irqs       = am33xx_timer3_irqs,
1732         .main_clk       = "timer3_fck",
1733         .clkdm_name     = "l4ls_clkdm",
1734         .prcm           = {
1735                 .omap4  = {
1736                         .clkctrl_offs   = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1737                         .modulemode     = MODULEMODE_SWCTRL,
1738                 },
1739         },
1740         .slaves         = am33xx_timer3_slaves,
1741         .slaves_cnt     = ARRAY_SIZE(am33xx_timer3_slaves),
1742 };
1744 /* timer4 */
1745 /* l4 per -> timer4 interface */
1746 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
1747         {
1748                 .pa_start       = AM33XX_TIMER4_BASE,
1749                 .pa_end         = AM33XX_TIMER4_BASE + SZ_1K - 1,
1750                 .flags          = ADDR_TYPE_RT
1751         },
1752         { }
1753 };
1755 static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = {
1756         .master         = &am33xx_l4per_hwmod,
1757         .slave          = &am33xx_timer4_hwmod,
1758         .clk            = "timer4_ick",
1759         .addr           = am33xx_timer4_addr_space,
1760         .user           = OCP_USER_MPU,
1761 };
1763 static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = {
1764         &am33xx_l4per__timer4,
1765 };
1767 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
1768         { .irq = AM33XX_IRQ_DMTIMER4 },
1769         { .irq = -1 }
1770 };
1772 static struct omap_hwmod am33xx_timer4_hwmod = {
1773         .name           = "timer4",
1774         .class          = &am33xx_timer_hwmod_class,
1775         .mpu_irqs       = am33xx_timer4_irqs,
1776         .main_clk       = "timer4_fck",
1777         .prcm           = {
1778                 .omap4  = {
1779                         .clkctrl_offs   = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1780                         .modulemode     = MODULEMODE_SWCTRL,
1781                 },
1782         },
1783         .slaves         = am33xx_timer4_slaves,
1784         .slaves_cnt     = ARRAY_SIZE(am33xx_timer4_slaves),
1785         .clkdm_name     = "l4ls_clkdm",
1786 };
1789 /* timer5 */
1790 /* l4 per -> timer5 interface */
1791 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
1792         {
1793                 .pa_start       = AM33XX_TIMER5_BASE,
1794                 .pa_end         = AM33XX_TIMER5_BASE + SZ_1K - 1,
1795                 .flags          = ADDR_TYPE_RT
1796         },
1797         { }
1798 };
1800 static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = {
1801         .master         = &am33xx_l4per_hwmod,
1802         .slave          = &am33xx_timer5_hwmod,
1803         .clk            = "timer5_ick",
1804         .addr           = am33xx_timer5_addr_space,
1805         .user           = OCP_USER_MPU,
1806 };
1808 static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = {
1809         &am33xx_l4per__timer5,
1810 };
1812 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
1813         { .irq = AM33XX_IRQ_DMTIMER5 },
1814         { .irq = -1 }
1815 };
1817 static struct omap_hwmod am33xx_timer5_hwmod = {
1818         .name           = "timer5",
1819         .class          = &am33xx_timer_hwmod_class,
1820         .mpu_irqs       = am33xx_timer5_irqs,
1821         .main_clk       = "timer5_fck",
1822         .prcm           = {
1823                 .omap4  = {
1824                         .clkctrl_offs   = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1825                         .modulemode     = MODULEMODE_SWCTRL,
1826                 },
1827         },
1828         .slaves         = am33xx_timer5_slaves,
1829         .slaves_cnt     = ARRAY_SIZE(am33xx_timer5_slaves),
1830         .clkdm_name     = "l4ls_clkdm",
1831 };
1833 /* timer6 */
1834 /* l4 per -> timer6 interface */
1835 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
1836         {
1837                 .pa_start       = AM33XX_TIMER6_BASE,
1838                 .pa_end         = AM33XX_TIMER6_BASE + SZ_1K - 1,
1839                 .flags          = ADDR_TYPE_RT
1840         },
1841         { }
1842 };
1844 static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = {
1845         .master         = &am33xx_l4per_hwmod,
1846         .slave          = &am33xx_timer6_hwmod,
1847         .clk            = "timer6_ick",
1848         .addr           = am33xx_timer6_addr_space,
1849         .user           = OCP_USER_MPU,
1850 };
1852 static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = {
1853         &am33xx_l4per__timer6,
1854 };
1856 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
1857         { .irq = AM33XX_IRQ_DMTIMER6 },
1858         { .irq = -1 }
1859 };
1861 static struct omap_hwmod am33xx_timer6_hwmod = {
1862         .name           = "timer6",
1863         .class          = &am33xx_timer_hwmod_class,
1864         .mpu_irqs       = am33xx_timer6_irqs,
1865         .main_clk       = "timer6_fck",
1866         .prcm           = {
1867                 .omap4  = {
1868                         .clkctrl_offs   = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
1869                         .modulemode     = MODULEMODE_SWCTRL,
1870                 },
1871         },
1872         .slaves         = am33xx_timer6_slaves,
1873         .slaves_cnt     = ARRAY_SIZE(am33xx_timer6_slaves),
1874         .clkdm_name     = "l4ls_clkdm",
1875 };
1877 /* timer7 */
1878 /* l4 per -> timer7 interface */
1879 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
1880         {
1881                 .pa_start       = AM33XX_TIMER7_BASE,
1882                 .pa_end         = AM33XX_TIMER7_BASE + SZ_1K - 1,
1883                 .flags          = ADDR_TYPE_RT
1884         },
1885         { }
1886 };
1888 static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = {
1889         .master         = &am33xx_l4per_hwmod,
1890         .slave          = &am33xx_timer7_hwmod,
1891         .clk            = "timer7_ick",
1892         .addr           = am33xx_timer7_addr_space,
1893         .user           = OCP_USER_MPU,
1894 };
1896 static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = {
1897         &am33xx_l4per__timer7,
1898 };
1900 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
1901         { .irq = AM33XX_IRQ_DMTIMER7 },
1902         { .irq = -1 }
1903 };
1905 static struct omap_hwmod am33xx_timer7_hwmod = {
1906         .name           = "timer7",
1907         .class          = &am33xx_timer_hwmod_class,
1908         .mpu_irqs       = am33xx_timer7_irqs,
1909         .main_clk       = "timer7_fck",
1910         .prcm           = {
1911                 .omap4  = {
1912                         .clkctrl_offs   = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
1913                         .modulemode     = MODULEMODE_SWCTRL,
1914                 },
1915         },
1916         .slaves         = am33xx_timer7_slaves,
1917         .slaves_cnt     = ARRAY_SIZE(am33xx_timer7_slaves),
1918         .clkdm_name     = "l4ls_clkdm",
1919 };
1921 /* 'tpcc' class */
1922 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1923         .name           = "tpcc",
1924 };
1926 /* tpcc */
1927 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
1928         { .irq = AM33XX_IRQ_TPCC0_INT_PO0 },
1929         { .irq = -1 },
1930 };
1932 static struct omap_hwmod am33xx_tpcc_hwmod = {
1933         .name           = "tpcc",
1934         .class          = &am33xx_tpcc_hwmod_class,
1935         .mpu_irqs       = am33xx_tpcc_irqs,
1936         .main_clk       = "tpcc_ick",
1937         .clkdm_name     = "l3_clkdm",
1938         .prcm           = {
1939                 .omap4  = {
1940                         .clkctrl_offs   = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
1941                         .modulemode     = MODULEMODE_SWCTRL,
1942                 },
1943         },
1944 };
1946 /* 'tptc' class */
1947 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1948         .name           = "tptc",
1949 };
1951 /* tptc0 */
1952 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
1953         { .irq = AM33XX_IRQ_TPTC0 },
1954         { .irq = -1 }
1955 };
1957 static struct omap_hwmod am33xx_tptc0_hwmod = {
1958         .name           = "tptc0",
1959         .class          = &am33xx_tptc_hwmod_class,
1960         .mpu_irqs       = am33xx_tptc0_irqs,
1961         .main_clk       = "tptc0_ick",
1962         .clkdm_name     = "l3_clkdm",
1963         .prcm           = {
1964                 .omap4  = {
1965                         .clkctrl_offs   = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
1966                         .modulemode     = MODULEMODE_SWCTRL,
1967                 },
1968         },
1969 };
1971 /* tptc1 */
1972 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
1973         { .irq = AM33XX_IRQ_TPTC1 },
1974         { .irq = -1 }
1975 };
1977 static struct omap_hwmod am33xx_tptc1_hwmod = {
1978         .name           = "tptc1",
1979         .class          = &am33xx_tptc_hwmod_class,
1980         .mpu_irqs       = am33xx_tptc1_irqs,
1981         .main_clk       = "tptc1_ick",
1982         .clkdm_name     = "l3_clkdm",
1983         .prcm           = {
1984                 .omap4  = {
1985                         .clkctrl_offs   = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
1986                         .modulemode     = MODULEMODE_SWCTRL,
1987                 },
1988         },
1989 };
1991 /* tptc2 */
1992 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
1993         { .irq = AM33XX_IRQ_TPTC2 },
1994         { .irq = -1 }
1995 };
1997 static struct omap_hwmod am33xx_tptc2_hwmod = {
1998         .name           = "tptc2",
1999         .class          = &am33xx_tptc_hwmod_class,
2000         .mpu_irqs       = am33xx_tptc2_irqs,
2001         .main_clk       = "tptc2_ick",
2002         .clkdm_name     = "l3_clkdm",
2003         .prcm           = {
2004                 .omap4  = {
2005                         .clkctrl_offs   = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
2006                         .modulemode     = MODULEMODE_SWCTRL,
2007                 },
2008         },
2009 };
2011 /* 'uart' class */
2012 static struct omap_hwmod_class_sysconfig uart_sysc = {
2013         .rev_offs       = 0x50,
2014         .sysc_offs      = 0x54,
2015         .syss_offs      = 0x58,
2016         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
2017                         SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2018                         SYSC_HAS_AUTOIDLE),
2019         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2020         .sysc_fields    = &omap_hwmod_sysc_type1,
2021 };
2023 static struct omap_hwmod_class uart_class = {
2024         .name           = "uart",
2025         .sysc           = &uart_sysc,
2026 };
2028 /* uart1 */
2029 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
2030         { .name = "tx", .dma_req = 26, },
2031         { .name = "rx", .dma_req = 27, },
2032         { .dma_req = -1 }
2033 };
2035 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
2036         {
2037                 .pa_start       = AM33XX_UART1_BASE,
2038                 .pa_end         = AM33XX_UART1_BASE + SZ_8K - 1,
2039                 .flags          = ADDR_TYPE_RT
2040         },
2041         { }
2042 };
2044 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
2045         .master         = &am33xx_l4wkup_hwmod,
2046         .slave          = &am33xx_uart1_hwmod,
2047         .clk            = "uart1_ick",
2048         .addr           = am33xx_uart1_addr_space,
2049         .user           = OCP_USER_MPU,
2050 };
2052 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
2053         { .irq = AM33XX_IRQ_UART0 },
2054         { .irq = -1 }
2055 };
2057 static struct omap_hwmod_ocp_if *am33xx_uart1_slaves[] = {
2058         &am33xx_l4_wkup__uart1,
2059 };
2061 static struct omap_hwmod am33xx_uart1_hwmod = {
2062         .name           = "uart1",
2063         .class          = &uart_class,
2064         .mpu_irqs       = am33xx_uart1_irqs,
2065         .sdma_reqs      = uart1_edma_reqs,
2066         .main_clk       = "uart1_fck",
2067         .clkdm_name     = "l4_wkup_clkdm",
2068         .prcm           = {
2069                 .omap4  = {
2070                         .clkctrl_offs   = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
2071                         .modulemode     = MODULEMODE_SWCTRL,
2072                 },
2073         },
2074         .slaves         = am33xx_uart1_slaves,
2075         .slaves_cnt     = ARRAY_SIZE(am33xx_uart1_slaves),
2076 };
2078 /* uart2 */
2079 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
2080         {
2081                 .pa_start       = AM33XX_UART2_BASE,
2082                 .pa_end         = AM33XX_UART2_BASE + SZ_8K - 1,
2083                 .flags          = ADDR_TYPE_RT
2084         },
2085         { }
2086 };
2088 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
2089         .slave          = &am33xx_uart2_hwmod,
2090         .clk            = "uart2_ick",
2091         .addr           = am33xx_uart2_addr_space,
2092         .user           = OCP_USER_MPU,
2093 };
2095 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
2096         { .irq = AM33XX_IRQ_UART1 },
2097         { .irq = -1 }
2098 };
2100 static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = {
2101         &am33xx_l4_ls__uart2,
2102 };
2104 static struct omap_hwmod am33xx_uart2_hwmod = {
2105         .name           = "uart2",
2106         .class          = &uart_class,
2107         .mpu_irqs       = am33xx_uart2_irqs,
2108         .main_clk       = "uart2_fck",
2109         .clkdm_name     = "l4ls_clkdm",
2110         .sdma_reqs      = uart1_edma_reqs,
2111         .prcm           = {
2112                 .omap4  = {
2113                         .clkctrl_offs   = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
2114                         .modulemode     = MODULEMODE_SWCTRL,
2115                 },
2116         },
2117         .slaves         = am33xx_uart2_slaves,
2118         .slaves_cnt     = ARRAY_SIZE(am33xx_uart2_slaves),
2119 };
2121 /* uart3 */
2122 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
2123         {
2124                 .pa_start       = AM33XX_UART3_BASE,
2125                 .pa_end         = AM33XX_UART3_BASE + SZ_8K - 1,
2126                 .flags          = ADDR_TYPE_RT
2127         },
2128         { }
2129 };
2131 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
2132         .slave          = &am33xx_uart3_hwmod,
2133         .clk            = "uart3_ick",
2134         .addr           = am33xx_uart3_addr_space,
2135         .user           = OCP_USER_MPU,
2136 };
2138 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2139         { .irq = AM33XX_IRQ_UART2 },
2140         { .irq = -1 }
2141 };
2143 static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = {
2144         &am33xx_l4_ls__uart3,
2145 };
2147 static struct omap_hwmod am33xx_uart3_hwmod = {
2148         .name           = "uart3",
2149         .class          = &uart_class,
2150         .mpu_irqs       = am33xx_uart3_irqs,
2151         .main_clk       = "uart3_fck",
2152         .clkdm_name     = "l4ls_clkdm",
2153         .sdma_reqs      = uart1_edma_reqs,
2154         .prcm           = {
2155                 .omap4  = {
2156                         .clkctrl_offs   = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
2157                         .modulemode     = MODULEMODE_SWCTRL,
2158                 },
2159         },
2160         .slaves         = am33xx_uart3_slaves,
2161         .slaves_cnt     = ARRAY_SIZE(am33xx_uart3_slaves),
2162 };
2164 /* uart4 */
2165 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
2166         {
2167                 .pa_start       = AM33XX_UART4_BASE,
2168                 .pa_end         = AM33XX_UART4_BASE + SZ_8K - 1,
2169                 .flags          = ADDR_TYPE_RT
2170         },
2171         { }
2172 };
2174 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
2175         .slave          = &am33xx_uart4_hwmod,
2176         .clk            = "uart4_ick",
2177         .addr           = am33xx_uart4_addr_space,
2178         .user           = OCP_USER_MPU,
2179 };
2181 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2182         { .irq = AM33XX_IRQ_UART3 },
2183         { .irq = -1 }
2184 };
2186 static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = {
2187         &am33xx_l4_ls__uart4,
2188 };
2190 static struct omap_hwmod am33xx_uart4_hwmod = {
2191         .name           = "uart4",
2192         .class          = &uart_class,
2193         .mpu_irqs       = am33xx_uart4_irqs,
2194         .main_clk       = "uart4_fck",
2195         .clkdm_name     = "l4ls_clkdm",
2196         .sdma_reqs      = uart1_edma_reqs,
2197         .prcm           = {
2198                 .omap4  = {
2199                         .clkctrl_offs   = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
2200                         .modulemode     = MODULEMODE_SWCTRL,
2201                 },
2202         },
2203         .slaves         = am33xx_uart4_slaves,
2204         .slaves_cnt     = ARRAY_SIZE(am33xx_uart4_slaves),
2205 };
2207 /* uart5 */
2208 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
2209         {
2210                 .pa_start       = AM33XX_UART5_BASE,
2211                 .pa_end         = AM33XX_UART5_BASE + SZ_8K - 1,
2212                 .flags          = ADDR_TYPE_RT
2213         },
2214         { }
2215 };
2217 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
2218         .slave          = &am33xx_uart5_hwmod,
2219         .clk            = "uart5_ick",
2220         .addr           = am33xx_uart5_addr_space,
2221         .user           = OCP_USER_MPU,
2222 };
2224 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2225         { .irq = AM33XX_IRQ_UART4 },
2226         { .irq = -1 }
2227 };
2229 static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = {
2230         &am33xx_l4_ls__uart5,
2231 };
2233 static struct omap_hwmod am33xx_uart5_hwmod = {
2234         .name           = "uart5",
2235         .class          = &uart_class,
2236         .mpu_irqs       = am33xx_uart5_irqs,
2237         .main_clk       = "uart5_fck",
2238         .clkdm_name     = "l4ls_clkdm",
2239         .sdma_reqs      = uart1_edma_reqs,
2240         .prcm           = {
2241                 .omap4  = {
2242                         .clkctrl_offs   = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2243                         .modulemode     = MODULEMODE_SWCTRL,
2244                 },
2245         },
2246         .slaves         = am33xx_uart5_slaves,
2247         .slaves_cnt     = ARRAY_SIZE(am33xx_uart5_slaves),
2248 };
2250 /* uart6 */
2251 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
2252         {
2253                 .pa_start       = AM33XX_UART6_BASE,
2254                 .pa_end         = AM33XX_UART6_BASE + SZ_8K - 1,
2255                 .flags          = ADDR_TYPE_RT
2256         },
2257         { }
2258 };
2260 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
2261         .slave          = &am33xx_uart6_hwmod,
2262         .clk            = "uart6_ick",
2263         .addr           = am33xx_uart6_addr_space,
2264         .user           = OCP_USER_MPU,
2265 };
2267 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2268         { .irq = AM33XX_IRQ_UART5 },
2269         { .irq = -1 }
2270 };
2272 static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = {
2273         &am33xx_l4_ls__uart6,
2274 };
2276 static struct omap_hwmod am33xx_uart6_hwmod = {
2277         .name           = "uart6",
2278         .class          = &uart_class,
2279         .mpu_irqs       = am33xx_uart6_irqs,
2280         .main_clk       = "uart6_fck",
2281         .clkdm_name     = "l4ls_clkdm",
2282         .sdma_reqs      = uart1_edma_reqs,
2283         .prcm           = {
2284                 .omap4  = {
2285                         .clkctrl_offs   = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2286                         .modulemode     = MODULEMODE_SWCTRL,
2287                 },
2288         },
2289         .slaves         = am33xx_uart6_slaves,
2290         .slaves_cnt     = ARRAY_SIZE(am33xx_uart6_slaves),
2291 };
2293 /* 'wd_timer' class */
2294 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2295         .name           = "wd_timer",
2296 };
2298 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
2299         {
2300                 .pa_start       = AM33XX_WDT1_BASE,
2301                 .pa_end         = AM33XX_WDT1_BASE + SZ_4K - 1,
2302                 .flags          = ADDR_TYPE_RT
2303         },
2304         { }
2305 };
2307 /* l4_wkup -> wd_timer1 */
2308 static struct omap_hwmod_ocp_if am33xx_l4wkup__wd_timer1 = {
2309         .master         = &am33xx_l4wkup_hwmod,
2310         .slave          = &am33xx_wd_timer1_hwmod,
2311         .addr           = am33xx_wd_timer1_addrs,
2312         .user           = OCP_USER_MPU,
2313 };
2315 /* wd_timer1 slave ports */
2316 static struct omap_hwmod_ocp_if *am33xx_wd_timer1_slaves[] = {
2317         &am33xx_l4wkup__wd_timer1,
2318 };
2320 /* wd_timer1 */
2321 /*
2322  * TODO: device.c file uses hardcoded name for watchdog
2323          timer driver "wd_timer2, so we are also using
2324          same name as of now...
2325  */
2326 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2327         .name           = "wd_timer2",
2328         .class          = &am33xx_wd_timer_hwmod_class,
2329         .main_clk       = "wd_timer1_fck",
2330         .clkdm_name     = "l4_wkup_clkdm",
2331         .prcm           = {
2332                 .omap4  = {
2333                         .clkctrl_offs   = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2334                         .modulemode     = MODULEMODE_SWCTRL,
2335                 },
2336         },
2337         .slaves         = am33xx_wd_timer1_slaves,
2338         .slaves_cnt     = ARRAY_SIZE(am33xx_wd_timer1_slaves),
2339 };
2341 /* wdt0 */
2342 static struct omap_hwmod_irq_info am33xx_wdt0_irqs[] = {
2343         { .irq = AM33XX_IRQ_WDT0 },
2344         { .irq = -1 },
2345 };
2347 static struct omap_hwmod am33xx_wdt0_hwmod = {
2348         .name           = "wdt0",
2349         .class          = &am33xx_wd_timer_hwmod_class,
2350         .mpu_irqs       = am33xx_wdt0_irqs,
2351         .main_clk       = "wdt0_fck",
2352         .clkdm_name     = "l4_wkup_clkdm",
2353         .prcm           = {
2354                 .omap4  = {
2355                         .clkctrl_offs   = AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET,
2356                         .modulemode     = MODULEMODE_SWCTRL,
2357                 },
2358         },
2359 };
2361 /* 'wkup_m3' class */
2362 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
2363         .name           = "wkup_m3",
2364 };
2366 /* wkup_m3 */
2367 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
2368         .name           = "wkup_m3",
2369         .class          = &am33xx_wkup_m3_hwmod_class,
2370         .clkdm_name     = "l4_wkup_aon_clkdm",
2371         .main_clk       = "wkup_m3_fck",
2372         .prcm           = {
2373                 .omap4  = {
2374                         .clkctrl_offs   = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
2375                         .modulemode     = MODULEMODE_SWCTRL,
2376                 },
2377         },
2378 };
2380 /* L3 SLOW -> USBSS interface */
2381 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
2382         {
2383                 .name           = "usbss",
2384                 .pa_start       = AM33XX_USBSS_BASE,
2385                 .pa_end         = AM33XX_USBSS_BASE + SZ_4K - 1,
2386                 .flags          = ADDR_TYPE_RT
2387         },
2388         {
2389                 .name           = "musb0",
2390                 .pa_start       = AM33XX_USB0_BASE,
2391                 .pa_end         = AM33XX_USB0_BASE + SZ_2K - 1,
2392                 .flags          = ADDR_TYPE_RT
2393         },
2394         {
2395                 .name           = "musb1",
2396                 .pa_start       = AM33XX_USB1_BASE,
2397                 .pa_end         = AM33XX_USB1_BASE + SZ_2K - 1,
2398                 .flags          = ADDR_TYPE_RT
2399         },
2400         { }
2401 };
2403 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2404         .rev_offs       = 0x0,
2405         .sysc_offs      = 0x10,
2406         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2407         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2408         .sysc_fields    = &omap_hwmod_sysc_type1,
2409 };
2411 static struct omap_hwmod_class am33xx_usbotg_class = {
2412         .name           = "usbotg",
2413         .sysc           = &am33xx_usbhsotg_sysc,
2414 };
2416 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2417         { .name = "usbss-irq", .irq = AM33XX_IRQ_USBSS, },
2418         { .name = "musb0-irq", .irq = AM33XX_IRQ_USB0, },
2419         { .name = "musb1-irq", .irq = AM33XX_IRQ_USB1, },
2420         { .irq = -1, },
2421 };
2423 static struct omap_hwmod_ocp_if am33xx_l3_slow__usbss = {
2424         .master         = &am33xx_l3slow_hwmod,
2425         .slave          = &am33xx_usbss_hwmod,
2426         .addr           = am33xx_usbss_addr_space,
2427         .user           = OCP_USER_MPU,
2428         .flags          = OCPIF_SWSUP_IDLE,
2429 };
2431 static struct omap_hwmod_ocp_if *am33xx_usbss_slaves[] = {
2432         &am33xx_l3_slow__usbss,
2433 };
2435 static struct omap_hwmod_opt_clk usbss_opt_clks[] = {
2436         { .role = "clkdcoldo", .clk = "usbotg_fck" },
2437 };
2439 static struct omap_hwmod am33xx_usbss_hwmod = {
2440         .name           = "usb_otg_hs",
2441         .mpu_irqs       = am33xx_usbss_mpu_irqs,
2442         .main_clk       = "usbotg_ick",
2443         .clkdm_name     = "l4ls_clkdm",
2444         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2445         .prcm           = {
2446                 .omap4  = {
2447                         .clkctrl_offs   = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2448                         .modulemode     = MODULEMODE_SWCTRL,
2449                 },
2450         },
2451         .opt_clks       = usbss_opt_clks,
2452         .opt_clks_cnt   = ARRAY_SIZE(usbss_opt_clks),
2453         .slaves         = am33xx_usbss_slaves,
2454         .slaves_cnt     = ARRAY_SIZE(am33xx_usbss_slaves),
2455         .class          = &am33xx_usbotg_class,
2456 };
2458 static __initdata struct omap_hwmod *am33xx_hwmods[] = {
2459         /* l3 class */
2460         &am33xx_l3_instr_hwmod,
2461         &am33xx_l3_main_hwmod,
2462         /* l3s class */
2463         &am33xx_l3slow_hwmod,
2464         /* l4hs class */
2465         &am33xx_l4_hs_hwmod,
2466         /* l4fw class */
2467         &am33xx_l4fw_hwmod,
2468         /* l4ls class */
2469         &am33xx_l4ls_hwmod,
2470         /* l4per class */
2471         &am33xx_l4per_hwmod,
2472         /* l4wkup class */
2473         &am33xx_l4wkup_hwmod,
2475         /* clkdiv32k class */
2476         &am33xx_clkdiv32k_hwmod,
2477         /* mpu class */
2478         &am33xx_mpu_hwmod,
2479         /* adc_tsc class */
2480         &am33xx_adc_tsc_hwmod,
2481         /* aes class */
2482         &am33xx_aes0_hwmod,
2483         /* cefuse class */
2484         &am33xx_cefuse_hwmod,
2485         /* control class */
2486         &am33xx_control_hwmod,
2487         /* dcan class */
2488         &am33xx_dcan0_hwmod,
2489         &am33xx_dcan1_hwmod,
2490         /* debugss class */
2491         &am33xx_debugss_hwmod,
2492         /* elm class */
2493         &am33xx_elm_hwmod,
2494         /* emif_fw class */
2495         &am33xx_emif_fw_hwmod,
2496         /* epwmss class */
2497         &am33xx_epwmss0_hwmod,
2498         &am33xx_epwmss1_hwmod,
2499         &am33xx_epwmss2_hwmod,
2500         /* gpio class */
2501         &am33xx_gpio0_hwmod,
2502         &am33xx_gpio1_hwmod,
2503         &am33xx_gpio2_hwmod,
2504         &am33xx_gpio3_hwmod,
2505         /* gpmc class */
2506         &am33xx_gpmc_hwmod,
2507         /* i2c class */
2508         &am33xx_i2c1_hwmod,
2509         &am33xx_i2c2_hwmod,
2510         /* icss class */
2511         &am33xx_icss_hwmod,
2512         /* ieee5000 class */
2513         &am33xx_ieee5000_hwmod,
2514         /* mcasp class */
2515         &am33xx_mcasp0_hwmod,
2516         /* mmc class */
2517         &am33xx_mmc0_hwmod,
2518         &am33xx_mmc1_hwmod,
2519         &am33xx_mmc2_hwmod,
2520         /* ocmcram class */
2521         &am33xx_ocmcram_hwmod,
2522         /* ocpwp class */
2523         &am33xx_ocpwp_hwmod,
2524         /* rtc class */
2525 #if 0
2526         &am33xx_rtc_hwmod,
2527 #endif
2528         /* sha0 class */
2529         &am33xx_sha0_hwmod,
2530         /* smartreflex class */
2531         &am33xx_smartreflex0_hwmod,
2532         &am33xx_smartreflex1_hwmod,
2533         /* spi class */
2534         &am33xx_spi0_hwmod,
2535         &am33xx_spi1_hwmod,
2536         /* spinlock class */
2537         &am33xx_spinlock_hwmod,
2538         /* uart class */
2539         &am33xx_uart1_hwmod,
2540         &am33xx_uart2_hwmod,
2541         &am33xx_uart3_hwmod,
2542         &am33xx_uart4_hwmod,
2543         &am33xx_uart5_hwmod,
2544         &am33xx_uart6_hwmod,
2545         /* timer class */
2546         &am33xx_timer0_hwmod,
2547         &am33xx_timer1_hwmod,
2548         &am33xx_timer2_hwmod,
2549         &am33xx_timer3_hwmod,
2550         &am33xx_timer4_hwmod,
2551         &am33xx_timer5_hwmod,
2552         &am33xx_timer6_hwmod,
2553         &am33xx_timer7_hwmod,
2554         /* wkup_m3 class */
2555         &am33xx_wkup_m3_hwmod,
2556         /* wd_timer class */
2557         &am33xx_wd_timer1_hwmod,
2558         /* usbss hwmod */
2559         &am33xx_usbss_hwmod,
2560         /* cpgmac0 class */
2561         &am33xx_cpgmac0_hwmod,
2562         &am33xx_wdt0_hwmod, /* Secure WDT */
2563         /* tptc class */
2564         &am33xx_tptc0_hwmod,
2565         &am33xx_tptc1_hwmod,
2566         &am33xx_tptc2_hwmod,
2567         /* tpcc class */
2568         &am33xx_tpcc_hwmod,
2569         /* LCDC class */
2570         &am33xx_lcdc_hwmod,
2571         /* rtc */
2572         &am33xx_rtc_hwmod,
2573         NULL,
2574 };
2576 int __init am33xx_hwmod_init(void)
2578         return omap_hwmod_register(am33xx_hwmods);