ARM: OMAP: AM33XX: Keep the CLKDIV32K module enabled
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / omap_hwmod_33xx_data.c
1 /*
2  * Hardware modules present on the AM33XX chips
3  *
4  * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
5  *
6  * This file is automatically generated from the AM33XX hardware databases.
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation version 2.
10  *
11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12  * kind, whether express or implied; without even the implied warranty
13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  */
17 #include <linux/io.h>
19 #include <plat/omap_hwmod.h>
20 #include <plat/i2c.h>
21 #include <plat/cpu.h>
22 #include <plat/gpio.h>
23 #include <plat/dma.h>
24 #include <plat/mmc.h>
25 #include <plat/mcspi.h>
27 #include "omap_hwmod_common_data.h"
28 #include "control.h"
29 #include "cm33xx.h"
30 #include "prm33xx.h"
32 /* Backward references (IPs with Bus Master capability) */
33 static struct omap_hwmod am33xx_mpu_hwmod;
34 static struct omap_hwmod am33xx_l3_main_hwmod;
35 static struct omap_hwmod am33xx_l3slow_hwmod;
36 static struct omap_hwmod am33xx_l4wkup_hwmod;
37 static struct omap_hwmod am33xx_l4per_hwmod;
38 static struct omap_hwmod am33xx_uart1_hwmod;
39 static struct omap_hwmod am33xx_uart2_hwmod;
40 static struct omap_hwmod am33xx_uart3_hwmod;
41 static struct omap_hwmod am33xx_uart4_hwmod;
42 static struct omap_hwmod am33xx_uart5_hwmod;
43 static struct omap_hwmod am33xx_uart6_hwmod;
44 static struct omap_hwmod am33xx_timer0_hwmod;
45 static struct omap_hwmod am33xx_timer1_hwmod;
46 static struct omap_hwmod am33xx_timer2_hwmod;
47 static struct omap_hwmod am33xx_timer3_hwmod;
48 static struct omap_hwmod am33xx_timer4_hwmod;
49 static struct omap_hwmod am33xx_timer5_hwmod;
50 static struct omap_hwmod am33xx_timer6_hwmod;
51 static struct omap_hwmod am33xx_timer7_hwmod;
52 static struct omap_hwmod am33xx_wd_timer1_hwmod;
53 static struct omap_hwmod am33xx_cpgmac0_hwmod;
54 static struct omap_hwmod am33xx_icss_hwmod;
55 static struct omap_hwmod am33xx_ieee5000_hwmod;
56 static struct omap_hwmod am33xx_tptc0_hwmod;
57 static struct omap_hwmod am33xx_tptc1_hwmod;
58 static struct omap_hwmod am33xx_tptc2_hwmod;
59 static struct omap_hwmod am33xx_gpio0_hwmod;
60 static struct omap_hwmod am33xx_gpio1_hwmod;
61 static struct omap_hwmod am33xx_gpio2_hwmod;
62 static struct omap_hwmod am33xx_gpio3_hwmod;
63 static struct omap_hwmod am33xx_i2c1_hwmod;
64 static struct omap_hwmod am33xx_i2c2_hwmod;
65 static struct omap_hwmod am33xx_i2c3_hwmod;
66 static struct omap_hwmod am33xx_usbss_hwmod;
67 static struct omap_hwmod am33xx_mmc0_hwmod;
68 static struct omap_hwmod am33xx_mmc1_hwmod;
69 static struct omap_hwmod am33xx_mmc2_hwmod;
70 static struct omap_hwmod am33xx_spi0_hwmod;
71 static struct omap_hwmod am33xx_spi1_hwmod;
72 static struct omap_hwmod am33xx_elm_hwmod;
73 static struct omap_hwmod am33xx_adc_tsc_hwmod;
74 static struct omap_hwmod am33xx_tpcc_hwmod;
75 static struct omap_hwmod am33xx_mcasp0_hwmod;
76 static struct omap_hwmod am33xx_mcasp1_hwmod;
77 static struct omap_hwmod am33xx_epwmss0_hwmod;
78 static struct omap_hwmod am33xx_epwmss1_hwmod;
79 static struct omap_hwmod am33xx_epwmss2_hwmod;
80 static struct omap_hwmod am33xx_gpmc_hwmod;
81 static struct omap_hwmod am33xx_lcdc_hwmod;
83 /*
84  * Interconnects hwmod structures
85  * hwmods that compose the global AM33XX OCP interconnect
86  */
88 /* MPU -> L3_SLOW Peripheral interface */
89 static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = {
90         .master         = &am33xx_mpu_hwmod,
91         .slave          = &am33xx_l3slow_hwmod,
92         .user           = OCP_USER_MPU,
93 };
95 /* L3 SLOW -> L4_PER Peripheral interface */
96 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = {
97         .master         = &am33xx_l3slow_hwmod,
98         .slave          = &am33xx_l4per_hwmod,
99         .user           = OCP_USER_MPU,
100 };
102 /* L3 SLOW -> L4_WKUP Peripheral interface */
103 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = {
104         .master         = &am33xx_l3slow_hwmod,
105         .slave          = &am33xx_l4wkup_hwmod,
106         .user           = OCP_USER_MPU,
107 };
109 /* Master interfaces on the L4_WKUP interconnect */
110 static struct omap_hwmod_ocp_if *am33xx_l3_slow_masters[] = {
111         &am33xx_l3_slow__l4_per,
112         &am33xx_l3_slow__l4_wkup,
113 };
115 /* Slave interfaces on the L3_SLOW interconnect */
116 static struct omap_hwmod_ocp_if *am33xx_l3_slow_slaves[] = {
117         &am33xx_mpu__l3_slow,
118 };
120 static struct omap_hwmod am33xx_l3slow_hwmod = {
121         .name           = "l3_slow",
122         .class          = &l3_hwmod_class,
123         .clkdm_name     = "l3s_clkdm",
124         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
125         .masters        = am33xx_l3_slow_masters,
126         .masters_cnt    = ARRAY_SIZE(am33xx_l3_slow_masters),
127         .slaves         = am33xx_l3_slow_slaves,
128         .slaves_cnt     = ARRAY_SIZE(am33xx_l3_slow_slaves),
129 };
131 /* L4 PER -> GPIO2 */
132 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
133         {
134                 .pa_start       = AM33XX_GPIO1_BASE,
135                 .pa_end         = AM33XX_GPIO1_BASE + SZ_4K - 1,
136                 .flags          = ADDR_TYPE_RT
137         },
138         { }
139 };
141 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
142         .master         = &am33xx_l4per_hwmod,
143         .slave          = &am33xx_gpio1_hwmod,
144         .clk            = "l4ls_fck",
145         .addr           = am33xx_gpio1_addrs,
146         .user           = OCP_USER_MPU | OCP_USER_SDMA,
147 };
149 /* L4 PER -> GPIO3 */
150 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
151         {
152                 .pa_start       = AM33XX_GPIO2_BASE,
153                 .pa_end         = AM33XX_GPIO2_BASE + SZ_4K - 1,
154                 .flags          = ADDR_TYPE_RT
155         },
156         { }
157 };
159 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
160         .master         = &am33xx_l4per_hwmod,
161         .slave          = &am33xx_gpio2_hwmod,
162         .clk            = "l4ls_fck",
163         .addr           = am33xx_gpio2_addrs,
164         .user           = OCP_USER_MPU | OCP_USER_SDMA,
165 };
167 /* L4 PER -> GPIO4 */
168 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
169         {
170                 .pa_start       = AM33XX_GPIO3_BASE,
171                 .pa_end         = AM33XX_GPIO3_BASE + SZ_4K - 1,
172                 .flags          = ADDR_TYPE_RT
173         },
174         { }
175 };
177 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
178         .master         = &am33xx_l4per_hwmod,
179         .slave          = &am33xx_gpio3_hwmod,
180         .clk            = "l4ls_fck",
181         .addr           = am33xx_gpio3_addrs,
182         .user           = OCP_USER_MPU | OCP_USER_SDMA,
183 };
185 /* Master interfaces on the L4_PER interconnect */
186 static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = {
187         &am33xx_l4_per__gpio1,
188         &am33xx_l4_per__gpio2,
189         &am33xx_l4_per__gpio3,
190 };
191 /* Slave interfaces on the L4_PER interconnect */
192 static struct omap_hwmod_ocp_if *am33xx_l4_per_slaves[] = {
193         &am33xx_l3_slow__l4_per,
194 };
196 static struct omap_hwmod am33xx_l4per_hwmod = {
197         .name           = "l4_per",
198         .class          = &l4_hwmod_class,
199         .clkdm_name     = "l4ls_clkdm",
200         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
201         .masters        = am33xx_l4_per_masters,
202         .masters_cnt    = ARRAY_SIZE(am33xx_l4_per_masters),
203         .slaves         = am33xx_l4_per_slaves,
204         .slaves_cnt     = ARRAY_SIZE(am33xx_l4_per_slaves),
205 };
207 /* L4 WKUP -> I2C1 */
208 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
209         {
210                 .pa_start       = AM33XX_I2C0_BASE,
211                 .pa_end         = AM33XX_I2C0_BASE + SZ_4K - 1,
212                 .flags          = ADDR_TYPE_RT
213         },
214         { }
215 };
217 static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = {
218         .master         = &am33xx_l4wkup_hwmod,
219         .slave          = &am33xx_i2c1_hwmod,
220         .addr           = am33xx_i2c1_addr_space,
221         .user           = OCP_USER_MPU,
222 };
224 /* L4 WKUP -> GPIO1 */
225 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
226         {
227                 .pa_start       = AM33XX_GPIO0_BASE,
228                 .pa_end         = AM33XX_GPIO0_BASE + SZ_4K - 1,
229                 .flags          = ADDR_TYPE_RT
230         },
231         { }
232 };
234 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
235         .master         = &am33xx_l4wkup_hwmod,
236         .slave          = &am33xx_gpio0_hwmod,
237         .clk            = "l4ls_fck",
238         .addr           = am33xx_gpio0_addrs,
239         .user           = OCP_USER_MPU | OCP_USER_SDMA,
240 };
242 /* L4 WKUP -> ADC_TSC */
243 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
244         {
245                 .pa_start       = AM33XX_TSC_BASE,
246                 .pa_end         = AM33XX_TSC_BASE + SZ_8K - 1,
247                 .flags          = ADDR_TYPE_RT
248         },
249         { }
250 };
252 static struct omap_hwmod_ocp_if am33xx_l4_wkup_adc_tsc = {
253         .master         = &am33xx_l4wkup_hwmod,
254         .slave          = &am33xx_adc_tsc_hwmod,
255         .addr           = am33xx_adc_tsc_addrs,
256         .user           = OCP_USER_MPU,
257 };
259 /* Master interfaces on the L4_WKUP interconnect */
260 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = {
261         &am33xx_l4_wkup__gpio0,
262 };
263 /* Slave interfaces on the L4_WKUP interconnect */
264 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_slaves[] = {
265         &am33xx_l3_slow__l4_wkup,
266 };
268 static struct omap_hwmod am33xx_l4wkup_hwmod = {
269         .name           = "l4_wkup",
270         .class          = &l4_hwmod_class,
271         .clkdm_name     = "l4_wkup_clkdm",
272         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
273         .masters        = am33xx_l4_wkup_masters,
274         .masters_cnt    = ARRAY_SIZE(am33xx_l4_wkup_masters),
275         .slaves         = am33xx_l4_wkup_slaves,
276         .slaves_cnt     = ARRAY_SIZE(am33xx_l4_wkup_slaves),
277 };
279 /* 'adc_tsc' class */
280 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
281         .rev_offs       = 0x00,
282         .sysc_offs      = 0x10,
283         .sysc_flags     = SYSC_HAS_SIDLEMODE,
284         .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
285                                 SIDLE_SMART | SIDLE_SMART_WKUP),
286         .sysc_fields    = &omap_hwmod_sysc_type2,
287 };
289 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
290         .name           = "adc_tsc",
291         .sysc           = &am33xx_adc_tsc_sysc,
292 };
294 /* adc_tsc */
295 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
296         { .irq = AM33XX_IRQ_TSC },
297         { .irq = -1 }
298 };
300 static struct omap_hwmod_ocp_if *am33xx_adc_tsc_slaves[] = {
301         &am33xx_l4_wkup_adc_tsc,
302 };
304 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
305         .name           = "adc_tsc",
306         .class          = &am33xx_adc_tsc_hwmod_class,
307         .mpu_irqs       = am33xx_adc_tsc_irqs,
308         .main_clk       = "adc_tsc_fck",
309         .clkdm_name     = "l4_wkup_clkdm",
310         .prcm           = {
311                 .omap4  = {
312                         .clkctrl_offs   = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
313                         .modulemode     = MODULEMODE_SWCTRL,
314                 },
315         },
316         .flags          = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
317         .slaves         = am33xx_adc_tsc_slaves,
318         .slaves_cnt     = ARRAY_SIZE(am33xx_adc_tsc_slaves),
319 };
321 /* 'aes' class */
322 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
323         .name           = "aes",
324 };
326 /* aes0 */
327 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
328         { .irq = AM33XX_IRQ_AESEIP36t0_S },
329         { .irq = -1 }
330 };
332 static struct omap_hwmod am33xx_aes0_hwmod = {
333         .name           = "aes0",
334         .class          = &am33xx_aes_hwmod_class,
335         .mpu_irqs       = am33xx_aes0_irqs,
336         .main_clk       = "aes0_fck",
337         .clkdm_name     = "l3_clkdm",
338         .prcm           = {
339                 .omap4  = {
340                         .clkctrl_offs   = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
341                         .modulemode     = MODULEMODE_SWCTRL,
342                 },
343         },
344 };
346 /* 'cefuse' class */
347 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
348         .name           = "cefuse",
349 };
351 /* cefuse */
352 static struct omap_hwmod am33xx_cefuse_hwmod = {
353         .name           = "cefuse",
354         .class          = &am33xx_cefuse_hwmod_class,
355         .main_clk       = "cefuse_fck",
356         .clkdm_name     = "l4_cefuse_clkdm",
357         .prcm           = {
358                 .omap4  = {
359                         .clkctrl_offs   = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
360                         .modulemode     = MODULEMODE_SWCTRL,
361                 },
362         },
363 };
365 /* 'clkdiv32k' class */
366 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
367         .name           = "clkdiv32k",
368 };
370 /* clkdiv32k */
371 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
372         .name           = "clkdiv32k",
373         .class          = &am33xx_clkdiv32k_hwmod_class,
374         .main_clk       = "clkdiv32k_fck",
375         .clkdm_name     = "clk_24mhz_clkdm",
376         .prcm           = {
377                 .omap4  = {
378                         .clkctrl_offs   = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
379                         .modulemode     = MODULEMODE_SWCTRL,
380                 },
381         },
382         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
383 };
385 /* 'control' class */
386 static struct omap_hwmod_class am33xx_control_hwmod_class = {
387         .name           = "control",
388 };
390 /* control */
391 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
392         { .irq = AM33XX_IRQ_CONTROL_PLATFORM },
393         { .irq = -1 }
394 };
396 static struct omap_hwmod am33xx_control_hwmod = {
397         .name           = "control",
398         .class          = &am33xx_control_hwmod_class,
399         .mpu_irqs       = am33xx_control_irqs,
400         .main_clk       = "control_fck",
401         .clkdm_name     = "l4_wkup_clkdm",
402         .prcm           = {
403                 .omap4  = {
404                         .clkctrl_offs   = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
405                         .modulemode     = MODULEMODE_SWCTRL,
406                 },
407         },
408         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
409 };
411 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
412         .rev_offs       = 0x0,
413         .sysc_offs      = 0x8,
414         .syss_offs      = 0x4,
415         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE
416                                 | SYSS_HAS_RESET_STATUS),
417         .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
418                                 MSTANDBY_FORCE | MSTANDBY_NO),
419         .sysc_fields    = &omap_hwmod_sysc_type3,
420 };
422 /* 'cpgmac' class */
423 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
424         .name           = "cpgmac0",
425         .sysc           = &am33xx_cpgmac_sysc,
426 };
428 /* cpgmac0 - has 4 IRQs */
429 #if 0
430 static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
431         { .irq = AM33XX_IRQ_TPTC0 },
432         { .irq = -1 }
433 };
434 #endif
436 struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
437         {
438                 .pa_start       = AM33XX_CPSW_SS_BASE,
439                 .pa_end         = AM33XX_CPSW_SS_BASE + SZ_8K - 1,
440                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
441         },
442         { }
443 };
445 struct omap_hwmod_ocp_if am33xx_l3_main__cpgmac0 = {
446         .master         = &am33xx_l3_main_hwmod,
447         .slave          = &am33xx_cpgmac0_hwmod,
448         .addr           = am33xx_cpgmac0_addr_space,
449         .user           = OCP_USER_MPU,
450 };
452 static struct omap_hwmod_ocp_if *am33xx_cpgmac0_slaves[] = {
453         &am33xx_l3_main__cpgmac0,
454 };
456 /* cpgmac0 */
457 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
458         .name           = "cpgmac0",
459         .class          = &am33xx_cpgmac0_hwmod_class,
460         .main_clk       = "cpgmac0_fck",
461         .clkdm_name     = "cpsw_125mhz_clkdm",
462         .prcm           = {
463                 .omap4  = {
464                         .clkctrl_offs   = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
465                         .modulemode     = MODULEMODE_SWCTRL,
466                 },
467         },
468         .slaves         = am33xx_cpgmac0_slaves,
469         .slaves_cnt     = ARRAY_SIZE(am33xx_cpgmac0_slaves),
470 };
472 /* 'dcan' class */
473 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
474         .name           = "dcan",
475 };
477 /* dcan0 */
478 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
479         { .irq = AM33XX_IRQ_DCAN0_0 },
480         { .irq = -1 }
481 };
483 static struct omap_hwmod am33xx_dcan0_hwmod = {
484         .name           = "dcan0",
485         .class          = &am33xx_dcan_hwmod_class,
486         .mpu_irqs       = am33xx_dcan0_irqs,
487         .main_clk       = "dcan0_fck",
488         .clkdm_name     = "l4ls_clkdm",
489         .prcm           = {
490                 .omap4  = {
491                         .clkctrl_offs   = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
492                         .modulemode     = MODULEMODE_SWCTRL,
493                 },
494         },
495 };
497 /* dcan1 */
498 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
499         { .irq = AM33XX_IRQ_DCAN1_0 },
500         { .irq = -1 }
501 };
502 static struct omap_hwmod am33xx_dcan1_hwmod = {
503         .name           = "dcan1",
504         .class          = &am33xx_dcan_hwmod_class,
505         .mpu_irqs       = am33xx_dcan1_irqs,
506         .main_clk       = "dcan1_fck",
507         .clkdm_name     = "l4ls_clkdm",
508         .prcm           = {
509                 .omap4  = {
510                         .clkctrl_offs   = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
511                         .modulemode     = MODULEMODE_SWCTRL,
512                 },
513         },
514 };
516 /* 'debugss' class */
517 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
518         .name           = "debugss",
519 };
521 /* debugss */
522 static struct omap_hwmod am33xx_debugss_hwmod = {
523         .name           = "debugss",
524         .class          = &am33xx_debugss_hwmod_class,
525         .main_clk       = "debugss_fck",
526         .clkdm_name     = "l3_aon_clkdm",
527         .prcm           = {
528                 .omap4  = {
529                         .clkctrl_offs   = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
530                         .modulemode     = MODULEMODE_SWCTRL,
531                 },
532         },
533 #ifdef CONFIG_DEBUG_JTAG_ENABLE
534         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
535 #endif
536 };
538 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
539         .rev_offs       = 0x0000,
540         .sysc_offs      = 0x0010,
541         .syss_offs      = 0x0014,
542         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
543                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
544                         SYSS_HAS_RESET_STATUS),
545         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
546         .sysc_fields    = &omap_hwmod_sysc_type1,
547 };
548 /* 'elm' class */
549 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
550         .name           = "elm",
551         .sysc           = &am33xx_elm_sysc,
552 };
554 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
555         { .irq = AM33XX_IRQ_ELM },
556         { .irq = -1 }
557 };
559 struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
560         {
561                 .pa_start       = AM33XX_ELM_BASE,
562                 .pa_end         = AM33XX_ELM_BASE + SZ_8K - 1,
563                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
564         },
565         { }
566 };
568 struct omap_hwmod_ocp_if am33xx_l4_core__elm = {
569         .master         = &am33xx_l4per_hwmod,
570         .slave          = &am33xx_elm_hwmod,
571         .addr           = am33xx_elm_addr_space,
572         .user           = OCP_USER_MPU,
573 };
575 static struct omap_hwmod_ocp_if *am33xx_elm_slaves[] = {
576         &am33xx_l4_core__elm,
577 };
579 /* elm */
580 static struct omap_hwmod am33xx_elm_hwmod = {
581         .name           = "elm",
582         .class          = &am33xx_elm_hwmod_class,
583         .mpu_irqs       = am33xx_elm_irqs,
584         .main_clk       = "elm_fck",
585         .clkdm_name     = "l4ls_clkdm",
586         .slaves         = am33xx_elm_slaves,
587         .slaves_cnt     = ARRAY_SIZE(am33xx_elm_slaves),
588         .prcm           = {
589                 .omap4  = {
590                         .clkctrl_offs   = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
591                         .modulemode     = MODULEMODE_SWCTRL,
592                 },
593         },
594 };
596 /* 'emif_fw' class */
597 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
598         .name           = "emif_fw",
599 };
601 /* emif_fw */
602 static struct omap_hwmod am33xx_emif_fw_hwmod = {
603         .name           = "emif_fw",
604         .class          = &am33xx_emif_fw_hwmod_class,
605         .main_clk       = "emif_fw_fck",
606         .clkdm_name     = "l4fw_clkdm",
607         .prcm           = {
608                 .omap4  = {
609                         .clkctrl_offs   = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
610                         .modulemode     = MODULEMODE_SWCTRL,
611                 },
612         },
613         .flags          = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
614 };
616 /* 'epwmss' class */
617 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
618         .rev_offs       = 0x0,
619         .sysc_offs      = 0x10,
620         .sysc_flags     = SYSC_HAS_SIDLEMODE,
621         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
622                         SIDLE_SMART_WKUP),
623         .sysc_fields    = &omap_hwmod_sysc_type2,
624 };
626 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
627         .name           = "epwmss",
628         .sysc           = &am33xx_epwmss_sysc,
629 };
631 /* epwmss0 */
632 static struct omap_hwmod_irq_info am33xx_epwmss0_irqs[] = {
633         { .irq          = AM33XX_IRQ_PWMSS0_EPWM },
634         { .irq          = AM33XX_IRQ_PWMSS0 },
635         { .irq          = AM33XX_IRQ_PWMSS0_ECAP },
636         { .irq          = -1 }
637 };
639 struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
640         {
641                 .pa_start       = AM33XX_EPWMSS0_BASE,
642                 .pa_end         = AM33XX_EPWMSS0_BASE + SZ_4K - 1,
643                 .flags          = ADDR_TYPE_RT
644         },
645         { }
646 };
648 struct omap_hwmod_ocp_if am33xx_l4_core__epwmss0 = {
649         .master         = &am33xx_l4per_hwmod,
650         .slave          = &am33xx_epwmss0_hwmod,
651         .addr           = am33xx_epwmss0_addr_space,
652         .user           = OCP_USER_MPU,
653 };
655 static struct omap_hwmod_ocp_if *am33xx_epwmss0_slaves[] = {
656         &am33xx_l4_core__epwmss0,
657 };
659 static struct omap_hwmod am33xx_epwmss0_hwmod = {
660         .name           = "epwmss0",
661         .mpu_irqs       = am33xx_epwmss0_irqs,
662         .class          = &am33xx_epwmss_hwmod_class,
663         .main_clk       = "epwmss0_fck",
664         .clkdm_name     = "l4ls_clkdm",
665         .prcm           = {
666                 .omap4  = {
667                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
668                         .modulemode     = MODULEMODE_SWCTRL,
669                 },
670         },
671         .slaves         = am33xx_epwmss0_slaves,
672         .slaves_cnt     = ARRAY_SIZE(am33xx_epwmss0_slaves),
673 };
675 /* epwmss1 */
676 static struct omap_hwmod_irq_info am33xx_epwmss1_irqs[] = {
677         { .irq          = AM33XX_IRQ_PWMSS1_EPWM },
678         { .irq          = AM33XX_IRQ_PWMSS1 },
679         { .irq          = AM33XX_IRQ_PWMSS1_ECAP },
680         { .irq          = -1 }
681 };
683 struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
684         {
685                 .pa_start       = AM33XX_EPWMSS1_BASE,
686                 .pa_end         = AM33XX_EPWMSS1_BASE + SZ_4K - 1,
687                 .flags          = ADDR_TYPE_RT
688         },
689         { }
690 };
692 struct omap_hwmod_ocp_if am33xx_l4_core__epwmss1 = {
693         .master         = &am33xx_l4per_hwmod,
694         .slave          = &am33xx_epwmss1_hwmod,
695         .addr           = am33xx_epwmss1_addr_space,
696         .user           = OCP_USER_MPU,
697 };
699 static struct omap_hwmod_ocp_if *am33xx_epwmss1_slaves[] = {
700         &am33xx_l4_core__epwmss1,
701 };
703 static struct omap_hwmod am33xx_epwmss1_hwmod = {
704         .name           = "epwmss1",
705         .mpu_irqs       = am33xx_epwmss1_irqs,
706         .class          = &am33xx_epwmss_hwmod_class,
707         .main_clk       = "epwmss1_fck",
708         .clkdm_name     = "l4ls_clkdm",
709         .prcm           = {
710                 .omap4  = {
711                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
712                         .modulemode     = MODULEMODE_SWCTRL,
713                 },
714         },
715         .slaves         = am33xx_epwmss1_slaves,
716         .slaves_cnt     = ARRAY_SIZE(am33xx_epwmss1_slaves),
717 };
719 /* epwmss2 */
720 static struct omap_hwmod_irq_info am33xx_epwmss2_irqs[] = {
721         { .irq          = AM33XX_IRQ_PWMSS2_EPWM },
722         { .irq          = AM33XX_IRQ_PWMSS2 },
723         { .irq          = AM33XX_IRQ_PWMSS2_ECAP },
724         { .irq          = -1 }
725 };
727 struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
728         {
729                 .pa_start       = AM33XX_EPWMSS2_BASE,
730                 .pa_end         = AM33XX_EPWMSS2_BASE + SZ_4K - 1,
731                 .flags          = ADDR_TYPE_RT
732         },
733         { }
734 };
736 struct omap_hwmod_ocp_if am33xx_l4_core__epwmss2 = {
737         .master         = &am33xx_l4per_hwmod,
738         .slave          = &am33xx_epwmss2_hwmod,
739         .addr           = am33xx_epwmss2_addr_space,
740         .user           = OCP_USER_MPU,
741 };
743 static struct omap_hwmod_ocp_if *am33xx_epwmss2_slaves[] = {
744         &am33xx_l4_core__epwmss2,
745 };
747 static struct omap_hwmod am33xx_epwmss2_hwmod = {
748         .name           = "epwmss2",
749         .mpu_irqs       = am33xx_epwmss2_irqs,
750         .class          = &am33xx_epwmss_hwmod_class,
751         .main_clk       = "epwmss2_fck",
752         .clkdm_name     = "l4ls_clkdm",
753         .prcm           = {
754                 .omap4  = {
755                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
756                         .modulemode     = MODULEMODE_SWCTRL,
757                 },
758         },
759         .slaves         = am33xx_epwmss2_slaves,
760         .slaves_cnt     = ARRAY_SIZE(am33xx_epwmss2_slaves),
761 };
763 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
764         .rev_offs       = 0x0000,
765         .sysc_offs      = 0x0010,
766         .syss_offs      = 0x0114,
767         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
768                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
769         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
770                                 SIDLE_SMART_WKUP),
771         .sysc_fields    = &omap_hwmod_sysc_type1,
772 };
774 /* 'gpio' class */
775 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
776         .name           = "gpio",
777         .sysc           = &am33xx_gpio_sysc,
778         .rev            = 2,
779 };
781 /* gpio dev_attr */
782 static struct omap_gpio_dev_attr gpio_dev_attr = {
783         .bank_width     = 32,
784         .dbck_flag      = true,
785 };
787 /* gpio0 */
788 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
789         { .irq = AM33XX_IRQ_GPIO0_1 },
790         { .irq = -1 }
791 };
793 /* gpio0 slave ports */
794 static struct omap_hwmod_ocp_if *am33xx_gpio0_slaves[] = {
795         &am33xx_l4_wkup__gpio0,
796 };
798 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
799         { .role = "dbclk", .clk = "gpio0_dbclk" },
800         { .role = "fclk", .clk = "gpio0_fck" },
801 };
803 /* gpio0 */
804 static struct omap_hwmod am33xx_gpio0_hwmod = {
805         .name           = "gpio1",
806         .class          = &am33xx_gpio_hwmod_class,
807         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
808         .mpu_irqs       = am33xx_gpio0_irqs,
809         .main_clk       = "gpio0_fck",
810         .clkdm_name     = "l4_wkup_clkdm",
811         .prcm           = {
812                 .omap4  = {
813                         .clkctrl_offs   = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
814                         .modulemode     = MODULEMODE_SWCTRL,
815                 },
816         },
817         .opt_clks       = gpio0_opt_clks,
818         .opt_clks_cnt   = ARRAY_SIZE(gpio0_opt_clks),
819         .dev_attr       = &gpio_dev_attr,
820         .slaves         = am33xx_gpio0_slaves,
821         .slaves_cnt     = ARRAY_SIZE(am33xx_gpio0_slaves),
822 };
824 /* gpio1 */
825 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
826         { .irq = AM33XX_IRQ_GPIO1_1 },
827         { .irq = -1 }
828 };
830 /* gpio1 slave ports */
831 static struct omap_hwmod_ocp_if *am33xx_gpio1_slaves[] = {
832         &am33xx_l4_per__gpio1,
833 };
835 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
836         { .role = "dbclk", .clk = "gpio1_dbclk" },
837         { .role = "fclk", .clk = "gpio1_fck" },
838 };
840 static struct omap_hwmod am33xx_gpio1_hwmod = {
841         .name           = "gpio2",
842         .class          = &am33xx_gpio_hwmod_class,
843         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
844         .mpu_irqs       = am33xx_gpio1_irqs,
845         .main_clk       = "gpio1_fck",
846         .clkdm_name     = "l4ls_clkdm",
847         .prcm           = {
848                 .omap4  = {
849                         .clkctrl_offs   = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
850                         .modulemode     = MODULEMODE_SWCTRL,
851                 },
852         },
853         .opt_clks       = gpio1_opt_clks,
854         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
855         .dev_attr       = &gpio_dev_attr,
856         .slaves         = am33xx_gpio1_slaves,
857         .slaves_cnt     = ARRAY_SIZE(am33xx_gpio1_slaves),
858 };
860 /* gpio2 */
861 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
862         { .irq = AM33XX_IRQ_GPIO2_1 },
863         { .irq = -1 }
864 };
866 /* gpio2 slave ports */
867 static struct omap_hwmod_ocp_if *am33xx_gpio2_slaves[] = {
868         &am33xx_l4_per__gpio2,
869 };
871 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
872         { .role = "dbclk", .clk = "gpio2_dbclk" },
873         { .role = "fclk", .clk = "gpio2_fck" },
874 };
876 /* gpio2 */
877 static struct omap_hwmod am33xx_gpio2_hwmod = {
878         .name           = "gpio3",
879         .class          = &am33xx_gpio_hwmod_class,
880         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
881         .mpu_irqs       = am33xx_gpio2_irqs,
882         .main_clk       = "gpio2_fck",
883         .clkdm_name     = "l4ls_clkdm",
884         .prcm           = {
885                 .omap4  = {
886                         .clkctrl_offs   = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
887                         .modulemode     = MODULEMODE_SWCTRL,
888                 },
889         },
890         .opt_clks       = gpio2_opt_clks,
891         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
892         .dev_attr       = &gpio_dev_attr,
893         .slaves         = am33xx_gpio2_slaves,
894         .slaves_cnt     = ARRAY_SIZE(am33xx_gpio2_slaves),
895 };
897 /* gpio3 */
898 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
899         { .irq = AM33XX_IRQ_GPIO3_1 },
900         { .irq = -1 }
901 };
903 /* gpio3 slave ports */
904 static struct omap_hwmod_ocp_if *am33xx_gpio3_slaves[] = {
905         &am33xx_l4_per__gpio3,
906 };
908 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
909         { .role = "dbclk", .clk = "gpio3_dbclk" },
910         { .role = "fclk", .clk = "gpio3_fck" },
911 };
913 /* gpio3 */
914 static struct omap_hwmod am33xx_gpio3_hwmod = {
915         .name           = "gpio4",
916         .class          = &am33xx_gpio_hwmod_class,
917         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
918         .mpu_irqs       = am33xx_gpio3_irqs,
919         .main_clk       = "gpio3_fck",
920         .clkdm_name     = "l4ls_clkdm",
921         .prcm           = {
922                 .omap4  = {
923                         .clkctrl_offs   = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
924                         .modulemode     = MODULEMODE_SWCTRL,
925                 },
926         },
927         .opt_clks       = gpio3_opt_clks,
928         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
929         .dev_attr       = &gpio_dev_attr,
930         .slaves         = am33xx_gpio3_slaves,
931         .slaves_cnt     = ARRAY_SIZE(am33xx_gpio3_slaves),
932 };
934 /* 'gpmc' class */
935 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
936         .rev_offs       = 0x0,
937         .sysc_offs      = 0x10,
938         .syss_offs      = 0x14,
939         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
940                                 SYSC_HAS_MIDLEMODE | SYSC_HAS_SOFTRESET |
941                                 SYSS_HAS_RESET_STATUS),
942         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
943                                 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
944         .sysc_fields    = &omap_hwmod_sysc_type4,
945 };
947 struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
948         {
949                 .pa_start       = 0x50000000,
950                 .pa_end         = 0x50000000 + SZ_8K - 1,
951                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
952         },
953         { }
954 };
956 struct omap_hwmod_ocp_if am33xx_l3_main__gpmc = {
957         .master         = &am33xx_l3_main_hwmod,
958         .slave          = &am33xx_gpmc_hwmod,
959         .addr           = am33xx_gpmc_addr_space,
960         .user           = OCP_USER_MPU,
961 };
963 static struct omap_hwmod_ocp_if *am33xx_gpmc_slaves[] = {
964         &am33xx_l3_main__gpmc,
965 };
967 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
968         .name           = "gpmc",
969         .sysc           = &gpmc_sysc,
970 };
972 /* gpmc */
973 static struct omap_hwmod am33xx_gpmc_hwmod = {
974         .name           = "gpmc",
975         .class          = &am33xx_gpmc_hwmod_class,
976         .main_clk       = "gpmc_fck",
977         .clkdm_name     = "l3s_clkdm",
978         .prcm           = {
979                 .omap4  = {
980                         .clkctrl_offs   = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
981                         .modulemode     = MODULEMODE_SWCTRL,
982                 },
983         },
984         .slaves         = am33xx_gpmc_slaves,
985         .slaves_cnt     = ARRAY_SIZE(am33xx_gpmc_slaves),
986 };
988 /* 'i2c' class */
990 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
991         .sysc_offs      = 0x0010,
992         .syss_offs      = 0x0090,
993         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
994                         SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
995                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
996         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
997                         SIDLE_SMART_WKUP),
998         .sysc_fields    = &omap_hwmod_sysc_type1,
999 };
1001 static struct omap_i2c_dev_attr i2c_dev_attr = {
1002         .flags          = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1003 };
1005 static struct omap_hwmod_class i2c_class = {
1006         .name           = "i2c",
1007         .sysc           = &am33xx_i2c_sysc,
1008         .rev            = OMAP_I2C_IP_VERSION_2,
1009         .reset          = &omap_i2c_reset,
1010 };
1012 /* I2C1 */
1013 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1014         { .irq = AM33XX_IRQ_MSHSI2COCP0 },
1015         { .irq = -1 }
1016 };
1018 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
1019         { .name = "tx", .dma_req = 0, },
1020         { .name = "rx", .dma_req = 0, },
1021         { .dma_req = -1 }
1022 };
1024 static struct omap_hwmod_ocp_if *am33xx_i2c1_slaves[] = {
1025         &am33xx_l4_wkup_i2c1,
1026 };
1028 static struct omap_hwmod am33xx_i2c1_hwmod = {
1029         .name           = "i2c1",
1030         .mpu_irqs       = i2c1_mpu_irqs,
1031         .sdma_reqs      = i2c1_edma_reqs,
1032         .main_clk       = "i2c1_fck",
1033         .clkdm_name     = "l4_wkup_clkdm",
1034         .prcm           = {
1035                 .omap4  = {
1036                         .clkctrl_offs   = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
1037                         .modulemode     = MODULEMODE_SWCTRL,
1038                 },
1039         },
1040         .flags          = HWMOD_16BIT_REG,
1041         .dev_attr       = &i2c_dev_attr,
1042         .slaves         = am33xx_i2c1_slaves,
1043         .slaves_cnt     = ARRAY_SIZE(am33xx_i2c1_slaves),
1044         .class          = &i2c_class,
1045 };
1047 /* i2c2 */
1048 /* l4 per -> i2c2 */
1049 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
1050         {
1051                 .pa_start       = AM33XX_I2C1_BASE,
1052                 .pa_end         = AM33XX_I2C1_BASE + SZ_4K - 1,
1053                 .flags          = ADDR_TYPE_RT
1054         },
1055         { }
1056 };
1058 static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = {
1059         .master         = &am33xx_l4per_hwmod,
1060         .slave          = &am33xx_i2c2_hwmod,
1061         .addr           = am33xx_i2c2_addr_space,
1062         .user           = OCP_USER_MPU,
1063 };
1065 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1066         { .irq = AM33XX_IRQ_MSHSI2COCP1 },
1067         { .irq = -1 }
1068 };
1070 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
1071         { .name = "tx", .dma_req = 0, },
1072         { .name = "rx", .dma_req = 0, },
1073         { .dma_req = -1 }
1074 };
1076 static struct omap_hwmod_ocp_if *am33xx_i2c2_slaves[] = {
1077         &am335_l4_per_i2c2,
1078 };
1080 static struct omap_hwmod am33xx_i2c2_hwmod = {
1081         .name           = "i2c2",
1082         .mpu_irqs       = i2c2_mpu_irqs,
1083         .sdma_reqs      = i2c2_edma_reqs,
1084         .main_clk       = "i2c2_fck",
1085         .clkdm_name     = "l4ls_clkdm",
1086         .prcm           = {
1087                 .omap4 = {
1088                         .clkctrl_offs   = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
1089                         .modulemode     = MODULEMODE_SWCTRL,
1090                 },
1091         },
1092         .flags          = HWMOD_16BIT_REG,
1093         .dev_attr       = &i2c_dev_attr,
1094         .slaves         = am33xx_i2c2_slaves,
1095         .slaves_cnt     = ARRAY_SIZE(am33xx_i2c2_slaves),
1096         .class          = &i2c_class,
1097 };
1099 /* i2c3 */
1100 /* l4 per -> i2c3 */
1101 static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
1102         {
1103                 .pa_start       = AM33XX_I2C2_BASE,
1104                 .pa_end         = AM33XX_I2C2_BASE + SZ_4K - 1,
1105                 .flags          = ADDR_TYPE_RT
1106         },
1107         { }
1108 };
1110 static struct omap_hwmod_ocp_if am335_l4_per_i2c3 = {
1111         .master         = &am33xx_l4per_hwmod,
1112         .slave          = &am33xx_i2c3_hwmod,
1113         .addr           = am33xx_i2c3_addr_space,
1114         .user           = OCP_USER_MPU,
1115 };
1117 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1118         { .irq = AM33XX_IRQ_MSHSI2COCP2 },
1119         { .irq = -1 }
1120 };
1122 static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
1123         { .name = "tx", .dma_req = 0, },
1124         { .name = "rx", .dma_req = 0, },
1125         { .dma_req = -1 }
1126 };
1128 static struct omap_hwmod_ocp_if *am33xx_i2c3_slaves[] = {
1129         &am335_l4_per_i2c3,
1130 };
1132 static struct omap_hwmod am33xx_i2c3_hwmod = {
1133         .name           = "i2c3",
1134         .mpu_irqs       = i2c3_mpu_irqs,
1135         .sdma_reqs      = i2c3_edma_reqs,
1136         .main_clk       = "i2c3_fck",
1137         .clkdm_name     = "l4ls_clkdm",
1138         .prcm           = {
1139                 .omap4 = {
1140                         .clkctrl_offs   = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
1141                         .modulemode     = MODULEMODE_SWCTRL,
1142                 },
1143         },
1144         .flags          = HWMOD_16BIT_REG,
1145         .dev_attr       = &i2c_dev_attr,
1146         .slaves         = am33xx_i2c3_slaves,
1147         .slaves_cnt     = ARRAY_SIZE(am33xx_i2c3_slaves),
1148         .class          = &i2c_class,
1149 };
1151 /* 'icss' class */
1152 static struct omap_hwmod_class am33xx_icss_hwmod_class = {
1153         .name = "icss",
1154 };
1156 /* icss */
1157 static struct omap_hwmod am33xx_icss_hwmod = {
1158         .name           = "icss",
1159         .class          = &am33xx_icss_hwmod_class,
1160         .main_clk       = "icss_fck",
1161         .clkdm_name     = "icss_ocp_clkdm",
1162         .prcm           = {
1163                 .omap4  = {
1164                         .clkctrl_offs   = AM33XX_CM_PER_ICSS_CLKCTRL_OFFSET,
1165                         .modulemode     = MODULEMODE_SWCTRL,
1166                 },
1167         },
1168 };
1170 /* 'ieee5000' class */
1171 static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = {
1172         .name           = "ieee5000",
1173 };
1175 /* ieee5000 */
1176 static struct omap_hwmod am33xx_ieee5000_hwmod = {
1177         .name           = "ieee5000",
1178         .class          = &am33xx_ieee5000_hwmod_class,
1179         .main_clk       = "ieee5000_fck",
1180         .clkdm_name     = "l3s_clkdm",
1181         .prcm           = {
1182                 .omap4  = {
1183                         .clkctrl_offs   = AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET,
1184                         .modulemode     = MODULEMODE_SWCTRL,
1185                 },
1186         },
1187 };
1190 /* 'l3' class */
1191 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
1192         .name           = "l3",
1193 };
1195 /* l4_hs */
1196 static struct omap_hwmod am33xx_l4_hs_hwmod = {
1197         .name           = "l4_hs",
1198         .class          = &am33xx_l3_hwmod_class,
1199         .clkdm_name     = "l4hs_clkdm",
1200         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1201         .prcm           = {
1202                 .omap4  = {
1203                         .clkctrl_offs   = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
1204                         .modulemode     = MODULEMODE_SWCTRL,
1205                 },
1206         },
1207 };
1209 /* l3_instr */
1210 static struct omap_hwmod am33xx_l3_instr_hwmod = {
1211         .name           = "l3_instr",
1212         .class          = &am33xx_l3_hwmod_class,
1213         .clkdm_name     = "l3_clkdm",
1214         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1215         .prcm           = {
1216                 .omap4  = {
1217                         .clkctrl_offs   = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
1218                         .modulemode     = MODULEMODE_SWCTRL,
1219                 },
1220         },
1221 };
1223 /* l3_main */
1224 static struct omap_hwmod am33xx_l3_main_hwmod = {
1225         .name           = "l3_main",
1226         .class          = &am33xx_l3_hwmod_class,
1227         .clkdm_name     = "l3_clkdm",
1228         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1229         .prcm           = {
1230                 .omap4  = {
1231                         .clkctrl_offs   = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
1232                         .modulemode     = MODULEMODE_SWCTRL,
1233                 },
1234         },
1235 };
1237 /* 'l4fw' class */
1238 static struct omap_hwmod_class am33xx_l4fw_hwmod_class = {
1239         .name           = "l4fw",
1240 };
1242 /* l4fw */
1243 static struct omap_hwmod am33xx_l4fw_hwmod = {
1244         .name           = "l4fw",
1245         .class          = &am33xx_l4fw_hwmod_class,
1246         .clkdm_name     = "l4fw_clkdm",
1247         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1248         .prcm           = {
1249                 .omap4  = {
1250                         .clkctrl_offs   = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
1251                         .modulemode     = MODULEMODE_SWCTRL,
1252                 },
1253         },
1254 };
1256 /* 'l4ls' class */
1257 static struct omap_hwmod_class am33xx_l4ls_hwmod_class = {
1258         .name           = "l4ls",
1259 };
1261 /* l4ls */
1262 static struct omap_hwmod am33xx_l4ls_hwmod = {
1263         .name           = "l4ls",
1264         .class          = &am33xx_l4ls_hwmod_class,
1265         .main_clk       = "l4ls_fck",
1266         .clkdm_name     = "l4ls_clkdm",
1267         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1268         .prcm           = {
1269                 .omap4  = {
1270                         .clkctrl_offs   = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
1271                         .modulemode     = MODULEMODE_SWCTRL,
1272                 },
1273         },
1274 };
1276 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
1277         .rev_offs       = 0x0,
1278         .sysc_offs      = 0x54,
1279         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
1280         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1281         .sysc_fields    = &omap_hwmod_sysc_type2,
1282 };
1284 /* 'lcdc' class */
1285 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1286         .name           = "lcdc",
1287         .sysc           = &lcdc_sysc,
1288 };
1290 /* lcdc */
1291 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1292         { .irq = AM33XX_IRQ_LCD },
1293         { .irq = -1 }
1294 };
1296 struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
1297         {
1298                 .pa_start       = 0x4830E000,
1299                 .pa_end         = 0x4830E000 + SZ_8K - 1,
1300                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
1301         },
1302         { }
1303 };
1305 struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
1306         .master         = &am33xx_l3_main_hwmod,
1307         .slave          = &am33xx_lcdc_hwmod,
1308         .addr           = am33xx_lcdc_addr_space,
1309         .user           = OCP_USER_MPU,
1310 };
1312 static struct omap_hwmod_ocp_if *am33xx_lcdc_slaves[] = {
1313         &am33xx_l3_main__lcdc,
1314 };
1316 static struct omap_hwmod am33xx_lcdc_hwmod = {
1317         .name           = "lcdc",
1318         .class          = &am33xx_lcdc_hwmod_class,
1319         .mpu_irqs       = am33xx_lcdc_irqs,
1320         .main_clk       = "lcdc_fck",
1321         .clkdm_name     = "lcdc_clkdm",
1322         .prcm           = {
1323                 .omap4  = {
1324                         .clkctrl_offs   = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1325                         .modulemode     = MODULEMODE_SWCTRL,
1326                 },
1327         },
1328         .slaves         = am33xx_lcdc_slaves,
1329         .slaves_cnt     = ARRAY_SIZE(am33xx_lcdc_slaves),
1330 };
1332 /*
1333  * 'mailbox' class
1334  * mailbox module allowing communication between the on-chip processors using a
1335  * queued mailbox-interrupt mechanism.
1336  */
1338 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1339         .rev_offs       = 0x0000,
1340         .sysc_offs      = 0x0010,
1341         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1342                            SYSC_HAS_SOFTRESET),
1343         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1344         .sysc_fields    = &omap_hwmod_sysc_type2,
1345 };
1347 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1348         .name   = "mailbox",
1349         .sysc   = &am33xx_mailbox_sysc,
1350 };
1352 /* mailbox */
1353 static struct omap_hwmod am33xx_mailbox_hwmod;
1354 static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1355         { .irq = AM33XX_IRQ_MAILBOX },
1356         { .irq = -1 }
1357 };
1359 static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
1360         {
1361                 .pa_start       = AM33XX_MAILBOX0_BASE,
1362                 .pa_end         = AM33XX_MAILBOX0_BASE + (SZ_4K - 1),
1363                 .flags          = ADDR_TYPE_RT
1364         },
1365         { }
1366 };
1368 /* l4_cfg -> mailbox */
1369 static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
1370         .master         = &am33xx_l4per_hwmod,
1371         .slave          = &am33xx_mailbox_hwmod,
1372         .addr           = am33xx_mailbox_addrs,
1373         .user           = OCP_USER_MPU,
1374 };
1376 /* mailbox slave ports */
1377 static struct omap_hwmod_ocp_if *am33xx_mailbox_slaves[] = {
1378         &am33xx_l4_per__mailbox,
1379 };
1381 static struct omap_hwmod am33xx_mailbox_hwmod = {
1382         .name           = "mailbox",
1383         .class          = &am33xx_mailbox_hwmod_class,
1384         .clkdm_name     = "l4ls_clkdm",
1385         .mpu_irqs       = am33xx_mailbox_irqs,
1386         .main_clk       = "mailbox0_fck",
1387         .prcm = {
1388                 .omap4 = {
1389                         .clkctrl_offs   = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1390                         .modulemode     = MODULEMODE_SWCTRL,
1391                 },
1392         },
1393         .slaves         = am33xx_mailbox_slaves,
1394         .slaves_cnt     = ARRAY_SIZE(am33xx_mailbox_slaves),
1395 };
1397 /* 'mcasp' class */
1398 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1399         .name           = "mcasp",
1400 };
1402 /* mcasp0 */
1403 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1404         { .name = "ax", .irq = AM33XX_IRQ_MCASP0_AX, },
1405         { .name = "ar", .irq = AM33XX_IRQ_MCASP0_AR, },
1406         { .irq = -1 }
1407 };
1409 static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
1410         {
1411                 .pa_start       = AM33XX_ASP0_BASE,
1412                 .pa_end         = AM33XX_ASP0_BASE + (SZ_1K * 12) - 1,
1413                 .flags          = ADDR_TYPE_RT
1414         },
1415         { }
1416 };
1418 static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp0 = {
1419         .master         = &am33xx_l3slow_hwmod,
1420         .slave          = &am33xx_mcasp0_hwmod,
1421         .clk            = "mcasp0_ick",
1422         .addr           = am33xx_mcasp0_addr_space,
1423         .user           = OCP_USER_MPU,
1424 };
1426 static struct omap_hwmod_ocp_if *am33xx_mcasp0_slaves[] = {
1427         &am33xx_l3_slow__mcasp0,
1428 };
1430 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1431         .name           = "mcasp0",
1432         .class          = &am33xx_mcasp_hwmod_class,
1433         .mpu_irqs       = am33xx_mcasp0_irqs,
1434         .main_clk       = "mcasp0_fck",
1435         .clkdm_name     = "l3s_clkdm",
1436         .prcm           = {
1437                 .omap4  = {
1438                         .clkctrl_offs   = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1439                         .modulemode     = MODULEMODE_SWCTRL,
1440                 },
1441         },
1442         .slaves         = am33xx_mcasp0_slaves,
1443         .slaves_cnt     = ARRAY_SIZE(am33xx_mcasp0_slaves),
1444 };
1446 /* mcasp1 */
1447 static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
1448         { .name = "ax", .irq = AM33XX_IRQ_MCASP1_AX, },
1449         { .name = "ar", .irq = AM33XX_IRQ_MCASP1_AR, },
1450         { .irq = -1 }
1451 };
1453 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
1454         {
1455                 .pa_start       = AM33XX_ASP1_BASE,
1456                 .pa_end         = AM33XX_ASP1_BASE + (SZ_1K * 12) - 1,
1457                 .flags          = ADDR_TYPE_RT
1458         },
1459         { }
1460 };
1462 static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp1 = {
1463         .master         = &am33xx_l3slow_hwmod,
1464         .slave          = &am33xx_mcasp1_hwmod,
1465         .clk            = "mcasp1_ick",
1466         .addr           = am33xx_mcasp1_addr_space,
1467         .user           = OCP_USER_MPU,
1468 };
1470 static struct omap_hwmod_ocp_if *am33xx_mcasp1_slaves[] = {
1471         &am33xx_l3_slow__mcasp1,
1472 };
1474 static struct omap_hwmod am33xx_mcasp1_hwmod = {
1475         .name           = "mcasp1",
1476         .class          = &am33xx_mcasp_hwmod_class,
1477         .mpu_irqs       = am33xx_mcasp1_irqs,
1478         .main_clk       = "mcasp1_fck",
1479         .clkdm_name     = "l3s_clkdm",
1480         .prcm           = {
1481                 .omap4  = {
1482                         .clkctrl_offs   = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
1483                         .modulemode     = MODULEMODE_SWCTRL,
1484                 },
1485         },
1486         .slaves         = am33xx_mcasp1_slaves,
1487         .slaves_cnt     = ARRAY_SIZE(am33xx_mcasp1_slaves),
1488 };
1491 /* 'mmc' class */
1493 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1494         .rev_offs       = 0x1fc,
1495         .sysc_offs      = 0x10,
1496         .syss_offs      = 0x14,
1497         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1498                         SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1499                         SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1500         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1501         .sysc_fields    = &omap_hwmod_sysc_type1,
1502 };
1504 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1505         .name           = "mmc",
1506         .sysc           = &am33xx_mmc_sysc,
1507 };
1509 /* mmc0 */
1510 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1511         { .irq = AM33XX_IRQ_MMCHS0 },
1512         { .irq = -1 }
1513 };
1515 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1516         { .name = "tx", .dma_req = AM33XX_DMA_MMCHS0_W, },
1517         { .name = "rx", .dma_req = AM33XX_DMA_MMCHS0_R, },
1518         { .dma_req = -1 }
1519 };
1521 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
1522         {
1523                 .pa_start       = AM33XX_MMC0_BASE,
1524                 .pa_end         = AM33XX_MMC0_BASE + SZ_4K - 1,
1525                 .flags          = ADDR_TYPE_RT
1526         },
1527         { }
1528 };
1530 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc0 = {
1531         .master         = &am33xx_l4ls_hwmod,
1532         .slave          = &am33xx_mmc0_hwmod,
1533         .clk            = "mmc0_ick",
1534         .addr           = am33xx_mmc0_addr_space,
1535         .user           = OCP_USER_MPU,
1536 };
1538 static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = {
1539         &am33xx_l4ls__mmc0,
1540 };
1542 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1543         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1544 };
1546 static struct omap_hwmod am33xx_mmc0_hwmod = {
1547         .name           = "mmc1",
1548         .class          = &am33xx_mmc_hwmod_class,
1549         .mpu_irqs       = am33xx_mmc0_irqs,
1550         .sdma_reqs      = am33xx_mmc0_edma_reqs,
1551         .main_clk       = "mmc0_fck",
1552         .clkdm_name     = "l4ls_clkdm",
1553         .prcm           = {
1554                 .omap4  = {
1555                         .clkctrl_offs   = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1556                         .modulemode     = MODULEMODE_SWCTRL,
1557                 },
1558         },
1559         .dev_attr       = &am33xx_mmc0_dev_attr,
1560         .slaves         = am33xx_mmc0_slaves,
1561         .slaves_cnt     = ARRAY_SIZE(am33xx_mmc0_slaves),
1562 };
1564 /* mmc1 */
1565 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1566         { .irq = AM33XX_IRQ_MMCHS1 },
1567         { .irq = -1 }
1568 };
1570 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1571         { .name = "tx", .dma_req = AM33XX_DMA_MMCHS1_W, },
1572         { .name = "rx", .dma_req = AM33XX_DMA_MMCHS1_R, },
1573         { .dma_req = -1 }
1574 };
1576 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
1577         {
1578                 .pa_start       = AM33XX_MMC1_BASE,
1579                 .pa_end         = AM33XX_MMC1_BASE + SZ_4K - 1,
1580                 .flags          = ADDR_TYPE_RT
1581         },
1582         { }
1583 };
1585 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc1 = {
1586         .master         = &am33xx_l4ls_hwmod,
1587         .slave          = &am33xx_mmc1_hwmod,
1588         .clk            = "mmc1_ick",
1589         .addr           = am33xx_mmc1_addr_space,
1590         .user           = OCP_USER_MPU,
1591 };
1593 static struct omap_hwmod_ocp_if *am33xx_mmc1_slaves[] = {
1594         &am33xx_l4ls__mmc1,
1595 };
1597 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1598         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1599 };
1601 static struct omap_hwmod am33xx_mmc1_hwmod = {
1602         .name           = "mmc2",
1603         .class          = &am33xx_mmc_hwmod_class,
1604         .mpu_irqs       = am33xx_mmc1_irqs,
1605         .sdma_reqs      = am33xx_mmc1_edma_reqs,
1606         .main_clk       = "mmc1_fck",
1607         .clkdm_name     = "l4ls_clkdm",
1608         .prcm           = {
1609                 .omap4  = {
1610                         .clkctrl_offs   = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1611                         .modulemode     = MODULEMODE_SWCTRL,
1612                 },
1613         },
1614         .dev_attr       = &am33xx_mmc1_dev_attr,
1615         .slaves         = am33xx_mmc1_slaves,
1616         .slaves_cnt     = ARRAY_SIZE(am33xx_mmc1_slaves),
1617 };
1619 /* mmc2 */
1620 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1621         { .irq = AM33XX_IRQ_MMCHS2 },
1622         { .irq = -1 }
1623 };
1625 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1626         { .name = "tx", .dma_req = AM33XX_DMA_MMCHS2_W, },
1627         { .name = "rx", .dma_req = AM33XX_DMA_MMCHS2_R, },
1628         { .dma_req = -1 }
1629 };
1631 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
1632         {
1633                 .pa_start       = AM33XX_MMC2_BASE,
1634                 .pa_end         = AM33XX_MMC2_BASE + SZ_64K - 1,
1635                 .flags          = ADDR_TYPE_RT
1636         },
1637         { }
1638 };
1640 static struct omap_hwmod_ocp_if am33xx_l3_main__mmc2 = {
1641         .master         = &am33xx_l3_main_hwmod,
1642         .slave          = &am33xx_mmc2_hwmod,
1643         .clk            = "mmc2_ick",
1644         .addr           = am33xx_mmc2_addr_space,
1645         .user           = OCP_USER_MPU,
1646 };
1648 static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = {
1649         &am33xx_l3_main__mmc2,
1650 };
1652 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1653         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1654 };
1655 static struct omap_hwmod am33xx_mmc2_hwmod = {
1656         .name           = "mmc3",
1657         .class          = &am33xx_mmc_hwmod_class,
1658         .mpu_irqs       = am33xx_mmc2_irqs,
1659         .sdma_reqs      = am33xx_mmc2_edma_reqs,
1660         .main_clk       = "mmc2_fck",
1661         .clkdm_name     = "l3s_clkdm",
1662         .prcm           = {
1663                 .omap4  = {
1664                         .clkctrl_offs   = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1665                         .modulemode     = MODULEMODE_SWCTRL,
1666                 },
1667         },
1668         .dev_attr       = &am33xx_mmc2_dev_attr,
1669         .slaves         = am33xx_mmc2_slaves,
1670         .slaves_cnt     = ARRAY_SIZE(am33xx_mmc2_slaves),
1671 };
1673 /* Master interfaces on the MPU interconnect */
1674 static struct omap_hwmod_ocp_if *am33xx_l3_mpu_masters[] = {
1675         &am33xx_mpu__l3_slow,
1676 };
1678 /* mpu */
1679 static struct omap_hwmod am33xx_mpu_hwmod = {
1680         .name           = "mpu",
1681         .class          = &mpu_hwmod_class,
1682         .masters        = am33xx_l3_mpu_masters,
1683         .masters_cnt    = ARRAY_SIZE(am33xx_l3_mpu_masters),
1684         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1685         .main_clk       = "mpu_fck",
1686         .clkdm_name     = "mpu_clkdm",
1687         .prcm           = {
1688                 .omap4  = {
1689                         .clkctrl_offs   = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1690                         .modulemode     = MODULEMODE_SWCTRL,
1691                 },
1692         },
1693 };
1695 /* 'ocmcram' class */
1696 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
1697         .name = "ocmcram",
1698 };
1700 /* ocmcram */
1701 static struct omap_hwmod am33xx_ocmcram_hwmod = {
1702         .name           = "ocmcram",
1703         .class          = &am33xx_ocmcram_hwmod_class,
1704         .main_clk       = "ocmcram_fck",
1705         .clkdm_name     = "l3_clkdm",
1706         .prcm           = {
1707                 .omap4  = {
1708                         .clkctrl_offs   = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
1709                         .modulemode     = MODULEMODE_SWCTRL,
1710                 },
1711         },
1712         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1713 };
1715 /* 'ocpwp' class */
1716 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
1717         .name           = "ocpwp",
1718 };
1720 /* ocpwp */
1721 static struct omap_hwmod am33xx_ocpwp_hwmod = {
1722         .name           = "ocpwp",
1723         .class          = &am33xx_ocpwp_hwmod_class,
1724         .main_clk       = "ocpwp_fck",
1725         .clkdm_name     = "l4ls_clkdm",
1726         .prcm           = {
1727                 .omap4  = {
1728                         .clkctrl_offs   = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
1729                         .modulemode     = MODULEMODE_SWCTRL,
1730                 },
1731         },
1732 };
1734 /* 'rtc' class */
1735 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1736         .name           = "rtc",
1737 };
1739 /* rtc */
1740 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1741         { .irq = AM33XX_IRQ_RTC_TIMER },
1742         { .irq = -1 }
1743 };
1745 static struct omap_hwmod am33xx_rtc_hwmod = {
1746         .name           = "rtc",
1747         .class          = &am33xx_rtc_hwmod_class,
1748         .mpu_irqs       = am33xx_rtc_irqs,
1749         .main_clk       = "rtc_fck",
1750         .clkdm_name     = "l4_rtc_clkdm",
1751         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), /* ??? */
1752         .prcm           = {
1753                 .omap4  = {
1754                         .clkctrl_offs   = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1755                         .modulemode     = MODULEMODE_SWCTRL,
1756                 },
1757         },
1758 };
1760 /* 'sha0' class */
1761 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
1762         .name           = "sha0",
1763 };
1765 /* sha0 */
1766 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
1767         { .irq = AM33XX_IRQ_SHAEIP57t0_S },
1768         { .irq = -1 }
1769 };
1771 static struct omap_hwmod am33xx_sha0_hwmod = {
1772         .name           = "sha0",
1773         .class          = &am33xx_sha0_hwmod_class,
1774         .mpu_irqs       = am33xx_sha0_irqs,
1775         .main_clk       = "sha0_fck",
1776         .clkdm_name     = "l3_clkdm",
1777         .prcm           = {
1778                 .omap4  = {
1779                         .clkctrl_offs   = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
1780                         .modulemode     = MODULEMODE_SWCTRL,
1781                 },
1782         },
1783 };
1785 /* 'smartreflex' class */
1786 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
1787         .name           = "smartreflex",
1788 };
1790 /* smartreflex0 */
1791 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
1792         { .irq = AM33XX_IRQ_SMARTREFLEX0 },
1793         { .irq = -1 }
1794 };
1796 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
1797         .name           = "smartreflex0",
1798         .class          = &am33xx_smartreflex_hwmod_class,
1799         .mpu_irqs       = am33xx_smartreflex0_irqs,
1800         .main_clk       = "smartreflex0_fck",
1801         .clkdm_name     = "l4_wkup_clkdm",
1802         .prcm           = {
1803                 .omap4  = {
1804                         .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
1805                         .modulemode     = MODULEMODE_SWCTRL,
1806                 },
1807         },
1808 };
1810 /* smartreflex1 */
1811 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
1812         { .irq = AM33XX_IRQ_SMARTREFLEX1 },
1813         { .irq = -1 }
1814 };
1816 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
1817         .name           = "smartreflex1",
1818         .class          = &am33xx_smartreflex_hwmod_class,
1819         .mpu_irqs       = am33xx_smartreflex1_irqs,
1820         .main_clk       = "smartreflex1_fck",
1821         .clkdm_name     = "l4_wkup_clkdm",
1822         .prcm           = {
1823                 .omap4  = {
1824                         .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
1825                         .modulemode     = MODULEMODE_SWCTRL,
1826                 },
1827         },
1828 };
1830 /* 'spi' class */
1832 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1833         .rev_offs       = 0x0000,
1834         .sysc_offs      = 0x0110,
1835         .syss_offs      = 0x0114,
1836         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1837                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1838                         SYSS_HAS_RESET_STATUS),
1839         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1840         .sysc_fields    = &omap_hwmod_sysc_type1,
1841 };
1843 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1844         .name           = "mcspi",
1845         .sysc           = &am33xx_mcspi_sysc,
1846         .rev            = OMAP4_MCSPI_REV,
1847 };
1849 /* spi0 */
1850 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1851         { .irq = AM33XX_IRQ_MCSPIOCP0 },
1852         { .irq = -1 }
1853 };
1855 struct omap_hwmod_dma_info am33xx_mcspi0_sdma_reqs[] = {
1856         { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0R },
1857         { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0W },
1858         { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1R },
1859         { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1W },
1860         { .dma_req = -1 }
1861 };
1863 struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
1864         {
1865                 .pa_start       = AM33XX_SPI0_BASE,
1866                 .pa_end         = AM33XX_SPI0_BASE + SZ_1K - 1,
1867                 .flags          = ADDR_TYPE_RT
1868         },
1869         { }
1870 };
1872 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = {
1873         .master         = &am33xx_l4per_hwmod,
1874         .slave          = &am33xx_spi0_hwmod,
1875         .clk            = "spi0_ick",
1876         .addr           = am33xx_mcspi0_addr_space,
1877         .user           = OCP_USER_MPU,
1878 };
1880 static struct omap_hwmod_ocp_if *am33xx_mcspi0_slaves[] = {
1881         &am33xx_l4_core__mcspi0,
1882 };
1884 struct omap2_mcspi_dev_attr mcspi_attrib = {
1885         .num_chipselect = 2,
1886 };
1887 static struct omap_hwmod am33xx_spi0_hwmod = {
1888         .name           = "spi0",
1889         .class          = &am33xx_spi_hwmod_class,
1890         .mpu_irqs       = am33xx_spi0_irqs,
1891         .sdma_reqs      = am33xx_mcspi0_sdma_reqs,
1892         .main_clk       = "spi0_fck",
1893         .clkdm_name     = "l4ls_clkdm",
1894         .prcm           = {
1895                 .omap4  = {
1896                         .clkctrl_offs   = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1897                         .modulemode     = MODULEMODE_SWCTRL,
1898                 },
1899         },
1900         .dev_attr       = &mcspi_attrib,
1901         .slaves         = am33xx_mcspi0_slaves,
1902         .slaves_cnt     = ARRAY_SIZE(am33xx_mcspi0_slaves),
1903 };
1905 /* spi1 */
1906 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1907         { .irq = AM33XX_IRQ_SPI1 },
1908         { .irq = -1 }
1909 };
1911 struct omap_hwmod_dma_info am33xx_mcspi1_sdma_reqs[] = {
1912         { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0R },
1913         { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0W },
1914         { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1R },
1915         { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1W },
1916         { .dma_req = -1 }
1917 };
1919 struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
1920         {
1921                 .pa_start       = AM33XX_SPI1_BASE,
1922                 .pa_end         = AM33XX_SPI1_BASE + SZ_1K - 1,
1923                 .flags          = ADDR_TYPE_RT
1924         },
1925         { }
1926 };
1928 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = {
1929         .master         = &am33xx_l4per_hwmod,
1930         .slave          = &am33xx_spi1_hwmod,
1931         .clk            = "spi1_ick",
1932         .addr           = am33xx_mcspi1_addr_space,
1933         .user           = OCP_USER_MPU,
1934 };
1936 static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = {
1937         &am33xx_l4_core__mcspi1,
1938 };
1939 static struct omap_hwmod am33xx_spi1_hwmod = {
1940         .name           = "spi1",
1941         .class          = &am33xx_spi_hwmod_class,
1942         .mpu_irqs       = am33xx_spi1_irqs,
1943         .sdma_reqs      = am33xx_mcspi1_sdma_reqs,
1944         .main_clk       = "spi1_fck",
1945         .clkdm_name     = "l4ls_clkdm",
1946         .prcm           = {
1947                 .omap4  = {
1948                         .clkctrl_offs   = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1949                         .modulemode     = MODULEMODE_SWCTRL,
1950                 },
1951         },
1952         .dev_attr       = &mcspi_attrib,
1953         .slaves         = am33xx_mcspi1_slaves,
1954         .slaves_cnt     = ARRAY_SIZE(am33xx_mcspi1_slaves),
1955 };
1957 /* 'spinlock' class */
1958 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1959         .name           = "spinlock",
1960 };
1962 /* spinlock */
1963 static struct omap_hwmod am33xx_spinlock_hwmod = {
1964         .name           = "spinlock",
1965         .class          = &am33xx_spinlock_hwmod_class,
1966         .main_clk       = "spinlock_fck",
1967         .clkdm_name     = "l4ls_clkdm",
1968         .prcm           = {
1969                 .omap4  = {
1970                         .clkctrl_offs   = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1971                         .modulemode     = MODULEMODE_SWCTRL,
1972                 },
1973         },
1974 };
1976 /* 'timer 0 & 2-7' class */
1977 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1978         .rev_offs       = 0x0000,
1979         .sysc_offs      = 0x0010,
1980         .syss_offs      = 0x0014,
1981         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1982         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1983                         SIDLE_SMART_WKUP),
1984         .sysc_fields    = &omap_hwmod_sysc_type2,
1985 };
1987 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1988         .name           = "timer",
1989         .sysc           = &am33xx_timer_sysc,
1990 };
1992 /* timer0 */
1993 /* l4 wkup -> timer0 interface */
1994 static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = {
1995         {
1996                 .pa_start       = AM33XX_TIMER0_BASE,
1997                 .pa_end         = AM33XX_TIMER0_BASE + SZ_1K - 1,
1998                 .flags          = ADDR_TYPE_RT
1999         },
2000         { }
2001 };
2003 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = {
2004         .master         = &am33xx_l4wkup_hwmod,
2005         .slave          = &am33xx_timer0_hwmod,
2006         .clk            = "timer0_ick",
2007         .addr           = am33xx_timer0_addr_space,
2008         .user           = OCP_USER_MPU,
2009 };
2011 static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = {
2012         &am33xx_l4wkup__timer0,
2013 };
2015 static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = {
2016         { .irq = AM33XX_IRQ_DMTIMER0 },
2017         { .irq = -1 }
2018 };
2020 static struct omap_hwmod am33xx_timer0_hwmod = {
2021         .name           = "timer0",
2022         .class          = &am33xx_timer_hwmod_class,
2023         .mpu_irqs       = am33xx_timer0_irqs,
2024         .main_clk       = "timer0_fck",
2025         .clkdm_name     = "l4_wkup_clkdm",
2026         .prcm           = {
2027                 .omap4  = {
2028                         .clkctrl_offs   = AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET,
2029                         .modulemode     = MODULEMODE_SWCTRL,
2030                 },
2031         },
2032         .slaves         = am33xx_timer0_slaves,
2033         .slaves_cnt     = ARRAY_SIZE(am33xx_timer0_slaves),
2034 };
2036 /* timer1 1ms */
2037 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
2038         .rev_offs       = 0x0000,
2039         .sysc_offs      = 0x0010,
2040         .syss_offs      = 0x0014,
2041         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2042                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
2043                         SYSS_HAS_RESET_STATUS),
2044         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2045         .sysc_fields    = &omap_hwmod_sysc_type1,
2046 };
2048 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
2049         .name           = "timer",
2050         .sysc           = &am33xx_timer1ms_sysc,
2051 };
2053 /* l4 wkup -> timer1 interface */
2054 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
2055         {
2056                 .pa_start       = AM33XX_TIMER1_BASE,
2057                 .pa_end         = AM33XX_TIMER1_BASE + SZ_1K - 1,
2058                 .flags          = ADDR_TYPE_RT
2059         },
2060         { }
2061 };
2063 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = {
2064         .master         = &am33xx_l4wkup_hwmod,
2065         .slave          = &am33xx_timer1_hwmod,
2066         .clk            = "timer1_ick",
2067         .addr           = am33xx_timer1_addr_space,
2068         .user           = OCP_USER_MPU,
2069 };
2071 static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = {
2072         &am33xx_l4wkup__timer1,
2073 };
2075 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
2076         { .irq = AM33XX_IRQ_DMTIMER1 },
2077         { .irq = -1 }
2078 };
2080 static struct omap_hwmod am33xx_timer1_hwmod = {
2081         .name           = "timer1",
2082         .class          = &am33xx_timer1ms_hwmod_class,
2083         .mpu_irqs       = am33xx_timer1_irqs,
2084         .main_clk       = "timer1_fck",
2085         .clkdm_name     = "l4_wkup_clkdm",
2086         .prcm           = {
2087                 .omap4  = {
2088                         .clkctrl_offs   = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2089                         .modulemode     = MODULEMODE_SWCTRL,
2090                 },
2091         },
2092         .slaves         = am33xx_timer1_slaves,
2093         .slaves_cnt     = ARRAY_SIZE(am33xx_timer1_slaves),
2094 };
2096 /* timer2 */
2097 /* l4 per -> timer2 interface */
2098 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
2099         {
2100                 .pa_start       = AM33XX_TIMER2_BASE,
2101                 .pa_end         = AM33XX_TIMER2_BASE + SZ_1K - 1,
2102                 .flags          = ADDR_TYPE_RT
2103         },
2104         { }
2105 };
2107 static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = {
2108         .master         = &am33xx_l4per_hwmod,
2109         .slave          = &am33xx_timer2_hwmod,
2110         .clk            = "timer2_ick",
2111         .addr           = am33xx_timer2_addr_space,
2112         .user           = OCP_USER_MPU,
2113 };
2115 static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = {
2116         &am33xx_l4per__timer2,
2117 };
2119 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
2120         { .irq = AM33XX_IRQ_DMTIMER2 },
2121         { .irq = -1 }
2122 };
2124 static struct omap_hwmod am33xx_timer2_hwmod = {
2125         .name           = "timer2",
2126         .class          = &am33xx_timer_hwmod_class,
2127         .mpu_irqs       = am33xx_timer2_irqs,
2128         .main_clk       = "timer2_fck",
2129         .prcm           = {
2130                 .omap4  = {
2131                         .clkctrl_offs   = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
2132                         .modulemode     = MODULEMODE_SWCTRL,
2133                 },
2134         },
2135         .slaves         = am33xx_timer2_slaves,
2136         .slaves_cnt     = ARRAY_SIZE(am33xx_timer2_slaves),
2137         .clkdm_name     = "l4ls_clkdm",
2138 };
2140 /* timer3 */
2141 /* l4 per -> timer3 interface */
2142 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
2143         {
2144                 .pa_start       = AM33XX_TIMER3_BASE,
2145                 .pa_end         = AM33XX_TIMER3_BASE + SZ_1K - 1,
2146                 .flags          = ADDR_TYPE_RT
2147         },
2148         { }
2149 };
2151 static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = {
2152         .master         = &am33xx_l4per_hwmod,
2153         .slave          = &am33xx_timer3_hwmod,
2154         .clk            = "timer3_ick",
2155         .addr           = am33xx_timer3_addr_space,
2156         .user           = OCP_USER_MPU,
2157 };
2159 static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = {
2160         &am33xx_l4per__timer3,
2161 };
2163 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
2164         { .irq = AM33XX_IRQ_DMTIMER3 },
2165         { .irq = -1 }
2166 };
2168 static struct omap_hwmod am33xx_timer3_hwmod = {
2169         .name           = "timer3",
2170         .class          = &am33xx_timer_hwmod_class,
2171         .mpu_irqs       = am33xx_timer3_irqs,
2172         .main_clk       = "timer3_fck",
2173         .clkdm_name     = "l4ls_clkdm",
2174         .prcm           = {
2175                 .omap4  = {
2176                         .clkctrl_offs   = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
2177                         .modulemode     = MODULEMODE_SWCTRL,
2178                 },
2179         },
2180         .slaves         = am33xx_timer3_slaves,
2181         .slaves_cnt     = ARRAY_SIZE(am33xx_timer3_slaves),
2182 };
2184 /* timer4 */
2185 /* l4 per -> timer4 interface */
2186 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
2187         {
2188                 .pa_start       = AM33XX_TIMER4_BASE,
2189                 .pa_end         = AM33XX_TIMER4_BASE + SZ_1K - 1,
2190                 .flags          = ADDR_TYPE_RT
2191         },
2192         { }
2193 };
2195 static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = {
2196         .master         = &am33xx_l4per_hwmod,
2197         .slave          = &am33xx_timer4_hwmod,
2198         .clk            = "timer4_ick",
2199         .addr           = am33xx_timer4_addr_space,
2200         .user           = OCP_USER_MPU,
2201 };
2203 static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = {
2204         &am33xx_l4per__timer4,
2205 };
2207 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
2208         { .irq = AM33XX_IRQ_DMTIMER4 },
2209         { .irq = -1 }
2210 };
2212 static struct omap_hwmod am33xx_timer4_hwmod = {
2213         .name           = "timer4",
2214         .class          = &am33xx_timer_hwmod_class,
2215         .mpu_irqs       = am33xx_timer4_irqs,
2216         .main_clk       = "timer4_fck",
2217         .prcm           = {
2218                 .omap4  = {
2219                         .clkctrl_offs   = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
2220                         .modulemode     = MODULEMODE_SWCTRL,
2221                 },
2222         },
2223         .slaves         = am33xx_timer4_slaves,
2224         .slaves_cnt     = ARRAY_SIZE(am33xx_timer4_slaves),
2225         .clkdm_name     = "l4ls_clkdm",
2226 };
2229 /* timer5 */
2230 /* l4 per -> timer5 interface */
2231 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
2232         {
2233                 .pa_start       = AM33XX_TIMER5_BASE,
2234                 .pa_end         = AM33XX_TIMER5_BASE + SZ_1K - 1,
2235                 .flags          = ADDR_TYPE_RT
2236         },
2237         { }
2238 };
2240 static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = {
2241         .master         = &am33xx_l4per_hwmod,
2242         .slave          = &am33xx_timer5_hwmod,
2243         .clk            = "timer5_ick",
2244         .addr           = am33xx_timer5_addr_space,
2245         .user           = OCP_USER_MPU,
2246 };
2248 static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = {
2249         &am33xx_l4per__timer5,
2250 };
2252 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
2253         { .irq = AM33XX_IRQ_DMTIMER5 },
2254         { .irq = -1 }
2255 };
2257 static struct omap_hwmod am33xx_timer5_hwmod = {
2258         .name           = "timer5",
2259         .class          = &am33xx_timer_hwmod_class,
2260         .mpu_irqs       = am33xx_timer5_irqs,
2261         .main_clk       = "timer5_fck",
2262         .prcm           = {
2263                 .omap4  = {
2264                         .clkctrl_offs   = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
2265                         .modulemode     = MODULEMODE_SWCTRL,
2266                 },
2267         },
2268         .slaves         = am33xx_timer5_slaves,
2269         .slaves_cnt     = ARRAY_SIZE(am33xx_timer5_slaves),
2270         .clkdm_name     = "l4ls_clkdm",
2271 };
2273 /* timer6 */
2274 /* l4 per -> timer6 interface */
2275 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
2276         {
2277                 .pa_start       = AM33XX_TIMER6_BASE,
2278                 .pa_end         = AM33XX_TIMER6_BASE + SZ_1K - 1,
2279                 .flags          = ADDR_TYPE_RT
2280         },
2281         { }
2282 };
2284 static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = {
2285         .master         = &am33xx_l4per_hwmod,
2286         .slave          = &am33xx_timer6_hwmod,
2287         .clk            = "timer6_ick",
2288         .addr           = am33xx_timer6_addr_space,
2289         .user           = OCP_USER_MPU,
2290 };
2292 static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = {
2293         &am33xx_l4per__timer6,
2294 };
2296 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
2297         { .irq = AM33XX_IRQ_DMTIMER6 },
2298         { .irq = -1 }
2299 };
2301 static struct omap_hwmod am33xx_timer6_hwmod = {
2302         .name           = "timer6",
2303         .class          = &am33xx_timer_hwmod_class,
2304         .mpu_irqs       = am33xx_timer6_irqs,
2305         .main_clk       = "timer6_fck",
2306         .prcm           = {
2307                 .omap4  = {
2308                         .clkctrl_offs   = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
2309                         .modulemode     = MODULEMODE_SWCTRL,
2310                 },
2311         },
2312         .slaves         = am33xx_timer6_slaves,
2313         .slaves_cnt     = ARRAY_SIZE(am33xx_timer6_slaves),
2314         .clkdm_name     = "l4ls_clkdm",
2315 };
2317 /* timer7 */
2318 /* l4 per -> timer7 interface */
2319 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
2320         {
2321                 .pa_start       = AM33XX_TIMER7_BASE,
2322                 .pa_end         = AM33XX_TIMER7_BASE + SZ_1K - 1,
2323                 .flags          = ADDR_TYPE_RT
2324         },
2325         { }
2326 };
2328 static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = {
2329         .master         = &am33xx_l4per_hwmod,
2330         .slave          = &am33xx_timer7_hwmod,
2331         .clk            = "timer7_ick",
2332         .addr           = am33xx_timer7_addr_space,
2333         .user           = OCP_USER_MPU,
2334 };
2336 static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = {
2337         &am33xx_l4per__timer7,
2338 };
2340 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
2341         { .irq = AM33XX_IRQ_DMTIMER7 },
2342         { .irq = -1 }
2343 };
2345 static struct omap_hwmod am33xx_timer7_hwmod = {
2346         .name           = "timer7",
2347         .class          = &am33xx_timer_hwmod_class,
2348         .mpu_irqs       = am33xx_timer7_irqs,
2349         .main_clk       = "timer7_fck",
2350         .prcm           = {
2351                 .omap4  = {
2352                         .clkctrl_offs   = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
2353                         .modulemode     = MODULEMODE_SWCTRL,
2354                 },
2355         },
2356         .slaves         = am33xx_timer7_slaves,
2357         .slaves_cnt     = ARRAY_SIZE(am33xx_timer7_slaves),
2358         .clkdm_name     = "l4ls_clkdm",
2359 };
2361 /* 'tpcc' class */
2362 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
2363         .name           = "tpcc",
2364 };
2366 /* tpcc */
2367 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
2368         { .name = "edma0", .irq = AM33XX_IRQ_TPCC0_INT_PO0 },
2369         { .name = "edma0_err", .irq = AM33XX_IRQ_TPCC0_ERRINT_PO },
2370         { .irq = -1 },
2371 };
2373 /* TODO move this appropriate header. */
2374 #define AM33XX_TPCC_BASE                0x49000000
2376 static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
2377         {
2378                 .pa_start       = AM33XX_TPCC_BASE,
2379                 .pa_end         = AM33XX_TPCC_BASE + SZ_32K - 1,
2380                 .flags          = ADDR_TYPE_RT
2381         },
2382         { }
2383 };
2385 static struct omap_hwmod_ocp_if am33xx_l3_slow__tpcc = {
2386         .master         = &am33xx_l3slow_hwmod,
2387         .slave          = &am33xx_tpcc_hwmod,
2388         .addr           = am33xx_tpcc_addr_space,
2389         .user           = OCP_USER_MPU,
2390 };
2392 static struct omap_hwmod_ocp_if *am33xx_tpcc_slaves[] = {
2393         &am33xx_l3_slow__tpcc,
2394 };
2396 static struct omap_hwmod am33xx_tpcc_hwmod = {
2397         .name           = "tpcc",
2398         .class          = &am33xx_tpcc_hwmod_class,
2399         .mpu_irqs       = am33xx_tpcc_irqs,
2400         .main_clk       = "tpcc_ick",
2401         .clkdm_name     = "l3_clkdm",
2402         .prcm           = {
2403                 .omap4  = {
2404                         .clkctrl_offs   = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
2405                         .modulemode     = MODULEMODE_SWCTRL,
2406                 },
2407         },
2408         .slaves         = am33xx_tpcc_slaves,
2409         .slaves_cnt     = ARRAY_SIZE(am33xx_tpcc_slaves),
2410 };
2412 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
2413         .rev_offs       = 0x0,
2414         .sysc_offs      = 0x10,
2415         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2416                                 SYSC_HAS_MIDLEMODE),
2417         .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
2418         .sysc_fields    = &omap_hwmod_sysc_type2,
2419 };
2421 /* 'tptc' class */
2422 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
2423         .name           = "tptc",
2424         .sysc           = &am33xx_tptc_sysc,
2425 };
2427 /* tptc0 */
2428 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
2429         { .irq = AM33XX_IRQ_TPTC0 },
2430         { .irq = -1 }
2431 };
2433 struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
2434         {
2435                 .pa_start       = 0x49800000,
2436                 .pa_end         = 0x49800000 + SZ_8K - 1,
2437                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2438         },
2439         { }
2440 };
2442 struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
2443         .master         = &am33xx_l3_main_hwmod,
2444         .slave          = &am33xx_tptc0_hwmod,
2445         .addr           = am33xx_tptc0_addr_space,
2446         .user           = OCP_USER_MPU,
2447 };
2449 static struct omap_hwmod_ocp_if *am33xx_tptc0_slaves[] = {
2450         &am33xx_l3_main__tptc0,
2451 };
2453 static struct omap_hwmod am33xx_tptc0_hwmod = {
2454         .name           = "tptc0",
2455         .class          = &am33xx_tptc_hwmod_class,
2456         .mpu_irqs       = am33xx_tptc0_irqs,
2457         .main_clk       = "tptc0_ick",
2458         .clkdm_name     = "l3_clkdm",
2459         .prcm           = {
2460                 .omap4  = {
2461                         .clkctrl_offs   = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
2462                         .modulemode     = MODULEMODE_SWCTRL,
2463                 },
2464         },
2465         .slaves         = am33xx_tptc0_slaves,
2466         .slaves_cnt     = ARRAY_SIZE(am33xx_tptc0_slaves),
2467 };
2469 /* tptc1 */
2470 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
2471         { .irq = AM33XX_IRQ_TPTC1 },
2472         { .irq = -1 }
2473 };
2475 struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
2476         {
2477                 .pa_start       = 0x49900000,
2478                 .pa_end         = 0x49900000 + SZ_8K - 1,
2479                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2480         },
2481         { }
2482 };
2484 struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
2485         .master         = &am33xx_l3_main_hwmod,
2486         .slave          = &am33xx_tptc1_hwmod,
2487         .addr           = am33xx_tptc1_addr_space,
2488         .user           = OCP_USER_MPU,
2489 };
2491 static struct omap_hwmod_ocp_if *am33xx_tptc1_slaves[] = {
2492         &am33xx_l3_main__tptc1,
2493 };
2495 static struct omap_hwmod am33xx_tptc1_hwmod = {
2496         .name           = "tptc1",
2497         .class          = &am33xx_tptc_hwmod_class,
2498         .mpu_irqs       = am33xx_tptc1_irqs,
2499         .main_clk       = "tptc1_ick",
2500         .clkdm_name     = "l3_clkdm",
2501         .prcm           = {
2502                 .omap4  = {
2503                         .clkctrl_offs   = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
2504                         .modulemode     = MODULEMODE_SWCTRL,
2505                 },
2506         },
2507         .slaves         = am33xx_tptc1_slaves,
2508         .slaves_cnt     = ARRAY_SIZE(am33xx_tptc1_slaves),
2509 };
2511 /* tptc2 */
2512 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
2513         { .irq = AM33XX_IRQ_TPTC2 },
2514         { .irq = -1 }
2515 };
2517 struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
2518         {
2519                 .pa_start       = 0x49a00000,
2520                 .pa_end         = 0x49a00000 + SZ_8K - 1,
2521                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2522         },
2523         { }
2524 };
2526 struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
2527         .master         = &am33xx_l3_main_hwmod,
2528         .slave          = &am33xx_tptc2_hwmod,
2529         .addr           = am33xx_tptc2_addr_space,
2530         .user           = OCP_USER_MPU,
2531 };
2533 static struct omap_hwmod_ocp_if *am33xx_tptc2_slaves[] = {
2534         &am33xx_l3_main__tptc2,
2535 };
2537 static struct omap_hwmod am33xx_tptc2_hwmod = {
2538         .name           = "tptc2",
2539         .class          = &am33xx_tptc_hwmod_class,
2540         .mpu_irqs       = am33xx_tptc2_irqs,
2541         .main_clk       = "tptc2_ick",
2542         .clkdm_name     = "l3_clkdm",
2543         .prcm           = {
2544                 .omap4  = {
2545                         .clkctrl_offs   = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
2546                         .modulemode     = MODULEMODE_SWCTRL,
2547                 },
2548         },
2549         .slaves         = am33xx_tptc2_slaves,
2550         .slaves_cnt     = ARRAY_SIZE(am33xx_tptc2_slaves),
2551 };
2553 /* 'uart' class */
2554 static struct omap_hwmod_class_sysconfig uart_sysc = {
2555         .rev_offs       = 0x50,
2556         .sysc_offs      = 0x54,
2557         .syss_offs      = 0x58,
2558         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
2559                         SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2560                         SYSC_HAS_AUTOIDLE),
2561         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2562                         SIDLE_SMART_WKUP),
2563         .sysc_fields    = &omap_hwmod_sysc_type1,
2564 };
2566 static struct omap_hwmod_class uart_class = {
2567         .name           = "uart",
2568         .sysc           = &uart_sysc,
2569 };
2571 /* uart1 */
2572 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
2573         { .name = "tx", .dma_req = 26, },
2574         { .name = "rx", .dma_req = 27, },
2575         { .dma_req = -1 }
2576 };
2578 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
2579         {
2580                 .pa_start       = AM33XX_UART1_BASE,
2581                 .pa_end         = AM33XX_UART1_BASE + SZ_8K - 1,
2582                 .flags          = ADDR_TYPE_RT
2583         },
2584         { }
2585 };
2587 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
2588         .master         = &am33xx_l4wkup_hwmod,
2589         .slave          = &am33xx_uart1_hwmod,
2590         .clk            = "uart1_ick",
2591         .addr           = am33xx_uart1_addr_space,
2592         .user           = OCP_USER_MPU,
2593 };
2595 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
2596         { .irq = AM33XX_IRQ_UART0 },
2597         { .irq = -1 }
2598 };
2600 static struct omap_hwmod_ocp_if *am33xx_uart1_slaves[] = {
2601         &am33xx_l4_wkup__uart1,
2602 };
2604 static struct omap_hwmod am33xx_uart1_hwmod = {
2605         .name           = "uart1",
2606         .class          = &uart_class,
2607         .mpu_irqs       = am33xx_uart1_irqs,
2608         .sdma_reqs      = uart1_edma_reqs,
2609         .main_clk       = "uart1_fck",
2610         .clkdm_name     = "l4_wkup_clkdm",
2611         .prcm           = {
2612                 .omap4  = {
2613                         .clkctrl_offs   = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
2614                         .modulemode     = MODULEMODE_SWCTRL,
2615                 },
2616         },
2617         .slaves         = am33xx_uart1_slaves,
2618         .slaves_cnt     = ARRAY_SIZE(am33xx_uart1_slaves),
2619 };
2621 /* uart2 */
2622 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
2623         {
2624                 .pa_start       = AM33XX_UART2_BASE,
2625                 .pa_end         = AM33XX_UART2_BASE + SZ_8K - 1,
2626                 .flags          = ADDR_TYPE_RT
2627         },
2628         { }
2629 };
2631 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
2632         .slave          = &am33xx_uart2_hwmod,
2633         .clk            = "uart2_ick",
2634         .addr           = am33xx_uart2_addr_space,
2635         .user           = OCP_USER_MPU,
2636 };
2638 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
2639         { .irq = AM33XX_IRQ_UART1 },
2640         { .irq = -1 }
2641 };
2643 static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = {
2644         &am33xx_l4_ls__uart2,
2645 };
2647 static struct omap_hwmod am33xx_uart2_hwmod = {
2648         .name           = "uart2",
2649         .class          = &uart_class,
2650         .mpu_irqs       = am33xx_uart2_irqs,
2651         .main_clk       = "uart2_fck",
2652         .clkdm_name     = "l4ls_clkdm",
2653         .sdma_reqs      = uart1_edma_reqs,
2654         .prcm           = {
2655                 .omap4  = {
2656                         .clkctrl_offs   = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
2657                         .modulemode     = MODULEMODE_SWCTRL,
2658                 },
2659         },
2660         .slaves         = am33xx_uart2_slaves,
2661         .slaves_cnt     = ARRAY_SIZE(am33xx_uart2_slaves),
2662 };
2664 /* uart3 */
2665 static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
2666         { .name = "tx", .dma_req = 30, },
2667         { .name = "rx", .dma_req = 31, },
2668         { .dma_req = -1 }
2669 };
2671 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
2672         {
2673                 .pa_start       = AM33XX_UART3_BASE,
2674                 .pa_end         = AM33XX_UART3_BASE + SZ_8K - 1,
2675                 .flags          = ADDR_TYPE_RT
2676         },
2677         { }
2678 };
2680 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
2681         .slave          = &am33xx_uart3_hwmod,
2682         .clk            = "uart3_ick",
2683         .addr           = am33xx_uart3_addr_space,
2684         .user           = OCP_USER_MPU,
2685 };
2687 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2688         { .irq = AM33XX_IRQ_UART2 },
2689         { .irq = -1 }
2690 };
2692 static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = {
2693         &am33xx_l4_ls__uart3,
2694 };
2696 static struct omap_hwmod am33xx_uart3_hwmod = {
2697         .name           = "uart3",
2698         .class          = &uart_class,
2699         .mpu_irqs       = am33xx_uart3_irqs,
2700         .main_clk       = "uart3_fck",
2701         .clkdm_name     = "l4ls_clkdm",
2702         .sdma_reqs      = uart3_edma_reqs,
2703         .prcm           = {
2704                 .omap4  = {
2705                         .clkctrl_offs   = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
2706                         .modulemode     = MODULEMODE_SWCTRL,
2707                 },
2708         },
2709         .slaves         = am33xx_uart3_slaves,
2710         .slaves_cnt     = ARRAY_SIZE(am33xx_uart3_slaves),
2711 };
2713 /* uart4 */
2714 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
2715         {
2716                 .pa_start       = AM33XX_UART4_BASE,
2717                 .pa_end         = AM33XX_UART4_BASE + SZ_8K - 1,
2718                 .flags          = ADDR_TYPE_RT
2719         },
2720         { }
2721 };
2723 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
2724         .slave          = &am33xx_uart4_hwmod,
2725         .clk            = "uart4_ick",
2726         .addr           = am33xx_uart4_addr_space,
2727         .user           = OCP_USER_MPU,
2728 };
2730 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2731         { .irq = AM33XX_IRQ_UART3 },
2732         { .irq = -1 }
2733 };
2735 static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = {
2736         &am33xx_l4_ls__uart4,
2737 };
2739 static struct omap_hwmod am33xx_uart4_hwmod = {
2740         .name           = "uart4",
2741         .class          = &uart_class,
2742         .mpu_irqs       = am33xx_uart4_irqs,
2743         .main_clk       = "uart4_fck",
2744         .clkdm_name     = "l4ls_clkdm",
2745         .sdma_reqs      = uart1_edma_reqs,
2746         .prcm           = {
2747                 .omap4  = {
2748                         .clkctrl_offs   = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
2749                         .modulemode     = MODULEMODE_SWCTRL,
2750                 },
2751         },
2752         .slaves         = am33xx_uart4_slaves,
2753         .slaves_cnt     = ARRAY_SIZE(am33xx_uart4_slaves),
2754 };
2756 /* uart5 */
2757 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
2758         {
2759                 .pa_start       = AM33XX_UART5_BASE,
2760                 .pa_end         = AM33XX_UART5_BASE + SZ_8K - 1,
2761                 .flags          = ADDR_TYPE_RT
2762         },
2763         { }
2764 };
2766 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
2767         .slave          = &am33xx_uart5_hwmod,
2768         .clk            = "uart5_ick",
2769         .addr           = am33xx_uart5_addr_space,
2770         .user           = OCP_USER_MPU,
2771 };
2773 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2774         { .irq = AM33XX_IRQ_UART4 },
2775         { .irq = -1 }
2776 };
2778 static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = {
2779         &am33xx_l4_ls__uart5,
2780 };
2782 static struct omap_hwmod am33xx_uart5_hwmod = {
2783         .name           = "uart5",
2784         .class          = &uart_class,
2785         .mpu_irqs       = am33xx_uart5_irqs,
2786         .main_clk       = "uart5_fck",
2787         .clkdm_name     = "l4ls_clkdm",
2788         .sdma_reqs      = uart1_edma_reqs,
2789         .prcm           = {
2790                 .omap4  = {
2791                         .clkctrl_offs   = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2792                         .modulemode     = MODULEMODE_SWCTRL,
2793                 },
2794         },
2795         .slaves         = am33xx_uart5_slaves,
2796         .slaves_cnt     = ARRAY_SIZE(am33xx_uart5_slaves),
2797 };
2799 /* uart6 */
2800 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
2801         {
2802                 .pa_start       = AM33XX_UART6_BASE,
2803                 .pa_end         = AM33XX_UART6_BASE + SZ_8K - 1,
2804                 .flags          = ADDR_TYPE_RT
2805         },
2806         { }
2807 };
2809 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
2810         .slave          = &am33xx_uart6_hwmod,
2811         .clk            = "uart6_ick",
2812         .addr           = am33xx_uart6_addr_space,
2813         .user           = OCP_USER_MPU,
2814 };
2816 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2817         { .irq = AM33XX_IRQ_UART5 },
2818         { .irq = -1 }
2819 };
2821 static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = {
2822         &am33xx_l4_ls__uart6,
2823 };
2825 static struct omap_hwmod am33xx_uart6_hwmod = {
2826         .name           = "uart6",
2827         .class          = &uart_class,
2828         .mpu_irqs       = am33xx_uart6_irqs,
2829         .main_clk       = "uart6_fck",
2830         .clkdm_name     = "l4ls_clkdm",
2831         .sdma_reqs      = uart1_edma_reqs,
2832         .prcm           = {
2833                 .omap4  = {
2834                         .clkctrl_offs   = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2835                         .modulemode     = MODULEMODE_SWCTRL,
2836                 },
2837         },
2838         .slaves         = am33xx_uart6_slaves,
2839         .slaves_cnt     = ARRAY_SIZE(am33xx_uart6_slaves),
2840 };
2842 /* 'wd_timer' class */
2843 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2844         .name           = "wd_timer",
2845 };
2847 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
2848         {
2849                 .pa_start       = AM33XX_WDT1_BASE,
2850                 .pa_end         = AM33XX_WDT1_BASE + SZ_4K - 1,
2851                 .flags          = ADDR_TYPE_RT
2852         },
2853         { }
2854 };
2856 /* l4_wkup -> wd_timer1 */
2857 static struct omap_hwmod_ocp_if am33xx_l4wkup__wd_timer1 = {
2858         .master         = &am33xx_l4wkup_hwmod,
2859         .slave          = &am33xx_wd_timer1_hwmod,
2860         .addr           = am33xx_wd_timer1_addrs,
2861         .user           = OCP_USER_MPU,
2862 };
2864 /* wd_timer1 slave ports */
2865 static struct omap_hwmod_ocp_if *am33xx_wd_timer1_slaves[] = {
2866         &am33xx_l4wkup__wd_timer1,
2867 };
2869 /* wd_timer1 */
2870 /*
2871  * TODO: device.c file uses hardcoded name for watchdog
2872          timer driver "wd_timer2, so we are also using
2873          same name as of now...
2874  */
2875 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2876         .name           = "wd_timer2",
2877         .class          = &am33xx_wd_timer_hwmod_class,
2878         .main_clk       = "wd_timer1_fck",
2879         .clkdm_name     = "l4_wkup_clkdm",
2880         .prcm           = {
2881                 .omap4  = {
2882                         .clkctrl_offs   = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2883                         .modulemode     = MODULEMODE_SWCTRL,
2884                 },
2885         },
2886         .slaves         = am33xx_wd_timer1_slaves,
2887         .slaves_cnt     = ARRAY_SIZE(am33xx_wd_timer1_slaves),
2888 };
2890 /* wdt0 */
2891 static struct omap_hwmod_irq_info am33xx_wdt0_irqs[] = {
2892         { .irq = AM33XX_IRQ_WDT0 },
2893         { .irq = -1 },
2894 };
2896 static struct omap_hwmod am33xx_wdt0_hwmod = {
2897         .name           = "wdt0",
2898         .class          = &am33xx_wd_timer_hwmod_class,
2899         .mpu_irqs       = am33xx_wdt0_irqs,
2900         .main_clk       = "wdt0_fck",
2901         .clkdm_name     = "l4_wkup_clkdm",
2902         .prcm           = {
2903                 .omap4  = {
2904                         .clkctrl_offs   = AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET,
2905                         .modulemode     = MODULEMODE_SWCTRL,
2906                 },
2907         },
2908 };
2910 /* 'wkup_m3' class */
2911 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
2912         .name           = "wkup_m3",
2913 };
2915 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
2916         { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
2917 };
2919 /* wkup_m3 */
2920 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
2921         .name           = "wkup_m3",
2922         .class          = &am33xx_wkup_m3_hwmod_class,
2923         .clkdm_name     = "l4_wkup_aon_clkdm",
2924         .main_clk       = "wkup_m3_fck",
2925         .rst_lines      = am33xx_wkup_m3_resets,
2926         .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
2927         .prcm           = {
2928                 .omap4  = {
2929                         .clkctrl_offs   = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
2930                         .rstctrl_offs   = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
2931                         .modulemode     = MODULEMODE_SWCTRL,
2932                 },
2933         },
2934         .flags          = HWMOD_INIT_NO_RESET,  /* Keep hardreset asserted */
2935 };
2937 /* L3 SLOW -> USBSS interface */
2938 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
2939         {
2940                 .name           = "usbss",
2941                 .pa_start       = AM33XX_USBSS_BASE,
2942                 .pa_end         = AM33XX_USBSS_BASE + SZ_4K - 1,
2943                 .flags          = ADDR_TYPE_RT
2944         },
2945         {
2946                 .name           = "musb0",
2947                 .pa_start       = AM33XX_USB0_BASE,
2948                 .pa_end         = AM33XX_USB0_BASE + SZ_2K - 1,
2949                 .flags          = ADDR_TYPE_RT
2950         },
2951         {
2952                 .name           = "musb1",
2953                 .pa_start       = AM33XX_USB1_BASE,
2954                 .pa_end         = AM33XX_USB1_BASE + SZ_2K - 1,
2955                 .flags          = ADDR_TYPE_RT
2956         },
2957         { }
2958 };
2960 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2961         .rev_offs       = 0x0,
2962         .sysc_offs      = 0x10,
2963         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
2964         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2965                                 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2966         .sysc_fields    = &omap_hwmod_sysc_type4,
2967 };
2969 static struct omap_hwmod_class am33xx_usbotg_class = {
2970         .name           = "usbotg",
2971         .sysc           = &am33xx_usbhsotg_sysc,
2972 };
2974 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2975         { .name = "usbss-irq", .irq = AM33XX_IRQ_USBSS, },
2976         { .name = "musb0-irq", .irq = AM33XX_IRQ_USB0, },
2977         { .name = "musb1-irq", .irq = AM33XX_IRQ_USB1, },
2978         { .irq = -1, },
2979 };
2981 static struct omap_hwmod_ocp_if am33xx_l3_slow__usbss = {
2982         .master         = &am33xx_l3slow_hwmod,
2983         .slave          = &am33xx_usbss_hwmod,
2984         .addr           = am33xx_usbss_addr_space,
2985         .user           = OCP_USER_MPU,
2986         .flags          = OCPIF_SWSUP_IDLE,
2987 };
2989 static struct omap_hwmod_ocp_if *am33xx_usbss_slaves[] = {
2990         &am33xx_l3_slow__usbss,
2991 };
2993 static struct omap_hwmod_opt_clk usbss_opt_clks[] = {
2994         { .role = "clkdcoldo", .clk = "usbotg_fck" },
2995 };
2997 static struct omap_hwmod am33xx_usbss_hwmod = {
2998         .name           = "usb_otg_hs",
2999         .mpu_irqs       = am33xx_usbss_mpu_irqs,