f9b91fa988511b0110522033527e02fd86b5dc52
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / omap_hwmod_33xx_data.c
1 /*
2  * Hardware modules present on the AM33XX chips
3  *
4  * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
5  *
6  * This file is automatically generated from the AM33XX hardware databases.
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation version 2.
10  *
11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12  * kind, whether express or implied; without even the implied warranty
13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  */
17 #include <linux/io.h>
19 #include <plat/omap_hwmod.h>
20 #include <plat/i2c.h>
21 #include <plat/cpu.h>
22 #include <plat/gpio.h>
23 #include <plat/dma.h>
24 #include <plat/mmc.h>
25 #include <plat/mcspi.h>
27 #include "omap_hwmod_common_data.h"
28 #include "control.h"
29 #include "cm33xx.h"
30 #include "prm33xx.h"
32 /* Backward references (IPs with Bus Master capability) */
33 static struct omap_hwmod am33xx_mpu_hwmod;
34 static struct omap_hwmod am33xx_l3_main_hwmod;
35 static struct omap_hwmod am33xx_l3slow_hwmod;
36 static struct omap_hwmod am33xx_l4wkup_hwmod;
37 static struct omap_hwmod am33xx_l4per_hwmod;
38 static struct omap_hwmod am33xx_uart1_hwmod;
39 static struct omap_hwmod am33xx_uart2_hwmod;
40 static struct omap_hwmod am33xx_uart3_hwmod;
41 static struct omap_hwmod am33xx_uart4_hwmod;
42 static struct omap_hwmod am33xx_uart5_hwmod;
43 static struct omap_hwmod am33xx_uart6_hwmod;
44 static struct omap_hwmod am33xx_timer0_hwmod;
45 static struct omap_hwmod am33xx_timer1_hwmod;
46 static struct omap_hwmod am33xx_timer2_hwmod;
47 static struct omap_hwmod am33xx_timer3_hwmod;
48 static struct omap_hwmod am33xx_timer4_hwmod;
49 static struct omap_hwmod am33xx_timer5_hwmod;
50 static struct omap_hwmod am33xx_timer6_hwmod;
51 static struct omap_hwmod am33xx_timer7_hwmod;
52 static struct omap_hwmod am33xx_wd_timer1_hwmod;
53 static struct omap_hwmod am33xx_cpgmac0_hwmod;
54 static struct omap_hwmod am33xx_icss_hwmod;
55 static struct omap_hwmod am33xx_ieee5000_hwmod;
56 static struct omap_hwmod am33xx_tptc0_hwmod;
57 static struct omap_hwmod am33xx_tptc1_hwmod;
58 static struct omap_hwmod am33xx_tptc2_hwmod;
59 static struct omap_hwmod am33xx_gpio0_hwmod;
60 static struct omap_hwmod am33xx_gpio1_hwmod;
61 static struct omap_hwmod am33xx_gpio2_hwmod;
62 static struct omap_hwmod am33xx_gpio3_hwmod;
63 static struct omap_hwmod am33xx_i2c1_hwmod;
64 static struct omap_hwmod am33xx_i2c2_hwmod;
65 static struct omap_hwmod am33xx_i2c3_hwmod;
66 static struct omap_hwmod am33xx_usbss_hwmod;
67 static struct omap_hwmod am33xx_mmc0_hwmod;
68 static struct omap_hwmod am33xx_mmc1_hwmod;
69 static struct omap_hwmod am33xx_mmc2_hwmod;
70 static struct omap_hwmod am33xx_spi0_hwmod;
71 static struct omap_hwmod am33xx_spi1_hwmod;
72 static struct omap_hwmod am33xx_elm_hwmod;
73 static struct omap_hwmod am33xx_adc_tsc_hwmod;
74 static struct omap_hwmod am33xx_tpcc_hwmod;
75 static struct omap_hwmod am33xx_mcasp0_hwmod;
76 static struct omap_hwmod am33xx_mcasp1_hwmod;
77 static struct omap_hwmod am33xx_epwmss0_hwmod;
78 static struct omap_hwmod am33xx_epwmss1_hwmod;
79 static struct omap_hwmod am33xx_epwmss2_hwmod;
80 static struct omap_hwmod am33xx_gpmc_hwmod;
81 static struct omap_hwmod am33xx_lcdc_hwmod;
83 /*
84  * Interconnects hwmod structures
85  * hwmods that compose the global AM33XX OCP interconnect
86  */
88 /* MPU -> L3_SLOW Peripheral interface */
89 static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = {
90         .master         = &am33xx_mpu_hwmod,
91         .slave          = &am33xx_l3slow_hwmod,
92         .user           = OCP_USER_MPU,
93 };
95 /* L3 SLOW -> L4_PER Peripheral interface */
96 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = {
97         .master         = &am33xx_l3slow_hwmod,
98         .slave          = &am33xx_l4per_hwmod,
99         .user           = OCP_USER_MPU,
100 };
102 /* L3 SLOW -> L4_WKUP Peripheral interface */
103 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = {
104         .master         = &am33xx_l3slow_hwmod,
105         .slave          = &am33xx_l4wkup_hwmod,
106         .user           = OCP_USER_MPU,
107 };
109 /* Master interfaces on the L4_WKUP interconnect */
110 static struct omap_hwmod_ocp_if *am33xx_l3_slow_masters[] = {
111         &am33xx_l3_slow__l4_per,
112         &am33xx_l3_slow__l4_wkup,
113 };
115 /* Slave interfaces on the L3_SLOW interconnect */
116 static struct omap_hwmod_ocp_if *am33xx_l3_slow_slaves[] = {
117         &am33xx_mpu__l3_slow,
118 };
120 static struct omap_hwmod am33xx_l3slow_hwmod = {
121         .name           = "l3_slow",
122         .class          = &l3_hwmod_class,
123         .clkdm_name     = "l3s_clkdm",
124         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
125         .masters        = am33xx_l3_slow_masters,
126         .masters_cnt    = ARRAY_SIZE(am33xx_l3_slow_masters),
127         .slaves         = am33xx_l3_slow_slaves,
128         .slaves_cnt     = ARRAY_SIZE(am33xx_l3_slow_slaves),
129 };
131 /* L4 PER -> GPIO2 */
132 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
133         {
134                 .pa_start       = AM33XX_GPIO1_BASE,
135                 .pa_end         = AM33XX_GPIO1_BASE + SZ_4K - 1,
136                 .flags          = ADDR_TYPE_RT
137         },
138         { }
139 };
141 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
142         .master         = &am33xx_l4per_hwmod,
143         .slave          = &am33xx_gpio1_hwmod,
144         .clk            = "l4ls_fck",
145         .addr           = am33xx_gpio1_addrs,
146         .user           = OCP_USER_MPU | OCP_USER_SDMA,
147 };
149 /* L4 PER -> GPIO3 */
150 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
151         {
152                 .pa_start       = AM33XX_GPIO2_BASE,
153                 .pa_end         = AM33XX_GPIO2_BASE + SZ_4K - 1,
154                 .flags          = ADDR_TYPE_RT
155         },
156         { }
157 };
159 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
160         .master         = &am33xx_l4per_hwmod,
161         .slave          = &am33xx_gpio2_hwmod,
162         .clk            = "l4ls_fck",
163         .addr           = am33xx_gpio2_addrs,
164         .user           = OCP_USER_MPU | OCP_USER_SDMA,
165 };
167 /* L4 PER -> GPIO4 */
168 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
169         {
170                 .pa_start       = AM33XX_GPIO3_BASE,
171                 .pa_end         = AM33XX_GPIO3_BASE + SZ_4K - 1,
172                 .flags          = ADDR_TYPE_RT
173         },
174         { }
175 };
177 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
178         .master         = &am33xx_l4per_hwmod,
179         .slave          = &am33xx_gpio3_hwmod,
180         .clk            = "l4ls_fck",
181         .addr           = am33xx_gpio3_addrs,
182         .user           = OCP_USER_MPU | OCP_USER_SDMA,
183 };
185 /* Master interfaces on the L4_PER interconnect */
186 static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = {
187         &am33xx_l4_per__gpio1,
188         &am33xx_l4_per__gpio2,
189         &am33xx_l4_per__gpio3,
190 };
191 /* Slave interfaces on the L4_PER interconnect */
192 static struct omap_hwmod_ocp_if *am33xx_l4_per_slaves[] = {
193         &am33xx_l3_slow__l4_per,
194 };
196 static struct omap_hwmod am33xx_l4per_hwmod = {
197         .name           = "l4_per",
198         .class          = &l4_hwmod_class,
199         .clkdm_name     = "l4ls_clkdm",
200         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
201         .masters        = am33xx_l4_per_masters,
202         .masters_cnt    = ARRAY_SIZE(am33xx_l4_per_masters),
203         .slaves         = am33xx_l4_per_slaves,
204         .slaves_cnt     = ARRAY_SIZE(am33xx_l4_per_slaves),
205 };
207 /* L4 WKUP -> I2C1 */
208 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
209         {
210                 .pa_start       = AM33XX_I2C0_BASE,
211                 .pa_end         = AM33XX_I2C0_BASE + SZ_4K - 1,
212                 .flags          = ADDR_TYPE_RT
213         },
214         { }
215 };
217 static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = {
218         .master         = &am33xx_l4wkup_hwmod,
219         .slave          = &am33xx_i2c1_hwmod,
220         .addr           = am33xx_i2c1_addr_space,
221         .user           = OCP_USER_MPU,
222 };
224 /* L4 WKUP -> GPIO1 */
225 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
226         {
227                 .pa_start       = AM33XX_GPIO0_BASE,
228                 .pa_end         = AM33XX_GPIO0_BASE + SZ_4K - 1,
229                 .flags          = ADDR_TYPE_RT
230         },
231         { }
232 };
234 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
235         .master         = &am33xx_l4wkup_hwmod,
236         .slave          = &am33xx_gpio0_hwmod,
237         .clk            = "l4ls_fck",
238         .addr           = am33xx_gpio0_addrs,
239         .user           = OCP_USER_MPU | OCP_USER_SDMA,
240 };
242 /* L4 WKUP -> ADC_TSC */
243 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
244         {
245                 .pa_start       = AM33XX_TSC_BASE,
246                 .pa_end         = AM33XX_TSC_BASE + SZ_8K - 1,
247                 .flags          = ADDR_TYPE_RT
248         },
249         { }
250 };
252 static struct omap_hwmod_ocp_if am33xx_l4_wkup_adc_tsc = {
253         .master         = &am33xx_l4wkup_hwmod,
254         .slave          = &am33xx_adc_tsc_hwmod,
255         .addr           = am33xx_adc_tsc_addrs,
256         .user           = OCP_USER_MPU,
257 };
259 /* Master interfaces on the L4_WKUP interconnect */
260 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = {
261         &am33xx_l4_wkup__gpio0,
262 };
263 /* Slave interfaces on the L4_WKUP interconnect */
264 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_slaves[] = {
265         &am33xx_l3_slow__l4_wkup,
266 };
268 static struct omap_hwmod am33xx_l4wkup_hwmod = {
269         .name           = "l4_wkup",
270         .class          = &l4_hwmod_class,
271         .clkdm_name     = "l4_wkup_clkdm",
272         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
273         .masters        = am33xx_l4_wkup_masters,
274         .masters_cnt    = ARRAY_SIZE(am33xx_l4_wkup_masters),
275         .slaves         = am33xx_l4_wkup_slaves,
276         .slaves_cnt     = ARRAY_SIZE(am33xx_l4_wkup_slaves),
277 };
279 /* 'adc_tsc' class */
280 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
281         .name           = "adc_tsc",
282 };
284 /* adc_tsc */
285 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
286         { .irq = AM33XX_IRQ_TSC },
287         { .irq = -1 }
288 };
290 static struct omap_hwmod_ocp_if *am33xx_adc_tsc_slaves[] = {
291         &am33xx_l4_wkup_adc_tsc,
292 };
294 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
295         .name           = "adc_tsc",
296         .class          = &am33xx_adc_tsc_hwmod_class,
297         .mpu_irqs       = am33xx_adc_tsc_irqs,
298         .main_clk       = "adc_tsc_fck",
299         .clkdm_name     = "l4_wkup_clkdm",
300         .prcm           = {
301                 .omap4  = {
302                         .clkctrl_offs   = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
303                         .modulemode     = MODULEMODE_SWCTRL,
304                 },
305         },
306         .flags          = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
307         .slaves         = am33xx_adc_tsc_slaves,
308         .slaves_cnt     = ARRAY_SIZE(am33xx_adc_tsc_slaves),
309 };
311 /* 'aes' class */
312 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
313         .name           = "aes",
314 };
316 /* aes0 */
317 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
318         { .irq = AM33XX_IRQ_AESEIP36t0_S },
319         { .irq = -1 }
320 };
322 static struct omap_hwmod am33xx_aes0_hwmod = {
323         .name           = "aes0",
324         .class          = &am33xx_aes_hwmod_class,
325         .mpu_irqs       = am33xx_aes0_irqs,
326         .main_clk       = "aes0_fck",
327         .clkdm_name     = "l3_clkdm",
328         .prcm           = {
329                 .omap4  = {
330                         .clkctrl_offs   = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
331                         .modulemode     = MODULEMODE_SWCTRL,
332                 },
333         },
334 };
336 /* 'cefuse' class */
337 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
338         .name           = "cefuse",
339 };
341 /* cefuse */
342 static struct omap_hwmod am33xx_cefuse_hwmod = {
343         .name           = "cefuse",
344         .class          = &am33xx_cefuse_hwmod_class,
345         .main_clk       = "cefuse_fck",
346         .clkdm_name     = "l4_cefuse_clkdm",
347         .prcm           = {
348                 .omap4  = {
349                         .clkctrl_offs   = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
350                         .modulemode     = MODULEMODE_SWCTRL,
351                 },
352         },
353 };
355 /* 'clkdiv32k' class */
356 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
357         .name           = "clkdiv32k",
358 };
360 /* clkdiv32k */
361 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
362         .name           = "clkdiv32k",
363         .class          = &am33xx_clkdiv32k_hwmod_class,
364         .main_clk       = "clkdiv32k_fck",
365         .clkdm_name     = "clk_24mhz_clkdm",
366         .prcm           = {
367                 .omap4  = {
368                         .clkctrl_offs   = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
369                         .modulemode     = MODULEMODE_SWCTRL,
370                 },
371         },
372 };
374 /* 'control' class */
375 static struct omap_hwmod_class am33xx_control_hwmod_class = {
376         .name           = "control",
377 };
379 /* control */
380 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
381         { .irq = AM33XX_IRQ_CONTROL_PLATFORM },
382         { .irq = -1 }
383 };
385 static struct omap_hwmod am33xx_control_hwmod = {
386         .name           = "control",
387         .class          = &am33xx_control_hwmod_class,
388         .mpu_irqs       = am33xx_control_irqs,
389         .main_clk       = "control_fck",
390         .clkdm_name     = "l4_wkup_clkdm",
391         .prcm           = {
392                 .omap4  = {
393                         .clkctrl_offs   = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
394                         .modulemode     = MODULEMODE_SWCTRL,
395                 },
396         },
397         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
398 };
400 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
401         .rev_offs       = 0x0,
402         .sysc_offs      = 0x8,
403         .syss_offs      = 0x4,
404         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE
405                                 | SYSS_HAS_RESET_STATUS),
406         .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
407                                 MSTANDBY_FORCE | MSTANDBY_NO),
408         .sysc_fields    = &omap_hwmod_sysc_type3,
409 };
411 /* 'cpgmac' class */
412 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
413         .name           = "cpgmac0",
414         .sysc           = &am33xx_cpgmac_sysc,
415 };
417 /* cpgmac0 - has 4 IRQs */
418 #if 0
419 static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
420         { .irq = AM33XX_IRQ_TPTC0 },
421         { .irq = -1 }
422 };
423 #endif
425 struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
426         {
427                 .pa_start       = AM33XX_CPSW_SS_BASE,
428                 .pa_end         = AM33XX_CPSW_SS_BASE + SZ_8K - 1,
429                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
430         },
431         { }
432 };
434 struct omap_hwmod_ocp_if am33xx_l3_main__cpgmac0 = {
435         .master         = &am33xx_l3_main_hwmod,
436         .slave          = &am33xx_cpgmac0_hwmod,
437         .addr           = am33xx_cpgmac0_addr_space,
438         .user           = OCP_USER_MPU,
439 };
441 static struct omap_hwmod_ocp_if *am33xx_cpgmac0_slaves[] = {
442         &am33xx_l3_main__cpgmac0,
443 };
445 /* cpgmac0 */
446 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
447         .name           = "cpgmac0",
448         .class          = &am33xx_cpgmac0_hwmod_class,
449         .main_clk       = "cpgmac0_fck",
450         .clkdm_name     = "cpsw_125mhz_clkdm",
451         .prcm           = {
452                 .omap4  = {
453                         .clkctrl_offs   = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
454                         .modulemode     = MODULEMODE_SWCTRL,
455                 },
456         },
457         .slaves         = am33xx_cpgmac0_slaves,
458         .slaves_cnt     = ARRAY_SIZE(am33xx_cpgmac0_slaves),
459 };
461 /* 'dcan' class */
462 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
463         .name           = "dcan",
464 };
466 /* dcan0 */
467 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
468         { .irq = AM33XX_IRQ_DCAN0_0 },
469         { .irq = -1 }
470 };
472 static struct omap_hwmod am33xx_dcan0_hwmod = {
473         .name           = "dcan0",
474         .class          = &am33xx_dcan_hwmod_class,
475         .mpu_irqs       = am33xx_dcan0_irqs,
476         .main_clk       = "dcan0_fck",
477         .clkdm_name     = "l4ls_clkdm",
478         .prcm           = {
479                 .omap4  = {
480                         .clkctrl_offs   = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
481                         .modulemode     = MODULEMODE_SWCTRL,
482                 },
483         },
484 };
486 /* dcan1 */
487 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
488         { .irq = AM33XX_IRQ_DCAN1_0 },
489         { .irq = -1 }
490 };
491 static struct omap_hwmod am33xx_dcan1_hwmod = {
492         .name           = "dcan1",
493         .class          = &am33xx_dcan_hwmod_class,
494         .mpu_irqs       = am33xx_dcan1_irqs,
495         .main_clk       = "dcan1_fck",
496         .clkdm_name     = "l4ls_clkdm",
497         .prcm           = {
498                 .omap4  = {
499                         .clkctrl_offs   = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
500                         .modulemode     = MODULEMODE_SWCTRL,
501                 },
502         },
503 };
505 /* 'debugss' class */
506 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
507         .name           = "debugss",
508 };
510 /* debugss */
511 static struct omap_hwmod am33xx_debugss_hwmod = {
512         .name           = "debugss",
513         .class          = &am33xx_debugss_hwmod_class,
514         .main_clk       = "debugss_fck",
515         .clkdm_name     = "l3_aon_clkdm",
516         .prcm           = {
517                 .omap4  = {
518                         .clkctrl_offs   = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
519                         .modulemode     = MODULEMODE_SWCTRL,
520                 },
521         },
522 #ifdef CONFIG_DEBUG_JTAG_ENABLE
523         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
524 #endif
525 };
527 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
528         .rev_offs       = 0x0000,
529         .sysc_offs      = 0x0010,
530         .syss_offs      = 0x0014,
531         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
532                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
533                         SYSS_HAS_RESET_STATUS),
534         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
535         .sysc_fields    = &omap_hwmod_sysc_type1,
536 };
537 /* 'elm' class */
538 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
539         .name           = "elm",
540         .sysc           = &am33xx_elm_sysc,
541 };
543 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
544         { .irq = AM33XX_IRQ_ELM },
545         { .irq = -1 }
546 };
548 struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
549         {
550                 .pa_start       = AM33XX_ELM_BASE,
551                 .pa_end         = AM33XX_ELM_BASE + SZ_8K - 1,
552                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
553         },
554         { }
555 };
557 struct omap_hwmod_ocp_if am33xx_l4_core__elm = {
558         .master         = &am33xx_l4per_hwmod,
559         .slave          = &am33xx_elm_hwmod,
560         .addr           = am33xx_elm_addr_space,
561         .user           = OCP_USER_MPU,
562 };
564 static struct omap_hwmod_ocp_if *am33xx_elm_slaves[] = {
565         &am33xx_l4_core__elm,
566 };
568 /* elm */
569 static struct omap_hwmod am33xx_elm_hwmod = {
570         .name           = "elm",
571         .class          = &am33xx_elm_hwmod_class,
572         .mpu_irqs       = am33xx_elm_irqs,
573         .main_clk       = "elm_fck",
574         .clkdm_name     = "l4ls_clkdm",
575         .slaves         = am33xx_elm_slaves,
576         .slaves_cnt     = ARRAY_SIZE(am33xx_elm_slaves),
577         .prcm           = {
578                 .omap4  = {
579                         .clkctrl_offs   = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
580                         .modulemode     = MODULEMODE_SWCTRL,
581                 },
582         },
583 };
585 /* 'emif_fw' class */
586 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
587         .name           = "emif_fw",
588 };
590 /* emif_fw */
591 static struct omap_hwmod am33xx_emif_fw_hwmod = {
592         .name           = "emif_fw",
593         .class          = &am33xx_emif_fw_hwmod_class,
594         .main_clk       = "emif_fw_fck",
595         .clkdm_name     = "l4fw_clkdm",
596         .prcm           = {
597                 .omap4  = {
598                         .clkctrl_offs   = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
599                         .modulemode     = MODULEMODE_SWCTRL,
600                 },
601         },
602         .flags          = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
603 };
605 /* 'epwmss' class */
606 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
607         .rev_offs       = 0x0,
608         .sysc_offs      = 0x10,
609         .sysc_flags     = SYSC_HAS_SIDLEMODE,
610         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
611                         SIDLE_SMART_WKUP),
612         .sysc_fields    = &omap_hwmod_sysc_type2,
613 };
615 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
616         .name           = "epwmss",
617         .sysc           = &am33xx_epwmss_sysc,
618 };
620 /* epwmss0 */
621 static struct omap_hwmod_irq_info am33xx_epwmss0_irqs[] = {
622         { .irq          = AM33XX_IRQ_PWMSS0_EPWM },
623         { .irq          = AM33XX_IRQ_PWMSS0 },
624         { .irq          = AM33XX_IRQ_PWMSS0_ECAP },
625         { .irq          = -1 }
626 };
628 struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
629         {
630                 .pa_start       = AM33XX_EPWMSS0_BASE,
631                 .pa_end         = AM33XX_EPWMSS0_BASE + SZ_4K - 1,
632                 .flags          = ADDR_TYPE_RT
633         },
634         { }
635 };
637 struct omap_hwmod_ocp_if am33xx_l4_core__epwmss0 = {
638         .master         = &am33xx_l4per_hwmod,
639         .slave          = &am33xx_epwmss0_hwmod,
640         .addr           = am33xx_epwmss0_addr_space,
641         .user           = OCP_USER_MPU,
642 };
644 static struct omap_hwmod_ocp_if *am33xx_epwmss0_slaves[] = {
645         &am33xx_l4_core__epwmss0,
646 };
648 static struct omap_hwmod am33xx_epwmss0_hwmod = {
649         .name           = "epwmss0",
650         .mpu_irqs       = am33xx_epwmss0_irqs,
651         .class          = &am33xx_epwmss_hwmod_class,
652         .main_clk       = "epwmss0_fck",
653         .clkdm_name     = "l4ls_clkdm",
654         .prcm           = {
655                 .omap4  = {
656                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
657                         .modulemode     = MODULEMODE_SWCTRL,
658                 },
659         },
660         .slaves         = am33xx_epwmss0_slaves,
661         .slaves_cnt     = ARRAY_SIZE(am33xx_epwmss0_slaves),
662 };
664 /* epwmss1 */
665 static struct omap_hwmod_irq_info am33xx_epwmss1_irqs[] = {
666         { .irq          = AM33XX_IRQ_PWMSS1_EPWM },
667         { .irq          = AM33XX_IRQ_PWMSS1 },
668         { .irq          = AM33XX_IRQ_PWMSS1_ECAP },
669         { .irq          = -1 }
670 };
672 struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
673         {
674                 .pa_start       = AM33XX_EPWMSS1_BASE,
675                 .pa_end         = AM33XX_EPWMSS1_BASE + SZ_4K - 1,
676                 .flags          = ADDR_TYPE_RT
677         },
678         { }
679 };
681 struct omap_hwmod_ocp_if am33xx_l4_core__epwmss1 = {
682         .master         = &am33xx_l4per_hwmod,
683         .slave          = &am33xx_epwmss1_hwmod,
684         .addr           = am33xx_epwmss1_addr_space,
685         .user           = OCP_USER_MPU,
686 };
688 static struct omap_hwmod_ocp_if *am33xx_epwmss1_slaves[] = {
689         &am33xx_l4_core__epwmss1,
690 };
692 static struct omap_hwmod am33xx_epwmss1_hwmod = {
693         .name           = "epwmss1",
694         .mpu_irqs       = am33xx_epwmss1_irqs,
695         .class          = &am33xx_epwmss_hwmod_class,
696         .main_clk       = "epwmss1_fck",
697         .clkdm_name     = "l4ls_clkdm",
698         .prcm           = {
699                 .omap4  = {
700                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
701                         .modulemode     = MODULEMODE_SWCTRL,
702                 },
703         },
704         .slaves         = am33xx_epwmss1_slaves,
705         .slaves_cnt     = ARRAY_SIZE(am33xx_epwmss1_slaves),
706 };
708 /* epwmss2 */
709 static struct omap_hwmod_irq_info am33xx_epwmss2_irqs[] = {
710         { .irq          = AM33XX_IRQ_PWMSS2_EPWM },
711         { .irq          = AM33XX_IRQ_PWMSS2 },
712         { .irq          = AM33XX_IRQ_PWMSS2_ECAP },
713         { .irq          = -1 }
714 };
716 struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
717         {
718                 .pa_start       = AM33XX_EPWMSS2_BASE,
719                 .pa_end         = AM33XX_EPWMSS2_BASE + SZ_4K - 1,
720                 .flags          = ADDR_TYPE_RT
721         },
722         { }
723 };
725 struct omap_hwmod_ocp_if am33xx_l4_core__epwmss2 = {
726         .master         = &am33xx_l4per_hwmod,
727         .slave          = &am33xx_epwmss2_hwmod,
728         .addr           = am33xx_epwmss2_addr_space,
729         .user           = OCP_USER_MPU,
730 };
732 static struct omap_hwmod_ocp_if *am33xx_epwmss2_slaves[] = {
733         &am33xx_l4_core__epwmss2,
734 };
736 static struct omap_hwmod am33xx_epwmss2_hwmod = {
737         .name           = "epwmss2",
738         .mpu_irqs       = am33xx_epwmss2_irqs,
739         .class          = &am33xx_epwmss_hwmod_class,
740         .main_clk       = "epwmss2_fck",
741         .clkdm_name     = "l4ls_clkdm",
742         .prcm           = {
743                 .omap4  = {
744                         .clkctrl_offs   = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
745                         .modulemode     = MODULEMODE_SWCTRL,
746                 },
747         },
748         .slaves         = am33xx_epwmss2_slaves,
749         .slaves_cnt     = ARRAY_SIZE(am33xx_epwmss2_slaves),
750 };
752 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
753         .rev_offs       = 0x0000,
754         .sysc_offs      = 0x0010,
755         .syss_offs      = 0x0114,
756         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
757                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
758         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
759                                 SIDLE_SMART_WKUP),
760         .sysc_fields    = &omap_hwmod_sysc_type1,
761 };
763 /* 'gpio' class */
764 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
765         .name           = "gpio",
766         .sysc           = &am33xx_gpio_sysc,
767         .rev            = 2,
768 };
770 /* gpio dev_attr */
771 static struct omap_gpio_dev_attr gpio_dev_attr = {
772         .bank_width     = 32,
773         .dbck_flag      = true,
774 };
776 /* gpio0 */
777 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
778         { .irq = AM33XX_IRQ_GPIO0_1 },
779         { .irq = -1 }
780 };
782 /* gpio0 slave ports */
783 static struct omap_hwmod_ocp_if *am33xx_gpio0_slaves[] = {
784         &am33xx_l4_wkup__gpio0,
785 };
787 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
788         { .role = "dbclk", .clk = "gpio0_dbclk" },
789         { .role = "fclk", .clk = "gpio0_fck" },
790 };
792 /* gpio0 */
793 static struct omap_hwmod am33xx_gpio0_hwmod = {
794         .name           = "gpio1",
795         .class          = &am33xx_gpio_hwmod_class,
796         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
797         .mpu_irqs       = am33xx_gpio0_irqs,
798         .main_clk       = "gpio0_fck",
799         .clkdm_name     = "l4_wkup_clkdm",
800         .prcm           = {
801                 .omap4  = {
802                         .clkctrl_offs   = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
803                         .modulemode     = MODULEMODE_SWCTRL,
804                 },
805         },
806         .opt_clks       = gpio0_opt_clks,
807         .opt_clks_cnt   = ARRAY_SIZE(gpio0_opt_clks),
808         .dev_attr       = &gpio_dev_attr,
809         .slaves         = am33xx_gpio0_slaves,
810         .slaves_cnt     = ARRAY_SIZE(am33xx_gpio0_slaves),
811 };
813 /* gpio1 */
814 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
815         { .irq = AM33XX_IRQ_GPIO1_1 },
816         { .irq = -1 }
817 };
819 /* gpio1 slave ports */
820 static struct omap_hwmod_ocp_if *am33xx_gpio1_slaves[] = {
821         &am33xx_l4_per__gpio1,
822 };
824 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
825         { .role = "dbclk", .clk = "gpio1_dbclk" },
826         { .role = "fclk", .clk = "gpio1_fck" },
827 };
829 static struct omap_hwmod am33xx_gpio1_hwmod = {
830         .name           = "gpio2",
831         .class          = &am33xx_gpio_hwmod_class,
832         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
833         .mpu_irqs       = am33xx_gpio1_irqs,
834         .main_clk       = "gpio1_fck",
835         .clkdm_name     = "l4ls_clkdm",
836         .prcm           = {
837                 .omap4  = {
838                         .clkctrl_offs   = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
839                         .modulemode     = MODULEMODE_SWCTRL,
840                 },
841         },
842         .opt_clks       = gpio1_opt_clks,
843         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
844         .dev_attr       = &gpio_dev_attr,
845         .slaves         = am33xx_gpio1_slaves,
846         .slaves_cnt     = ARRAY_SIZE(am33xx_gpio1_slaves),
847 };
849 /* gpio2 */
850 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
851         { .irq = AM33XX_IRQ_GPIO2_1 },
852         { .irq = -1 }
853 };
855 /* gpio2 slave ports */
856 static struct omap_hwmod_ocp_if *am33xx_gpio2_slaves[] = {
857         &am33xx_l4_per__gpio2,
858 };
860 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
861         { .role = "dbclk", .clk = "gpio2_dbclk" },
862         { .role = "fclk", .clk = "gpio2_fck" },
863 };
865 /* gpio2 */
866 static struct omap_hwmod am33xx_gpio2_hwmod = {
867         .name           = "gpio3",
868         .class          = &am33xx_gpio_hwmod_class,
869         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
870         .mpu_irqs       = am33xx_gpio2_irqs,
871         .main_clk       = "gpio2_fck",
872         .clkdm_name     = "l4ls_clkdm",
873         .prcm           = {
874                 .omap4  = {
875                         .clkctrl_offs   = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
876                         .modulemode     = MODULEMODE_SWCTRL,
877                 },
878         },
879         .opt_clks       = gpio2_opt_clks,
880         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
881         .dev_attr       = &gpio_dev_attr,
882         .slaves         = am33xx_gpio2_slaves,
883         .slaves_cnt     = ARRAY_SIZE(am33xx_gpio2_slaves),
884 };
886 /* gpio3 */
887 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
888         { .irq = AM33XX_IRQ_GPIO3_1 },
889         { .irq = -1 }
890 };
892 /* gpio3 slave ports */
893 static struct omap_hwmod_ocp_if *am33xx_gpio3_slaves[] = {
894         &am33xx_l4_per__gpio3,
895 };
897 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
898         { .role = "dbclk", .clk = "gpio3_dbclk" },
899         { .role = "fclk", .clk = "gpio3_fck" },
900 };
902 /* gpio3 */
903 static struct omap_hwmod am33xx_gpio3_hwmod = {
904         .name           = "gpio4",
905         .class          = &am33xx_gpio_hwmod_class,
906         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
907         .mpu_irqs       = am33xx_gpio3_irqs,
908         .main_clk       = "gpio3_fck",
909         .clkdm_name     = "l4ls_clkdm",
910         .prcm           = {
911                 .omap4  = {
912                         .clkctrl_offs   = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
913                         .modulemode     = MODULEMODE_SWCTRL,
914                 },
915         },
916         .opt_clks       = gpio3_opt_clks,
917         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
918         .dev_attr       = &gpio_dev_attr,
919         .slaves         = am33xx_gpio3_slaves,
920         .slaves_cnt     = ARRAY_SIZE(am33xx_gpio3_slaves),
921 };
923 /* 'gpmc' class */
924 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
925         .rev_offs       = 0x0,
926         .sysc_offs      = 0x10,
927         .syss_offs      = 0x14,
928         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
929                                 SYSC_HAS_MIDLEMODE | SYSC_HAS_SOFTRESET |
930                                 SYSS_HAS_RESET_STATUS),
931         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
932                                 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
933         .sysc_fields    = &omap_hwmod_sysc_type4,
934 };
936 struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
937         {
938                 .pa_start       = 0x50000000,
939                 .pa_end         = 0x50000000 + SZ_8K - 1,
940                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
941         },
942         { }
943 };
945 struct omap_hwmod_ocp_if am33xx_l3_main__gpmc = {
946         .master         = &am33xx_l3_main_hwmod,
947         .slave          = &am33xx_gpmc_hwmod,
948         .addr           = am33xx_gpmc_addr_space,
949         .user           = OCP_USER_MPU,
950 };
952 static struct omap_hwmod_ocp_if *am33xx_gpmc_slaves[] = {
953         &am33xx_l3_main__gpmc,
954 };
956 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
957         .name           = "gpmc",
958         .sysc           = &gpmc_sysc,
959 };
961 /* gpmc */
962 static struct omap_hwmod am33xx_gpmc_hwmod = {
963         .name           = "gpmc",
964         .class          = &am33xx_gpmc_hwmod_class,
965         .main_clk       = "gpmc_fck",
966         .clkdm_name     = "l3s_clkdm",
967         .prcm           = {
968                 .omap4  = {
969                         .clkctrl_offs   = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
970                         .modulemode     = MODULEMODE_SWCTRL,
971                 },
972         },
973         .slaves         = am33xx_gpmc_slaves,
974         .slaves_cnt     = ARRAY_SIZE(am33xx_gpmc_slaves),
975 };
977 /* 'i2c' class */
979 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
980         .sysc_offs      = 0x0010,
981         .syss_offs      = 0x0090,
982         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
983                         SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
984                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
985         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
986                         SIDLE_SMART_WKUP),
987         .sysc_fields    = &omap_hwmod_sysc_type1,
988 };
990 static struct omap_i2c_dev_attr i2c_dev_attr = {
991         .flags          = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
992 };
994 static struct omap_hwmod_class i2c_class = {
995         .name           = "i2c",
996         .sysc           = &am33xx_i2c_sysc,
997         .rev            = OMAP_I2C_IP_VERSION_2,
998         .reset          = &omap_i2c_reset,
999 };
1001 /* I2C1 */
1002 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1003         { .irq = AM33XX_IRQ_MSHSI2COCP0 },
1004         { .irq = -1 }
1005 };
1007 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
1008         { .name = "tx", .dma_req = 0, },
1009         { .name = "rx", .dma_req = 0, },
1010         { .dma_req = -1 }
1011 };
1013 static struct omap_hwmod_ocp_if *am33xx_i2c1_slaves[] = {
1014         &am33xx_l4_wkup_i2c1,
1015 };
1017 static struct omap_hwmod am33xx_i2c1_hwmod = {
1018         .name           = "i2c1",
1019         .mpu_irqs       = i2c1_mpu_irqs,
1020         .sdma_reqs      = i2c1_edma_reqs,
1021         .main_clk       = "i2c1_fck",
1022         .clkdm_name     = "l4_wkup_clkdm",
1023         .prcm           = {
1024                 .omap4  = {
1025                         .clkctrl_offs   = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
1026                         .modulemode     = MODULEMODE_SWCTRL,
1027                 },
1028         },
1029         .flags          = HWMOD_16BIT_REG,
1030         .dev_attr       = &i2c_dev_attr,
1031         .slaves         = am33xx_i2c1_slaves,
1032         .slaves_cnt     = ARRAY_SIZE(am33xx_i2c1_slaves),
1033         .class          = &i2c_class,
1034 };
1036 /* i2c2 */
1037 /* l4 per -> i2c2 */
1038 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
1039         {
1040                 .pa_start       = AM33XX_I2C1_BASE,
1041                 .pa_end         = AM33XX_I2C1_BASE + SZ_4K - 1,
1042                 .flags          = ADDR_TYPE_RT
1043         },
1044         { }
1045 };
1047 static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = {
1048         .master         = &am33xx_l4per_hwmod,
1049         .slave          = &am33xx_i2c2_hwmod,
1050         .addr           = am33xx_i2c2_addr_space,
1051         .user           = OCP_USER_MPU,
1052 };
1054 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1055         { .irq = AM33XX_IRQ_MSHSI2COCP1 },
1056         { .irq = -1 }
1057 };
1059 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
1060         { .name = "tx", .dma_req = 0, },
1061         { .name = "rx", .dma_req = 0, },
1062         { .dma_req = -1 }
1063 };
1065 static struct omap_hwmod_ocp_if *am33xx_i2c2_slaves[] = {
1066         &am335_l4_per_i2c2,
1067 };
1069 static struct omap_hwmod am33xx_i2c2_hwmod = {
1070         .name           = "i2c2",
1071         .mpu_irqs       = i2c2_mpu_irqs,
1072         .sdma_reqs      = i2c2_edma_reqs,
1073         .main_clk       = "i2c2_fck",
1074         .clkdm_name     = "l4ls_clkdm",
1075         .prcm           = {
1076                 .omap4 = {
1077                         .clkctrl_offs   = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
1078                         .modulemode     = MODULEMODE_SWCTRL,
1079                 },
1080         },
1081         .flags          = HWMOD_16BIT_REG,
1082         .dev_attr       = &i2c_dev_attr,
1083         .slaves         = am33xx_i2c2_slaves,
1084         .slaves_cnt     = ARRAY_SIZE(am33xx_i2c2_slaves),
1085         .class          = &i2c_class,
1086 };
1088 /* i2c3 */
1089 /* l4 per -> i2c3 */
1090 static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
1091         {
1092                 .pa_start       = AM33XX_I2C2_BASE,
1093                 .pa_end         = AM33XX_I2C2_BASE + SZ_4K - 1,
1094                 .flags          = ADDR_TYPE_RT
1095         },
1096         { }
1097 };
1099 static struct omap_hwmod_ocp_if am335_l4_per_i2c3 = {
1100         .master         = &am33xx_l4per_hwmod,
1101         .slave          = &am33xx_i2c3_hwmod,
1102         .addr           = am33xx_i2c3_addr_space,
1103         .user           = OCP_USER_MPU,
1104 };
1106 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1107         { .irq = AM33XX_IRQ_MSHSI2COCP2 },
1108         { .irq = -1 }
1109 };
1111 static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
1112         { .name = "tx", .dma_req = 0, },
1113         { .name = "rx", .dma_req = 0, },
1114         { .dma_req = -1 }
1115 };
1117 static struct omap_hwmod_ocp_if *am33xx_i2c3_slaves[] = {
1118         &am335_l4_per_i2c3,
1119 };
1121 static struct omap_hwmod am33xx_i2c3_hwmod = {
1122         .name           = "i2c3",
1123         .mpu_irqs       = i2c3_mpu_irqs,
1124         .sdma_reqs      = i2c3_edma_reqs,
1125         .main_clk       = "i2c3_fck",
1126         .clkdm_name     = "l4ls_clkdm",
1127         .prcm           = {
1128                 .omap4 = {
1129                         .clkctrl_offs   = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
1130                         .modulemode     = MODULEMODE_SWCTRL,
1131                 },
1132         },
1133         .flags          = HWMOD_16BIT_REG,
1134         .dev_attr       = &i2c_dev_attr,
1135         .slaves         = am33xx_i2c3_slaves,
1136         .slaves_cnt     = ARRAY_SIZE(am33xx_i2c3_slaves),
1137         .class          = &i2c_class,
1138 };
1140 /* 'icss' class */
1141 static struct omap_hwmod_class am33xx_icss_hwmod_class = {
1142         .name = "icss",
1143 };
1145 /* icss */
1146 static struct omap_hwmod am33xx_icss_hwmod = {
1147         .name           = "icss",
1148         .class          = &am33xx_icss_hwmod_class,
1149         .main_clk       = "icss_fck",
1150         .clkdm_name     = "icss_ocp_clkdm",
1151         .prcm           = {
1152                 .omap4  = {
1153                         .clkctrl_offs   = AM33XX_CM_PER_ICSS_CLKCTRL_OFFSET,
1154                         .modulemode     = MODULEMODE_SWCTRL,
1155                 },
1156         },
1157 };
1159 /* 'ieee5000' class */
1160 static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = {
1161         .name           = "ieee5000",
1162 };
1164 /* ieee5000 */
1165 static struct omap_hwmod am33xx_ieee5000_hwmod = {
1166         .name           = "ieee5000",
1167         .class          = &am33xx_ieee5000_hwmod_class,
1168         .main_clk       = "ieee5000_fck",
1169         .clkdm_name     = "l3s_clkdm",
1170         .prcm           = {
1171                 .omap4  = {
1172                         .clkctrl_offs   = AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET,
1173                         .modulemode     = MODULEMODE_SWCTRL,
1174                 },
1175         },
1176 };
1179 /* 'l3' class */
1180 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
1181         .name           = "l3",
1182 };
1184 /* l4_hs */
1185 static struct omap_hwmod am33xx_l4_hs_hwmod = {
1186         .name           = "l4_hs",
1187         .class          = &am33xx_l3_hwmod_class,
1188         .clkdm_name     = "l4hs_clkdm",
1189         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1190         .prcm           = {
1191                 .omap4  = {
1192                         .clkctrl_offs   = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
1193                         .modulemode     = MODULEMODE_SWCTRL,
1194                 },
1195         },
1196 };
1198 /* l3_instr */
1199 static struct omap_hwmod am33xx_l3_instr_hwmod = {
1200         .name           = "l3_instr",
1201         .class          = &am33xx_l3_hwmod_class,
1202         .clkdm_name     = "l3_clkdm",
1203         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1204         .prcm           = {
1205                 .omap4  = {
1206                         .clkctrl_offs   = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
1207                         .modulemode     = MODULEMODE_SWCTRL,
1208                 },
1209         },
1210 };
1212 /* l3_main */
1213 static struct omap_hwmod am33xx_l3_main_hwmod = {
1214         .name           = "l3_main",
1215         .class          = &am33xx_l3_hwmod_class,
1216         .clkdm_name     = "l3_clkdm",
1217         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1218         .prcm           = {
1219                 .omap4  = {
1220                         .clkctrl_offs   = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
1221                         .modulemode     = MODULEMODE_SWCTRL,
1222                 },
1223         },
1224 };
1226 /* 'l4fw' class */
1227 static struct omap_hwmod_class am33xx_l4fw_hwmod_class = {
1228         .name           = "l4fw",
1229 };
1231 /* l4fw */
1232 static struct omap_hwmod am33xx_l4fw_hwmod = {
1233         .name           = "l4fw",
1234         .class          = &am33xx_l4fw_hwmod_class,
1235         .clkdm_name     = "l4fw_clkdm",
1236         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1237         .prcm           = {
1238                 .omap4  = {
1239                         .clkctrl_offs   = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
1240                         .modulemode     = MODULEMODE_SWCTRL,
1241                 },
1242         },
1243 };
1245 /* 'l4ls' class */
1246 static struct omap_hwmod_class am33xx_l4ls_hwmod_class = {
1247         .name           = "l4ls",
1248 };
1250 /* l4ls */
1251 static struct omap_hwmod am33xx_l4ls_hwmod = {
1252         .name           = "l4ls",
1253         .class          = &am33xx_l4ls_hwmod_class,
1254         .main_clk       = "l4ls_fck",
1255         .clkdm_name     = "l4ls_clkdm",
1256         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1257         .prcm           = {
1258                 .omap4  = {
1259                         .clkctrl_offs   = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
1260                         .modulemode     = MODULEMODE_SWCTRL,
1261                 },
1262         },
1263 };
1265 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
1266         .rev_offs       = 0x0,
1267         .sysc_offs      = 0x54,
1268         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
1269         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1270         .sysc_fields    = &omap_hwmod_sysc_type2,
1271 };
1273 /* 'lcdc' class */
1274 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1275         .name           = "lcdc",
1276         .sysc           = &lcdc_sysc,
1277 };
1279 /* lcdc */
1280 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1281         { .irq = AM33XX_IRQ_LCD },
1282         { .irq = -1 }
1283 };
1285 struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
1286         {
1287                 .pa_start       = 0x4830E000,
1288                 .pa_end         = 0x4830E000 + SZ_8K - 1,
1289                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
1290         },
1291         { }
1292 };
1294 struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
1295         .master         = &am33xx_l3_main_hwmod,
1296         .slave          = &am33xx_lcdc_hwmod,
1297         .addr           = am33xx_lcdc_addr_space,
1298         .user           = OCP_USER_MPU,
1299 };
1301 static struct omap_hwmod_ocp_if *am33xx_lcdc_slaves[] = {
1302         &am33xx_l3_main__lcdc,
1303 };
1305 static struct omap_hwmod am33xx_lcdc_hwmod = {
1306         .name           = "lcdc",
1307         .class          = &am33xx_lcdc_hwmod_class,
1308         .mpu_irqs       = am33xx_lcdc_irqs,
1309         .main_clk       = "lcdc_fck",
1310         .clkdm_name     = "lcdc_clkdm",
1311         .prcm           = {
1312                 .omap4  = {
1313                         .clkctrl_offs   = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1314                         .modulemode     = MODULEMODE_SWCTRL,
1315                 },
1316         },
1317         .slaves         = am33xx_lcdc_slaves,
1318         .slaves_cnt     = ARRAY_SIZE(am33xx_lcdc_slaves),
1319 };
1321 /*
1322  * 'mailbox' class
1323  * mailbox module allowing communication between the on-chip processors using a
1324  * queued mailbox-interrupt mechanism.
1325  */
1327 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1328         .rev_offs       = 0x0000,
1329         .sysc_offs      = 0x0010,
1330         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1331                            SYSC_HAS_SOFTRESET),
1332         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1333         .sysc_fields    = &omap_hwmod_sysc_type2,
1334 };
1336 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1337         .name   = "mailbox",
1338         .sysc   = &am33xx_mailbox_sysc,
1339 };
1341 /* mailbox */
1342 static struct omap_hwmod am33xx_mailbox_hwmod;
1343 static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1344         { .irq = AM33XX_IRQ_MAILBOX },
1345         { .irq = -1 }
1346 };
1348 static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
1349         {
1350                 .pa_start       = AM33XX_MAILBOX0_BASE,
1351                 .pa_end         = AM33XX_MAILBOX0_BASE + (SZ_4K - 1),
1352                 .flags          = ADDR_TYPE_RT
1353         },
1354         { }
1355 };
1357 /* l4_cfg -> mailbox */
1358 static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
1359         .master         = &am33xx_l4per_hwmod,
1360         .slave          = &am33xx_mailbox_hwmod,
1361         .addr           = am33xx_mailbox_addrs,
1362         .user           = OCP_USER_MPU,
1363 };
1365 /* mailbox slave ports */
1366 static struct omap_hwmod_ocp_if *am33xx_mailbox_slaves[] = {
1367         &am33xx_l4_per__mailbox,
1368 };
1370 static struct omap_hwmod am33xx_mailbox_hwmod = {
1371         .name           = "mailbox",
1372         .class          = &am33xx_mailbox_hwmod_class,
1373         .clkdm_name     = "l4ls_clkdm",
1374         .mpu_irqs       = am33xx_mailbox_irqs,
1375         .main_clk       = "mailbox0_fck",
1376         .prcm = {
1377                 .omap4 = {
1378                         .clkctrl_offs   = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1379                         .modulemode     = MODULEMODE_SWCTRL,
1380                 },
1381         },
1382         .slaves         = am33xx_mailbox_slaves,
1383         .slaves_cnt     = ARRAY_SIZE(am33xx_mailbox_slaves),
1384 };
1386 /* 'mcasp' class */
1387 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1388         .name           = "mcasp",
1389 };
1391 /* mcasp0 */
1392 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1393         { .name = "ax", .irq = AM33XX_IRQ_MCASP0_AX, },
1394         { .name = "ar", .irq = AM33XX_IRQ_MCASP0_AR, },
1395         { .irq = -1 }
1396 };
1398 static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
1399         {
1400                 .pa_start       = AM33XX_ASP0_BASE,
1401                 .pa_end         = AM33XX_ASP0_BASE + (SZ_1K * 12) - 1,
1402                 .flags          = ADDR_TYPE_RT
1403         },
1404         { }
1405 };
1407 static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp0 = {
1408         .master         = &am33xx_l3slow_hwmod,
1409         .slave          = &am33xx_mcasp0_hwmod,
1410         .clk            = "mcasp0_ick",
1411         .addr           = am33xx_mcasp0_addr_space,
1412         .user           = OCP_USER_MPU,
1413 };
1415 static struct omap_hwmod_ocp_if *am33xx_mcasp0_slaves[] = {
1416         &am33xx_l3_slow__mcasp0,
1417 };
1419 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1420         .name           = "mcasp0",
1421         .class          = &am33xx_mcasp_hwmod_class,
1422         .mpu_irqs       = am33xx_mcasp0_irqs,
1423         .main_clk       = "mcasp0_fck",
1424         .clkdm_name     = "l3s_clkdm",
1425         .prcm           = {
1426                 .omap4  = {
1427                         .clkctrl_offs   = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1428                         .modulemode     = MODULEMODE_SWCTRL,
1429                 },
1430         },
1431         .slaves         = am33xx_mcasp0_slaves,
1432         .slaves_cnt     = ARRAY_SIZE(am33xx_mcasp0_slaves),
1433 };
1435 /* mcasp1 */
1436 static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
1437         { .name = "ax", .irq = AM33XX_IRQ_MCASP1_AX, },
1438         { .name = "ar", .irq = AM33XX_IRQ_MCASP1_AR, },
1439         { .irq = -1 }
1440 };
1442 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
1443         {
1444                 .pa_start       = AM33XX_ASP1_BASE,
1445                 .pa_end         = AM33XX_ASP1_BASE + (SZ_1K * 12) - 1,
1446                 .flags          = ADDR_TYPE_RT
1447         },
1448         { }
1449 };
1451 static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp1 = {
1452         .master         = &am33xx_l3slow_hwmod,
1453         .slave          = &am33xx_mcasp1_hwmod,
1454         .clk            = "mcasp1_ick",
1455         .addr           = am33xx_mcasp1_addr_space,
1456         .user           = OCP_USER_MPU,
1457 };
1459 static struct omap_hwmod_ocp_if *am33xx_mcasp1_slaves[] = {
1460         &am33xx_l3_slow__mcasp1,
1461 };
1463 static struct omap_hwmod am33xx_mcasp1_hwmod = {
1464         .name           = "mcasp1",
1465         .class          = &am33xx_mcasp_hwmod_class,
1466         .mpu_irqs       = am33xx_mcasp1_irqs,
1467         .main_clk       = "mcasp1_fck",
1468         .clkdm_name     = "l3s_clkdm",
1469         .prcm           = {
1470                 .omap4  = {
1471                         .clkctrl_offs   = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
1472                         .modulemode     = MODULEMODE_SWCTRL,
1473                 },
1474         },
1475         .slaves         = am33xx_mcasp1_slaves,
1476         .slaves_cnt     = ARRAY_SIZE(am33xx_mcasp1_slaves),
1477 };
1480 /* 'mmc' class */
1482 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1483         .rev_offs       = 0x1fc,
1484         .sysc_offs      = 0x10,
1485         .syss_offs      = 0x14,
1486         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1487                         SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1488                         SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1489         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1490         .sysc_fields    = &omap_hwmod_sysc_type1,
1491 };
1493 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1494         .name           = "mmc",
1495         .sysc           = &am33xx_mmc_sysc,
1496 };
1498 /* mmc0 */
1499 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1500         { .irq = AM33XX_IRQ_MMCHS0 },
1501         { .irq = -1 }
1502 };
1504 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1505         { .name = "tx", .dma_req = AM33XX_DMA_MMCHS0_W, },
1506         { .name = "rx", .dma_req = AM33XX_DMA_MMCHS0_R, },
1507         { .dma_req = -1 }
1508 };
1510 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
1511         {
1512                 .pa_start       = AM33XX_MMC0_BASE,
1513                 .pa_end         = AM33XX_MMC0_BASE + SZ_4K - 1,
1514                 .flags          = ADDR_TYPE_RT
1515         },
1516         { }
1517 };
1519 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc0 = {
1520         .master         = &am33xx_l4ls_hwmod,
1521         .slave          = &am33xx_mmc0_hwmod,
1522         .clk            = "mmc0_ick",
1523         .addr           = am33xx_mmc0_addr_space,
1524         .user           = OCP_USER_MPU,
1525 };
1527 static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = {
1528         &am33xx_l4ls__mmc0,
1529 };
1531 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1532         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1533 };
1535 static struct omap_hwmod am33xx_mmc0_hwmod = {
1536         .name           = "mmc1",
1537         .class          = &am33xx_mmc_hwmod_class,
1538         .mpu_irqs       = am33xx_mmc0_irqs,
1539         .sdma_reqs      = am33xx_mmc0_edma_reqs,
1540         .main_clk       = "mmc0_fck",
1541         .clkdm_name     = "l4ls_clkdm",
1542         .prcm           = {
1543                 .omap4  = {
1544                         .clkctrl_offs   = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1545                         .modulemode     = MODULEMODE_SWCTRL,
1546                 },
1547         },
1548         .dev_attr       = &am33xx_mmc0_dev_attr,
1549         .slaves         = am33xx_mmc0_slaves,
1550         .slaves_cnt     = ARRAY_SIZE(am33xx_mmc0_slaves),
1551 };
1553 /* mmc1 */
1554 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1555         { .irq = AM33XX_IRQ_MMCHS1 },
1556         { .irq = -1 }
1557 };
1559 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1560         { .name = "tx", .dma_req = AM33XX_DMA_MMCHS1_W, },
1561         { .name = "rx", .dma_req = AM33XX_DMA_MMCHS1_R, },
1562         { .dma_req = -1 }
1563 };
1565 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
1566         {
1567                 .pa_start       = AM33XX_MMC1_BASE,
1568                 .pa_end         = AM33XX_MMC1_BASE + SZ_4K - 1,
1569                 .flags          = ADDR_TYPE_RT
1570         },
1571         { }
1572 };
1574 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc1 = {
1575         .master         = &am33xx_l4ls_hwmod,
1576         .slave          = &am33xx_mmc1_hwmod,
1577         .clk            = "mmc1_ick",
1578         .addr           = am33xx_mmc1_addr_space,
1579         .user           = OCP_USER_MPU,
1580 };
1582 static struct omap_hwmod_ocp_if *am33xx_mmc1_slaves[] = {
1583         &am33xx_l4ls__mmc1,
1584 };
1586 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1587         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1588 };
1590 static struct omap_hwmod am33xx_mmc1_hwmod = {
1591         .name           = "mmc2",
1592         .class          = &am33xx_mmc_hwmod_class,
1593         .mpu_irqs       = am33xx_mmc1_irqs,
1594         .sdma_reqs      = am33xx_mmc1_edma_reqs,
1595         .main_clk       = "mmc1_fck",
1596         .clkdm_name     = "l4ls_clkdm",
1597         .prcm           = {
1598                 .omap4  = {
1599                         .clkctrl_offs   = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1600                         .modulemode     = MODULEMODE_SWCTRL,
1601                 },
1602         },
1603         .dev_attr       = &am33xx_mmc1_dev_attr,
1604         .slaves         = am33xx_mmc1_slaves,
1605         .slaves_cnt     = ARRAY_SIZE(am33xx_mmc1_slaves),
1606 };
1608 /* mmc2 */
1609 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1610         { .irq = AM33XX_IRQ_MMCHS2 },
1611         { .irq = -1 }
1612 };
1614 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1615         { .name = "tx", .dma_req = AM33XX_DMA_MMCHS2_W, },
1616         { .name = "rx", .dma_req = AM33XX_DMA_MMCHS2_R, },
1617         { .dma_req = -1 }
1618 };
1620 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
1621         {
1622                 .pa_start       = AM33XX_MMC2_BASE,
1623                 .pa_end         = AM33XX_MMC2_BASE + SZ_64K - 1,
1624                 .flags          = ADDR_TYPE_RT
1625         },
1626         { }
1627 };
1629 static struct omap_hwmod_ocp_if am33xx_l3_main__mmc2 = {
1630         .master         = &am33xx_l3_main_hwmod,
1631         .slave          = &am33xx_mmc2_hwmod,
1632         .clk            = "mmc2_ick",
1633         .addr           = am33xx_mmc2_addr_space,
1634         .user           = OCP_USER_MPU,
1635 };
1637 static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = {
1638         &am33xx_l3_main__mmc2,
1639 };
1641 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1642         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1643 };
1644 static struct omap_hwmod am33xx_mmc2_hwmod = {
1645         .name           = "mmc3",
1646         .class          = &am33xx_mmc_hwmod_class,
1647         .mpu_irqs       = am33xx_mmc2_irqs,
1648         .sdma_reqs      = am33xx_mmc2_edma_reqs,
1649         .main_clk       = "mmc2_fck",
1650         .clkdm_name     = "l3s_clkdm",
1651         .prcm           = {
1652                 .omap4  = {
1653                         .clkctrl_offs   = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1654                         .modulemode     = MODULEMODE_SWCTRL,
1655                 },
1656         },
1657         .dev_attr       = &am33xx_mmc2_dev_attr,
1658         .slaves         = am33xx_mmc2_slaves,
1659         .slaves_cnt     = ARRAY_SIZE(am33xx_mmc2_slaves),
1660 };
1662 /* Master interfaces on the MPU interconnect */
1663 static struct omap_hwmod_ocp_if *am33xx_l3_mpu_masters[] = {
1664         &am33xx_mpu__l3_slow,
1665 };
1667 /* mpu */
1668 static struct omap_hwmod am33xx_mpu_hwmod = {
1669         .name           = "mpu",
1670         .class          = &mpu_hwmod_class,
1671         .masters        = am33xx_l3_mpu_masters,
1672         .masters_cnt    = ARRAY_SIZE(am33xx_l3_mpu_masters),
1673         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1674         .main_clk       = "mpu_fck",
1675         .clkdm_name     = "mpu_clkdm",
1676         .prcm           = {
1677                 .omap4  = {
1678                         .clkctrl_offs   = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1679                         .modulemode     = MODULEMODE_SWCTRL,
1680                 },
1681         },
1682 };
1684 /* 'ocmcram' class */
1685 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
1686         .name = "ocmcram",
1687 };
1689 /* ocmcram */
1690 static struct omap_hwmod am33xx_ocmcram_hwmod = {
1691         .name           = "ocmcram",
1692         .class          = &am33xx_ocmcram_hwmod_class,
1693         .main_clk       = "ocmcram_fck",
1694         .clkdm_name     = "l3_clkdm",
1695         .prcm           = {
1696                 .omap4  = {
1697                         .clkctrl_offs   = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
1698                         .modulemode     = MODULEMODE_SWCTRL,
1699                 },
1700         },
1701         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1702 };
1704 /* 'ocpwp' class */
1705 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
1706         .name           = "ocpwp",
1707 };
1709 /* ocpwp */
1710 static struct omap_hwmod am33xx_ocpwp_hwmod = {
1711         .name           = "ocpwp",
1712         .class          = &am33xx_ocpwp_hwmod_class,
1713         .main_clk       = "ocpwp_fck",
1714         .clkdm_name     = "l4ls_clkdm",
1715         .prcm           = {
1716                 .omap4  = {
1717                         .clkctrl_offs   = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
1718                         .modulemode     = MODULEMODE_SWCTRL,
1719                 },
1720         },
1721 };
1723 /* 'rtc' class */
1724 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1725         .name           = "rtc",
1726 };
1728 /* rtc */
1729 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1730         { .irq = AM33XX_IRQ_RTC_TIMER },
1731         { .irq = -1 }
1732 };
1734 static struct omap_hwmod am33xx_rtc_hwmod = {
1735         .name           = "rtc",
1736         .class          = &am33xx_rtc_hwmod_class,
1737         .mpu_irqs       = am33xx_rtc_irqs,
1738         .main_clk       = "rtc_fck",
1739         .clkdm_name     = "l4_rtc_clkdm",
1740         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), /* ??? */
1741         .prcm           = {
1742                 .omap4  = {
1743                         .clkctrl_offs   = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1744                         .modulemode     = MODULEMODE_SWCTRL,
1745                 },
1746         },
1747 };
1749 /* 'sha0' class */
1750 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
1751         .name           = "sha0",
1752 };
1754 /* sha0 */
1755 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
1756         { .irq = AM33XX_IRQ_SHAEIP57t0_S },
1757         { .irq = -1 }
1758 };
1760 static struct omap_hwmod am33xx_sha0_hwmod = {
1761         .name           = "sha0",
1762         .class          = &am33xx_sha0_hwmod_class,
1763         .mpu_irqs       = am33xx_sha0_irqs,
1764         .main_clk       = "sha0_fck",
1765         .clkdm_name     = "l3_clkdm",
1766         .prcm           = {
1767                 .omap4  = {
1768                         .clkctrl_offs   = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
1769                         .modulemode     = MODULEMODE_SWCTRL,
1770                 },
1771         },
1772 };
1774 /* 'smartreflex' class */
1775 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
1776         .name           = "smartreflex",
1777 };
1779 /* smartreflex0 */
1780 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
1781         { .irq = AM33XX_IRQ_SMARTREFLEX0 },
1782         { .irq = -1 }
1783 };
1785 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
1786         .name           = "smartreflex0",
1787         .class          = &am33xx_smartreflex_hwmod_class,
1788         .mpu_irqs       = am33xx_smartreflex0_irqs,
1789         .main_clk       = "smartreflex0_fck",
1790         .clkdm_name     = "l4_wkup_clkdm",
1791         .prcm           = {
1792                 .omap4  = {
1793                         .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
1794                         .modulemode     = MODULEMODE_SWCTRL,
1795                 },
1796         },
1797 };
1799 /* smartreflex1 */
1800 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
1801         { .irq = AM33XX_IRQ_SMARTREFLEX1 },
1802         { .irq = -1 }
1803 };
1805 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
1806         .name           = "smartreflex1",
1807         .class          = &am33xx_smartreflex_hwmod_class,
1808         .mpu_irqs       = am33xx_smartreflex1_irqs,
1809         .main_clk       = "smartreflex1_fck",
1810         .clkdm_name     = "l4_wkup_clkdm",
1811         .prcm           = {
1812                 .omap4  = {
1813                         .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
1814                         .modulemode     = MODULEMODE_SWCTRL,
1815                 },
1816         },
1817 };
1819 /* 'spi' class */
1821 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1822         .rev_offs       = 0x0000,
1823         .sysc_offs      = 0x0110,
1824         .syss_offs      = 0x0114,
1825         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1826                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1827                         SYSS_HAS_RESET_STATUS),
1828         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1829         .sysc_fields    = &omap_hwmod_sysc_type1,
1830 };
1832 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1833         .name           = "mcspi",
1834         .sysc           = &am33xx_mcspi_sysc,
1835         .rev            = OMAP4_MCSPI_REV,
1836 };
1838 /* spi0 */
1839 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1840         { .irq = AM33XX_IRQ_MCSPIOCP0 },
1841         { .irq = -1 }
1842 };
1844 struct omap_hwmod_dma_info am33xx_mcspi0_sdma_reqs[] = {
1845         { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0R },
1846         { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0W },
1847         { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1R },
1848         { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1W },
1849         { .dma_req = -1 }
1850 };
1852 struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
1853         {
1854                 .pa_start       = AM33XX_SPI0_BASE,
1855                 .pa_end         = AM33XX_SPI0_BASE + SZ_1K - 1,
1856                 .flags          = ADDR_TYPE_RT
1857         },
1858         { }
1859 };
1861 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = {
1862         .master         = &am33xx_l4per_hwmod,
1863         .slave          = &am33xx_spi0_hwmod,
1864         .clk            = "spi0_ick",
1865         .addr           = am33xx_mcspi0_addr_space,
1866         .user           = OCP_USER_MPU,
1867 };
1869 static struct omap_hwmod_ocp_if *am33xx_mcspi0_slaves[] = {
1870         &am33xx_l4_core__mcspi0,
1871 };
1873 struct omap2_mcspi_dev_attr mcspi_attrib = {
1874         .num_chipselect = 2,
1875 };
1876 static struct omap_hwmod am33xx_spi0_hwmod = {
1877         .name           = "spi0",
1878         .class          = &am33xx_spi_hwmod_class,
1879         .mpu_irqs       = am33xx_spi0_irqs,
1880         .sdma_reqs      = am33xx_mcspi0_sdma_reqs,
1881         .main_clk       = "spi0_fck",
1882         .clkdm_name     = "l4ls_clkdm",
1883         .prcm           = {
1884                 .omap4  = {
1885                         .clkctrl_offs   = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1886                         .modulemode     = MODULEMODE_SWCTRL,
1887                 },
1888         },
1889         .dev_attr       = &mcspi_attrib,
1890         .slaves         = am33xx_mcspi0_slaves,
1891         .slaves_cnt     = ARRAY_SIZE(am33xx_mcspi0_slaves),
1892 };
1894 /* spi1 */
1895 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1896         { .irq = AM33XX_IRQ_SPI1 },
1897         { .irq = -1 }
1898 };
1900 struct omap_hwmod_dma_info am33xx_mcspi1_sdma_reqs[] = {
1901         { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0R },
1902         { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0W },
1903         { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1R },
1904         { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1W },
1905         { .dma_req = -1 }
1906 };
1908 struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
1909         {
1910                 .pa_start       = AM33XX_SPI1_BASE,
1911                 .pa_end         = AM33XX_SPI1_BASE + SZ_1K - 1,
1912                 .flags          = ADDR_TYPE_RT
1913         },
1914         { }
1915 };
1917 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = {
1918         .master         = &am33xx_l4per_hwmod,
1919         .slave          = &am33xx_spi1_hwmod,
1920         .clk            = "spi1_ick",
1921         .addr           = am33xx_mcspi1_addr_space,
1922         .user           = OCP_USER_MPU,
1923 };
1925 static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = {
1926         &am33xx_l4_core__mcspi1,
1927 };
1928 static struct omap_hwmod am33xx_spi1_hwmod = {
1929         .name           = "spi1",
1930         .class          = &am33xx_spi_hwmod_class,
1931         .mpu_irqs       = am33xx_spi1_irqs,
1932         .sdma_reqs      = am33xx_mcspi1_sdma_reqs,
1933         .main_clk       = "spi1_fck",
1934         .clkdm_name     = "l4ls_clkdm",
1935         .prcm           = {
1936                 .omap4  = {
1937                         .clkctrl_offs   = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1938                         .modulemode     = MODULEMODE_SWCTRL,
1939                 },
1940         },
1941         .dev_attr       = &mcspi_attrib,
1942         .slaves         = am33xx_mcspi1_slaves,
1943         .slaves_cnt     = ARRAY_SIZE(am33xx_mcspi1_slaves),
1944 };
1946 /* 'spinlock' class */
1947 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1948         .name           = "spinlock",
1949 };
1951 /* spinlock */
1952 static struct omap_hwmod am33xx_spinlock_hwmod = {
1953         .name           = "spinlock",
1954         .class          = &am33xx_spinlock_hwmod_class,
1955         .main_clk       = "spinlock_fck",
1956         .clkdm_name     = "l4ls_clkdm",
1957         .prcm           = {
1958                 .omap4  = {
1959                         .clkctrl_offs   = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1960                         .modulemode     = MODULEMODE_SWCTRL,
1961                 },
1962         },
1963 };
1965 /* 'timer 0 & 2-7' class */
1966 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1967         .rev_offs       = 0x0000,
1968         .sysc_offs      = 0x0010,
1969         .syss_offs      = 0x0014,
1970         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1971         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1972                         SIDLE_SMART_WKUP),
1973         .sysc_fields    = &omap_hwmod_sysc_type2,
1974 };
1976 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1977         .name           = "timer",
1978         .sysc           = &am33xx_timer_sysc,
1979 };
1981 /* timer0 */
1982 /* l4 wkup -> timer0 interface */
1983 static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = {
1984         {
1985                 .pa_start       = AM33XX_TIMER0_BASE,
1986                 .pa_end         = AM33XX_TIMER0_BASE + SZ_1K - 1,
1987                 .flags          = ADDR_TYPE_RT
1988         },
1989         { }
1990 };
1992 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = {
1993         .master         = &am33xx_l4wkup_hwmod,
1994         .slave          = &am33xx_timer0_hwmod,
1995         .clk            = "timer0_ick",
1996         .addr           = am33xx_timer0_addr_space,
1997         .user           = OCP_USER_MPU,
1998 };
2000 static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = {
2001         &am33xx_l4wkup__timer0,
2002 };
2004 static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = {
2005         { .irq = AM33XX_IRQ_DMTIMER0 },
2006         { .irq = -1 }
2007 };
2009 static struct omap_hwmod am33xx_timer0_hwmod = {
2010         .name           = "timer0",
2011         .class          = &am33xx_timer_hwmod_class,
2012         .mpu_irqs       = am33xx_timer0_irqs,
2013         .main_clk       = "timer0_fck",
2014         .clkdm_name     = "l4_wkup_clkdm",
2015         .prcm           = {
2016                 .omap4  = {
2017                         .clkctrl_offs   = AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET,
2018                         .modulemode     = MODULEMODE_SWCTRL,
2019                 },
2020         },
2021         .slaves         = am33xx_timer0_slaves,
2022         .slaves_cnt     = ARRAY_SIZE(am33xx_timer0_slaves),
2023 };
2025 /* timer1 1ms */
2026 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
2027         .rev_offs       = 0x0000,
2028         .sysc_offs      = 0x0010,
2029         .syss_offs      = 0x0014,
2030         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2031                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
2032                         SYSS_HAS_RESET_STATUS),
2033         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2034         .sysc_fields    = &omap_hwmod_sysc_type1,
2035 };
2037 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
2038         .name           = "timer",
2039         .sysc           = &am33xx_timer1ms_sysc,
2040 };
2042 /* l4 wkup -> timer1 interface */
2043 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
2044         {
2045                 .pa_start       = AM33XX_TIMER1_BASE,
2046                 .pa_end         = AM33XX_TIMER1_BASE + SZ_1K - 1,
2047                 .flags          = ADDR_TYPE_RT
2048         },
2049         { }
2050 };
2052 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = {
2053         .master         = &am33xx_l4wkup_hwmod,
2054         .slave          = &am33xx_timer1_hwmod,
2055         .clk            = "timer1_ick",
2056         .addr           = am33xx_timer1_addr_space,
2057         .user           = OCP_USER_MPU,
2058 };
2060 static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = {
2061         &am33xx_l4wkup__timer1,
2062 };
2064 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
2065         { .irq = AM33XX_IRQ_DMTIMER1 },
2066         { .irq = -1 }
2067 };
2069 static struct omap_hwmod am33xx_timer1_hwmod = {
2070         .name           = "timer1",
2071         .class          = &am33xx_timer1ms_hwmod_class,
2072         .mpu_irqs       = am33xx_timer1_irqs,
2073         .main_clk       = "timer1_fck",
2074         .clkdm_name     = "l4_wkup_clkdm",
2075         .prcm           = {
2076                 .omap4  = {
2077                         .clkctrl_offs   = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2078                         .modulemode     = MODULEMODE_SWCTRL,
2079                 },
2080         },
2081         .slaves         = am33xx_timer1_slaves,
2082         .slaves_cnt     = ARRAY_SIZE(am33xx_timer1_slaves),
2083 };
2085 /* timer2 */
2086 /* l4 per -> timer2 interface */
2087 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
2088         {
2089                 .pa_start       = AM33XX_TIMER2_BASE,
2090                 .pa_end         = AM33XX_TIMER2_BASE + SZ_1K - 1,
2091                 .flags          = ADDR_TYPE_RT
2092         },
2093         { }
2094 };
2096 static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = {
2097         .master         = &am33xx_l4per_hwmod,
2098         .slave          = &am33xx_timer2_hwmod,
2099         .clk            = "timer2_ick",
2100         .addr           = am33xx_timer2_addr_space,
2101         .user           = OCP_USER_MPU,
2102 };
2104 static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = {
2105         &am33xx_l4per__timer2,
2106 };
2108 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
2109         { .irq = AM33XX_IRQ_DMTIMER2 },
2110         { .irq = -1 }
2111 };
2113 static struct omap_hwmod am33xx_timer2_hwmod = {
2114         .name           = "timer2",
2115         .class          = &am33xx_timer_hwmod_class,
2116         .mpu_irqs       = am33xx_timer2_irqs,
2117         .main_clk       = "timer2_fck",
2118         .prcm           = {
2119                 .omap4  = {
2120                         .clkctrl_offs   = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
2121                         .modulemode     = MODULEMODE_SWCTRL,
2122                 },
2123         },
2124         .slaves         = am33xx_timer2_slaves,
2125         .slaves_cnt     = ARRAY_SIZE(am33xx_timer2_slaves),
2126         .clkdm_name     = "l4ls_clkdm",
2127 };
2129 /* timer3 */
2130 /* l4 per -> timer3 interface */
2131 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
2132         {
2133                 .pa_start       = AM33XX_TIMER3_BASE,
2134                 .pa_end         = AM33XX_TIMER3_BASE + SZ_1K - 1,
2135                 .flags          = ADDR_TYPE_RT
2136         },
2137         { }
2138 };
2140 static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = {
2141         .master         = &am33xx_l4per_hwmod,
2142         .slave          = &am33xx_timer3_hwmod,
2143         .clk            = "timer3_ick",
2144         .addr           = am33xx_timer3_addr_space,
2145         .user           = OCP_USER_MPU,
2146 };
2148 static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = {
2149         &am33xx_l4per__timer3,
2150 };
2152 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
2153         { .irq = AM33XX_IRQ_DMTIMER3 },
2154         { .irq = -1 }
2155 };
2157 static struct omap_hwmod am33xx_timer3_hwmod = {
2158         .name           = "timer3",
2159         .class          = &am33xx_timer_hwmod_class,
2160         .mpu_irqs       = am33xx_timer3_irqs,
2161         .main_clk       = "timer3_fck",
2162         .clkdm_name     = "l4ls_clkdm",
2163         .prcm           = {
2164                 .omap4  = {
2165                         .clkctrl_offs   = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
2166                         .modulemode     = MODULEMODE_SWCTRL,
2167                 },
2168         },
2169         .slaves         = am33xx_timer3_slaves,
2170         .slaves_cnt     = ARRAY_SIZE(am33xx_timer3_slaves),
2171 };
2173 /* timer4 */
2174 /* l4 per -> timer4 interface */
2175 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
2176         {
2177                 .pa_start       = AM33XX_TIMER4_BASE,
2178                 .pa_end         = AM33XX_TIMER4_BASE + SZ_1K - 1,
2179                 .flags          = ADDR_TYPE_RT
2180         },
2181         { }
2182 };
2184 static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = {
2185         .master         = &am33xx_l4per_hwmod,
2186         .slave          = &am33xx_timer4_hwmod,
2187         .clk            = "timer4_ick",
2188         .addr           = am33xx_timer4_addr_space,
2189         .user           = OCP_USER_MPU,
2190 };
2192 static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = {
2193         &am33xx_l4per__timer4,
2194 };
2196 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
2197         { .irq = AM33XX_IRQ_DMTIMER4 },
2198         { .irq = -1 }
2199 };
2201 static struct omap_hwmod am33xx_timer4_hwmod = {
2202         .name           = "timer4",
2203         .class          = &am33xx_timer_hwmod_class,
2204         .mpu_irqs       = am33xx_timer4_irqs,
2205         .main_clk       = "timer4_fck",
2206         .prcm           = {
2207                 .omap4  = {
2208                         .clkctrl_offs   = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
2209                         .modulemode     = MODULEMODE_SWCTRL,
2210                 },
2211         },
2212         .slaves         = am33xx_timer4_slaves,
2213         .slaves_cnt     = ARRAY_SIZE(am33xx_timer4_slaves),
2214         .clkdm_name     = "l4ls_clkdm",
2215 };
2218 /* timer5 */
2219 /* l4 per -> timer5 interface */
2220 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
2221         {
2222                 .pa_start       = AM33XX_TIMER5_BASE,
2223                 .pa_end         = AM33XX_TIMER5_BASE + SZ_1K - 1,
2224                 .flags          = ADDR_TYPE_RT
2225         },
2226         { }
2227 };
2229 static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = {
2230         .master         = &am33xx_l4per_hwmod,
2231         .slave          = &am33xx_timer5_hwmod,
2232         .clk            = "timer5_ick",
2233         .addr           = am33xx_timer5_addr_space,
2234         .user           = OCP_USER_MPU,
2235 };
2237 static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = {
2238         &am33xx_l4per__timer5,
2239 };
2241 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
2242         { .irq = AM33XX_IRQ_DMTIMER5 },
2243         { .irq = -1 }
2244 };
2246 static struct omap_hwmod am33xx_timer5_hwmod = {
2247         .name           = "timer5",
2248         .class          = &am33xx_timer_hwmod_class,
2249         .mpu_irqs       = am33xx_timer5_irqs,
2250         .main_clk       = "timer5_fck",
2251         .prcm           = {
2252                 .omap4  = {
2253                         .clkctrl_offs   = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
2254                         .modulemode     = MODULEMODE_SWCTRL,
2255                 },
2256         },
2257         .slaves         = am33xx_timer5_slaves,
2258         .slaves_cnt     = ARRAY_SIZE(am33xx_timer5_slaves),
2259         .clkdm_name     = "l4ls_clkdm",
2260 };
2262 /* timer6 */
2263 /* l4 per -> timer6 interface */
2264 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
2265         {
2266                 .pa_start       = AM33XX_TIMER6_BASE,
2267                 .pa_end         = AM33XX_TIMER6_BASE + SZ_1K - 1,
2268                 .flags          = ADDR_TYPE_RT
2269         },
2270         { }
2271 };
2273 static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = {
2274         .master         = &am33xx_l4per_hwmod,
2275         .slave          = &am33xx_timer6_hwmod,
2276         .clk            = "timer6_ick",
2277         .addr           = am33xx_timer6_addr_space,
2278         .user           = OCP_USER_MPU,
2279 };
2281 static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = {
2282         &am33xx_l4per__timer6,
2283 };
2285 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
2286         { .irq = AM33XX_IRQ_DMTIMER6 },
2287         { .irq = -1 }
2288 };
2290 static struct omap_hwmod am33xx_timer6_hwmod = {
2291         .name           = "timer6",
2292         .class          = &am33xx_timer_hwmod_class,
2293         .mpu_irqs       = am33xx_timer6_irqs,
2294         .main_clk       = "timer6_fck",
2295         .prcm           = {
2296                 .omap4  = {
2297                         .clkctrl_offs   = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
2298                         .modulemode     = MODULEMODE_SWCTRL,
2299                 },
2300         },
2301         .slaves         = am33xx_timer6_slaves,
2302         .slaves_cnt     = ARRAY_SIZE(am33xx_timer6_slaves),
2303         .clkdm_name     = "l4ls_clkdm",
2304 };
2306 /* timer7 */
2307 /* l4 per -> timer7 interface */
2308 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
2309         {
2310                 .pa_start       = AM33XX_TIMER7_BASE,
2311                 .pa_end         = AM33XX_TIMER7_BASE + SZ_1K - 1,
2312                 .flags          = ADDR_TYPE_RT
2313         },
2314         { }
2315 };
2317 static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = {
2318         .master         = &am33xx_l4per_hwmod,
2319         .slave          = &am33xx_timer7_hwmod,
2320         .clk            = "timer7_ick",
2321         .addr           = am33xx_timer7_addr_space,
2322         .user           = OCP_USER_MPU,
2323 };
2325 static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = {
2326         &am33xx_l4per__timer7,
2327 };
2329 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
2330         { .irq = AM33XX_IRQ_DMTIMER7 },
2331         { .irq = -1 }
2332 };
2334 static struct omap_hwmod am33xx_timer7_hwmod = {
2335         .name           = "timer7",
2336         .class          = &am33xx_timer_hwmod_class,
2337         .mpu_irqs       = am33xx_timer7_irqs,
2338         .main_clk       = "timer7_fck",
2339         .prcm           = {
2340                 .omap4  = {
2341                         .clkctrl_offs   = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
2342                         .modulemode     = MODULEMODE_SWCTRL,
2343                 },
2344         },
2345         .slaves         = am33xx_timer7_slaves,
2346         .slaves_cnt     = ARRAY_SIZE(am33xx_timer7_slaves),
2347         .clkdm_name     = "l4ls_clkdm",
2348 };
2350 /* 'tpcc' class */
2351 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
2352         .name           = "tpcc",
2353 };
2355 /* tpcc */
2356 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
2357         { .name = "edma0", .irq = AM33XX_IRQ_TPCC0_INT_PO0 },
2358         { .name = "edma0_err", .irq = AM33XX_IRQ_TPCC0_ERRINT_PO },
2359         { .irq = -1 },
2360 };
2362 /* TODO move this appropriate header. */
2363 #define AM33XX_TPCC_BASE                0x49000000
2365 static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
2366         {
2367                 .pa_start       = AM33XX_TPCC_BASE,
2368                 .pa_end         = AM33XX_TPCC_BASE + SZ_32K - 1,
2369                 .flags          = ADDR_TYPE_RT
2370         },
2371         { }
2372 };
2374 static struct omap_hwmod_ocp_if am33xx_l3_slow__tpcc = {
2375         .master         = &am33xx_l3slow_hwmod,
2376         .slave          = &am33xx_tpcc_hwmod,
2377         .addr           = am33xx_tpcc_addr_space,
2378         .user           = OCP_USER_MPU,
2379 };
2381 static struct omap_hwmod_ocp_if *am33xx_tpcc_slaves[] = {
2382         &am33xx_l3_slow__tpcc,
2383 };
2385 static struct omap_hwmod am33xx_tpcc_hwmod = {
2386         .name           = "tpcc",
2387         .class          = &am33xx_tpcc_hwmod_class,
2388         .mpu_irqs       = am33xx_tpcc_irqs,
2389         .main_clk       = "tpcc_ick",
2390         .clkdm_name     = "l3_clkdm",
2391         .prcm           = {
2392                 .omap4  = {
2393                         .clkctrl_offs   = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
2394                         .modulemode     = MODULEMODE_SWCTRL,
2395                 },
2396         },
2397         .slaves         = am33xx_tpcc_slaves,
2398         .slaves_cnt     = ARRAY_SIZE(am33xx_tpcc_slaves),
2399 };
2401 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
2402         .rev_offs       = 0x0,
2403         .sysc_offs      = 0x10,
2404         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2405                                 SYSC_HAS_MIDLEMODE),
2406         .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
2407         .sysc_fields    = &omap_hwmod_sysc_type2,
2408 };
2410 /* 'tptc' class */
2411 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
2412         .name           = "tptc",
2413         .sysc           = &am33xx_tptc_sysc,
2414 };
2416 /* tptc0 */
2417 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
2418         { .irq = AM33XX_IRQ_TPTC0 },
2419         { .irq = -1 }
2420 };
2422 struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
2423         {
2424                 .pa_start       = 0x49800000,
2425                 .pa_end         = 0x49800000 + SZ_8K - 1,
2426                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2427         },
2428         { }
2429 };
2431 struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
2432         .master         = &am33xx_l3_main_hwmod,
2433         .slave          = &am33xx_tptc0_hwmod,
2434         .addr           = am33xx_tptc0_addr_space,
2435         .user           = OCP_USER_MPU,
2436 };
2438 static struct omap_hwmod_ocp_if *am33xx_tptc0_slaves[] = {
2439         &am33xx_l3_main__tptc0,
2440 };
2442 static struct omap_hwmod am33xx_tptc0_hwmod = {
2443         .name           = "tptc0",
2444         .class          = &am33xx_tptc_hwmod_class,
2445         .mpu_irqs       = am33xx_tptc0_irqs,
2446         .main_clk       = "tptc0_ick",
2447         .clkdm_name     = "l3_clkdm",
2448         .prcm           = {
2449                 .omap4  = {
2450                         .clkctrl_offs   = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
2451                         .modulemode     = MODULEMODE_SWCTRL,
2452                 },
2453         },
2454         .slaves         = am33xx_tptc0_slaves,
2455         .slaves_cnt     = ARRAY_SIZE(am33xx_tptc0_slaves),
2456 };
2458 /* tptc1 */
2459 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
2460         { .irq = AM33XX_IRQ_TPTC1 },
2461         { .irq = -1 }
2462 };
2464 struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
2465         {
2466                 .pa_start       = 0x49900000,
2467                 .pa_end         = 0x49900000 + SZ_8K - 1,
2468                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2469         },
2470         { }
2471 };
2473 struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
2474         .master         = &am33xx_l3_main_hwmod,
2475         .slave          = &am33xx_tptc1_hwmod,
2476         .addr           = am33xx_tptc1_addr_space,
2477         .user           = OCP_USER_MPU,
2478 };
2480 static struct omap_hwmod_ocp_if *am33xx_tptc1_slaves[] = {
2481         &am33xx_l3_main__tptc1,
2482 };
2484 static struct omap_hwmod am33xx_tptc1_hwmod = {
2485         .name           = "tptc1",
2486         .class          = &am33xx_tptc_hwmod_class,
2487         .mpu_irqs       = am33xx_tptc1_irqs,
2488         .main_clk       = "tptc1_ick",
2489         .clkdm_name     = "l3_clkdm",
2490         .prcm           = {
2491                 .omap4  = {
2492                         .clkctrl_offs   = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
2493                         .modulemode     = MODULEMODE_SWCTRL,
2494                 },
2495         },
2496         .slaves         = am33xx_tptc1_slaves,
2497         .slaves_cnt     = ARRAY_SIZE(am33xx_tptc1_slaves),
2498 };
2500 /* tptc2 */
2501 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
2502         { .irq = AM33XX_IRQ_TPTC2 },
2503         { .irq = -1 }
2504 };
2506 struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
2507         {
2508                 .pa_start       = 0x49a00000,
2509                 .pa_end         = 0x49a00000 + SZ_8K - 1,
2510                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2511         },
2512         { }
2513 };
2515 struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
2516         .master         = &am33xx_l3_main_hwmod,
2517         .slave          = &am33xx_tptc2_hwmod,
2518         .addr           = am33xx_tptc2_addr_space,
2519         .user           = OCP_USER_MPU,
2520 };
2522 static struct omap_hwmod_ocp_if *am33xx_tptc2_slaves[] = {
2523         &am33xx_l3_main__tptc2,
2524 };
2526 static struct omap_hwmod am33xx_tptc2_hwmod = {
2527         .name           = "tptc2",
2528         .class          = &am33xx_tptc_hwmod_class,
2529         .mpu_irqs       = am33xx_tptc2_irqs,
2530         .main_clk       = "tptc2_ick",
2531         .clkdm_name     = "l3_clkdm",
2532         .prcm           = {
2533                 .omap4  = {
2534                         .clkctrl_offs   = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
2535                         .modulemode     = MODULEMODE_SWCTRL,
2536                 },
2537         },
2538         .slaves         = am33xx_tptc2_slaves,
2539         .slaves_cnt     = ARRAY_SIZE(am33xx_tptc2_slaves),
2540 };
2542 /* 'uart' class */
2543 static struct omap_hwmod_class_sysconfig uart_sysc = {
2544         .rev_offs       = 0x50,
2545         .sysc_offs      = 0x54,
2546         .syss_offs      = 0x58,
2547         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
2548                         SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2549                         SYSC_HAS_AUTOIDLE),
2550         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2551                         SIDLE_SMART_WKUP),
2552         .sysc_fields    = &omap_hwmod_sysc_type1,
2553 };
2555 static struct omap_hwmod_class uart_class = {
2556         .name           = "uart",
2557         .sysc           = &uart_sysc,
2558 };
2560 /* uart1 */
2561 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
2562         { .name = "tx", .dma_req = 26, },
2563         { .name = "rx", .dma_req = 27, },
2564         { .dma_req = -1 }
2565 };
2567 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
2568         {
2569                 .pa_start       = AM33XX_UART1_BASE,
2570                 .pa_end         = AM33XX_UART1_BASE + SZ_8K - 1,
2571                 .flags          = ADDR_TYPE_RT
2572         },
2573         { }
2574 };
2576 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
2577         .master         = &am33xx_l4wkup_hwmod,
2578         .slave          = &am33xx_uart1_hwmod,
2579         .clk            = "uart1_ick",
2580         .addr           = am33xx_uart1_addr_space,
2581         .user           = OCP_USER_MPU,
2582 };
2584 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
2585         { .irq = AM33XX_IRQ_UART0 },
2586         { .irq = -1 }
2587 };
2589 static struct omap_hwmod_ocp_if *am33xx_uart1_slaves[] = {
2590         &am33xx_l4_wkup__uart1,
2591 };
2593 static struct omap_hwmod am33xx_uart1_hwmod = {
2594         .name           = "uart1",
2595         .class          = &uart_class,
2596         .mpu_irqs       = am33xx_uart1_irqs,
2597         .sdma_reqs      = uart1_edma_reqs,
2598         .main_clk       = "uart1_fck",
2599         .clkdm_name     = "l4_wkup_clkdm",
2600         .prcm           = {
2601                 .omap4  = {
2602                         .clkctrl_offs   = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
2603                         .modulemode     = MODULEMODE_SWCTRL,
2604                 },
2605         },
2606         .slaves         = am33xx_uart1_slaves,
2607         .slaves_cnt     = ARRAY_SIZE(am33xx_uart1_slaves),
2608 };
2610 /* uart2 */
2611 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
2612         {
2613                 .pa_start       = AM33XX_UART2_BASE,
2614                 .pa_end         = AM33XX_UART2_BASE + SZ_8K - 1,
2615                 .flags          = ADDR_TYPE_RT
2616         },
2617         { }
2618 };
2620 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
2621         .slave          = &am33xx_uart2_hwmod,
2622         .clk            = "uart2_ick",
2623         .addr           = am33xx_uart2_addr_space,
2624         .user           = OCP_USER_MPU,
2625 };
2627 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
2628         { .irq = AM33XX_IRQ_UART1 },
2629         { .irq = -1 }
2630 };
2632 static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = {
2633         &am33xx_l4_ls__uart2,
2634 };
2636 static struct omap_hwmod am33xx_uart2_hwmod = {
2637         .name           = "uart2",
2638         .class          = &uart_class,
2639         .mpu_irqs       = am33xx_uart2_irqs,
2640         .main_clk       = "uart2_fck",
2641         .clkdm_name     = "l4ls_clkdm",
2642         .sdma_reqs      = uart1_edma_reqs,
2643         .prcm           = {
2644                 .omap4  = {
2645                         .clkctrl_offs   = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
2646                         .modulemode     = MODULEMODE_SWCTRL,
2647                 },
2648         },
2649         .slaves         = am33xx_uart2_slaves,
2650         .slaves_cnt     = ARRAY_SIZE(am33xx_uart2_slaves),
2651 };
2653 /* uart3 */
2654 static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
2655         { .name = "tx", .dma_req = 30, },
2656         { .name = "rx", .dma_req = 31, },
2657         { .dma_req = -1 }
2658 };
2660 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
2661         {
2662                 .pa_start       = AM33XX_UART3_BASE,
2663                 .pa_end         = AM33XX_UART3_BASE + SZ_8K - 1,
2664                 .flags          = ADDR_TYPE_RT
2665         },
2666         { }
2667 };
2669 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
2670         .slave          = &am33xx_uart3_hwmod,
2671         .clk            = "uart3_ick",
2672         .addr           = am33xx_uart3_addr_space,
2673         .user           = OCP_USER_MPU,
2674 };
2676 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2677         { .irq = AM33XX_IRQ_UART2 },
2678         { .irq = -1 }
2679 };
2681 static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = {
2682         &am33xx_l4_ls__uart3,
2683 };
2685 static struct omap_hwmod am33xx_uart3_hwmod = {
2686         .name           = "uart3",
2687         .class          = &uart_class,
2688         .mpu_irqs       = am33xx_uart3_irqs,
2689         .main_clk       = "uart3_fck",
2690         .clkdm_name     = "l4ls_clkdm",
2691         .sdma_reqs      = uart3_edma_reqs,
2692         .prcm           = {
2693                 .omap4  = {
2694                         .clkctrl_offs   = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
2695                         .modulemode     = MODULEMODE_SWCTRL,
2696                 },
2697         },
2698         .slaves         = am33xx_uart3_slaves,
2699         .slaves_cnt     = ARRAY_SIZE(am33xx_uart3_slaves),
2700 };
2702 /* uart4 */
2703 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
2704         {
2705                 .pa_start       = AM33XX_UART4_BASE,
2706                 .pa_end         = AM33XX_UART4_BASE + SZ_8K - 1,
2707                 .flags          = ADDR_TYPE_RT
2708         },
2709         { }
2710 };
2712 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
2713         .slave          = &am33xx_uart4_hwmod,
2714         .clk            = "uart4_ick",
2715         .addr           = am33xx_uart4_addr_space,
2716         .user           = OCP_USER_MPU,
2717 };
2719 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2720         { .irq = AM33XX_IRQ_UART3 },
2721         { .irq = -1 }
2722 };
2724 static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = {
2725         &am33xx_l4_ls__uart4,
2726 };
2728 static struct omap_hwmod am33xx_uart4_hwmod = {
2729         .name           = "uart4",
2730         .class          = &uart_class,
2731         .mpu_irqs       = am33xx_uart4_irqs,
2732         .main_clk       = "uart4_fck",
2733         .clkdm_name     = "l4ls_clkdm",
2734         .sdma_reqs      = uart1_edma_reqs,
2735         .prcm           = {
2736                 .omap4  = {
2737                         .clkctrl_offs   = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
2738                         .modulemode     = MODULEMODE_SWCTRL,
2739                 },
2740         },
2741         .slaves         = am33xx_uart4_slaves,
2742         .slaves_cnt     = ARRAY_SIZE(am33xx_uart4_slaves),
2743 };
2745 /* uart5 */
2746 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
2747         {
2748                 .pa_start       = AM33XX_UART5_BASE,
2749                 .pa_end         = AM33XX_UART5_BASE + SZ_8K - 1,
2750                 .flags          = ADDR_TYPE_RT
2751         },
2752         { }
2753 };
2755 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
2756         .slave          = &am33xx_uart5_hwmod,
2757         .clk            = "uart5_ick",
2758         .addr           = am33xx_uart5_addr_space,
2759         .user           = OCP_USER_MPU,
2760 };
2762 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2763         { .irq = AM33XX_IRQ_UART4 },
2764         { .irq = -1 }
2765 };
2767 static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = {
2768         &am33xx_l4_ls__uart5,
2769 };
2771 static struct omap_hwmod am33xx_uart5_hwmod = {
2772         .name           = "uart5",
2773         .class          = &uart_class,
2774         .mpu_irqs       = am33xx_uart5_irqs,
2775         .main_clk       = "uart5_fck",
2776         .clkdm_name     = "l4ls_clkdm",
2777         .sdma_reqs      = uart1_edma_reqs,
2778         .prcm           = {
2779                 .omap4  = {
2780                         .clkctrl_offs   = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2781                         .modulemode     = MODULEMODE_SWCTRL,
2782                 },
2783         },
2784         .slaves         = am33xx_uart5_slaves,
2785         .slaves_cnt     = ARRAY_SIZE(am33xx_uart5_slaves),
2786 };
2788 /* uart6 */
2789 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
2790         {
2791                 .pa_start       = AM33XX_UART6_BASE,
2792                 .pa_end         = AM33XX_UART6_BASE + SZ_8K - 1,
2793                 .flags          = ADDR_TYPE_RT
2794         },
2795         { }
2796 };
2798 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
2799         .slave          = &am33xx_uart6_hwmod,
2800         .clk            = "uart6_ick",
2801         .addr           = am33xx_uart6_addr_space,
2802         .user           = OCP_USER_MPU,
2803 };
2805 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2806         { .irq = AM33XX_IRQ_UART5 },
2807         { .irq = -1 }
2808 };
2810 static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = {
2811         &am33xx_l4_ls__uart6,
2812 };
2814 static struct omap_hwmod am33xx_uart6_hwmod = {
2815         .name           = "uart6",
2816         .class          = &uart_class,
2817         .mpu_irqs       = am33xx_uart6_irqs,
2818         .main_clk       = "uart6_fck",
2819         .clkdm_name     = "l4ls_clkdm",
2820         .sdma_reqs      = uart1_edma_reqs,
2821         .prcm           = {
2822                 .omap4  = {
2823                         .clkctrl_offs   = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2824                         .modulemode     = MODULEMODE_SWCTRL,
2825                 },
2826         },
2827         .slaves         = am33xx_uart6_slaves,
2828         .slaves_cnt     = ARRAY_SIZE(am33xx_uart6_slaves),
2829 };
2831 /* 'wd_timer' class */
2832 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2833         .name           = "wd_timer",
2834 };
2836 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
2837         {
2838                 .pa_start       = AM33XX_WDT1_BASE,
2839                 .pa_end         = AM33XX_WDT1_BASE + SZ_4K - 1,
2840                 .flags          = ADDR_TYPE_RT
2841         },
2842         { }
2843 };
2845 /* l4_wkup -> wd_timer1 */
2846 static struct omap_hwmod_ocp_if am33xx_l4wkup__wd_timer1 = {
2847         .master         = &am33xx_l4wkup_hwmod,
2848         .slave          = &am33xx_wd_timer1_hwmod,
2849         .addr           = am33xx_wd_timer1_addrs,
2850         .user           = OCP_USER_MPU,
2851 };
2853 /* wd_timer1 slave ports */
2854 static struct omap_hwmod_ocp_if *am33xx_wd_timer1_slaves[] = {
2855         &am33xx_l4wkup__wd_timer1,
2856 };
2858 /* wd_timer1 */
2859 /*
2860  * TODO: device.c file uses hardcoded name for watchdog
2861          timer driver "wd_timer2, so we are also using
2862          same name as of now...
2863  */
2864 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2865         .name           = "wd_timer2",
2866         .class          = &am33xx_wd_timer_hwmod_class,
2867         .main_clk       = "wd_timer1_fck",
2868         .clkdm_name     = "l4_wkup_clkdm",
2869         .prcm           = {
2870                 .omap4  = {
2871                         .clkctrl_offs   = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2872                         .modulemode     = MODULEMODE_SWCTRL,
2873                 },
2874         },
2875         .slaves         = am33xx_wd_timer1_slaves,
2876         .slaves_cnt     = ARRAY_SIZE(am33xx_wd_timer1_slaves),
2877 };
2879 /* wdt0 */
2880 static struct omap_hwmod_irq_info am33xx_wdt0_irqs[] = {
2881         { .irq = AM33XX_IRQ_WDT0 },
2882         { .irq = -1 },
2883 };
2885 static struct omap_hwmod am33xx_wdt0_hwmod = {
2886         .name           = "wdt0",
2887         .class          = &am33xx_wd_timer_hwmod_class,
2888         .mpu_irqs       = am33xx_wdt0_irqs,
2889         .main_clk       = "wdt0_fck",
2890         .clkdm_name     = "l4_wkup_clkdm",
2891         .prcm           = {
2892                 .omap4  = {
2893                         .clkctrl_offs   = AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET,
2894                         .modulemode     = MODULEMODE_SWCTRL,
2895                 },
2896         },
2897 };
2899 /* 'wkup_m3' class */
2900 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
2901         .name           = "wkup_m3",
2902 };
2904 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
2905         { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
2906 };
2908 /* wkup_m3 */
2909 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
2910         .name           = "wkup_m3",
2911         .class          = &am33xx_wkup_m3_hwmod_class,
2912         .clkdm_name     = "l4_wkup_aon_clkdm",
2913         .main_clk       = "wkup_m3_fck",
2914         .rst_lines      = am33xx_wkup_m3_resets,
2915         .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
2916         .prcm           = {
2917                 .omap4  = {
2918                         .clkctrl_offs   = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
2919                         .rstctrl_offs   = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
2920                         .modulemode     = MODULEMODE_SWCTRL,
2921                 },
2922         },
2923         .flags          = HWMOD_INIT_NO_RESET,  /* Keep hardreset asserted */
2924 };
2926 /* L3 SLOW -> USBSS interface */
2927 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
2928         {
2929                 .name           = "usbss",
2930                 .pa_start       = AM33XX_USBSS_BASE,
2931                 .pa_end         = AM33XX_USBSS_BASE + SZ_4K - 1,
2932                 .flags          = ADDR_TYPE_RT
2933         },
2934         {
2935                 .name           = "musb0",
2936                 .pa_start       = AM33XX_USB0_BASE,
2937                 .pa_end         = AM33XX_USB0_BASE + SZ_2K - 1,
2938                 .flags          = ADDR_TYPE_RT
2939         },
2940         {
2941                 .name           = "musb1",
2942                 .pa_start       = AM33XX_USB1_BASE,
2943                 .pa_end         = AM33XX_USB1_BASE + SZ_2K - 1,
2944                 .flags          = ADDR_TYPE_RT
2945         },
2946         { }
2947 };
2949 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2950         .rev_offs       = 0x0,
2951         .sysc_offs      = 0x10,
2952         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
2953         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2954                                 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2955         .sysc_fields    = &omap_hwmod_sysc_type4,
2956 };
2958 static struct omap_hwmod_class am33xx_usbotg_class = {
2959         .name           = "usbotg",
2960         .sysc           = &am33xx_usbhsotg_sysc,
2961 };
2963 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2964         { .name = "usbss-irq", .irq = AM33XX_IRQ_USBSS, },
2965         { .name = "musb0-irq", .irq = AM33XX_IRQ_USB0, },
2966         { .name = "musb1-irq", .irq = AM33XX_IRQ_USB1, },
2967         { .irq = -1, },
2968 };
2970 static struct omap_hwmod_ocp_if am33xx_l3_slow__usbss = {
2971         .master         = &am33xx_l3slow_hwmod,
2972         .slave          = &am33xx_usbss_hwmod,
2973         .addr           = am33xx_usbss_addr_space,
2974         .user           = OCP_USER_MPU,
2975         .flags          = OCPIF_SWSUP_IDLE,
2976 };
2978 static struct omap_hwmod_ocp_if *am33xx_usbss_slaves[] = {
2979         &am33xx_l3_slow__usbss,
2980 };
2982 static struct omap_hwmod_opt_clk usbss_opt_clks[] = {
2983         { .role = "clkdcoldo", .clk = "usbotg_fck" },
2984 };
2986 static struct omap_hwmod am33xx_usbss_hwmod = {
2987         .name           = "usb_otg_hs",
2988         .mpu_irqs       = am33xx_usbss_mpu_irqs,
2989         .main_clk       = "usbotg_ick",
2990         .clkdm_name     = "l4ls_clkdm",
2991         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2992         .prcm           = {
2993                 .omap4  = {
2994                         .clkctrl_offs   = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2995                         .modulemode     = MODULEMODE_SWCTRL,
2996                 },
2997         },
2998         .opt_clks       = usbss_opt_clks,
2999         .opt_clks_cnt   = ARRAY_SIZE(usbss_opt_clks),
3000         .slaves         = am33xx_usbss_slaves,
3001         .slaves_cnt     = ARRAY_SIZE(am33xx_usbss_slaves),
3002         .class          = &am33xx_usbotg_class,
3003 };
3005 static __initdata struct omap_hwmod *am33xx_hwmods[] = {
3006         /* l3 class */
3007         &am33xx_l3_instr_hwmod,
3008         &am33xx_l3_main_hwmod,
3009         /* l3s class */
3010         &am33xx_l3slow_hwmod,
3011         /* l4hs class */
3012         &am33xx_l4_hs_hwmod,
3013         /* l4fw class */
3014         &am33xx_l4fw_hwmod,
3015         /* l4ls class */
3016         &am33xx_l4ls_hwmod,
3017         /* l4per class */
3018         &am33xx_l4per_hwmod,
3019         /* l4wkup class */
3020         &am33xx_l4wkup_hwmod,
3022         /* clkdiv32k class */
3023         &am33xx_clkdiv32k_hwmod,
3024         /* mpu class */
3025         &am33xx_mpu_hwmod,
3026         /* adc_tsc class */
3027         &am33xx_adc_tsc_hwmod,
3028         /* aes class */
3029         &am33xx_aes0_hwmod,
3030         /* cefuse class */
3031         &am33xx_cefuse_hwmod,
3032         /* control class */
3033         &am33xx_control_hwmod,
3034         /* dcan class */
3035         &am33xx_dcan0_hwmod,
3036         &am33xx_dcan1_hwmod,
3037         /* debugss class */
3038         &am33xx_debugss_hwmod,
3039         /* elm class */
3040         &am33xx_elm_hwmod,
3041         /* emif_fw class */
3042         &am33xx_emif_fw_hwmod,
3043         /* epwmss class */
3044         &am33xx_epwmss0_hwmod,
3045         &am33xx_epwmss1_hwmod,
3046         &am33xx_epwmss2_hwmod,
3047         /* gpio class */
3048         &am33xx_gpio0_hwmod,
3049         &am33xx_gpio1_hwmod,
3050         &am33xx_gpio2_hwmod,
3051         &am33xx_gpio3_hwmod,
3052         /* gpmc class */
3053         &am33xx_gpmc_hwmod,
3054         /* i2c class */
3055         &am33xx_i2c1_hwmod,
3056         &am33xx_i2c2_hwmod,
3057         &am33xx_i2c3_hwmod,
3058         /* icss class */
3059         &am33xx_icss_hwmod,
3060         /* ieee5000 class */
3061         &am33xx_ieee5000_hwmod,
3062         /* mailbox class */
3063         &am33xx_mailbox_hwmod,
3064         /* mcasp class */
3065         &am33xx_mcasp0_hwmod,
3066         &am33xx_mcasp1_hwmod,
3067         /* mmc class */
3068         &am33xx_mmc0_hwmod,
3069         &am33xx_mmc1_hwmod,
3070         &am33xx_mmc2_hwmod,
3071         /* ocmcram class */
3072         &am33xx_ocmcram_hwmod,
3073         /* ocpwp class */
3074         &am33xx_ocpwp_hwmod,
3075         /* sha0 class */
3076         &am33xx_sha0_hwmod,
3077         /* smartreflex class */
3078         &am33xx_smartreflex0_hwmod,
3079         &am33xx_smartreflex1_hwmod,
3080         /* spi class */
3081         &am33xx_spi0_hwmod,
3082         &am33xx_spi1_hwmod,
3083         /* spinlock class */
3084         &am33xx_spinlock_hwmod,
3085         /* uart class */
3086         &am33xx_uart1_hwmod,
3087         &am33xx_uart2_hwmod,
3088         &am33xx_uart3_hwmod,
3089         &am33xx_uart4_hwmod,
3090         &am33xx_uart5_hwmod,
3091         &am33xx_uart6_hwmod,
3092         /* timer class */
3093         &am33xx_timer0_hwmod,
3094         &am33xx_timer1_hwmod,
3095         &am33xx_timer2_hwmod,
3096         &am33xx_timer3_hwmod,
3097         &am33xx_timer4_hwmod,
3098         &am33xx_timer5_hwmod,
3099         &am33xx_timer6_hwmod,
3100         &am33xx_timer7_hwmod,
3101         /* wkup_m3 class */
3102         &am33xx_wkup_m3_hwmod,
3103         /* wd_timer class */
3104         &am33xx_wd_timer1_hwmod,
3105         /* usbss hwmod */
3106         &am33xx_usbss_hwmod,
3107         /* cpgmac0 class */
3108         &am33xx_cpgmac0_hwmod,
3109         &am33xx_wdt0_hwmod, /* Secure WDT */
3110         /* tptc class */
3111         &am33xx_tptc0_hwmod,
3112         &am33xx_tptc1_hwmod,
3113         &am33xx_tptc2_hwmod,
3114         /* tpcc class */
3115         &am33xx_tpcc_hwmod,
3116         /* LCDC class */
3117         &am33xx_lcdc_hwmod,
3118         /* rtc */
3119         &am33xx_rtc_hwmod,
3120         NULL,
3121 };
3123 int __init am33xx_hwmod_init(void)
3125         return omap_hwmod_register(am33xx_hwmods);