1 /*
2 * Hardware modules present on the AM33XX chips
3 *
4 * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
17 #include <linux/io.h>
19 #include <plat/omap_hwmod.h>
20 #include <plat/cpu.h>
21 #include <plat/gpio.h>
22 #include <plat/dma.h>
23 #include <plat/mmc.h>
24 #include <plat/mcspi.h>
26 #include "omap_hwmod_common_data.h"
27 #include "control.h"
28 #include "cm33xx.h"
29 #include "prm33xx.h"
31 /* Backward references (IPs with Bus Master capability) */
32 static struct omap_hwmod am33xx_mpu_hwmod;
33 static struct omap_hwmod am33xx_l3slow_hwmod;
34 static struct omap_hwmod am33xx_l4wkup_hwmod;
35 static struct omap_hwmod am33xx_l4per_hwmod;
36 static struct omap_hwmod am33xx_uart1_hwmod;
37 static struct omap_hwmod am33xx_uart2_hwmod;
38 static struct omap_hwmod am33xx_uart3_hwmod;
39 static struct omap_hwmod am33xx_uart4_hwmod;
40 static struct omap_hwmod am33xx_uart5_hwmod;
41 static struct omap_hwmod am33xx_uart6_hwmod;
42 static struct omap_hwmod am33xx_timer0_hwmod;
43 static struct omap_hwmod am33xx_timer1_hwmod;
44 static struct omap_hwmod am33xx_timer2_hwmod;
45 static struct omap_hwmod am33xx_timer3_hwmod;
46 static struct omap_hwmod am33xx_timer4_hwmod;
47 static struct omap_hwmod am33xx_timer5_hwmod;
48 static struct omap_hwmod am33xx_timer6_hwmod;
49 static struct omap_hwmod am33xx_timer7_hwmod;
50 static struct omap_hwmod am33xx_wd_timer1_hwmod;
51 static struct omap_hwmod am33xx_cpgmac0_hwmod;
52 static struct omap_hwmod am33xx_icss_hwmod;
53 static struct omap_hwmod am33xx_ieee5000_hwmod;
54 static struct omap_hwmod am33xx_tptc0_hwmod;
55 static struct omap_hwmod am33xx_tptc1_hwmod;
56 static struct omap_hwmod am33xx_tptc2_hwmod;
57 static struct omap_hwmod am33xx_gpio0_hwmod;
58 static struct omap_hwmod am33xx_gpio1_hwmod;
59 static struct omap_hwmod am33xx_gpio2_hwmod;
60 static struct omap_hwmod am33xx_gpio3_hwmod;
61 static struct omap_hwmod am33xx_i2c1_hwmod;
62 static struct omap_hwmod am33xx_i2c2_hwmod;
63 static struct omap_hwmod am33xx_usbss_hwmod;
64 static struct omap_hwmod am33xx_mmc0_hwmod;
65 static struct omap_hwmod am33xx_mmc1_hwmod;
66 static struct omap_hwmod am33xx_mmc2_hwmod;
67 static struct omap_hwmod am33xx_spi0_hwmod;
68 static struct omap_hwmod am33xx_spi1_hwmod;
69 static struct omap_hwmod am33xx_elm_hwmod;
70 static struct omap_hwmod am33xx_adc_tsc_hwmod;
71 static struct omap_hwmod am33xx_tpcc_hwmod;
72 static struct omap_hwmod am33xx_mcasp0_hwmod;
73 static struct omap_hwmod am33xx_mcasp1_hwmod;
75 /*
76 * Interconnects hwmod structures
77 * hwmods that compose the global AM33XX OCP interconnect
78 */
80 /* MPU -> L3_SLOW Peripheral interface */
81 static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = {
82 .master = &am33xx_mpu_hwmod,
83 .slave = &am33xx_l3slow_hwmod,
84 .user = OCP_USER_MPU,
85 };
87 /* L3 SLOW -> L4_PER Peripheral interface */
88 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = {
89 .master = &am33xx_l3slow_hwmod,
90 .slave = &am33xx_l4per_hwmod,
91 .user = OCP_USER_MPU,
92 };
94 /* L3 SLOW -> L4_WKUP Peripheral interface */
95 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = {
96 .master = &am33xx_l3slow_hwmod,
97 .slave = &am33xx_l4wkup_hwmod,
98 .user = OCP_USER_MPU,
99 };
101 /* Master interfaces on the L4_WKUP interconnect */
102 static struct omap_hwmod_ocp_if *am33xx_l3_slow_masters[] = {
103 &am33xx_l3_slow__l4_per,
104 &am33xx_l3_slow__l4_wkup,
105 };
107 /* Slave interfaces on the L3_SLOW interconnect */
108 static struct omap_hwmod_ocp_if *am33xx_l3_slow_slaves[] = {
109 &am33xx_mpu__l3_slow,
110 };
112 static struct omap_hwmod am33xx_l3slow_hwmod = {
113 .name = "l3_slow",
114 .class = &l3_hwmod_class,
115 .clkdm_name = "l3s_clkdm",
116 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
117 .masters = am33xx_l3_slow_masters,
118 .masters_cnt = ARRAY_SIZE(am33xx_l3_slow_masters),
119 .slaves = am33xx_l3_slow_slaves,
120 .slaves_cnt = ARRAY_SIZE(am33xx_l3_slow_slaves),
121 };
123 /* L4 PER -> GPIO2 */
124 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
125 {
126 .pa_start = AM33XX_GPIO1_BASE,
127 .pa_end = AM33XX_GPIO1_BASE + SZ_4K - 1,
128 .flags = ADDR_TYPE_RT
129 },
130 { }
131 };
133 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
134 .master = &am33xx_l4per_hwmod,
135 .slave = &am33xx_gpio1_hwmod,
136 .clk = "l4ls_fck",
137 .addr = am33xx_gpio1_addrs,
138 .user = OCP_USER_MPU | OCP_USER_SDMA,
139 };
141 /* L4 PER -> GPIO3 */
142 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
143 {
144 .pa_start = AM33XX_GPIO2_BASE,
145 .pa_end = AM33XX_GPIO2_BASE + SZ_4K - 1,
146 .flags = ADDR_TYPE_RT
147 },
148 { }
149 };
151 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
152 .master = &am33xx_l4per_hwmod,
153 .slave = &am33xx_gpio2_hwmod,
154 .clk = "l4ls_fck",
155 .addr = am33xx_gpio2_addrs,
156 .user = OCP_USER_MPU | OCP_USER_SDMA,
157 };
159 /* L4 PER -> GPIO4 */
160 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
161 {
162 .pa_start = AM33XX_GPIO3_BASE,
163 .pa_end = AM33XX_GPIO3_BASE + SZ_4K - 1,
164 .flags = ADDR_TYPE_RT
165 },
166 { }
167 };
169 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
170 .master = &am33xx_l4per_hwmod,
171 .slave = &am33xx_gpio3_hwmod,
172 .clk = "l4ls_fck",
173 .addr = am33xx_gpio3_addrs,
174 .user = OCP_USER_MPU | OCP_USER_SDMA,
175 };
177 /* Master interfaces on the L4_PER interconnect */
178 static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = {
179 &am33xx_l4_per__gpio1,
180 &am33xx_l4_per__gpio2,
181 &am33xx_l4_per__gpio3,
182 };
183 /* Slave interfaces on the L4_PER interconnect */
184 static struct omap_hwmod_ocp_if *am33xx_l4_per_slaves[] = {
185 &am33xx_l3_slow__l4_per,
186 };
188 static struct omap_hwmod am33xx_l4per_hwmod = {
189 .name = "l4_per",
190 .class = &l4_hwmod_class,
191 .clkdm_name = "l4ls_clkdm",
192 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
193 .masters = am33xx_l4_per_masters,
194 .masters_cnt = ARRAY_SIZE(am33xx_l4_per_masters),
195 .slaves = am33xx_l4_per_slaves,
196 .slaves_cnt = ARRAY_SIZE(am33xx_l4_per_slaves),
197 };
199 /* L4 WKUP -> I2C1 */
200 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
201 {
202 .pa_start = AM33XX_I2C0_BASE,
203 .pa_end = AM33XX_I2C0_BASE + SZ_4K - 1,
204 .flags = ADDR_TYPE_RT
205 },
206 { }
207 };
209 static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = {
210 .master = &am33xx_l4wkup_hwmod,
211 .slave = &am33xx_i2c1_hwmod,
212 .addr = am33xx_i2c1_addr_space,
213 .user = OCP_USER_MPU,
214 };
216 /* L4 WKUP -> GPIO1 */
217 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
218 {
219 .pa_start = AM33XX_GPIO0_BASE,
220 .pa_end = AM33XX_GPIO0_BASE + SZ_4K - 1,
221 .flags = ADDR_TYPE_RT
222 },
223 { }
224 };
226 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
227 .master = &am33xx_l4wkup_hwmod,
228 .slave = &am33xx_gpio0_hwmod,
229 .clk = "l4ls_fck",
230 .addr = am33xx_gpio0_addrs,
231 .user = OCP_USER_MPU | OCP_USER_SDMA,
232 };
234 /* L4 WKUP -> ADC_TSC */
235 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
236 {
237 .pa_start = AM33XX_TSC_BASE,
238 .pa_end = AM33XX_TSC_BASE + SZ_8K - 1,
239 .flags = ADDR_TYPE_RT
240 },
241 { }
242 };
244 static struct omap_hwmod_ocp_if am33xx_l4_wkup_adc_tsc = {
245 .master = &am33xx_l4wkup_hwmod,
246 .slave = &am33xx_adc_tsc_hwmod,
247 .addr = am33xx_adc_tsc_addrs,
248 .user = OCP_USER_MPU,
249 };
251 /* Master interfaces on the L4_WKUP interconnect */
252 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = {
253 &am33xx_l4_wkup__gpio0,
254 };
255 /* Slave interfaces on the L4_WKUP interconnect */
256 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_slaves[] = {
257 &am33xx_l3_slow__l4_wkup,
258 };
260 static struct omap_hwmod am33xx_l4wkup_hwmod = {
261 .name = "l4_wkup",
262 .class = &l4_hwmod_class,
263 .clkdm_name = "l4_wkup_clkdm",
264 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
265 .masters = am33xx_l4_wkup_masters,
266 .masters_cnt = ARRAY_SIZE(am33xx_l4_wkup_masters),
267 .slaves = am33xx_l4_wkup_slaves,
268 .slaves_cnt = ARRAY_SIZE(am33xx_l4_wkup_slaves),
269 };
271 /* 'adc_tsc' class */
272 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
273 .name = "adc_tsc",
274 };
276 /* adc_tsc */
277 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
278 { .irq = AM33XX_IRQ_TSC },
279 { .irq = -1 }
280 };
282 static struct omap_hwmod_ocp_if *am33xx_adc_tsc_slaves[] = {
283 &am33xx_l4_wkup_adc_tsc,
284 };
286 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
287 .name = "adc_tsc",
288 .class = &am33xx_adc_tsc_hwmod_class,
289 .mpu_irqs = am33xx_adc_tsc_irqs,
290 .main_clk = "adc_tsc_fck",
291 .clkdm_name = "l4_wkup_clkdm",
292 .prcm = {
293 .omap4 = {
294 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
295 .modulemode = MODULEMODE_SWCTRL,
296 },
297 },
298 .flags = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
299 .slaves = am33xx_adc_tsc_slaves,
300 .slaves_cnt = ARRAY_SIZE(am33xx_adc_tsc_slaves),
301 };
303 /* 'aes' class */
304 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
305 .name = "aes",
306 };
308 /* aes0 */
309 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
310 { .irq = AM33XX_IRQ_AESEIP36t0_S },
311 { .irq = -1 }
312 };
314 static struct omap_hwmod am33xx_aes0_hwmod = {
315 .name = "aes0",
316 .class = &am33xx_aes_hwmod_class,
317 .mpu_irqs = am33xx_aes0_irqs,
318 .main_clk = "aes0_fck",
319 .clkdm_name = "l3_clkdm",
320 .prcm = {
321 .omap4 = {
322 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
323 .modulemode = MODULEMODE_SWCTRL,
324 },
325 },
326 };
328 /* 'cefuse' class */
329 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
330 .name = "cefuse",
331 };
333 /* cefuse */
334 static struct omap_hwmod am33xx_cefuse_hwmod = {
335 .name = "cefuse",
336 .class = &am33xx_cefuse_hwmod_class,
337 .main_clk = "cefuse_fck",
338 .clkdm_name = "l4_cefuse_clkdm",
339 .prcm = {
340 .omap4 = {
341 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
342 .modulemode = MODULEMODE_SWCTRL,
343 },
344 },
345 };
347 /* 'clkdiv32k' class */
348 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
349 .name = "clkdiv32k",
350 };
352 /* clkdiv32k */
353 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
354 .name = "clkdiv32k",
355 .class = &am33xx_clkdiv32k_hwmod_class,
356 .main_clk = "clkdiv32k_fck",
357 .clkdm_name = "clk_24mhz_clkdm",
358 .prcm = {
359 .omap4 = {
360 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
361 .modulemode = MODULEMODE_SWCTRL,
362 },
363 },
364 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
365 };
367 /* 'control' class */
368 static struct omap_hwmod_class am33xx_control_hwmod_class = {
369 .name = "control",
370 };
372 /* control */
373 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
374 { .irq = AM33XX_IRQ_CONTROL_PLATFORM },
375 { .irq = -1 }
376 };
378 static struct omap_hwmod am33xx_control_hwmod = {
379 .name = "control",
380 .class = &am33xx_control_hwmod_class,
381 .mpu_irqs = am33xx_control_irqs,
382 .main_clk = "control_fck",
383 .clkdm_name = "l4_wkup_clkdm",
384 .prcm = {
385 .omap4 = {
386 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
387 .modulemode = MODULEMODE_SWCTRL,
388 },
389 },
390 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
391 };
393 /* 'cpgmac0' class */
394 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
395 .name = "cpgmac0",
396 };
398 /* cpgmac0 */
399 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
400 .name = "cpgmac0",
401 .class = &am33xx_cpgmac0_hwmod_class,
402 .main_clk = "cpgmac0_fck",
403 .clkdm_name = "cpsw_125mhz_clkdm",
404 .prcm = {
405 .omap4 = {
406 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
407 .modulemode = MODULEMODE_SWCTRL,
408 },
409 },
410 };
412 /* 'dcan' class */
413 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
414 .name = "dcan",
415 };
417 /* dcan0 */
418 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
419 { .irq = AM33XX_IRQ_DCAN0_0 },
420 { .irq = -1 }
421 };
423 static struct omap_hwmod am33xx_dcan0_hwmod = {
424 .name = "dcan0",
425 .class = &am33xx_dcan_hwmod_class,
426 .mpu_irqs = am33xx_dcan0_irqs,
427 .main_clk = "dcan0_fck",
428 .clkdm_name = "l4ls_clkdm",
429 .prcm = {
430 .omap4 = {
431 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
432 .modulemode = MODULEMODE_SWCTRL,
433 },
434 },
435 };
437 /* dcan1 */
438 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
439 { .irq = AM33XX_IRQ_DCAN1_0 },
440 { .irq = -1 }
441 };
442 static struct omap_hwmod am33xx_dcan1_hwmod = {
443 .name = "dcan1",
444 .class = &am33xx_dcan_hwmod_class,
445 .mpu_irqs = am33xx_dcan1_irqs,
446 .main_clk = "dcan1_fck",
447 .clkdm_name = "l4ls_clkdm",
448 .prcm = {
449 .omap4 = {
450 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
451 .modulemode = MODULEMODE_SWCTRL,
452 },
453 },
454 };
456 /* 'debugss' class */
457 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
458 .name = "debugss",
459 };
461 /* debugss */
462 static struct omap_hwmod am33xx_debugss_hwmod = {
463 .name = "debugss",
464 .class = &am33xx_debugss_hwmod_class,
465 .main_clk = "debugss_fck",
466 .clkdm_name = "l3_aon_clkdm",
467 .prcm = {
468 .omap4 = {
469 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
470 .modulemode = MODULEMODE_SWCTRL,
471 },
472 },
473 #ifdef CONFIG_DEBUG_JTAG_ENABLE
474 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
475 #endif
476 };
478 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
479 .rev_offs = 0x0000,
480 .sysc_offs = 0x0010,
481 .syss_offs = 0x0014,
482 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
483 SYSC_HAS_SOFTRESET |
484 SYSS_HAS_RESET_STATUS),
485 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
486 .sysc_fields = &omap_hwmod_sysc_type1,
487 };
488 /* 'elm' class */
489 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
490 .name = "elm",
491 .sysc = &am33xx_elm_sysc,
492 };
494 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
495 { .irq = AM33XX_IRQ_ELM },
496 { .irq = -1 }
497 };
499 struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
500 {
501 .pa_start = AM33XX_ELM_BASE,
502 .pa_end = AM33XX_ELM_BASE + SZ_8K - 1,
503 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
504 },
505 { }
506 };
508 struct omap_hwmod_ocp_if am33xx_l4_core__elm = {
509 .master = &am33xx_l4per_hwmod,
510 .slave = &am33xx_elm_hwmod,
511 .addr = am33xx_elm_addr_space,
512 .user = OCP_USER_MPU,
513 };
515 static struct omap_hwmod_ocp_if *am33xx_elm_slaves[] = {
516 &am33xx_l4_core__elm,
517 };
519 /* elm */
520 static struct omap_hwmod am33xx_elm_hwmod = {
521 .name = "elm",
522 .class = &am33xx_elm_hwmod_class,
523 .mpu_irqs = am33xx_elm_irqs,
524 .main_clk = "elm_fck",
525 .clkdm_name = "l4ls_clkdm",
526 .slaves = am33xx_elm_slaves,
527 .slaves_cnt = ARRAY_SIZE(am33xx_elm_slaves),
528 .prcm = {
529 .omap4 = {
530 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
531 .modulemode = MODULEMODE_SWCTRL,
532 },
533 },
534 };
536 /* 'emif_fw' class */
537 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
538 .name = "emif_fw",
539 };
541 /* emif_fw */
542 static struct omap_hwmod am33xx_emif_fw_hwmod = {
543 .name = "emif_fw",
544 .class = &am33xx_emif_fw_hwmod_class,
545 .main_clk = "emif_fw_fck",
546 .clkdm_name = "l4fw_clkdm",
547 .prcm = {
548 .omap4 = {
549 .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
550 .modulemode = MODULEMODE_SWCTRL,
551 },
552 },
553 .flags = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
554 };
556 /* 'epwmss' class */
557 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
558 .name = "epwmss",
559 };
561 /* epwmss0 */
562 static struct omap_hwmod am33xx_epwmss0_hwmod = {
563 .name = "epwmss0",
564 .class = &am33xx_epwmss_hwmod_class,
565 .main_clk = "epwmss0_fck",
566 .clkdm_name = "l4ls_clkdm",
567 .prcm = {
568 .omap4 = {
569 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
570 .modulemode = MODULEMODE_SWCTRL,
571 },
572 },
573 };
575 /* epwmss1 */
576 static struct omap_hwmod am33xx_epwmss1_hwmod = {
577 .name = "epwmss1",
578 .class = &am33xx_epwmss_hwmod_class,
579 .main_clk = "epwmss1_fck",
580 .clkdm_name = "l4ls_clkdm",
581 .prcm = {
582 .omap4 = {
583 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
584 .modulemode = MODULEMODE_SWCTRL,
585 },
586 },
587 };
589 /* epwmss2 */
590 static struct omap_hwmod am33xx_epwmss2_hwmod = {
591 .name = "epwmss2",
592 .class = &am33xx_epwmss_hwmod_class,
593 .main_clk = "epwmss2_fck",
594 .clkdm_name = "l4ls_clkdm",
595 .prcm = {
596 .omap4 = {
597 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
598 .modulemode = MODULEMODE_SWCTRL,
599 },
600 },
601 };
603 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
604 .rev_offs = 0x0000,
605 .sysc_offs = 0x0010,
606 .syss_offs = 0x0114,
607 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
608 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
609 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
610 SIDLE_SMART_WKUP),
611 .sysc_fields = &omap_hwmod_sysc_type1,
612 };
614 /* 'gpio' class */
615 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
616 .name = "gpio",
617 .sysc = &am33xx_gpio_sysc,
618 .rev = 2,
619 };
621 /* gpio dev_attr */
622 static struct omap_gpio_dev_attr gpio_dev_attr = {
623 .bank_width = 32,
624 .dbck_flag = true,
625 };
627 /* gpio0 */
628 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
629 { .irq = AM33XX_IRQ_GPIO0_1 },
630 { .irq = -1 }
631 };
633 /* gpio0 slave ports */
634 static struct omap_hwmod_ocp_if *am33xx_gpio0_slaves[] = {
635 &am33xx_l4_wkup__gpio0,
636 };
638 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
639 { .role = "dbclk", .clk = "gpio0_dbclk" },
640 { .role = "fclk", .clk = "gpio0_fck" },
641 };
643 /* gpio0 */
644 static struct omap_hwmod am33xx_gpio0_hwmod = {
645 .name = "gpio1",
646 .class = &am33xx_gpio_hwmod_class,
647 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
648 .mpu_irqs = am33xx_gpio0_irqs,
649 .main_clk = "gpio0_fck",
650 .clkdm_name = "l4_wkup_clkdm",
651 .prcm = {
652 .omap4 = {
653 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
654 .modulemode = MODULEMODE_SWCTRL,
655 },
656 },
657 .opt_clks = gpio0_opt_clks,
658 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
659 .dev_attr = &gpio_dev_attr,
660 .slaves = am33xx_gpio0_slaves,
661 .slaves_cnt = ARRAY_SIZE(am33xx_gpio0_slaves),
662 };
664 /* gpio1 */
665 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
666 { .irq = AM33XX_IRQ_GPIO1_1 },
667 { .irq = -1 }
668 };
670 /* gpio1 slave ports */
671 static struct omap_hwmod_ocp_if *am33xx_gpio1_slaves[] = {
672 &am33xx_l4_per__gpio1,
673 };
675 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
676 { .role = "dbclk", .clk = "gpio1_dbclk" },
677 { .role = "fclk", .clk = "gpio1_fck" },
678 };
680 static struct omap_hwmod am33xx_gpio1_hwmod = {
681 .name = "gpio2",
682 .class = &am33xx_gpio_hwmod_class,
683 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
684 .mpu_irqs = am33xx_gpio1_irqs,
685 .main_clk = "gpio1_fck",
686 .clkdm_name = "l4ls_clkdm",
687 .prcm = {
688 .omap4 = {
689 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
690 .modulemode = MODULEMODE_SWCTRL,
691 },
692 },
693 .opt_clks = gpio1_opt_clks,
694 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
695 .dev_attr = &gpio_dev_attr,
696 .slaves = am33xx_gpio1_slaves,
697 .slaves_cnt = ARRAY_SIZE(am33xx_gpio1_slaves),
698 };
700 /* gpio2 */
701 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
702 { .irq = AM33XX_IRQ_GPIO2_1 },
703 { .irq = -1 }
704 };
706 /* gpio2 slave ports */
707 static struct omap_hwmod_ocp_if *am33xx_gpio2_slaves[] = {
708 &am33xx_l4_per__gpio2,
709 };
711 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
712 { .role = "dbclk", .clk = "gpio2_dbclk" },
713 { .role = "fclk", .clk = "gpio2_fck" },
714 };
716 /* gpio2 */
717 static struct omap_hwmod am33xx_gpio2_hwmod = {
718 .name = "gpio3",
719 .class = &am33xx_gpio_hwmod_class,
720 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
721 .mpu_irqs = am33xx_gpio2_irqs,
722 .main_clk = "gpio2_fck",
723 .clkdm_name = "l4ls_clkdm",
724 .prcm = {
725 .omap4 = {
726 .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
727 .modulemode = MODULEMODE_SWCTRL,
728 },
729 },
730 .opt_clks = gpio2_opt_clks,
731 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
732 .dev_attr = &gpio_dev_attr,
733 .slaves = am33xx_gpio2_slaves,
734 .slaves_cnt = ARRAY_SIZE(am33xx_gpio2_slaves),
735 };
737 /* gpio3 */
738 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
739 { .irq = AM33XX_IRQ_GPIO3_1 },
740 { .irq = -1 }
741 };
743 /* gpio3 slave ports */
744 static struct omap_hwmod_ocp_if *am33xx_gpio3_slaves[] = {
745 &am33xx_l4_per__gpio3,
746 };
748 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
749 { .role = "dbclk", .clk = "gpio3_dbclk" },
750 { .role = "fclk", .clk = "gpio3_fck" },
751 };
753 /* gpio3 */
754 static struct omap_hwmod am33xx_gpio3_hwmod = {
755 .name = "gpio4",
756 .class = &am33xx_gpio_hwmod_class,
757 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
758 .mpu_irqs = am33xx_gpio3_irqs,
759 .main_clk = "gpio3_fck",
760 .clkdm_name = "l4ls_clkdm",
761 .prcm = {
762 .omap4 = {
763 .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
764 .modulemode = MODULEMODE_SWCTRL,
765 },
766 },
767 .opt_clks = gpio3_opt_clks,
768 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
769 .dev_attr = &gpio_dev_attr,
770 .slaves = am33xx_gpio3_slaves,
771 .slaves_cnt = ARRAY_SIZE(am33xx_gpio3_slaves),
772 };
774 /* 'gpmc' class */
776 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
777 .name = "gpmc",
778 };
780 /* gpmc */
781 static struct omap_hwmod am33xx_gpmc_hwmod = {
782 .name = "gpmc",
783 .class = &am33xx_gpmc_hwmod_class,
784 .main_clk = "gpmc_fck",
785 .clkdm_name = "l3s_clkdm",
786 .prcm = {
787 .omap4 = {
788 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
789 .modulemode = MODULEMODE_SWCTRL,
790 },
791 },
792 };
794 /* 'i2c' class */
796 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
797 .sysc_offs = 0x0010,
798 .syss_offs = 0x0090,
799 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
800 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
801 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
802 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
803 SIDLE_SMART_WKUP),
804 .sysc_fields = &omap_hwmod_sysc_type1,
805 };
807 static struct omap_i2c_dev_attr i2c_dev_attr = {
808 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
809 };
811 static struct omap_hwmod_class i2c_class = {
812 .name = "i2c",
813 .sysc = &am33xx_i2c_sysc,
814 .rev = OMAP_I2C_IP_VERSION_2,
815 .reset = &omap_i2c_reset,
816 };
818 /* I2C1 */
819 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
820 { .irq = AM33XX_IRQ_MSHSI2COCP0 },
821 { .irq = -1 }
822 };
824 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
825 { .name = "tx", .dma_req = 0, },
826 { .name = "rx", .dma_req = 0, },
827 { .dma_req = -1 }
828 };
830 static struct omap_hwmod_ocp_if *am33xx_i2c1_slaves[] = {
831 &am33xx_l4_wkup_i2c1,
832 };
834 static struct omap_hwmod am33xx_i2c1_hwmod = {
835 .name = "i2c1",
836 .mpu_irqs = i2c1_mpu_irqs,
837 .sdma_reqs = i2c1_edma_reqs,
838 .main_clk = "i2c1_fck",
839 .clkdm_name = "l4_wkup_clkdm",
840 .prcm = {
841 .omap4 = {
842 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
843 .modulemode = MODULEMODE_SWCTRL,
844 },
845 },
846 .flags = HWMOD_16BIT_REG,
847 .dev_attr = &i2c_dev_attr,
848 .slaves = am33xx_i2c1_slaves,
849 .slaves_cnt = ARRAY_SIZE(am33xx_i2c1_slaves),
850 .class = &i2c_class,
851 };
853 /* i2c2 */
854 /* l4 per -> i2c2 */
855 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
856 {
857 .pa_start = AM33XX_I2C1_BASE,
858 .pa_end = AM33XX_I2C1_BASE + SZ_4K - 1,
859 .flags = ADDR_TYPE_RT
860 },
861 { }
862 };
864 static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = {
865 .master = &am33xx_l4per_hwmod,
866 .slave = &am33xx_i2c2_hwmod,
867 .addr = am33xx_i2c2_addr_space,
868 .user = OCP_USER_MPU,
869 };
871 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
872 { .irq = AM33XX_IRQ_MSHSI2COCP1 },
873 { .irq = -1 }
874 };
876 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
877 { .name = "tx", .dma_req = 0, },
878 { .name = "rx", .dma_req = 0, },
879 { .dma_req = -1 }
880 };
882 static struct omap_hwmod_ocp_if *am33xx_i2c2_slaves[] = {
883 &am335_l4_per_i2c2,
884 };
886 static struct omap_hwmod am33xx_i2c2_hwmod = {
887 .name = "i2c2",
888 .mpu_irqs = i2c2_mpu_irqs,
889 .sdma_reqs = i2c2_edma_reqs,
890 .main_clk = "i2c2_fck",
891 .clkdm_name = "l4ls_clkdm",
892 .prcm = {
893 .omap4 = {
894 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
895 .modulemode = MODULEMODE_SWCTRL,
896 },
897 },
898 .flags = HWMOD_16BIT_REG,
899 .dev_attr = &i2c_dev_attr,
900 .slaves = am33xx_i2c2_slaves,
901 .slaves_cnt = ARRAY_SIZE(am33xx_i2c2_slaves),
902 .class = &i2c_class,
903 };
905 /* 'icss' class */
906 static struct omap_hwmod_class am33xx_icss_hwmod_class = {
907 .name = "icss",
908 };
910 /* icss */
911 static struct omap_hwmod am33xx_icss_hwmod = {
912 .name = "icss",
913 .class = &am33xx_icss_hwmod_class,
914 .main_clk = "icss_fck",
915 .clkdm_name = "icss_ocp_clkdm",
916 .prcm = {
917 .omap4 = {
918 .clkctrl_offs = AM33XX_CM_PER_ICSS_CLKCTRL_OFFSET,
919 .modulemode = MODULEMODE_SWCTRL,
920 },
921 },
922 };
924 /* 'ieee5000' class */
925 static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = {
926 .name = "ieee5000",
927 };
929 /* ieee5000 */
930 static struct omap_hwmod am33xx_ieee5000_hwmod = {
931 .name = "ieee5000",
932 .class = &am33xx_ieee5000_hwmod_class,
933 .main_clk = "ieee5000_fck",
934 .clkdm_name = "l3s_clkdm",
935 .prcm = {
936 .omap4 = {
937 .clkctrl_offs = AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET,
938 .modulemode = MODULEMODE_SWCTRL,
939 },
940 },
941 };
944 /* 'l3' class */
945 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
946 .name = "l3",
947 };
949 /* l4_hs */
950 static struct omap_hwmod am33xx_l4_hs_hwmod = {
951 .name = "l4_hs",
952 .class = &am33xx_l3_hwmod_class,
953 .clkdm_name = "l4hs_clkdm",
954 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
955 .prcm = {
956 .omap4 = {
957 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
958 .modulemode = MODULEMODE_SWCTRL,
959 },
960 },
961 };
963 /* l3_instr */
964 static struct omap_hwmod am33xx_l3_instr_hwmod = {
965 .name = "l3_instr",
966 .class = &am33xx_l3_hwmod_class,
967 .clkdm_name = "l3_clkdm",
968 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
969 .prcm = {
970 .omap4 = {
971 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
972 .modulemode = MODULEMODE_SWCTRL,
973 },
974 },
975 };
977 /* l3_main */
978 static struct omap_hwmod am33xx_l3_main_hwmod = {
979 .name = "l3_main",
980 .class = &am33xx_l3_hwmod_class,
981 .clkdm_name = "l3_clkdm",
982 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
983 .prcm = {
984 .omap4 = {
985 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
986 .modulemode = MODULEMODE_SWCTRL,
987 },
988 },
989 };
991 /* 'l4fw' class */
992 static struct omap_hwmod_class am33xx_l4fw_hwmod_class = {
993 .name = "l4fw",
994 };
996 /* l4fw */
997 static struct omap_hwmod am33xx_l4fw_hwmod = {
998 .name = "l4fw",
999 .class = &am33xx_l4fw_hwmod_class,
1000 .clkdm_name = "l4fw_clkdm",
1001 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1002 .prcm = {
1003 .omap4 = {
1004 .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
1005 .modulemode = MODULEMODE_SWCTRL,
1006 },
1007 },
1008 };
1010 /* 'l4ls' class */
1011 static struct omap_hwmod_class am33xx_l4ls_hwmod_class = {
1012 .name = "l4ls",
1013 };
1015 /* l4ls */
1016 static struct omap_hwmod am33xx_l4ls_hwmod = {
1017 .name = "l4ls",
1018 .class = &am33xx_l4ls_hwmod_class,
1019 .main_clk = "l4ls_fck",
1020 .clkdm_name = "l4ls_clkdm",
1021 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1022 .prcm = {
1023 .omap4 = {
1024 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
1025 .modulemode = MODULEMODE_SWCTRL,
1026 },
1027 },
1028 };
1030 /* 'lcdc' class */
1031 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1032 .name = "lcdc",
1033 };
1035 /* lcdc */
1036 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1037 { .irq = AM33XX_IRQ_LCD },
1038 { .irq = -1 }
1039 };
1041 static struct omap_hwmod am33xx_lcdc_hwmod = {
1042 .name = "lcdc",
1043 .class = &am33xx_lcdc_hwmod_class,
1044 .mpu_irqs = am33xx_lcdc_irqs,
1045 .main_clk = "lcdc_fck",
1046 .clkdm_name = "lcdc_clkdm",
1047 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1048 .prcm = {
1049 .omap4 = {
1050 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1051 .modulemode = MODULEMODE_SWCTRL,
1052 },
1053 },
1054 };
1056 /*
1057 * 'mailbox' class
1058 * mailbox module allowing communication between the on-chip processors using a
1059 * queued mailbox-interrupt mechanism.
1060 */
1062 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1063 .rev_offs = 0x0000,
1064 .sysc_offs = 0x0010,
1065 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1066 SYSC_HAS_SOFTRESET),
1067 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1068 .sysc_fields = &omap_hwmod_sysc_type2,
1069 };
1071 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1072 .name = "mailbox",
1073 .sysc = &am33xx_mailbox_sysc,
1074 };
1076 /* mailbox */
1077 static struct omap_hwmod am33xx_mailbox_hwmod;
1078 static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1079 { .irq = AM33XX_IRQ_MAILBOX },
1080 { .irq = -1 }
1081 };
1083 static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
1084 {
1085 .pa_start = AM33XX_MAILBOX0_BASE,
1086 .pa_end = AM33XX_MAILBOX0_BASE + (SZ_4K - 1),
1087 .flags = ADDR_TYPE_RT
1088 },
1089 { }
1090 };
1092 /* l4_cfg -> mailbox */
1093 static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
1094 .master = &am33xx_l4per_hwmod,
1095 .slave = &am33xx_mailbox_hwmod,
1096 .addr = am33xx_mailbox_addrs,
1097 .user = OCP_USER_MPU,
1098 };
1100 /* mailbox slave ports */
1101 static struct omap_hwmod_ocp_if *am33xx_mailbox_slaves[] = {
1102 &am33xx_l4_per__mailbox,
1103 };
1105 static struct omap_hwmod am33xx_mailbox_hwmod = {
1106 .name = "mailbox",
1107 .class = &am33xx_mailbox_hwmod_class,
1108 .clkdm_name = "l4ls_clkdm",
1109 .mpu_irqs = am33xx_mailbox_irqs,
1110 .main_clk = "mailbox0_fck",
1111 .prcm = {
1112 .omap4 = {
1113 .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1114 .modulemode = MODULEMODE_SWCTRL,
1115 },
1116 },
1117 .slaves = am33xx_mailbox_slaves,
1118 .slaves_cnt = ARRAY_SIZE(am33xx_mailbox_slaves),
1119 };
1121 /* 'mcasp' class */
1122 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1123 .name = "mcasp",
1124 };
1126 /* mcasp0 */
1127 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1128 { .name = "ax", .irq = AM33XX_IRQ_MCASP0_AX, },
1129 { .name = "ar", .irq = AM33XX_IRQ_MCASP0_AR, },
1130 { .irq = -1 }
1131 };
1133 static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
1134 {
1135 .pa_start = AM33XX_ASP0_BASE,
1136 .pa_end = AM33XX_ASP0_BASE + (SZ_1K * 12) - 1,
1137 .flags = ADDR_TYPE_RT
1138 },
1139 { }
1140 };
1142 static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp0 = {
1143 .master = &am33xx_l3slow_hwmod,
1144 .slave = &am33xx_mcasp0_hwmod,
1145 .clk = "mcasp0_ick",
1146 .addr = am33xx_mcasp0_addr_space,
1147 .user = OCP_USER_MPU,
1148 };
1150 static struct omap_hwmod_ocp_if *am33xx_mcasp0_slaves[] = {
1151 &am33xx_l3_slow__mcasp0,
1152 };
1154 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1155 .name = "mcasp0",
1156 .class = &am33xx_mcasp_hwmod_class,
1157 .mpu_irqs = am33xx_mcasp0_irqs,
1158 .main_clk = "mcasp0_fck",
1159 .clkdm_name = "l3s_clkdm",
1160 .prcm = {
1161 .omap4 = {
1162 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1163 .modulemode = MODULEMODE_SWCTRL,
1164 },
1165 },
1166 .slaves = am33xx_mcasp0_slaves,
1167 .slaves_cnt = ARRAY_SIZE(am33xx_mcasp0_slaves),
1168 };
1170 /* mcasp1 */
1171 static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
1172 { .name = "ax", .irq = AM33XX_IRQ_MCASP1_AX, },
1173 { .name = "ar", .irq = AM33XX_IRQ_MCASP1_AR, },
1174 { .irq = -1 }
1175 };
1177 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
1178 {
1179 .pa_start = AM33XX_ASP1_BASE,
1180 .pa_end = AM33XX_ASP1_BASE + (SZ_1K * 12) - 1,
1181 .flags = ADDR_TYPE_RT
1182 },
1183 { }
1184 };
1186 static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp1 = {
1187 .master = &am33xx_l3slow_hwmod,
1188 .slave = &am33xx_mcasp1_hwmod,
1189 .clk = "mcasp1_ick",
1190 .addr = am33xx_mcasp1_addr_space,
1191 .user = OCP_USER_MPU,
1192 };
1194 static struct omap_hwmod_ocp_if *am33xx_mcasp1_slaves[] = {
1195 &am33xx_l3_slow__mcasp1,
1196 };
1198 static struct omap_hwmod am33xx_mcasp1_hwmod = {
1199 .name = "mcasp1",
1200 .class = &am33xx_mcasp_hwmod_class,
1201 .mpu_irqs = am33xx_mcasp1_irqs,
1202 .main_clk = "mcasp1_fck",
1203 .clkdm_name = "l3s_clkdm",
1204 .prcm = {
1205 .omap4 = {
1206 .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
1207 .modulemode = MODULEMODE_SWCTRL,
1208 },
1209 },
1210 .slaves = am33xx_mcasp1_slaves,
1211 .slaves_cnt = ARRAY_SIZE(am33xx_mcasp1_slaves),
1212 };
1215 /* 'mmc' class */
1217 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1218 .rev_offs = 0x1fc,
1219 .sysc_offs = 0x10,
1220 .syss_offs = 0x14,
1221 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1222 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1223 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1224 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1225 .sysc_fields = &omap_hwmod_sysc_type1,
1226 };
1228 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1229 .name = "mmc",
1230 .sysc = &am33xx_mmc_sysc,
1231 };
1233 /* mmc0 */
1234 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1235 { .irq = AM33XX_IRQ_MMCHS0 },
1236 { .irq = -1 }
1237 };
1239 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1240 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS0_W, },
1241 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS0_R, },
1242 { .dma_req = -1 }
1243 };
1245 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
1246 {
1247 .pa_start = AM33XX_MMC0_BASE,
1248 .pa_end = AM33XX_MMC0_BASE + SZ_4K - 1,
1249 .flags = ADDR_TYPE_RT
1250 },
1251 { }
1252 };
1254 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc0 = {
1255 .master = &am33xx_l4ls_hwmod,
1256 .slave = &am33xx_mmc0_hwmod,
1257 .clk = "mmc0_ick",
1258 .addr = am33xx_mmc0_addr_space,
1259 .user = OCP_USER_MPU,
1260 };
1262 static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = {
1263 &am33xx_l4ls__mmc0,
1264 };
1266 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1267 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1268 };
1270 static struct omap_hwmod am33xx_mmc0_hwmod = {
1271 .name = "mmc1",
1272 .class = &am33xx_mmc_hwmod_class,
1273 .mpu_irqs = am33xx_mmc0_irqs,
1274 .sdma_reqs = am33xx_mmc0_edma_reqs,
1275 .main_clk = "mmc0_fck",
1276 .clkdm_name = "l4ls_clkdm",
1277 .prcm = {
1278 .omap4 = {
1279 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1280 .modulemode = MODULEMODE_SWCTRL,
1281 },
1282 },
1283 .dev_attr = &am33xx_mmc0_dev_attr,
1284 .slaves = am33xx_mmc0_slaves,
1285 .slaves_cnt = ARRAY_SIZE(am33xx_mmc0_slaves),
1286 };
1288 /* mmc1 */
1289 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1290 { .irq = AM33XX_IRQ_MMCHS1 },
1291 { .irq = -1 }
1292 };
1294 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1295 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS1_W, },
1296 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS1_R, },
1297 { .dma_req = -1 }
1298 };
1300 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
1301 {
1302 .pa_start = AM33XX_MMC1_BASE,
1303 .pa_end = AM33XX_MMC1_BASE + SZ_4K - 1,
1304 .flags = ADDR_TYPE_RT
1305 },
1306 { }
1307 };
1309 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc1 = {
1310 .master = &am33xx_l4ls_hwmod,
1311 .slave = &am33xx_mmc1_hwmod,
1312 .clk = "mmc1_ick",
1313 .addr = am33xx_mmc1_addr_space,
1314 .user = OCP_USER_MPU,
1315 };
1317 static struct omap_hwmod_ocp_if *am33xx_mmc1_slaves[] = {
1318 &am33xx_l4ls__mmc1,
1319 };
1321 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1322 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1323 };
1325 static struct omap_hwmod am33xx_mmc1_hwmod = {
1326 .name = "mmc2",
1327 .class = &am33xx_mmc_hwmod_class,
1328 .mpu_irqs = am33xx_mmc1_irqs,
1329 .sdma_reqs = am33xx_mmc1_edma_reqs,
1330 .main_clk = "mmc1_fck",
1331 .clkdm_name = "l4ls_clkdm",
1332 .prcm = {
1333 .omap4 = {
1334 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1335 .modulemode = MODULEMODE_SWCTRL,
1336 },
1337 },
1338 .dev_attr = &am33xx_mmc1_dev_attr,
1339 .slaves = am33xx_mmc1_slaves,
1340 .slaves_cnt = ARRAY_SIZE(am33xx_mmc1_slaves),
1341 };
1343 /* mmc2 */
1344 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1345 { .irq = AM33XX_IRQ_MMCHS2 },
1346 { .irq = -1 }
1347 };
1349 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1350 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS2_W, },
1351 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS2_R, },
1352 { .dma_req = -1 }
1353 };
1355 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
1356 {
1357 .pa_start = AM33XX_MMC2_BASE,
1358 .pa_end = AM33XX_MMC2_BASE + SZ_64K - 1,
1359 .flags = ADDR_TYPE_RT
1360 },
1361 { }
1362 };
1364 static struct omap_hwmod_ocp_if am33xx_l3_main__mmc2 = {
1365 .master = &am33xx_l3_main_hwmod,
1366 .slave = &am33xx_mmc2_hwmod,
1367 .clk = "mmc2_ick",
1368 .addr = am33xx_mmc2_addr_space,
1369 .user = OCP_USER_MPU,
1370 };
1372 static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = {
1373 &am33xx_l3_main__mmc2,
1374 };
1376 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1377 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1378 };
1379 static struct omap_hwmod am33xx_mmc2_hwmod = {
1380 .name = "mmc3",
1381 .class = &am33xx_mmc_hwmod_class,
1382 .mpu_irqs = am33xx_mmc2_irqs,
1383 .sdma_reqs = am33xx_mmc2_edma_reqs,
1384 .main_clk = "mmc2_fck",
1385 .clkdm_name = "l3s_clkdm",
1386 .prcm = {
1387 .omap4 = {
1388 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1389 .modulemode = MODULEMODE_SWCTRL,
1390 },
1391 },
1392 .dev_attr = &am33xx_mmc2_dev_attr,
1393 .slaves = am33xx_mmc2_slaves,
1394 .slaves_cnt = ARRAY_SIZE(am33xx_mmc2_slaves),
1395 };
1397 /* Master interfaces on the MPU interconnect */
1398 static struct omap_hwmod_ocp_if *am33xx_l3_mpu_masters[] = {
1399 &am33xx_mpu__l3_slow,
1400 };
1402 /* mpu */
1403 static struct omap_hwmod am33xx_mpu_hwmod = {
1404 .name = "mpu",
1405 .class = &mpu_hwmod_class,
1406 .masters = am33xx_l3_mpu_masters,
1407 .masters_cnt = ARRAY_SIZE(am33xx_l3_mpu_masters),
1408 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1409 .main_clk = "mpu_fck",
1410 .clkdm_name = "mpu_clkdm",
1411 .prcm = {
1412 .omap4 = {
1413 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1414 .modulemode = MODULEMODE_SWCTRL,
1415 },
1416 },
1417 };
1419 /* 'ocmcram' class */
1420 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
1421 .name = "ocmcram",
1422 };
1424 /* ocmcram */
1425 static struct omap_hwmod am33xx_ocmcram_hwmod = {
1426 .name = "ocmcram",
1427 .class = &am33xx_ocmcram_hwmod_class,
1428 .main_clk = "ocmcram_fck",
1429 .clkdm_name = "l3_clkdm",
1430 .prcm = {
1431 .omap4 = {
1432 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
1433 .modulemode = MODULEMODE_SWCTRL,
1434 },
1435 },
1436 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1437 };
1439 /* 'ocpwp' class */
1440 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
1441 .name = "ocpwp",
1442 };
1444 /* ocpwp */
1445 static struct omap_hwmod am33xx_ocpwp_hwmod = {
1446 .name = "ocpwp",
1447 .class = &am33xx_ocpwp_hwmod_class,
1448 .main_clk = "ocpwp_fck",
1449 .clkdm_name = "l4ls_clkdm",
1450 .prcm = {
1451 .omap4 = {
1452 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
1453 .modulemode = MODULEMODE_SWCTRL,
1454 },
1455 },
1456 };
1458 /* 'rtc' class */
1459 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1460 .name = "rtc",
1461 };
1463 /* rtc */
1464 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1465 { .irq = AM33XX_IRQ_RTC_TIMER },
1466 { .irq = -1 }
1467 };
1469 static struct omap_hwmod am33xx_rtc_hwmod = {
1470 .name = "rtc",
1471 .class = &am33xx_rtc_hwmod_class,
1472 .mpu_irqs = am33xx_rtc_irqs,
1473 .main_clk = "rtc_fck",
1474 .clkdm_name = "l4_rtc_clkdm",
1475 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1476 .prcm = {
1477 .omap4 = {
1478 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1479 .modulemode = MODULEMODE_SWCTRL,
1480 },
1481 },
1482 };
1484 /* 'sha0' class */
1485 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
1486 .name = "sha0",
1487 };
1489 /* sha0 */
1490 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
1491 { .irq = AM33XX_IRQ_SHAEIP57t0_S },
1492 { .irq = -1 }
1493 };
1495 static struct omap_hwmod am33xx_sha0_hwmod = {
1496 .name = "sha0",
1497 .class = &am33xx_sha0_hwmod_class,
1498 .mpu_irqs = am33xx_sha0_irqs,
1499 .main_clk = "sha0_fck",
1500 .clkdm_name = "l3_clkdm",
1501 .prcm = {
1502 .omap4 = {
1503 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
1504 .modulemode = MODULEMODE_SWCTRL,
1505 },
1506 },
1507 };
1509 /* 'smartreflex' class */
1510 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
1511 .name = "smartreflex",
1512 };
1514 /* smartreflex0 */
1515 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
1516 { .irq = AM33XX_IRQ_SMARTREFLEX0 },
1517 { .irq = -1 }
1518 };
1520 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
1521 .name = "smartreflex0",
1522 .class = &am33xx_smartreflex_hwmod_class,
1523 .mpu_irqs = am33xx_smartreflex0_irqs,
1524 .main_clk = "smartreflex0_fck",
1525 .clkdm_name = "l4_wkup_clkdm",
1526 .prcm = {
1527 .omap4 = {
1528 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
1529 .modulemode = MODULEMODE_SWCTRL,
1530 },
1531 },
1532 };
1534 /* smartreflex1 */
1535 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
1536 { .irq = AM33XX_IRQ_SMARTREFLEX1 },
1537 { .irq = -1 }
1538 };
1540 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
1541 .name = "smartreflex1",
1542 .class = &am33xx_smartreflex_hwmod_class,
1543 .mpu_irqs = am33xx_smartreflex1_irqs,
1544 .main_clk = "smartreflex1_fck",
1545 .clkdm_name = "l4_wkup_clkdm",
1546 .prcm = {
1547 .omap4 = {
1548 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
1549 .modulemode = MODULEMODE_SWCTRL,
1550 },
1551 },
1552 };
1554 /* 'spi' class */
1556 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1557 .rev_offs = 0x0000,
1558 .sysc_offs = 0x0110,
1559 .syss_offs = 0x0114,
1560 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1561 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1562 SYSS_HAS_RESET_STATUS),
1563 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1564 .sysc_fields = &omap_hwmod_sysc_type1,
1565 };
1567 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1568 .name = "mcspi",
1569 .sysc = &am33xx_mcspi_sysc,
1570 .rev = OMAP4_MCSPI_REV,
1571 };
1573 /* spi0 */
1574 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1575 { .irq = AM33XX_IRQ_MCSPIOCP0 },
1576 { .irq = -1 }
1577 };
1579 struct omap_hwmod_dma_info am33xx_mcspi0_sdma_reqs[] = {
1580 { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0R },
1581 { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0W },
1582 { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1R },
1583 { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1W },
1584 { .dma_req = -1 }
1585 };
1587 struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
1588 {
1589 .pa_start = AM33XX_SPI0_BASE,
1590 .pa_end = AM33XX_SPI0_BASE + SZ_1K - 1,
1591 .flags = ADDR_TYPE_RT
1592 },
1593 { }
1594 };
1596 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = {
1597 .master = &am33xx_l4per_hwmod,
1598 .slave = &am33xx_spi0_hwmod,
1599 .clk = "spi0_ick",
1600 .addr = am33xx_mcspi0_addr_space,
1601 .user = OCP_USER_MPU,
1602 };
1604 static struct omap_hwmod_ocp_if *am33xx_mcspi0_slaves[] = {
1605 &am33xx_l4_core__mcspi0,
1606 };
1608 struct omap2_mcspi_dev_attr mcspi_attrib = {
1609 .num_chipselect = 2,
1610 };
1611 static struct omap_hwmod am33xx_spi0_hwmod = {
1612 .name = "spi0",
1613 .class = &am33xx_spi_hwmod_class,
1614 .mpu_irqs = am33xx_spi0_irqs,
1615 .sdma_reqs = am33xx_mcspi0_sdma_reqs,
1616 .main_clk = "spi0_fck",
1617 .clkdm_name = "l4ls_clkdm",
1618 .prcm = {
1619 .omap4 = {
1620 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1621 .modulemode = MODULEMODE_SWCTRL,
1622 },
1623 },
1624 .dev_attr = &mcspi_attrib,
1625 .slaves = am33xx_mcspi0_slaves,
1626 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi0_slaves),
1627 };
1629 /* spi1 */
1630 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1631 { .irq = AM33XX_IRQ_SPI1 },
1632 { .irq = -1 }
1633 };
1635 struct omap_hwmod_dma_info am33xx_mcspi1_sdma_reqs[] = {
1636 { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0R },
1637 { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0W },
1638 { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1R },
1639 { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1W },
1640 { .dma_req = -1 }
1641 };
1643 struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
1644 {
1645 .pa_start = AM33XX_SPI1_BASE,
1646 .pa_end = AM33XX_SPI1_BASE + SZ_1K - 1,
1647 .flags = ADDR_TYPE_RT
1648 },
1649 { }
1650 };
1652 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = {
1653 .master = &am33xx_l4per_hwmod,
1654 .slave = &am33xx_spi1_hwmod,
1655 .clk = "spi1_ick",
1656 .addr = am33xx_mcspi1_addr_space,
1657 .user = OCP_USER_MPU,
1658 };
1660 static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = {
1661 &am33xx_l4_core__mcspi1,
1662 };
1663 static struct omap_hwmod am33xx_spi1_hwmod = {
1664 .name = "spi1",
1665 .class = &am33xx_spi_hwmod_class,
1666 .mpu_irqs = am33xx_spi1_irqs,
1667 .sdma_reqs = am33xx_mcspi1_sdma_reqs,
1668 .main_clk = "spi1_fck",
1669 .clkdm_name = "l4ls_clkdm",
1670 .prcm = {
1671 .omap4 = {
1672 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1673 .modulemode = MODULEMODE_SWCTRL,
1674 },
1675 },
1676 .dev_attr = &mcspi_attrib,
1677 .slaves = am33xx_mcspi1_slaves,
1678 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi1_slaves),
1679 };
1681 /* 'spinlock' class */
1682 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1683 .name = "spinlock",
1684 };
1686 /* spinlock */
1687 static struct omap_hwmod am33xx_spinlock_hwmod = {
1688 .name = "spinlock",
1689 .class = &am33xx_spinlock_hwmod_class,
1690 .main_clk = "spinlock_fck",
1691 .clkdm_name = "l4ls_clkdm",
1692 .prcm = {
1693 .omap4 = {
1694 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1695 .modulemode = MODULEMODE_SWCTRL,
1696 },
1697 },
1698 };
1700 /* 'timer 0 & 2-7' class */
1701 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1702 .rev_offs = 0x0000,
1703 .sysc_offs = 0x0010,
1704 .syss_offs = 0x0014,
1705 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1706 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1707 SIDLE_SMART_WKUP),
1708 .sysc_fields = &omap_hwmod_sysc_type2,
1709 };
1711 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1712 .name = "timer",
1713 .sysc = &am33xx_timer_sysc,
1714 };
1716 /* timer0 */
1717 /* l4 wkup -> timer0 interface */
1718 static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = {
1719 {
1720 .pa_start = AM33XX_TIMER0_BASE,
1721 .pa_end = AM33XX_TIMER0_BASE + SZ_1K - 1,
1722 .flags = ADDR_TYPE_RT
1723 },
1724 { }
1725 };
1727 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = {
1728 .master = &am33xx_l4wkup_hwmod,
1729 .slave = &am33xx_timer0_hwmod,
1730 .clk = "timer0_ick",
1731 .addr = am33xx_timer0_addr_space,
1732 .user = OCP_USER_MPU,
1733 };
1735 static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = {
1736 &am33xx_l4wkup__timer0,
1737 };
1739 static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = {
1740 { .irq = AM33XX_IRQ_DMTIMER0 },
1741 { .irq = -1 }
1742 };
1744 static struct omap_hwmod am33xx_timer0_hwmod = {
1745 .name = "timer0",
1746 .class = &am33xx_timer_hwmod_class,
1747 .mpu_irqs = am33xx_timer0_irqs,
1748 .main_clk = "timer0_fck",
1749 .clkdm_name = "l4_wkup_clkdm",
1750 .prcm = {
1751 .omap4 = {
1752 .clkctrl_offs = AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET,
1753 .modulemode = MODULEMODE_SWCTRL,
1754 },
1755 },
1756 .slaves = am33xx_timer0_slaves,
1757 .slaves_cnt = ARRAY_SIZE(am33xx_timer0_slaves),
1758 };
1760 /* timer1 1ms */
1761 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1762 .rev_offs = 0x0000,
1763 .sysc_offs = 0x0010,
1764 .syss_offs = 0x0014,
1765 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1766 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1767 SYSS_HAS_RESET_STATUS),
1768 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1769 .sysc_fields = &omap_hwmod_sysc_type1,
1770 };
1772 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1773 .name = "timer",
1774 .sysc = &am33xx_timer1ms_sysc,
1775 };
1777 /* l4 wkup -> timer1 interface */
1778 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
1779 {
1780 .pa_start = AM33XX_TIMER1_BASE,
1781 .pa_end = AM33XX_TIMER1_BASE + SZ_1K - 1,
1782 .flags = ADDR_TYPE_RT
1783 },
1784 { }
1785 };
1787 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = {
1788 .master = &am33xx_l4wkup_hwmod,
1789 .slave = &am33xx_timer1_hwmod,
1790 .clk = "timer1_ick",
1791 .addr = am33xx_timer1_addr_space,
1792 .user = OCP_USER_MPU,
1793 };
1795 static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = {
1796 &am33xx_l4wkup__timer1,
1797 };
1799 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
1800 { .irq = AM33XX_IRQ_DMTIMER1 },
1801 { .irq = -1 }
1802 };
1804 static struct omap_hwmod am33xx_timer1_hwmod = {
1805 .name = "timer1",
1806 .class = &am33xx_timer1ms_hwmod_class,
1807 .mpu_irqs = am33xx_timer1_irqs,
1808 .main_clk = "timer1_fck",
1809 .clkdm_name = "l4_wkup_clkdm",
1810 .prcm = {
1811 .omap4 = {
1812 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1813 .modulemode = MODULEMODE_SWCTRL,
1814 },
1815 },
1816 .slaves = am33xx_timer1_slaves,
1817 .slaves_cnt = ARRAY_SIZE(am33xx_timer1_slaves),
1818 };
1820 /* timer2 */
1821 /* l4 per -> timer2 interface */
1822 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
1823 {
1824 .pa_start = AM33XX_TIMER2_BASE,
1825 .pa_end = AM33XX_TIMER2_BASE + SZ_1K - 1,
1826 .flags = ADDR_TYPE_RT
1827 },
1828 { }
1829 };
1831 static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = {
1832 .master = &am33xx_l4per_hwmod,
1833 .slave = &am33xx_timer2_hwmod,
1834 .clk = "timer2_ick",
1835 .addr = am33xx_timer2_addr_space,
1836 .user = OCP_USER_MPU,
1837 };
1839 static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = {
1840 &am33xx_l4per__timer2,
1841 };
1843 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
1844 { .irq = AM33XX_IRQ_DMTIMER2 },
1845 { .irq = -1 }
1846 };
1848 static struct omap_hwmod am33xx_timer2_hwmod = {
1849 .name = "timer2",
1850 .class = &am33xx_timer_hwmod_class,
1851 .mpu_irqs = am33xx_timer2_irqs,
1852 .main_clk = "timer2_fck",
1853 .prcm = {
1854 .omap4 = {
1855 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1856 .modulemode = MODULEMODE_SWCTRL,
1857 },
1858 },
1859 .slaves = am33xx_timer2_slaves,
1860 .slaves_cnt = ARRAY_SIZE(am33xx_timer2_slaves),
1861 .clkdm_name = "l4ls_clkdm",
1862 };
1864 /* timer3 */
1865 /* l4 per -> timer3 interface */
1866 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
1867 {
1868 .pa_start = AM33XX_TIMER3_BASE,
1869 .pa_end = AM33XX_TIMER3_BASE + SZ_1K - 1,
1870 .flags = ADDR_TYPE_RT
1871 },
1872 { }
1873 };
1875 static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = {
1876 .master = &am33xx_l4per_hwmod,
1877 .slave = &am33xx_timer3_hwmod,
1878 .clk = "timer3_ick",
1879 .addr = am33xx_timer3_addr_space,
1880 .user = OCP_USER_MPU,
1881 };
1883 static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = {
1884 &am33xx_l4per__timer3,
1885 };
1887 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
1888 { .irq = AM33XX_IRQ_DMTIMER3 },
1889 { .irq = -1 }
1890 };
1892 static struct omap_hwmod am33xx_timer3_hwmod = {
1893 .name = "timer3",
1894 .class = &am33xx_timer_hwmod_class,
1895 .mpu_irqs = am33xx_timer3_irqs,
1896 .main_clk = "timer3_fck",
1897 .clkdm_name = "l4ls_clkdm",
1898 .prcm = {
1899 .omap4 = {
1900 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1901 .modulemode = MODULEMODE_SWCTRL,
1902 },
1903 },
1904 .slaves = am33xx_timer3_slaves,
1905 .slaves_cnt = ARRAY_SIZE(am33xx_timer3_slaves),
1906 };
1908 /* timer4 */
1909 /* l4 per -> timer4 interface */
1910 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
1911 {
1912 .pa_start = AM33XX_TIMER4_BASE,
1913 .pa_end = AM33XX_TIMER4_BASE + SZ_1K - 1,
1914 .flags = ADDR_TYPE_RT
1915 },
1916 { }
1917 };
1919 static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = {
1920 .master = &am33xx_l4per_hwmod,
1921 .slave = &am33xx_timer4_hwmod,
1922 .clk = "timer4_ick",
1923 .addr = am33xx_timer4_addr_space,
1924 .user = OCP_USER_MPU,
1925 };
1927 static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = {
1928 &am33xx_l4per__timer4,
1929 };
1931 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
1932 { .irq = AM33XX_IRQ_DMTIMER4 },
1933 { .irq = -1 }
1934 };
1936 static struct omap_hwmod am33xx_timer4_hwmod = {
1937 .name = "timer4",
1938 .class = &am33xx_timer_hwmod_class,
1939 .mpu_irqs = am33xx_timer4_irqs,
1940 .main_clk = "timer4_fck",
1941 .prcm = {
1942 .omap4 = {
1943 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1944 .modulemode = MODULEMODE_SWCTRL,
1945 },
1946 },
1947 .slaves = am33xx_timer4_slaves,
1948 .slaves_cnt = ARRAY_SIZE(am33xx_timer4_slaves),
1949 .clkdm_name = "l4ls_clkdm",
1950 };
1953 /* timer5 */
1954 /* l4 per -> timer5 interface */
1955 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
1956 {
1957 .pa_start = AM33XX_TIMER5_BASE,
1958 .pa_end = AM33XX_TIMER5_BASE + SZ_1K - 1,
1959 .flags = ADDR_TYPE_RT
1960 },
1961 { }
1962 };
1964 static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = {
1965 .master = &am33xx_l4per_hwmod,
1966 .slave = &am33xx_timer5_hwmod,
1967 .clk = "timer5_ick",
1968 .addr = am33xx_timer5_addr_space,
1969 .user = OCP_USER_MPU,
1970 };
1972 static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = {
1973 &am33xx_l4per__timer5,
1974 };
1976 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
1977 { .irq = AM33XX_IRQ_DMTIMER5 },
1978 { .irq = -1 }
1979 };
1981 static struct omap_hwmod am33xx_timer5_hwmod = {
1982 .name = "timer5",
1983 .class = &am33xx_timer_hwmod_class,
1984 .mpu_irqs = am33xx_timer5_irqs,
1985 .main_clk = "timer5_fck",
1986 .prcm = {
1987 .omap4 = {
1988 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1989 .modulemode = MODULEMODE_SWCTRL,
1990 },
1991 },
1992 .slaves = am33xx_timer5_slaves,
1993 .slaves_cnt = ARRAY_SIZE(am33xx_timer5_slaves),
1994 .clkdm_name = "l4ls_clkdm",
1995 };
1997 /* timer6 */
1998 /* l4 per -> timer6 interface */
1999 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
2000 {
2001 .pa_start = AM33XX_TIMER6_BASE,
2002 .pa_end = AM33XX_TIMER6_BASE + SZ_1K - 1,
2003 .flags = ADDR_TYPE_RT
2004 },
2005 { }
2006 };
2008 static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = {
2009 .master = &am33xx_l4per_hwmod,
2010 .slave = &am33xx_timer6_hwmod,
2011 .clk = "timer6_ick",
2012 .addr = am33xx_timer6_addr_space,
2013 .user = OCP_USER_MPU,
2014 };
2016 static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = {
2017 &am33xx_l4per__timer6,
2018 };
2020 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
2021 { .irq = AM33XX_IRQ_DMTIMER6 },
2022 { .irq = -1 }
2023 };
2025 static struct omap_hwmod am33xx_timer6_hwmod = {
2026 .name = "timer6",
2027 .class = &am33xx_timer_hwmod_class,
2028 .mpu_irqs = am33xx_timer6_irqs,
2029 .main_clk = "timer6_fck",
2030 .prcm = {
2031 .omap4 = {
2032 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
2033 .modulemode = MODULEMODE_SWCTRL,
2034 },
2035 },
2036 .slaves = am33xx_timer6_slaves,
2037 .slaves_cnt = ARRAY_SIZE(am33xx_timer6_slaves),
2038 .clkdm_name = "l4ls_clkdm",
2039 };
2041 /* timer7 */
2042 /* l4 per -> timer7 interface */
2043 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
2044 {
2045 .pa_start = AM33XX_TIMER7_BASE,
2046 .pa_end = AM33XX_TIMER7_BASE + SZ_1K - 1,
2047 .flags = ADDR_TYPE_RT
2048 },
2049 { }
2050 };
2052 static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = {
2053 .master = &am33xx_l4per_hwmod,
2054 .slave = &am33xx_timer7_hwmod,
2055 .clk = "timer7_ick",
2056 .addr = am33xx_timer7_addr_space,
2057 .user = OCP_USER_MPU,
2058 };
2060 static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = {
2061 &am33xx_l4per__timer7,
2062 };
2064 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
2065 { .irq = AM33XX_IRQ_DMTIMER7 },
2066 { .irq = -1 }
2067 };
2069 static struct omap_hwmod am33xx_timer7_hwmod = {
2070 .name = "timer7",
2071 .class = &am33xx_timer_hwmod_class,
2072 .mpu_irqs = am33xx_timer7_irqs,
2073 .main_clk = "timer7_fck",
2074 .prcm = {
2075 .omap4 = {
2076 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
2077 .modulemode = MODULEMODE_SWCTRL,
2078 },
2079 },
2080 .slaves = am33xx_timer7_slaves,
2081 .slaves_cnt = ARRAY_SIZE(am33xx_timer7_slaves),
2082 .clkdm_name = "l4ls_clkdm",
2083 };
2085 /* 'tpcc' class */
2086 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
2087 .name = "tpcc",
2088 };
2090 /* tpcc */
2091 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
2092 { .name = "edma0", .irq = AM33XX_IRQ_TPCC0_INT_PO0 },
2093 { .name = "edma0_err", .irq = AM33XX_IRQ_TPCC0_ERRINT_PO },
2094 { .irq = -1 },
2095 };
2097 /* TODO move this appropriate header. */
2098 #define AM33XX_TPCC_BASE 0x49000000
2100 static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
2101 {
2102 .pa_start = AM33XX_TPCC_BASE,
2103 .pa_end = AM33XX_TPCC_BASE + SZ_32K - 1,
2104 .flags = ADDR_TYPE_RT
2105 },
2106 { }
2107 };
2109 static struct omap_hwmod_ocp_if am33xx_l3_slow__tpcc = {
2110 .master = &am33xx_l3slow_hwmod,
2111 .slave = &am33xx_tpcc_hwmod,
2112 .addr = am33xx_tpcc_addr_space,
2113 .user = OCP_USER_MPU,
2114 };
2116 static struct omap_hwmod_ocp_if *am33xx_tpcc_slaves[] = {
2117 &am33xx_l3_slow__tpcc,
2118 };
2120 static struct omap_hwmod am33xx_tpcc_hwmod = {
2121 .name = "tpcc",
2122 .class = &am33xx_tpcc_hwmod_class,
2123 .mpu_irqs = am33xx_tpcc_irqs,
2124 .main_clk = "tpcc_ick",
2125 .clkdm_name = "l3_clkdm",
2126 .prcm = {
2127 .omap4 = {
2128 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
2129 .modulemode = MODULEMODE_SWCTRL,
2130 },
2131 },
2132 .slaves = am33xx_tpcc_slaves,
2133 .slaves_cnt = ARRAY_SIZE(am33xx_tpcc_slaves),
2134 };
2136 /* 'tptc' class */
2137 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
2138 .name = "tptc",
2139 };
2141 /* tptc0 */
2142 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
2143 { .irq = AM33XX_IRQ_TPTC0 },
2144 { .irq = -1 }
2145 };
2147 static struct omap_hwmod am33xx_tptc0_hwmod = {
2148 .name = "tptc0",
2149 .class = &am33xx_tptc_hwmod_class,
2150 .mpu_irqs = am33xx_tptc0_irqs,
2151 .main_clk = "tptc0_ick",
2152 .clkdm_name = "l3_clkdm",
2153 .prcm = {
2154 .omap4 = {
2155 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
2156 .modulemode = MODULEMODE_SWCTRL,
2157 },
2158 },
2159 };
2161 /* tptc1 */
2162 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
2163 { .irq = AM33XX_IRQ_TPTC1 },
2164 { .irq = -1 }
2165 };
2167 static struct omap_hwmod am33xx_tptc1_hwmod = {
2168 .name = "tptc1",
2169 .class = &am33xx_tptc_hwmod_class,
2170 .mpu_irqs = am33xx_tptc1_irqs,
2171 .main_clk = "tptc1_ick",
2172 .clkdm_name = "l3_clkdm",
2173 .prcm = {
2174 .omap4 = {
2175 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
2176 .modulemode = MODULEMODE_SWCTRL,
2177 },
2178 },
2179 };
2181 /* tptc2 */
2182 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
2183 { .irq = AM33XX_IRQ_TPTC2 },
2184 { .irq = -1 }
2185 };
2187 static struct omap_hwmod am33xx_tptc2_hwmod = {
2188 .name = "tptc2",
2189 .class = &am33xx_tptc_hwmod_class,
2190 .mpu_irqs = am33xx_tptc2_irqs,
2191 .main_clk = "tptc2_ick",
2192 .clkdm_name = "l3_clkdm",
2193 .prcm = {
2194 .omap4 = {
2195 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
2196 .modulemode = MODULEMODE_SWCTRL,
2197 },
2198 },
2199 };
2201 /* 'uart' class */
2202 static struct omap_hwmod_class_sysconfig uart_sysc = {
2203 .rev_offs = 0x50,
2204 .sysc_offs = 0x54,
2205 .syss_offs = 0x58,
2206 .sysc_flags = (SYSC_HAS_SIDLEMODE |
2207 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2208 SYSC_HAS_AUTOIDLE),
2209 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2210 .sysc_fields = &omap_hwmod_sysc_type1,
2211 };
2213 static struct omap_hwmod_class uart_class = {
2214 .name = "uart",
2215 .sysc = &uart_sysc,
2216 };
2218 /* uart1 */
2219 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
2220 { .name = "tx", .dma_req = 26, },
2221 { .name = "rx", .dma_req = 27, },
2222 { .dma_req = -1 }
2223 };
2225 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
2226 {
2227 .pa_start = AM33XX_UART1_BASE,
2228 .pa_end = AM33XX_UART1_BASE + SZ_8K - 1,
2229 .flags = ADDR_TYPE_RT
2230 },
2231 { }
2232 };
2234 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
2235 .master = &am33xx_l4wkup_hwmod,
2236 .slave = &am33xx_uart1_hwmod,
2237 .clk = "uart1_ick",
2238 .addr = am33xx_uart1_addr_space,
2239 .user = OCP_USER_MPU,
2240 };
2242 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
2243 { .irq = AM33XX_IRQ_UART0 },
2244 { .irq = -1 }
2245 };
2247 static struct omap_hwmod_ocp_if *am33xx_uart1_slaves[] = {
2248 &am33xx_l4_wkup__uart1,
2249 };
2251 static struct omap_hwmod am33xx_uart1_hwmod = {
2252 .name = "uart1",
2253 .class = &uart_class,
2254 .mpu_irqs = am33xx_uart1_irqs,
2255 .sdma_reqs = uart1_edma_reqs,
2256 .main_clk = "uart1_fck",
2257 .clkdm_name = "l4_wkup_clkdm",
2258 .prcm = {
2259 .omap4 = {
2260 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
2261 .modulemode = MODULEMODE_SWCTRL,
2262 },
2263 },
2264 .slaves = am33xx_uart1_slaves,
2265 .slaves_cnt = ARRAY_SIZE(am33xx_uart1_slaves),
2266 };
2268 /* uart2 */
2269 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
2270 {
2271 .pa_start = AM33XX_UART2_BASE,
2272 .pa_end = AM33XX_UART2_BASE + SZ_8K - 1,
2273 .flags = ADDR_TYPE_RT
2274 },
2275 { }
2276 };
2278 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
2279 .slave = &am33xx_uart2_hwmod,
2280 .clk = "uart2_ick",
2281 .addr = am33xx_uart2_addr_space,
2282 .user = OCP_USER_MPU,
2283 };
2285 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
2286 { .irq = AM33XX_IRQ_UART1 },
2287 { .irq = -1 }
2288 };
2290 static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = {
2291 &am33xx_l4_ls__uart2,
2292 };
2294 static struct omap_hwmod am33xx_uart2_hwmod = {
2295 .name = "uart2",
2296 .class = &uart_class,
2297 .mpu_irqs = am33xx_uart2_irqs,
2298 .main_clk = "uart2_fck",
2299 .clkdm_name = "l4ls_clkdm",
2300 .sdma_reqs = uart1_edma_reqs,
2301 .prcm = {
2302 .omap4 = {
2303 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
2304 .modulemode = MODULEMODE_SWCTRL,
2305 },
2306 },
2307 .slaves = am33xx_uart2_slaves,
2308 .slaves_cnt = ARRAY_SIZE(am33xx_uart2_slaves),
2309 };
2311 /* uart3 */
2312 static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
2313 { .name = "tx", .dma_req = 30, },
2314 { .name = "rx", .dma_req = 31, },
2315 { .dma_req = -1 }
2316 };
2318 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
2319 {
2320 .pa_start = AM33XX_UART3_BASE,
2321 .pa_end = AM33XX_UART3_BASE + SZ_8K - 1,
2322 .flags = ADDR_TYPE_RT
2323 },
2324 { }
2325 };
2327 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
2328 .slave = &am33xx_uart3_hwmod,
2329 .clk = "uart3_ick",
2330 .addr = am33xx_uart3_addr_space,
2331 .user = OCP_USER_MPU,
2332 };
2334 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2335 { .irq = AM33XX_IRQ_UART2 },
2336 { .irq = -1 }
2337 };
2339 static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = {
2340 &am33xx_l4_ls__uart3,
2341 };
2343 static struct omap_hwmod am33xx_uart3_hwmod = {
2344 .name = "uart3",
2345 .class = &uart_class,
2346 .mpu_irqs = am33xx_uart3_irqs,
2347 .main_clk = "uart3_fck",
2348 .clkdm_name = "l4ls_clkdm",
2349 .sdma_reqs = uart3_edma_reqs,
2350 .prcm = {
2351 .omap4 = {
2352 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
2353 .modulemode = MODULEMODE_SWCTRL,
2354 },
2355 },
2356 .slaves = am33xx_uart3_slaves,
2357 .slaves_cnt = ARRAY_SIZE(am33xx_uart3_slaves),
2358 };
2360 /* uart4 */
2361 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
2362 {
2363 .pa_start = AM33XX_UART4_BASE,
2364 .pa_end = AM33XX_UART4_BASE + SZ_8K - 1,
2365 .flags = ADDR_TYPE_RT
2366 },
2367 { }
2368 };
2370 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
2371 .slave = &am33xx_uart4_hwmod,
2372 .clk = "uart4_ick",
2373 .addr = am33xx_uart4_addr_space,
2374 .user = OCP_USER_MPU,
2375 };
2377 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2378 { .irq = AM33XX_IRQ_UART3 },
2379 { .irq = -1 }
2380 };
2382 static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = {
2383 &am33xx_l4_ls__uart4,
2384 };
2386 static struct omap_hwmod am33xx_uart4_hwmod = {
2387 .name = "uart4",
2388 .class = &uart_class,
2389 .mpu_irqs = am33xx_uart4_irqs,
2390 .main_clk = "uart4_fck",
2391 .clkdm_name = "l4ls_clkdm",
2392 .sdma_reqs = uart1_edma_reqs,
2393 .prcm = {
2394 .omap4 = {
2395 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
2396 .modulemode = MODULEMODE_SWCTRL,
2397 },
2398 },
2399 .slaves = am33xx_uart4_slaves,
2400 .slaves_cnt = ARRAY_SIZE(am33xx_uart4_slaves),
2401 };
2403 /* uart5 */
2404 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
2405 {
2406 .pa_start = AM33XX_UART5_BASE,
2407 .pa_end = AM33XX_UART5_BASE + SZ_8K - 1,
2408 .flags = ADDR_TYPE_RT
2409 },
2410 { }
2411 };
2413 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
2414 .slave = &am33xx_uart5_hwmod,
2415 .clk = "uart5_ick",
2416 .addr = am33xx_uart5_addr_space,
2417 .user = OCP_USER_MPU,
2418 };
2420 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2421 { .irq = AM33XX_IRQ_UART4 },
2422 { .irq = -1 }
2423 };
2425 static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = {
2426 &am33xx_l4_ls__uart5,
2427 };
2429 static struct omap_hwmod am33xx_uart5_hwmod = {
2430 .name = "uart5",
2431 .class = &uart_class,
2432 .mpu_irqs = am33xx_uart5_irqs,
2433 .main_clk = "uart5_fck",
2434 .clkdm_name = "l4ls_clkdm",
2435 .sdma_reqs = uart1_edma_reqs,
2436 .prcm = {
2437 .omap4 = {
2438 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2439 .modulemode = MODULEMODE_SWCTRL,
2440 },
2441 },
2442 .slaves = am33xx_uart5_slaves,
2443 .slaves_cnt = ARRAY_SIZE(am33xx_uart5_slaves),
2444 };
2446 /* uart6 */
2447 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
2448 {
2449 .pa_start = AM33XX_UART6_BASE,
2450 .pa_end = AM33XX_UART6_BASE + SZ_8K - 1,
2451 .flags = ADDR_TYPE_RT
2452 },
2453 { }
2454 };
2456 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
2457 .slave = &am33xx_uart6_hwmod,
2458 .clk = "uart6_ick",
2459 .addr = am33xx_uart6_addr_space,
2460 .user = OCP_USER_MPU,
2461 };
2463 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2464 { .irq = AM33XX_IRQ_UART5 },
2465 { .irq = -1 }
2466 };
2468 static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = {
2469 &am33xx_l4_ls__uart6,
2470 };
2472 static struct omap_hwmod am33xx_uart6_hwmod = {
2473 .name = "uart6",
2474 .class = &uart_class,
2475 .mpu_irqs = am33xx_uart6_irqs,
2476 .main_clk = "uart6_fck",
2477 .clkdm_name = "l4ls_clkdm",
2478 .sdma_reqs = uart1_edma_reqs,
2479 .prcm = {
2480 .omap4 = {
2481 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2482 .modulemode = MODULEMODE_SWCTRL,
2483 },
2484 },
2485 .slaves = am33xx_uart6_slaves,
2486 .slaves_cnt = ARRAY_SIZE(am33xx_uart6_slaves),
2487 };
2489 /* 'wd_timer' class */
2490 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2491 .name = "wd_timer",
2492 };
2494 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
2495 {
2496 .pa_start = AM33XX_WDT1_BASE,
2497 .pa_end = AM33XX_WDT1_BASE + SZ_4K - 1,
2498 .flags = ADDR_TYPE_RT
2499 },
2500 { }
2501 };
2503 /* l4_wkup -> wd_timer1 */
2504 static struct omap_hwmod_ocp_if am33xx_l4wkup__wd_timer1 = {
2505 .master = &am33xx_l4wkup_hwmod,
2506 .slave = &am33xx_wd_timer1_hwmod,
2507 .addr = am33xx_wd_timer1_addrs,
2508 .user = OCP_USER_MPU,
2509 };
2511 /* wd_timer1 slave ports */
2512 static struct omap_hwmod_ocp_if *am33xx_wd_timer1_slaves[] = {
2513 &am33xx_l4wkup__wd_timer1,
2514 };
2516 /* wd_timer1 */
2517 /*
2518 * TODO: device.c file uses hardcoded name for watchdog
2519 timer driver "wd_timer2, so we are also using
2520 same name as of now...
2521 */
2522 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2523 .name = "wd_timer2",
2524 .class = &am33xx_wd_timer_hwmod_class,
2525 .main_clk = "wd_timer1_fck",
2526 .clkdm_name = "l4_wkup_clkdm",
2527 .prcm = {
2528 .omap4 = {
2529 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2530 .modulemode = MODULEMODE_SWCTRL,
2531 },
2532 },
2533 .slaves = am33xx_wd_timer1_slaves,
2534 .slaves_cnt = ARRAY_SIZE(am33xx_wd_timer1_slaves),
2535 };
2537 /* wdt0 */
2538 static struct omap_hwmod_irq_info am33xx_wdt0_irqs[] = {
2539 { .irq = AM33XX_IRQ_WDT0 },
2540 { .irq = -1 },
2541 };
2543 static struct omap_hwmod am33xx_wdt0_hwmod = {
2544 .name = "wdt0",
2545 .class = &am33xx_wd_timer_hwmod_class,
2546 .mpu_irqs = am33xx_wdt0_irqs,
2547 .main_clk = "wdt0_fck",
2548 .clkdm_name = "l4_wkup_clkdm",
2549 .prcm = {
2550 .omap4 = {
2551 .clkctrl_offs = AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET,
2552 .modulemode = MODULEMODE_SWCTRL,
2553 },
2554 },
2555 };
2557 /* 'wkup_m3' class */
2558 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
2559 .name = "wkup_m3",
2560 };
2562 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
2563 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
2564 };
2566 /* wkup_m3 */
2567 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
2568 .name = "wkup_m3",
2569 .class = &am33xx_wkup_m3_hwmod_class,
2570 .clkdm_name = "l4_wkup_aon_clkdm",
2571 .main_clk = "wkup_m3_fck",
2572 .rst_lines = am33xx_wkup_m3_resets,
2573 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
2574 .prcm = {
2575 .omap4 = {
2576 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
2577 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
2578 .modulemode = MODULEMODE_SWCTRL,
2579 },
2580 },
2581 .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */
2582 };
2584 /* L3 SLOW -> USBSS interface */
2585 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
2586 {
2587 .name = "usbss",
2588 .pa_start = AM33XX_USBSS_BASE,
2589 .pa_end = AM33XX_USBSS_BASE + SZ_4K - 1,
2590 .flags = ADDR_TYPE_RT
2591 },
2592 {
2593 .name = "musb0",
2594 .pa_start = AM33XX_USB0_BASE,
2595 .pa_end = AM33XX_USB0_BASE + SZ_2K - 1,
2596 .flags = ADDR_TYPE_RT
2597 },
2598 {
2599 .name = "musb1",
2600 .pa_start = AM33XX_USB1_BASE,
2601 .pa_end = AM33XX_USB1_BASE + SZ_2K - 1,
2602 .flags = ADDR_TYPE_RT
2603 },
2604 { }
2605 };
2607 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2608 .rev_offs = 0x0,
2609 .sysc_offs = 0x10,
2610 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2611 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2612 .sysc_fields = &omap_hwmod_sysc_type1,
2613 };
2615 static struct omap_hwmod_class am33xx_usbotg_class = {
2616 .name = "usbotg",
2617 .sysc = &am33xx_usbhsotg_sysc,
2618 };
2620 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2621 { .name = "usbss-irq", .irq = AM33XX_IRQ_USBSS, },
2622 { .name = "musb0-irq", .irq = AM33XX_IRQ_USB0, },
2623 { .name = "musb1-irq", .irq = AM33XX_IRQ_USB1, },
2624 { .irq = -1, },
2625 };
2627 static struct omap_hwmod_ocp_if am33xx_l3_slow__usbss = {
2628 .master = &am33xx_l3slow_hwmod,
2629 .slave = &am33xx_usbss_hwmod,
2630 .addr = am33xx_usbss_addr_space,
2631 .user = OCP_USER_MPU,
2632 .flags = OCPIF_SWSUP_IDLE,
2633 };
2635 static struct omap_hwmod_ocp_if *am33xx_usbss_slaves[] = {
2636 &am33xx_l3_slow__usbss,
2637 };
2639 static struct omap_hwmod_opt_clk usbss_opt_clks[] = {
2640 { .role = "clkdcoldo", .clk = "usbotg_fck" },
2641 };
2643 static struct omap_hwmod am33xx_usbss_hwmod = {
2644 .name = "usb_otg_hs",
2645 .mpu_irqs = am33xx_usbss_mpu_irqs,
2646 .main_clk = "usbotg_ick",
2647 .clkdm_name = "l4ls_clkdm",
2648 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2649 .prcm = {
2650 .omap4 = {
2651 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2652 .modulemode = MODULEMODE_SWCTRL,
2653 },
2654 },
2655 .opt_clks = usbss_opt_clks,
2656 .opt_clks_cnt = ARRAY_SIZE(usbss_opt_clks),
2657 .slaves = am33xx_usbss_slaves,
2658 .slaves_cnt = ARRAY_SIZE(am33xx_usbss_slaves),
2659 .class = &am33xx_usbotg_class,
2660 };
2662 static __initdata struct omap_hwmod *am33xx_hwmods[] = {
2663 /* l3 class */
2664 &am33xx_l3_instr_hwmod,
2665 &am33xx_l3_main_hwmod,
2666 /* l3s class */
2667 &am33xx_l3slow_hwmod,
2668 /* l4hs class */
2669 &am33xx_l4_hs_hwmod,
2670 /* l4fw class */
2671 &am33xx_l4fw_hwmod,
2672 /* l4ls class */
2673 &am33xx_l4ls_hwmod,
2674 /* l4per class */
2675 &am33xx_l4per_hwmod,
2676 /* l4wkup class */
2677 &am33xx_l4wkup_hwmod,
2679 /* clkdiv32k class */
2680 &am33xx_clkdiv32k_hwmod,
2681 /* mpu class */
2682 &am33xx_mpu_hwmod,
2683 /* adc_tsc class */
2684 &am33xx_adc_tsc_hwmod,
2685 /* aes class */
2686 &am33xx_aes0_hwmod,
2687 /* cefuse class */
2688 &am33xx_cefuse_hwmod,
2689 /* control class */
2690 &am33xx_control_hwmod,
2691 /* dcan class */
2692 &am33xx_dcan0_hwmod,
2693 &am33xx_dcan1_hwmod,
2694 /* debugss class */
2695 &am33xx_debugss_hwmod,
2696 /* elm class */
2697 &am33xx_elm_hwmod,
2698 /* emif_fw class */
2699 &am33xx_emif_fw_hwmod,
2700 /* epwmss class */
2701 &am33xx_epwmss0_hwmod,
2702 &am33xx_epwmss1_hwmod,
2703 &am33xx_epwmss2_hwmod,
2704 /* gpio class */
2705 &am33xx_gpio0_hwmod,
2706 &am33xx_gpio1_hwmod,
2707 &am33xx_gpio2_hwmod,
2708 &am33xx_gpio3_hwmod,
2709 /* gpmc class */
2710 &am33xx_gpmc_hwmod,
2711 /* i2c class */
2712 &am33xx_i2c1_hwmod,
2713 &am33xx_i2c2_hwmod,
2714 /* icss class */
2715 &am33xx_icss_hwmod,
2716 /* ieee5000 class */
2717 &am33xx_ieee5000_hwmod,
2718 /* mailbox class */
2719 &am33xx_mailbox_hwmod,
2720 /* mcasp class */
2721 &am33xx_mcasp0_hwmod,
2722 &am33xx_mcasp1_hwmod,
2723 /* mmc class */
2724 &am33xx_mmc0_hwmod,
2725 &am33xx_mmc1_hwmod,
2726 &am33xx_mmc2_hwmod,
2727 /* ocmcram class */
2728 &am33xx_ocmcram_hwmod,
2729 /* ocpwp class */
2730 &am33xx_ocpwp_hwmod,
2731 /* sha0 class */
2732 &am33xx_sha0_hwmod,
2733 /* smartreflex class */
2734 &am33xx_smartreflex0_hwmod,
2735 &am33xx_smartreflex1_hwmod,
2736 /* spi class */
2737 &am33xx_spi0_hwmod,
2738 &am33xx_spi1_hwmod,
2739 /* spinlock class */
2740 &am33xx_spinlock_hwmod,
2741 /* uart class */
2742 &am33xx_uart1_hwmod,
2743 &am33xx_uart2_hwmod,
2744 &am33xx_uart3_hwmod,
2745 &am33xx_uart4_hwmod,
2746 &am33xx_uart5_hwmod,
2747 &am33xx_uart6_hwmod,
2748 /* timer class */
2749 &am33xx_timer0_hwmod,
2750 &am33xx_timer1_hwmod,
2751 &am33xx_timer2_hwmod,
2752 &am33xx_timer3_hwmod,
2753 &am33xx_timer4_hwmod,
2754 &am33xx_timer5_hwmod,
2755 &am33xx_timer6_hwmod,
2756 &am33xx_timer7_hwmod,
2757 /* wkup_m3 class */
2758 &am33xx_wkup_m3_hwmod,
2759 /* wd_timer class */
2760 &am33xx_wd_timer1_hwmod,
2761 /* usbss hwmod */
2762 &am33xx_usbss_hwmod,
2763 /* cpgmac0 class */
2764 &am33xx_cpgmac0_hwmod,
2765 &am33xx_wdt0_hwmod, /* Secure WDT */
2766 /* tptc class */
2767 &am33xx_tptc0_hwmod,
2768 &am33xx_tptc1_hwmod,
2769 &am33xx_tptc2_hwmod,
2770 /* tpcc class */
2771 &am33xx_tpcc_hwmod,
2772 /* LCDC class */
2773 &am33xx_lcdc_hwmod,
2774 /* rtc */
2775 &am33xx_rtc_hwmod,
2776 NULL,
2777 };
2779 int __init am33xx_hwmod_init(void)
2780 {
2781 return omap_hwmod_register(am33xx_hwmods);
2782 }