1 /*
2 * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
3 *
4 * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
17 #include <plat/omap_hwmod.h>
18 #include <plat/cpu.h>
19 #include <plat/gpio.h>
20 #include <plat/dma.h>
21 #include <plat/mmc.h>
22 #include <plat/mcspi.h>
23 #include <plat/i2c.h>
25 #include "omap_hwmod_common_data.h"
26 #include "control.h"
27 #include "cm33xx.h"
28 #include "prm33xx.h"
30 /* Backward references (IPs with Bus Master capability) */
31 static struct omap_hwmod am33xx_mpu_hwmod;
32 static struct omap_hwmod am33xx_l3_main_hwmod;
33 static struct omap_hwmod am33xx_l3slow_hwmod;
34 static struct omap_hwmod am33xx_l4wkup_hwmod;
35 static struct omap_hwmod am33xx_l4per_hwmod;
36 static struct omap_hwmod am33xx_uart1_hwmod;
37 static struct omap_hwmod am33xx_uart2_hwmod;
38 static struct omap_hwmod am33xx_uart3_hwmod;
39 static struct omap_hwmod am33xx_uart4_hwmod;
40 static struct omap_hwmod am33xx_uart5_hwmod;
41 static struct omap_hwmod am33xx_uart6_hwmod;
42 static struct omap_hwmod am33xx_timer0_hwmod;
43 static struct omap_hwmod am33xx_timer1_hwmod;
44 static struct omap_hwmod am33xx_timer2_hwmod;
45 static struct omap_hwmod am33xx_timer3_hwmod;
46 static struct omap_hwmod am33xx_timer4_hwmod;
47 static struct omap_hwmod am33xx_timer5_hwmod;
48 static struct omap_hwmod am33xx_timer6_hwmod;
49 static struct omap_hwmod am33xx_timer7_hwmod;
50 static struct omap_hwmod am33xx_wd_timer1_hwmod;
51 static struct omap_hwmod am33xx_tpcc_hwmod;
52 static struct omap_hwmod am33xx_tptc0_hwmod;
53 static struct omap_hwmod am33xx_tptc1_hwmod;
54 static struct omap_hwmod am33xx_tptc2_hwmod;
55 static struct omap_hwmod am33xx_dcan0_hwmod;
56 static struct omap_hwmod am33xx_dcan1_hwmod;
57 static struct omap_hwmod am33xx_gpio0_hwmod;
58 static struct omap_hwmod am33xx_gpio1_hwmod;
59 static struct omap_hwmod am33xx_gpio2_hwmod;
60 static struct omap_hwmod am33xx_gpio3_hwmod;
61 static struct omap_hwmod am33xx_i2c1_hwmod;
62 static struct omap_hwmod am33xx_i2c2_hwmod;
63 static struct omap_hwmod am33xx_i2c3_hwmod;
64 static struct omap_hwmod am33xx_usbss_hwmod;
65 static struct omap_hwmod am33xx_mmc0_hwmod;
66 static struct omap_hwmod am33xx_mmc1_hwmod;
67 static struct omap_hwmod am33xx_mmc2_hwmod;
68 static struct omap_hwmod am33xx_spi0_hwmod;
69 static struct omap_hwmod am33xx_spi1_hwmod;
70 static struct omap_hwmod am33xx_elm_hwmod;
71 static struct omap_hwmod am33xx_adc_tsc_hwmod;
72 static struct omap_hwmod am33xx_mcasp0_hwmod;
73 static struct omap_hwmod am33xx_mcasp1_hwmod;
74 static struct omap_hwmod am33xx_epwmss0_hwmod;
75 static struct omap_hwmod am33xx_epwmss1_hwmod;
76 static struct omap_hwmod am33xx_epwmss2_hwmod;
77 static struct omap_hwmod am33xx_gpmc_hwmod;
78 static struct omap_hwmod am33xx_lcdc_hwmod;
79 static struct omap_hwmod am33xx_mailbox_hwmod;
80 static struct omap_hwmod am33xx_cpgmac0_hwmod;
82 /*
83 * Interconnects hwmod structures
84 * hwmods that compose the global AM33XX OCP interconnect
85 */
87 /* MPU -> L3_SLOW Peripheral interface */
88 static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = {
89 .master = &am33xx_mpu_hwmod,
90 .slave = &am33xx_l3slow_hwmod,
91 .user = OCP_USER_MPU,
92 };
94 /* L3 SLOW -> L4_PER Peripheral interface */
95 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = {
96 .master = &am33xx_l3slow_hwmod,
97 .slave = &am33xx_l4per_hwmod,
98 .user = OCP_USER_MPU,
99 };
101 /* L3 SLOW -> L4_WKUP Peripheral interface */
102 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = {
103 .master = &am33xx_l3slow_hwmod,
104 .slave = &am33xx_l4wkup_hwmod,
105 .user = OCP_USER_MPU,
106 };
108 /* Master interfaces on the L4_WKUP interconnect */
109 static struct omap_hwmod_ocp_if *am33xx_l3_slow_masters[] = {
110 &am33xx_l3_slow__l4_per,
111 &am33xx_l3_slow__l4_wkup,
112 };
114 /* Slave interfaces on the L3_SLOW interconnect */
115 static struct omap_hwmod_ocp_if *am33xx_l3_slow_slaves[] = {
116 &am33xx_mpu__l3_slow,
117 };
119 static struct omap_hwmod am33xx_l3slow_hwmod = {
120 .name = "l3_slow",
121 .class = &l3_hwmod_class,
122 .clkdm_name = "l3s_clkdm",
123 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
124 .masters = am33xx_l3_slow_masters,
125 .masters_cnt = ARRAY_SIZE(am33xx_l3_slow_masters),
126 .slaves = am33xx_l3_slow_slaves,
127 .slaves_cnt = ARRAY_SIZE(am33xx_l3_slow_slaves),
128 };
130 /* L4 PER -> DCAN0 */
131 static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
132 {
133 .pa_start = 0x481CC000,
134 .pa_end = 0x481CC000 + SZ_4K - 1,
135 .flags = ADDR_TYPE_RT
136 },
137 { }
138 };
140 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
141 .master = &am33xx_l4per_hwmod,
142 .slave = &am33xx_dcan0_hwmod,
143 .clk = "dcan0_ick",
144 .addr = am33xx_dcan0_addrs,
145 .user = OCP_USER_MPU | OCP_USER_SDMA,
146 };
148 /* L4 PER -> DCAN1 */
149 static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
150 {
151 .pa_start = 0x481D0000,
152 .pa_end = 0x481D0000 + SZ_4K - 1,
153 .flags = ADDR_TYPE_RT
154 },
155 { }
156 };
158 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
159 .master = &am33xx_l4per_hwmod,
160 .slave = &am33xx_dcan1_hwmod,
161 .clk = "dcan1_ick",
162 .addr = am33xx_dcan1_addrs,
163 .user = OCP_USER_MPU | OCP_USER_SDMA,
164 };
166 /* L4 PER -> GPIO2 */
167 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
168 {
169 .pa_start = 0x4804C000,
170 .pa_end = 0x4804C000 + SZ_4K - 1,
171 .flags = ADDR_TYPE_RT,
172 },
173 { }
174 };
176 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
177 .master = &am33xx_l4per_hwmod,
178 .slave = &am33xx_gpio1_hwmod,
179 .clk = "l4ls_gclk",
180 .addr = am33xx_gpio1_addrs,
181 .user = OCP_USER_MPU | OCP_USER_SDMA,
182 };
184 /* L4 PER -> GPIO3 */
185 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
186 {
187 .pa_start = 0x481AC000,
188 .pa_end = 0x481AC000 + SZ_4K - 1,
189 .flags = ADDR_TYPE_RT,
190 },
191 { }
192 };
194 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
195 .master = &am33xx_l4per_hwmod,
196 .slave = &am33xx_gpio2_hwmod,
197 .clk = "l4ls_gclk",
198 .addr = am33xx_gpio2_addrs,
199 .user = OCP_USER_MPU | OCP_USER_SDMA,
200 };
202 /* L4 PER -> GPIO4 */
203 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
204 {
205 .pa_start = 0x481AE000,
206 .pa_end = 0x481AE000 + SZ_4K - 1,
207 .flags = ADDR_TYPE_RT,
208 },
209 { }
210 };
212 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
213 .master = &am33xx_l4per_hwmod,
214 .slave = &am33xx_gpio3_hwmod,
215 .clk = "l4ls_gclk",
216 .addr = am33xx_gpio3_addrs,
217 .user = OCP_USER_MPU | OCP_USER_SDMA,
218 };
220 /* Master interfaces on the L4_PER interconnect */
221 static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = {
222 &am33xx_l4_per__dcan0,
223 &am33xx_l4_per__dcan1,
224 &am33xx_l4_per__gpio1,
225 &am33xx_l4_per__gpio2,
226 &am33xx_l4_per__gpio3,
227 };
229 /* Slave interfaces on the L4_PER interconnect */
230 static struct omap_hwmod_ocp_if *am33xx_l4_per_slaves[] = {
231 &am33xx_l3_slow__l4_per,
232 };
234 static struct omap_hwmod am33xx_l4per_hwmod = {
235 .name = "l4_per",
236 .class = &l4_hwmod_class,
237 .clkdm_name = "l4ls_clkdm",
238 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
239 .masters = am33xx_l4_per_masters,
240 .masters_cnt = ARRAY_SIZE(am33xx_l4_per_masters),
241 .slaves = am33xx_l4_per_slaves,
242 .slaves_cnt = ARRAY_SIZE(am33xx_l4_per_slaves),
243 };
245 /* L4 WKUP -> I2C1 */
246 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
247 {
248 .pa_start = 0x44E0B000,
249 .pa_end = 0x44E0B000 + SZ_4K - 1,
250 .flags = ADDR_TYPE_RT,
251 },
252 { }
253 };
255 static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = {
256 .master = &am33xx_l4wkup_hwmod,
257 .slave = &am33xx_i2c1_hwmod,
258 .addr = am33xx_i2c1_addr_space,
259 .user = OCP_USER_MPU,
260 };
262 /* L4 WKUP -> GPIO1 */
263 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
264 {
265 .pa_start = 0x44E07000,
266 .pa_end = 0x44E07000 + SZ_4K - 1,
267 .flags = ADDR_TYPE_RT,
268 },
269 { }
270 };
272 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
273 .master = &am33xx_l4wkup_hwmod,
274 .slave = &am33xx_gpio0_hwmod,
275 .clk = "l4ls_gclk",
276 .addr = am33xx_gpio0_addrs,
277 .user = OCP_USER_MPU | OCP_USER_SDMA,
278 };
280 /* Master interfaces on the L4_WKUP interconnect */
281 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = {
282 &am33xx_l4_wkup__gpio0,
283 };
284 /* Slave interfaces on the L4_WKUP interconnect */
285 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_slaves[] = {
286 &am33xx_l3_slow__l4_wkup,
287 };
289 static struct omap_hwmod am33xx_l4wkup_hwmod = {
290 .name = "l4_wkup",
291 .class = &l4_hwmod_class,
292 .clkdm_name = "l4_wkup_clkdm",
293 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
294 .masters = am33xx_l4_wkup_masters,
295 .masters_cnt = ARRAY_SIZE(am33xx_l4_wkup_masters),
296 .slaves = am33xx_l4_wkup_slaves,
297 .slaves_cnt = ARRAY_SIZE(am33xx_l4_wkup_slaves),
298 };
300 /* adc_tsc */
301 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
302 .rev_offs = 0x00,
303 .sysc_offs = 0x10,
304 .sysc_flags = SYSC_HAS_SIDLEMODE,
305 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
306 SIDLE_SMART_WKUP),
307 .sysc_fields = &omap_hwmod_sysc_type2,
308 };
310 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
311 .name = "adc_tsc",
312 .sysc = &am33xx_adc_tsc_sysc,
313 };
315 /* L4 WKUP -> ADC_TSC */
316 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
317 {
318 .pa_start = 0x44E0D000,
319 .pa_end = 0x44E0D000 + SZ_8K - 1,
320 .flags = ADDR_TYPE_RT
321 },
322 { }
323 };
325 static struct omap_hwmod_ocp_if am33xx_l4_wkup_adc_tsc = {
326 .master = &am33xx_l4wkup_hwmod,
327 .slave = &am33xx_adc_tsc_hwmod,
328 .clk = "adc_tsc_ick",
329 .addr = am33xx_adc_tsc_addrs,
330 .user = OCP_USER_MPU,
331 };
333 static struct omap_hwmod_ocp_if *am33xx_adc_tsc_slaves[] = {
334 &am33xx_l4_wkup_adc_tsc,
335 };
337 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
338 { .irq = 16 },
339 { .irq = -1 }
340 };
342 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
343 .name = "adc_tsc",
344 .class = &am33xx_adc_tsc_hwmod_class,
345 .clkdm_name = "l4_wkup_clkdm",
346 .mpu_irqs = am33xx_adc_tsc_irqs,
347 .main_clk = "adc_tsc_fck",
348 .prcm = {
349 .omap4 = {
350 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
351 .modulemode = MODULEMODE_SWCTRL,
352 },
353 },
354 .slaves = am33xx_adc_tsc_slaves,
355 .slaves_cnt = ARRAY_SIZE(am33xx_adc_tsc_slaves),
356 };
358 /* 'aes' class */
359 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
360 .name = "aes",
361 };
363 /* aes0 */
364 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
365 { .irq = 102 },
366 { .irq = -1 }
367 };
369 static struct omap_hwmod am33xx_aes0_hwmod = {
370 .name = "aes0",
371 .class = &am33xx_aes_hwmod_class,
372 .clkdm_name = "l3_clkdm",
373 .mpu_irqs = am33xx_aes0_irqs,
374 .main_clk = "aes0_fck",
375 .prcm = {
376 .omap4 = {
377 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
378 .modulemode = MODULEMODE_SWCTRL,
379 },
380 },
381 };
383 /* cefuse */
384 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
385 .name = "cefuse",
386 };
388 static struct omap_hwmod am33xx_cefuse_hwmod = {
389 .name = "cefuse",
390 .class = &am33xx_cefuse_hwmod_class,
391 .clkdm_name = "l4_cefuse_clkdm",
392 .main_clk = "cefuse_fck",
393 .prcm = {
394 .omap4 = {
395 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
396 .modulemode = MODULEMODE_SWCTRL,
397 },
398 },
399 };
401 /* clkdiv32k */
402 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
403 .name = "clkdiv32k",
404 };
406 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
407 .name = "clkdiv32k",
408 .class = &am33xx_clkdiv32k_hwmod_class,
409 .clkdm_name = "clk_24mhz_clkdm",
410 .main_clk = "clkdiv32k_ick",
411 .prcm = {
412 .omap4 = {
413 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
414 .modulemode = MODULEMODE_SWCTRL,
415 },
416 },
417 };
419 /* control */
420 static struct omap_hwmod_class am33xx_control_hwmod_class = {
421 .name = "control",
422 };
424 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
425 { .irq = 8 },
426 { .irq = -1 }
427 };
429 static struct omap_hwmod am33xx_control_hwmod = {
430 .name = "control",
431 .class = &am33xx_control_hwmod_class,
432 .clkdm_name = "l4_wkup_clkdm",
433 .mpu_irqs = am33xx_control_irqs,
434 .main_clk = "control_fck",
435 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
436 .prcm = {
437 .omap4 = {
438 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
439 .modulemode = MODULEMODE_SWCTRL,
440 },
441 },
442 };
444 /* cpgmac0 */
445 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
446 .rev_offs = 0x0,
447 .sysc_offs = 0x8,
448 .syss_offs = 0x4,
449 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
450 SYSS_HAS_RESET_STATUS),
451 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
452 MSTANDBY_NO),
453 .sysc_fields = &omap_hwmod_sysc_type3,
454 };
456 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
457 .name = "cpgmac0",
458 .sysc = &am33xx_cpgmac_sysc,
459 };
461 struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
462 {
463 .pa_start = 0x4A101200,
464 .pa_end = 0x4A101200 + SZ_8K - 1,
465 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
466 },
467 { }
468 };
470 struct omap_hwmod_ocp_if am33xx_l3_main__cpgmac0 = {
471 .master = &am33xx_l3_main_hwmod,
472 .slave = &am33xx_cpgmac0_hwmod,
473 .addr = am33xx_cpgmac0_addr_space,
474 .user = OCP_USER_MPU,
475 };
477 static struct omap_hwmod_ocp_if *am33xx_cpgmac0_slaves[] = {
478 &am33xx_l3_main__cpgmac0,
479 };
481 static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
482 { .name = "c0_rx_thresh_pend", .irq = 40 },
483 { .name = "c0_rx_pend", .irq = 41 },
484 { .name = "c0_tx_pend", .irq = 42 },
485 { .name = "c0_misc_pend", .irq = 43 },
486 { .irq = -1 }
487 };
489 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
490 .name = "cpgmac0",
491 .class = &am33xx_cpgmac0_hwmod_class,
492 .clkdm_name = "cpsw_125mhz_clkdm",
493 .mpu_irqs = am33xx_cpgmac0_irqs,
494 .main_clk = "cpgmac0_ick",
495 .prcm = {
496 .omap4 = {
497 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
498 .modulemode = MODULEMODE_SWCTRL,
499 },
500 },
501 .slaves = am33xx_cpgmac0_slaves,
502 .slaves_cnt = ARRAY_SIZE(am33xx_cpgmac0_slaves),
503 };
505 /* 'dcan' class */
506 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
507 .name = "d_can",
508 };
510 /* dcan0 slave ports */
511 static struct omap_hwmod_ocp_if *am33xx_dcan0_slaves[] = {
512 &am33xx_l4_per__dcan0,
513 };
515 /* dcan0 */
516 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
517 { .name = "d_can_ms", .irq = 52 },
518 { .name = "d_can_mo", .irq = 53 },
519 { .irq = -1 }
520 };
522 static struct omap_hwmod am33xx_dcan0_hwmod = {
523 .name = "d_can0",
524 .class = &am33xx_dcan_hwmod_class,
525 .clkdm_name = "l4ls_clkdm",
526 .mpu_irqs = am33xx_dcan0_irqs,
527 .main_clk = "dcan0_fck",
528 .prcm = {
529 .omap4 = {
530 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
531 .modulemode = MODULEMODE_SWCTRL,
532 },
533 },
534 .slaves = am33xx_dcan0_slaves,
535 .slaves_cnt = ARRAY_SIZE(am33xx_dcan0_slaves),
536 };
538 /* dcan1 slave ports */
539 static struct omap_hwmod_ocp_if *am33xx_dcan1_slaves[] = {
540 &am33xx_l4_per__dcan1,
541 };
543 /* dcan1 */
544 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
545 { .name = "d_can_ms", .irq = 55 },
546 { .name = "d_can_mo", .irq = 56 },
547 { .irq = -1 }
548 };
550 static struct omap_hwmod am33xx_dcan1_hwmod = {
551 .name = "d_can1",
552 .class = &am33xx_dcan_hwmod_class,
553 .clkdm_name = "l4ls_clkdm",
554 .mpu_irqs = am33xx_dcan1_irqs,
555 .main_clk = "dcan1_fck",
556 .prcm = {
557 .omap4 = {
558 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
559 .modulemode = MODULEMODE_SWCTRL,
560 },
561 },
562 .slaves = am33xx_dcan1_slaves,
563 .slaves_cnt = ARRAY_SIZE(am33xx_dcan1_slaves),
564 };
566 /* debugss */
567 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
568 .name = "debugss",
569 };
571 static struct omap_hwmod am33xx_debugss_hwmod = {
572 .name = "debugss",
573 .class = &am33xx_debugss_hwmod_class,
574 .clkdm_name = "l3_aon_clkdm",
575 .main_clk = "debugss_ick",
576 #ifdef CONFIG_DEBUG_JTAG_ENABLE
577 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
578 #endif
579 .prcm = {
580 .omap4 = {
581 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
582 .modulemode = MODULEMODE_SWCTRL,
583 },
584 },
585 };
587 /* elm */
588 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
589 .rev_offs = 0x0000,
590 .sysc_offs = 0x0010,
591 .syss_offs = 0x0014,
592 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
593 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
594 SYSS_HAS_RESET_STATUS),
595 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
596 .sysc_fields = &omap_hwmod_sysc_type1,
597 };
599 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
600 .name = "elm",
601 .sysc = &am33xx_elm_sysc,
602 };
604 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
605 { .irq = 4 },
606 { .irq = -1 }
607 };
609 struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
610 {
611 .pa_start = 0x48080000,
612 .pa_end = 0x48080000 + SZ_8K - 1,
613 .flags = ADDR_TYPE_RT
614 },
615 { }
616 };
618 struct omap_hwmod_ocp_if am33xx_l4_core__elm = {
619 .master = &am33xx_l4per_hwmod,
620 .slave = &am33xx_elm_hwmod,
621 .addr = am33xx_elm_addr_space,
622 .user = OCP_USER_MPU,
623 };
625 static struct omap_hwmod_ocp_if *am33xx_elm_slaves[] = {
626 &am33xx_l4_core__elm,
627 };
629 static struct omap_hwmod am33xx_elm_hwmod = {
630 .name = "elm",
631 .class = &am33xx_elm_hwmod_class,
632 .clkdm_name = "l4ls_clkdm",
633 .mpu_irqs = am33xx_elm_irqs,
634 .main_clk = "elm_fck",
635 .prcm = {
636 .omap4 = {
637 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
638 .modulemode = MODULEMODE_SWCTRL,
639 },
640 },
641 .slaves = am33xx_elm_slaves,
642 .slaves_cnt = ARRAY_SIZE(am33xx_elm_slaves),
643 };
645 /* emif_fw */
646 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
647 .name = "emif_fw",
648 };
650 static struct omap_hwmod am33xx_emif_fw_hwmod = {
651 .name = "emif_fw",
652 .class = &am33xx_emif_fw_hwmod_class,
653 .clkdm_name = "l4fw_clkdm",
654 .main_clk = "emif_fw_fck",
655 .flags = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
656 .prcm = {
657 .omap4 = {
658 .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
659 .modulemode = MODULEMODE_SWCTRL,
660 },
661 },
662 };
664 /* 'epwmss' class */
665 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
666 .rev_offs = 0x0,
667 .sysc_offs = 0x10,
668 .sysc_flags = SYSC_HAS_SIDLEMODE,
669 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
670 SIDLE_SMART_WKUP),
671 .sysc_fields = &omap_hwmod_sysc_type2,
672 };
674 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
675 .name = "epwmss",
676 .sysc = &am33xx_epwmss_sysc,
677 };
679 /* epwmss0 */
680 static struct omap_hwmod_irq_info am33xx_epwmss0_irqs[] = {
681 { .irq = 86 },
682 { .irq = 58 },
683 { .irq = 31 },
684 { .irq = -1 }
685 };
687 struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
688 {
689 .pa_start = 0x48300000,
690 .pa_end = 0x48300000 + SZ_4K - 1,
691 .flags = ADDR_TYPE_RT
692 },
693 { }
694 };
696 struct omap_hwmod_ocp_if am33xx_l4_core__epwmss0 = {
697 .master = &am33xx_l4per_hwmod,
698 .slave = &am33xx_epwmss0_hwmod,
699 .addr = am33xx_epwmss0_addr_space,
700 .user = OCP_USER_MPU,
701 };
703 static struct omap_hwmod_ocp_if *am33xx_epwmss0_slaves[] = {
704 &am33xx_l4_core__epwmss0,
705 };
707 static struct omap_hwmod am33xx_epwmss0_hwmod = {
708 .name = "epwmss0",
709 .class = &am33xx_epwmss_hwmod_class,
710 .clkdm_name = "l4ls_clkdm",
711 .mpu_irqs = am33xx_epwmss0_irqs,
712 .main_clk = "epwmss0_fck",
713 .prcm = {
714 .omap4 = {
715 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
716 .modulemode = MODULEMODE_SWCTRL,
717 },
718 },
719 .slaves = am33xx_epwmss0_slaves,
720 .slaves_cnt = ARRAY_SIZE(am33xx_epwmss0_slaves),
721 };
723 /* epwmss1 */
724 static struct omap_hwmod_irq_info am33xx_epwmss1_irqs[] = {
725 { .irq = 87 },
726 { .irq = 59 },
727 { .irq = 47 },
728 { .irq = -1 }
729 };
731 struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
732 {
733 .pa_start = 0x48302000,
734 .pa_end = 0x48302000 + SZ_4K - 1,
735 .flags = ADDR_TYPE_RT
736 },
737 { }
738 };
740 struct omap_hwmod_ocp_if am33xx_l4_core__epwmss1 = {
741 .master = &am33xx_l4per_hwmod,
742 .slave = &am33xx_epwmss1_hwmod,
743 .addr = am33xx_epwmss1_addr_space,
744 .user = OCP_USER_MPU,
745 };
747 static struct omap_hwmod_ocp_if *am33xx_epwmss1_slaves[] = {
748 &am33xx_l4_core__epwmss1,
749 };
751 static struct omap_hwmod am33xx_epwmss1_hwmod = {
752 .name = "epwmss1",
753 .class = &am33xx_epwmss_hwmod_class,
754 .clkdm_name = "l4ls_clkdm",
755 .mpu_irqs = am33xx_epwmss1_irqs,
756 .main_clk = "epwmss1_fck",
757 .prcm = {
758 .omap4 = {
759 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
760 .modulemode = MODULEMODE_SWCTRL,
761 },
762 },
763 .slaves = am33xx_epwmss1_slaves,
764 .slaves_cnt = ARRAY_SIZE(am33xx_epwmss1_slaves),
765 };
767 /* epwmss2 */
768 static struct omap_hwmod_irq_info am33xx_epwmss2_irqs[] = {
769 { .irq = 39 },
770 { .irq = 60 },
771 { .irq = 61 },
772 { .irq = -1 }
773 };
775 struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
776 {
777 .pa_start = 0x48304000,
778 .pa_end = 0x48304000 + SZ_4K - 1,
779 .flags = ADDR_TYPE_RT
780 },
781 { }
782 };
784 struct omap_hwmod_ocp_if am33xx_l4_core__epwmss2 = {
785 .master = &am33xx_l4per_hwmod,
786 .slave = &am33xx_epwmss2_hwmod,
787 .addr = am33xx_epwmss2_addr_space,
788 .user = OCP_USER_MPU,
789 };
791 static struct omap_hwmod_ocp_if *am33xx_epwmss2_slaves[] = {
792 &am33xx_l4_core__epwmss2,
793 };
795 static struct omap_hwmod am33xx_epwmss2_hwmod = {
796 .name = "epwmss2",
797 .class = &am33xx_epwmss_hwmod_class,
798 .clkdm_name = "l4ls_clkdm",
799 .mpu_irqs = am33xx_epwmss2_irqs,
800 .main_clk = "epwmss2_fck",
801 .prcm = {
802 .omap4 = {
803 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
804 .modulemode = MODULEMODE_SWCTRL,
805 },
806 },
807 .slaves = am33xx_epwmss2_slaves,
808 .slaves_cnt = ARRAY_SIZE(am33xx_epwmss2_slaves),
809 };
811 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
812 .rev_offs = 0x0000,
813 .sysc_offs = 0x0010,
814 .syss_offs = 0x0114,
815 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
816 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
817 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
818 SIDLE_SMART_WKUP),
819 .sysc_fields = &omap_hwmod_sysc_type1,
820 };
822 /* 'gpio' class */
823 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
824 .name = "gpio",
825 .sysc = &am33xx_gpio_sysc,
826 .rev = 2,
827 };
829 static struct omap_gpio_dev_attr gpio_dev_attr = {
830 .bank_width = 32,
831 .dbck_flag = true,
832 };
834 /* gpio0 */
835 static struct omap_hwmod_ocp_if *am33xx_gpio0_slaves[] = {
836 &am33xx_l4_wkup__gpio0,
837 };
839 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
840 { .role = "dbclk", .clk = "gpio0_dbclk" },
841 };
843 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
844 { .irq = 96 },
845 { .irq = -1 }
846 };
848 static struct omap_hwmod am33xx_gpio0_hwmod = {
849 .name = "gpio1",
850 .class = &am33xx_gpio_hwmod_class,
851 .clkdm_name = "l4_wkup_clkdm",
852 .mpu_irqs = am33xx_gpio0_irqs,
853 .main_clk = "gpio0_ick",
854 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
855 .prcm = {
856 .omap4 = {
857 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
858 .modulemode = MODULEMODE_SWCTRL,
859 },
860 },
861 .opt_clks = gpio0_opt_clks,
862 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
863 .dev_attr = &gpio_dev_attr,
864 .slaves = am33xx_gpio0_slaves,
865 .slaves_cnt = ARRAY_SIZE(am33xx_gpio0_slaves),
866 };
868 /* gpio1 */
869 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
870 { .irq = 98 },
871 { .irq = -1 }
872 };
874 static struct omap_hwmod_ocp_if *am33xx_gpio1_slaves[] = {
875 &am33xx_l4_per__gpio1,
876 };
878 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
879 { .role = "dbclk", .clk = "gpio1_dbclk" },
880 };
882 static struct omap_hwmod am33xx_gpio1_hwmod = {
883 .name = "gpio2",
884 .class = &am33xx_gpio_hwmod_class,
885 .clkdm_name = "l4ls_clkdm",
886 .mpu_irqs = am33xx_gpio1_irqs,
887 .main_clk = "gpio1_ick",
888 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
889 .prcm = {
890 .omap4 = {
891 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
892 .modulemode = MODULEMODE_SWCTRL,
893 },
894 },
895 .opt_clks = gpio1_opt_clks,
896 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
897 .dev_attr = &gpio_dev_attr,
898 .slaves = am33xx_gpio1_slaves,
899 .slaves_cnt = ARRAY_SIZE(am33xx_gpio1_slaves),
900 };
902 /* gpio2 */
903 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
904 { .irq = 32 },
905 { .irq = -1 }
906 };
908 static struct omap_hwmod_ocp_if *am33xx_gpio2_slaves[] = {
909 &am33xx_l4_per__gpio2,
910 };
912 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
913 { .role = "dbclk", .clk = "gpio2_dbclk" },
914 };
916 static struct omap_hwmod am33xx_gpio2_hwmod = {
917 .name = "gpio3",
918 .class = &am33xx_gpio_hwmod_class,
919 .clkdm_name = "l4ls_clkdm",
920 .mpu_irqs = am33xx_gpio2_irqs,
921 .main_clk = "gpio2_ick",
922 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
923 .prcm = {
924 .omap4 = {
925 .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
926 .modulemode = MODULEMODE_SWCTRL,
927 },
928 },
929 .opt_clks = gpio2_opt_clks,
930 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
931 .dev_attr = &gpio_dev_attr,
932 .slaves = am33xx_gpio2_slaves,
933 .slaves_cnt = ARRAY_SIZE(am33xx_gpio2_slaves),
934 };
936 /* gpio3 */
937 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
938 { .irq = 62 },
939 { .irq = -1 }
940 };
942 static struct omap_hwmod_ocp_if *am33xx_gpio3_slaves[] = {
943 &am33xx_l4_per__gpio3,
944 };
946 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
947 { .role = "dbclk", .clk = "gpio3_dbclk" },
948 };
950 static struct omap_hwmod am33xx_gpio3_hwmod = {
951 .name = "gpio4",
952 .class = &am33xx_gpio_hwmod_class,
953 .clkdm_name = "l4ls_clkdm",
954 .mpu_irqs = am33xx_gpio3_irqs,
955 .main_clk = "gpio3_ick",
956 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
957 .prcm = {
958 .omap4 = {
959 .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
960 .modulemode = MODULEMODE_SWCTRL,
961 },
962 },
963 .opt_clks = gpio3_opt_clks,
964 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
965 .dev_attr = &gpio_dev_attr,
966 .slaves = am33xx_gpio3_slaves,
967 .slaves_cnt = ARRAY_SIZE(am33xx_gpio3_slaves),
968 };
970 /* gpmc */
971 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
972 .rev_offs = 0x0,
973 .sysc_offs = 0x10,
974 .syss_offs = 0x14,
975 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
976 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
977 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
978 .sysc_fields = &omap_hwmod_sysc_type1,
979 };
981 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
982 .name = "gpmc",
983 .sysc = &gpmc_sysc,
984 };
986 struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
987 {
988 .pa_start = 0x50000000,
989 .pa_end = 0x50000000 + SZ_8K - 1,
990 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
991 },
992 { }
993 };
995 struct omap_hwmod_ocp_if am33xx_l3_main__gpmc = {
996 .master = &am33xx_l3_main_hwmod,
997 .slave = &am33xx_gpmc_hwmod,
998 .addr = am33xx_gpmc_addr_space,
999 .user = OCP_USER_MPU,
1000 };
1002 static struct omap_hwmod_ocp_if *am33xx_gpmc_slaves[] = {
1003 &am33xx_l3_main__gpmc,
1004 };
1006 static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
1007 { .irq = 100 },
1008 { .irq = -1 }
1009 };
1011 static struct omap_hwmod am33xx_gpmc_hwmod = {
1012 .name = "gpmc",
1013 .class = &am33xx_gpmc_hwmod_class,
1014 .clkdm_name = "l3s_clkdm",
1015 .mpu_irqs = am33xx_gpmc_irqs,
1016 .main_clk = "gpmc_fck",
1017 .prcm = {
1018 .omap4 = {
1019 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
1020 .modulemode = MODULEMODE_SWCTRL,
1021 },
1022 },
1023 .slaves = am33xx_gpmc_slaves,
1024 .slaves_cnt = ARRAY_SIZE(am33xx_gpmc_slaves),
1025 };
1027 /* 'i2c' class */
1028 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
1029 .sysc_offs = 0x0010,
1030 .syss_offs = 0x0090,
1031 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1032 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1033 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1034 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1035 SIDLE_SMART_WKUP),
1036 .sysc_fields = &omap_hwmod_sysc_type1,
1037 };
1039 static struct omap_i2c_dev_attr i2c_dev_attr = {
1040 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1041 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1042 };
1044 static struct omap_hwmod_class i2c_class = {
1045 .name = "i2c",
1046 .sysc = &am33xx_i2c_sysc,
1047 .rev = OMAP_I2C_IP_VERSION_2,
1048 .reset = &omap_i2c_reset,
1049 };
1051 /* I2C1 */
1052 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1053 { .irq = 70 },
1054 { .irq = -1 }
1055 };
1057 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
1058 { .name = "tx", .dma_req = 0, },
1059 { .name = "rx", .dma_req = 0, },
1060 { .dma_req = -1 }
1061 };
1063 static struct omap_hwmod_ocp_if *am33xx_i2c1_slaves[] = {
1064 &am33xx_l4_wkup_i2c1,
1065 };
1067 static struct omap_hwmod am33xx_i2c1_hwmod = {
1068 .name = "i2c1",
1069 .class = &i2c_class,
1070 .clkdm_name = "l4_wkup_clkdm",
1071 .mpu_irqs = i2c1_mpu_irqs,
1072 .main_clk = "i2c1_fck",
1073 .sdma_reqs = i2c1_edma_reqs,
1074 .flags = HWMOD_16BIT_REG,
1075 .prcm = {
1076 .omap4 = {
1077 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
1078 .modulemode = MODULEMODE_SWCTRL,
1079 },
1080 },
1081 .dev_attr = &i2c_dev_attr,
1082 .slaves = am33xx_i2c1_slaves,
1083 .slaves_cnt = ARRAY_SIZE(am33xx_i2c1_slaves),
1084 };
1086 /* i2c2 */
1087 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
1088 {
1089 .pa_start = 0x4802A000,
1090 .pa_end = 0x4802A000 + SZ_4K - 1,
1091 .flags = ADDR_TYPE_RT,
1092 },
1093 { }
1094 };
1096 static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = {
1097 .master = &am33xx_l4per_hwmod,
1098 .slave = &am33xx_i2c2_hwmod,
1099 .addr = am33xx_i2c2_addr_space,
1100 .user = OCP_USER_MPU,
1101 };
1103 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1104 { .irq = 71 },
1105 { .irq = -1 }
1106 };
1108 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
1109 { .name = "tx", .dma_req = 0, },
1110 { .name = "rx", .dma_req = 0, },
1111 { .dma_req = -1 }
1112 };
1114 static struct omap_hwmod_ocp_if *am33xx_i2c2_slaves[] = {
1115 &am335_l4_per_i2c2,
1116 };
1118 static struct omap_hwmod am33xx_i2c2_hwmod = {
1119 .name = "i2c2",
1120 .class = &i2c_class,
1121 .clkdm_name = "l4ls_clkdm",
1122 .mpu_irqs = i2c2_mpu_irqs,
1123 .main_clk = "i2c2_fck",
1124 .sdma_reqs = i2c2_edma_reqs,
1125 .flags = HWMOD_16BIT_REG,
1126 .prcm = {
1127 .omap4 = {
1128 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
1129 .modulemode = MODULEMODE_SWCTRL,
1130 },
1131 },
1132 .dev_attr = &i2c_dev_attr,
1133 .slaves = am33xx_i2c2_slaves,
1134 .slaves_cnt = ARRAY_SIZE(am33xx_i2c2_slaves),
1135 };
1137 /* I2C3 */
1138 static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
1139 {
1140 .pa_start = 0x4819C000,
1141 .pa_end = 0x4819C000 + SZ_4K - 1,
1142 .flags = ADDR_TYPE_RT
1143 },
1144 { }
1145 };
1147 static struct omap_hwmod_ocp_if am335_l4_per_i2c3 = {
1148 .master = &am33xx_l4per_hwmod,
1149 .slave = &am33xx_i2c3_hwmod,
1150 .addr = am33xx_i2c3_addr_space,
1151 .user = OCP_USER_MPU,
1152 };
1154 static struct omap_hwmod_ocp_if *am33xx_i2c3_slaves[] = {
1155 &am335_l4_per_i2c3,
1156 };
1158 static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
1159 { .name = "tx", .dma_req = 0, },
1160 { .name = "rx", .dma_req = 0, },
1161 { .dma_req = -1 }
1162 };
1164 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1165 { .irq = 30 },
1166 { .irq = -1 }
1167 };
1169 static struct omap_hwmod am33xx_i2c3_hwmod = {
1170 .name = "i2c3",
1171 .class = &i2c_class,
1172 .clkdm_name = "l4ls_clkdm",
1173 .mpu_irqs = i2c3_mpu_irqs,
1174 .main_clk = "i2c3_fck",
1175 .sdma_reqs = i2c3_edma_reqs,
1176 .flags = HWMOD_16BIT_REG,
1177 .prcm = {
1178 .omap4 = {
1179 .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
1180 .modulemode = MODULEMODE_SWCTRL,
1181 },
1182 },
1183 .dev_attr = &i2c_dev_attr,
1184 .slaves = am33xx_i2c3_slaves,
1185 .slaves_cnt = ARRAY_SIZE(am33xx_i2c3_slaves),
1186 };
1189 /* ieee5000 */
1190 static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = {
1191 .name = "ieee5000",
1192 };
1194 static struct omap_hwmod am33xx_ieee5000_hwmod = {
1195 .name = "ieee5000",
1196 .class = &am33xx_ieee5000_hwmod_class,
1197 .clkdm_name = "l3s_clkdm",
1198 .main_clk = "ieee5000_fck",
1199 .prcm = {
1200 .omap4 = {
1201 .clkctrl_offs = AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET,
1202 .modulemode = MODULEMODE_SWCTRL,
1203 },
1204 },
1205 };
1208 /* 'l3' class */
1209 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
1210 .name = "l3",
1211 };
1213 /* l4_hs */
1214 static struct omap_hwmod am33xx_l4_hs_hwmod = {
1215 .name = "l4_hs",
1216 .class = &am33xx_l3_hwmod_class,
1217 .clkdm_name = "l4hs_clkdm",
1218 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1219 .prcm = {
1220 .omap4 = {
1221 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
1222 .modulemode = MODULEMODE_SWCTRL,
1223 },
1224 },
1225 };
1227 /* l3_instr */
1228 static struct omap_hwmod am33xx_l3_instr_hwmod = {
1229 .name = "l3_instr",
1230 .class = &am33xx_l3_hwmod_class,
1231 .clkdm_name = "l3_clkdm",
1232 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1233 .prcm = {
1234 .omap4 = {
1235 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
1236 .modulemode = MODULEMODE_SWCTRL,
1237 },
1238 },
1239 };
1241 /* l3_main */
1242 static struct omap_hwmod am33xx_l3_main_hwmod = {
1243 .name = "l3_main",
1244 .class = &am33xx_l3_hwmod_class,
1245 .clkdm_name = "l3_clkdm",
1246 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1247 .prcm = {
1248 .omap4 = {
1249 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
1250 .modulemode = MODULEMODE_SWCTRL,
1251 },
1252 },
1253 };
1255 /* 'l4fw' class */
1256 static struct omap_hwmod_class am33xx_l4fw_hwmod_class = {
1257 .name = "l4fw",
1258 };
1260 /* l4fw */
1261 static struct omap_hwmod am33xx_l4fw_hwmod = {
1262 .name = "l4fw",
1263 .class = &am33xx_l4fw_hwmod_class,
1264 .clkdm_name = "l4fw_clkdm",
1265 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1266 .prcm = {
1267 .omap4 = {
1268 .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
1269 .modulemode = MODULEMODE_SWCTRL,
1270 },
1271 },
1272 };
1274 /* 'l4ls' class */
1275 static struct omap_hwmod_class am33xx_l4ls_hwmod_class = {
1276 .name = "l4ls",
1277 };
1279 /* l4ls */
1280 static struct omap_hwmod am33xx_l4ls_hwmod = {
1281 .name = "l4ls",
1282 .class = &am33xx_l4ls_hwmod_class,
1283 .clkdm_name = "l4ls_clkdm",
1284 .main_clk = "l4ls_gclk",
1285 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1286 .prcm = {
1287 .omap4 = {
1288 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
1289 .modulemode = MODULEMODE_SWCTRL,
1290 },
1291 },
1292 };
1294 /* lcdc */
1295 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
1296 .rev_offs = 0x0,
1297 .sysc_offs = 0x54,
1298 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
1299 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1300 .sysc_fields = &omap_hwmod_sysc_type2,
1301 };
1303 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1304 .name = "lcdc",
1305 .sysc = &lcdc_sysc,
1306 };
1308 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1309 { .irq = 36 },
1310 { .irq = -1 }
1311 };
1313 struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
1314 {
1315 .pa_start = 0x4830E000,
1316 .pa_end = 0x4830E000 + SZ_8K - 1,
1317 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
1318 },
1319 { }
1320 };
1322 struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
1323 .master = &am33xx_l3_main_hwmod,
1324 .slave = &am33xx_lcdc_hwmod,
1325 .addr = am33xx_lcdc_addr_space,
1326 .user = OCP_USER_MPU,
1327 };
1329 static struct omap_hwmod_ocp_if *am33xx_lcdc_slaves[] = {
1330 &am33xx_l3_main__lcdc,
1331 };
1333 static struct omap_hwmod am33xx_lcdc_hwmod = {
1334 .name = "lcdc",
1335 .class = &am33xx_lcdc_hwmod_class,
1336 .clkdm_name = "lcdc_clkdm",
1337 .mpu_irqs = am33xx_lcdc_irqs,
1338 .main_clk = "lcdc_fck",
1339 .prcm = {
1340 .omap4 = {
1341 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1342 .modulemode = MODULEMODE_SWCTRL,
1343 },
1344 },
1345 .slaves = am33xx_lcdc_slaves,
1346 .slaves_cnt = ARRAY_SIZE(am33xx_lcdc_slaves),
1347 };
1349 /*
1350 * 'mailbox' class
1351 * mailbox module allowing communication between the on-chip processors using a
1352 * queued mailbox-interrupt mechanism.
1353 */
1355 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1356 .rev_offs = 0x0000,
1357 .sysc_offs = 0x0010,
1358 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1359 SYSC_HAS_SOFTRESET),
1360 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1361 .sysc_fields = &omap_hwmod_sysc_type2,
1362 };
1364 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1365 .name = "mailbox",
1366 .sysc = &am33xx_mailbox_sysc,
1367 };
1369 static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1370 { .irq = 77 },
1371 { .irq = -1 }
1372 };
1374 static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
1375 {
1376 .pa_start = 0x480C8000,
1377 .pa_end = 0x480C8000 + (SZ_4K - 1),
1378 .flags = ADDR_TYPE_RT
1379 },
1380 { }
1381 };
1383 /* l4_cfg -> mailbox */
1384 static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
1385 .master = &am33xx_l4per_hwmod,
1386 .slave = &am33xx_mailbox_hwmod,
1387 .addr = am33xx_mailbox_addrs,
1388 .user = OCP_USER_MPU,
1389 };
1391 static struct omap_hwmod_ocp_if *am33xx_mailbox_slaves[] = {
1392 &am33xx_l4_per__mailbox,
1393 };
1395 static struct omap_hwmod am33xx_mailbox_hwmod = {
1396 .name = "mailbox",
1397 .class = &am33xx_mailbox_hwmod_class,
1398 .clkdm_name = "l4ls_clkdm",
1399 .mpu_irqs = am33xx_mailbox_irqs,
1400 .main_clk = "mailbox0_fck",
1401 .prcm = {
1402 .omap4 = {
1403 .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1404 .modulemode = MODULEMODE_SWCTRL,
1405 },
1406 },
1407 .slaves = am33xx_mailbox_slaves,
1408 .slaves_cnt = ARRAY_SIZE(am33xx_mailbox_slaves),
1409 };
1411 /* 'mcasp' class */
1412 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1413 .name = "mcasp",
1414 };
1416 /* mcasp0 */
1417 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1418 { .name = "ax", .irq = 80, },
1419 { .name = "ar", .irq = 81, },
1420 { .irq = -1 }
1421 };
1423 static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
1424 {
1425 .pa_start = 0x48038000,
1426 .pa_end = 0x48038000 + (SZ_1K * 12) - 1,
1427 .flags = ADDR_TYPE_RT
1428 },
1429 { }
1430 };
1432 static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp0 = {
1433 .master = &am33xx_l3slow_hwmod,
1434 .slave = &am33xx_mcasp0_hwmod,
1435 .clk = "mcasp0_ick",
1436 .addr = am33xx_mcasp0_addr_space,
1437 .user = OCP_USER_MPU,
1438 };
1440 static struct omap_hwmod_ocp_if *am33xx_mcasp0_slaves[] = {
1441 &am33xx_l3_slow__mcasp0,
1442 };
1444 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1445 .name = "mcasp0",
1446 .class = &am33xx_mcasp_hwmod_class,
1447 .clkdm_name = "l3s_clkdm",
1448 .mpu_irqs = am33xx_mcasp0_irqs,
1449 .main_clk = "mcasp0_fck",
1450 .prcm = {
1451 .omap4 = {
1452 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1453 .modulemode = MODULEMODE_SWCTRL,
1454 },
1455 },
1456 .slaves = am33xx_mcasp0_slaves,
1457 .slaves_cnt = ARRAY_SIZE(am33xx_mcasp0_slaves),
1458 };
1460 /* mcasp1 */
1461 static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
1462 { .name = "ax", .irq = 82, },
1463 { .name = "ar", .irq = 83, },
1464 { .irq = -1 }
1465 };
1467 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
1468 {
1469 .pa_start = 0x4803C000,
1470 .pa_end = 0x4803C000 + (SZ_1K * 12) - 1,
1471 .flags = ADDR_TYPE_RT
1472 },
1473 { }
1474 };
1476 static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp1 = {
1477 .master = &am33xx_l3slow_hwmod,
1478 .slave = &am33xx_mcasp1_hwmod,
1479 .clk = "mcasp1_ick",
1480 .addr = am33xx_mcasp1_addr_space,
1481 .user = OCP_USER_MPU,
1482 };
1484 static struct omap_hwmod_ocp_if *am33xx_mcasp1_slaves[] = {
1485 &am33xx_l3_slow__mcasp1,
1486 };
1488 static struct omap_hwmod am33xx_mcasp1_hwmod = {
1489 .name = "mcasp1",
1490 .class = &am33xx_mcasp_hwmod_class,
1491 .clkdm_name = "l3s_clkdm",
1492 .mpu_irqs = am33xx_mcasp1_irqs,
1493 .main_clk = "mcasp1_fck",
1494 .prcm = {
1495 .omap4 = {
1496 .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
1497 .modulemode = MODULEMODE_SWCTRL,
1498 },
1499 },
1500 .slaves = am33xx_mcasp1_slaves,
1501 .slaves_cnt = ARRAY_SIZE(am33xx_mcasp1_slaves),
1502 };
1504 /* 'mmc' class */
1505 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1506 .rev_offs = 0x1fc,
1507 .sysc_offs = 0x10,
1508 .syss_offs = 0x14,
1509 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1510 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1511 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1512 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1513 .sysc_fields = &omap_hwmod_sysc_type1,
1514 };
1516 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1517 .name = "mmc",
1518 .sysc = &am33xx_mmc_sysc,
1519 };
1521 /* mmc0 */
1522 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1523 { .irq = 64 },
1524 { .irq = -1 }
1525 };
1527 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1528 { .name = "tx", .dma_req = 24, },
1529 { .name = "rx", .dma_req = 25, },
1530 { .dma_req = -1 }
1531 };
1533 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
1534 {
1535 .pa_start = 0x48060100,
1536 .pa_end = 0x48060100 + SZ_4K - 1,
1537 .flags = ADDR_TYPE_RT,
1538 },
1539 { }
1540 };
1542 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc0 = {
1543 .master = &am33xx_l4ls_hwmod,
1544 .slave = &am33xx_mmc0_hwmod,
1545 .clk = "mmc0_ick",
1546 .addr = am33xx_mmc0_addr_space,
1547 .user = OCP_USER_MPU,
1548 };
1550 static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = {
1551 &am33xx_l4ls__mmc0,
1552 };
1554 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1555 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1556 };
1558 static struct omap_hwmod am33xx_mmc0_hwmod = {
1559 .name = "mmc1",
1560 .class = &am33xx_mmc_hwmod_class,
1561 .clkdm_name = "l4ls_clkdm",
1562 .mpu_irqs = am33xx_mmc0_irqs,
1563 .main_clk = "mmc0_fck",
1564 .sdma_reqs = am33xx_mmc0_edma_reqs,
1565 .prcm = {
1566 .omap4 = {
1567 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1568 .modulemode = MODULEMODE_SWCTRL,
1569 },
1570 },
1571 .dev_attr = &am33xx_mmc0_dev_attr,
1572 .slaves = am33xx_mmc0_slaves,
1573 .slaves_cnt = ARRAY_SIZE(am33xx_mmc0_slaves),
1574 };
1576 /* mmc1 */
1577 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1578 { .irq = 28 },
1579 { .irq = -1 }
1580 };
1582 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1583 { .name = "tx", .dma_req = 2, },
1584 { .name = "rx", .dma_req = 3, },
1585 { .dma_req = -1 }
1586 };
1588 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
1589 {
1590 .pa_start = 0x481D8100,
1591 .pa_end = 0x481D8100 + SZ_4K - 1,
1592 .flags = ADDR_TYPE_RT,
1593 },
1594 { }
1595 };
1597 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc1 = {
1598 .master = &am33xx_l4ls_hwmod,
1599 .slave = &am33xx_mmc1_hwmod,
1600 .clk = "mmc1_ick",
1601 .addr = am33xx_mmc1_addr_space,
1602 .user = OCP_USER_MPU,
1603 };
1605 static struct omap_hwmod_ocp_if *am33xx_mmc1_slaves[] = {
1606 &am33xx_l4ls__mmc1,
1607 };
1609 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1610 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1611 };
1613 static struct omap_hwmod am33xx_mmc1_hwmod = {
1614 .name = "mmc2",
1615 .class = &am33xx_mmc_hwmod_class,
1616 .clkdm_name = "l4ls_clkdm",
1617 .mpu_irqs = am33xx_mmc1_irqs,
1618 .main_clk = "mmc1_fck",
1619 .sdma_reqs = am33xx_mmc1_edma_reqs,
1620 .prcm = {
1621 .omap4 = {
1622 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1623 .modulemode = MODULEMODE_SWCTRL,
1624 },
1625 },
1626 .dev_attr = &am33xx_mmc1_dev_attr,
1627 .slaves = am33xx_mmc1_slaves,
1628 .slaves_cnt = ARRAY_SIZE(am33xx_mmc1_slaves),
1629 };
1631 /* mmc2 */
1632 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1633 { .irq = 29 },
1634 { .irq = -1 }
1635 };
1637 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1638 { .name = "tx", .dma_req = 64, },
1639 { .name = "rx", .dma_req = 65, },
1640 { .dma_req = -1 }
1641 };
1643 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
1644 {
1645 .pa_start = 0x47810100,
1646 .pa_end = 0x47810100 + SZ_64K - 1,
1647 .flags = ADDR_TYPE_RT,
1648 },
1649 { }
1650 };
1652 static struct omap_hwmod_ocp_if am33xx_l3_main__mmc2 = {
1653 .master = &am33xx_l3_main_hwmod,
1654 .slave = &am33xx_mmc2_hwmod,
1655 .clk = "mmc2_ick",
1656 .addr = am33xx_mmc2_addr_space,
1657 .user = OCP_USER_MPU,
1658 };
1660 static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = {
1661 &am33xx_l3_main__mmc2,
1662 };
1664 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1665 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1666 };
1667 static struct omap_hwmod am33xx_mmc2_hwmod = {
1668 .name = "mmc3",
1669 .class = &am33xx_mmc_hwmod_class,
1670 .clkdm_name = "l3s_clkdm",
1671 .mpu_irqs = am33xx_mmc2_irqs,
1672 .main_clk = "mmc2_fck",
1673 .sdma_reqs = am33xx_mmc2_edma_reqs,
1674 .prcm = {
1675 .omap4 = {
1676 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1677 .modulemode = MODULEMODE_SWCTRL,
1678 },
1679 },
1680 .dev_attr = &am33xx_mmc2_dev_attr,
1681 .slaves = am33xx_mmc2_slaves,
1682 .slaves_cnt = ARRAY_SIZE(am33xx_mmc2_slaves),
1683 };
1685 /* Master interfaces on the MPU interconnect */
1686 static struct omap_hwmod_ocp_if *am33xx_l3_mpu_masters[] = {
1687 &am33xx_mpu__l3_slow,
1688 };
1690 /* mpu */
1691 static struct omap_hwmod am33xx_mpu_hwmod = {
1692 .name = "mpu",
1693 .class = &mpu_hwmod_class,
1694 .clkdm_name = "mpu_clkdm",
1695 .main_clk = "mpu_fck",
1696 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1697 .prcm = {
1698 .omap4 = {
1699 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1700 .modulemode = MODULEMODE_SWCTRL,
1701 },
1702 },
1703 .masters = am33xx_l3_mpu_masters,
1704 .masters_cnt = ARRAY_SIZE(am33xx_l3_mpu_masters),
1705 };
1707 /* ocmcram */
1708 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
1709 .name = "ocmcram",
1710 };
1712 static struct omap_hwmod am33xx_ocmcram_hwmod = {
1713 .name = "ocmcram",
1714 .class = &am33xx_ocmcram_hwmod_class,
1715 .clkdm_name = "l3_clkdm",
1716 .main_clk = "ocmcram_ick",
1717 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1718 .prcm = {
1719 .omap4 = {
1720 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
1721 .modulemode = MODULEMODE_SWCTRL,
1722 },
1723 },
1724 };
1726 /* ocpwp */
1727 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
1728 .name = "ocpwp",
1729 };
1731 static struct omap_hwmod am33xx_ocpwp_hwmod = {
1732 .name = "ocpwp",
1733 .class = &am33xx_ocpwp_hwmod_class,
1734 .clkdm_name = "l4ls_clkdm",
1735 .main_clk = "ocpwp_fck",
1736 .prcm = {
1737 .omap4 = {
1738 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
1739 .modulemode = MODULEMODE_SWCTRL,
1740 },
1741 },
1742 };
1744 /* rtc */
1745 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1746 .name = "rtc",
1747 };
1749 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1750 { .irq = 75 },
1751 { .irq = -1 }
1752 };
1754 static struct omap_hwmod am33xx_rtc_hwmod = {
1755 .name = "rtc",
1756 .class = &am33xx_rtc_hwmod_class,
1757 .clkdm_name = "l4_rtc_clkdm",
1758 .mpu_irqs = am33xx_rtc_irqs,
1759 .main_clk = "rtc_fck",
1760 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), /* ??? */
1761 .prcm = {
1762 .omap4 = {
1763 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1764 .modulemode = MODULEMODE_SWCTRL,
1765 },
1766 },
1767 };
1769 /* sha0 */
1770 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
1771 .name = "sha0",
1772 };
1774 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
1775 { .irq = 108 },
1776 { .irq = -1 }
1777 };
1779 static struct omap_hwmod am33xx_sha0_hwmod = {
1780 .name = "sha0",
1781 .class = &am33xx_sha0_hwmod_class,
1782 .clkdm_name = "l3_clkdm",
1783 .mpu_irqs = am33xx_sha0_irqs,
1784 .main_clk = "sha0_fck",
1785 .prcm = {
1786 .omap4 = {
1787 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
1788 .modulemode = MODULEMODE_SWCTRL,
1789 },
1790 },
1791 };
1793 /* 'smartreflex' class */
1794 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
1795 .name = "smartreflex",
1796 };
1798 /* smartreflex0 */
1799 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
1800 { .irq = 120 },
1801 { .irq = -1 }
1802 };
1804 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
1805 .name = "smartreflex0",
1806 .class = &am33xx_smartreflex_hwmod_class,
1807 .clkdm_name = "l4_wkup_clkdm",
1808 .mpu_irqs = am33xx_smartreflex0_irqs,
1809 .main_clk = "smartreflex0_fck",
1810 .prcm = {
1811 .omap4 = {
1812 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
1813 .modulemode = MODULEMODE_SWCTRL,
1814 },
1815 },
1816 };
1818 /* smartreflex1 */
1819 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
1820 { .irq = 121 },
1821 { .irq = -1 }
1822 };
1824 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
1825 .name = "smartreflex1",
1826 .class = &am33xx_smartreflex_hwmod_class,
1827 .clkdm_name = "l4_wkup_clkdm",
1828 .mpu_irqs = am33xx_smartreflex1_irqs,
1829 .main_clk = "smartreflex1_fck",
1830 .prcm = {
1831 .omap4 = {
1832 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
1833 .modulemode = MODULEMODE_SWCTRL,
1834 },
1835 },
1836 };
1838 /* 'spi' class */
1839 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1840 .rev_offs = 0x0000,
1841 .sysc_offs = 0x0110,
1842 .syss_offs = 0x0114,
1843 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1844 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1845 SYSS_HAS_RESET_STATUS),
1846 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1847 .sysc_fields = &omap_hwmod_sysc_type1,
1848 };
1850 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1851 .name = "mcspi",
1852 .sysc = &am33xx_mcspi_sysc,
1853 .rev = OMAP4_MCSPI_REV,
1854 };
1856 /* spi0 */
1857 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1858 { .irq = 65 },
1859 { .irq = -1 }
1860 };
1862 struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
1863 { .name = "rx0", .dma_req = 17 },
1864 { .name = "tx0", .dma_req = 16 },
1865 { .name = "rx1", .dma_req = 19 },
1866 { .name = "tx1", .dma_req = 18 },
1867 { .dma_req = -1 }
1868 };
1870 struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
1871 {
1872 .pa_start = 0x48030000,
1873 .pa_end = 0x48030000 + SZ_1K - 1,
1874 .flags = ADDR_TYPE_RT,
1875 },
1876 { }
1877 };
1879 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = {
1880 .master = &am33xx_l4per_hwmod,
1881 .slave = &am33xx_spi0_hwmod,
1882 .clk = "spi0_ick",
1883 .addr = am33xx_mcspi0_addr_space,
1884 .user = OCP_USER_MPU,
1885 };
1887 static struct omap_hwmod_ocp_if *am33xx_mcspi0_slaves[] = {
1888 &am33xx_l4_core__mcspi0,
1889 };
1891 struct omap2_mcspi_dev_attr mcspi_attrib = {
1892 .num_chipselect = 2,
1893 };
1894 static struct omap_hwmod am33xx_spi0_hwmod = {
1895 .name = "spi0",
1896 .class = &am33xx_spi_hwmod_class,
1897 .clkdm_name = "l4ls_clkdm",
1898 .mpu_irqs = am33xx_spi0_irqs,
1899 .main_clk = "spi0_fck",
1900 .sdma_reqs = am33xx_mcspi0_edma_reqs,
1901 .prcm = {
1902 .omap4 = {
1903 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1904 .modulemode = MODULEMODE_SWCTRL,
1905 },
1906 },
1907 .dev_attr = &mcspi_attrib,
1908 .slaves = am33xx_mcspi0_slaves,
1909 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi0_slaves),
1910 };
1912 /* spi1 */
1913 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1914 { .irq = 125 },
1915 { .irq = -1 }
1916 };
1918 struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
1919 { .name = "rx0", .dma_req = 43 },
1920 { .name = "tx0", .dma_req = 42 },
1921 { .name = "rx1", .dma_req = 45 },
1922 { .name = "tx1", .dma_req = 44 },
1923 { .dma_req = -1 }
1924 };
1926 struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
1927 {
1928 .pa_start = 0x481A0000,
1929 .pa_end = 0x481A0000 + SZ_1K - 1,
1930 .flags = ADDR_TYPE_RT,
1931 },
1932 { }
1933 };
1935 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = {
1936 .master = &am33xx_l4per_hwmod,
1937 .slave = &am33xx_spi1_hwmod,
1938 .clk = "spi1_ick",
1939 .addr = am33xx_mcspi1_addr_space,
1940 .user = OCP_USER_MPU,
1941 };
1943 static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = {
1944 &am33xx_l4_core__mcspi1,
1945 };
1946 static struct omap_hwmod am33xx_spi1_hwmod = {
1947 .name = "spi1",
1948 .class = &am33xx_spi_hwmod_class,
1949 .clkdm_name = "l4ls_clkdm",
1950 .mpu_irqs = am33xx_spi1_irqs,
1951 .main_clk = "spi1_fck",
1952 .sdma_reqs = am33xx_mcspi1_edma_reqs,
1953 .prcm = {
1954 .omap4 = {
1955 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1956 .modulemode = MODULEMODE_SWCTRL,
1957 },
1958 },
1959 .dev_attr = &mcspi_attrib,
1960 .slaves = am33xx_mcspi1_slaves,
1961 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi1_slaves),
1962 };
1964 /* spinlock */
1965 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1966 .name = "spinlock",
1967 };
1969 static struct omap_hwmod am33xx_spinlock_hwmod = {
1970 .name = "spinlock",
1971 .class = &am33xx_spinlock_hwmod_class,
1972 .clkdm_name = "l4ls_clkdm",
1973 .main_clk = "spinlock_fck",
1974 .prcm = {
1975 .omap4 = {
1976 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1977 .modulemode = MODULEMODE_SWCTRL,
1978 },
1979 },
1980 };
1982 /* 'timer 0 & 2-7' class */
1983 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1984 .rev_offs = 0x0000,
1985 .sysc_offs = 0x0010,
1986 .syss_offs = 0x0014,
1987 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1988 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1989 SIDLE_SMART_WKUP),
1990 .sysc_fields = &omap_hwmod_sysc_type2,
1991 };
1993 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1994 .name = "timer",
1995 .sysc = &am33xx_timer_sysc,
1996 };
1998 /* timer0 */
1999 /* l4 wkup -> timer0 interface */
2000 static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = {
2001 {
2002 .pa_start = 0x44E05000,
2003 .pa_end = 0x44E05000 + SZ_1K - 1,
2004 .flags = ADDR_TYPE_RT
2005 },
2006 { }
2007 };
2009 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = {
2010 .master = &am33xx_l4wkup_hwmod,
2011 .slave = &am33xx_timer0_hwmod,
2012 .clk = "timer0_ick",
2013 .addr = am33xx_timer0_addr_space,
2014 .user = OCP_USER_MPU,
2015 };
2017 static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = {
2018 &am33xx_l4wkup__timer0,
2019 };
2021 static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = {
2022 { .irq = 66 },
2023 { .irq = -1 }
2024 };
2026 static struct omap_hwmod am33xx_timer0_hwmod = {
2027 .name = "timer0",
2028 .class = &am33xx_timer_hwmod_class,
2029 .clkdm_name = "l4_wkup_clkdm",
2030 .mpu_irqs = am33xx_timer0_irqs,
2031 .main_clk = "timer0_fck",
2032 .prcm = {
2033 .omap4 = {
2034 .clkctrl_offs = AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET,
2035 .modulemode = MODULEMODE_SWCTRL,
2036 },
2037 },
2038 .slaves = am33xx_timer0_slaves,
2039 .slaves_cnt = ARRAY_SIZE(am33xx_timer0_slaves),
2040 };
2042 /* timer1 1ms */
2043 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
2044 .rev_offs = 0x0000,
2045 .sysc_offs = 0x0010,
2046 .syss_offs = 0x0014,
2047 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2048 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
2049 SYSS_HAS_RESET_STATUS),
2050 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2051 .sysc_fields = &omap_hwmod_sysc_type1,
2052 };
2054 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
2055 .name = "timer",
2056 .sysc = &am33xx_timer1ms_sysc,
2057 };
2059 /* l4 wkup -> timer1 interface */
2060 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
2061 {
2062 .pa_start = 0x44E31000,
2063 .pa_end = 0x44E31000 + SZ_1K - 1,
2064 .flags = ADDR_TYPE_RT
2065 },
2066 { }
2067 };
2069 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = {
2070 .master = &am33xx_l4wkup_hwmod,
2071 .slave = &am33xx_timer1_hwmod,
2072 .clk = "timer1_ick",
2073 .addr = am33xx_timer1_addr_space,
2074 .user = OCP_USER_MPU,
2075 };
2077 static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = {
2078 &am33xx_l4wkup__timer1,
2079 };
2081 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
2082 { .irq = 67 },
2083 { .irq = -1 }
2084 };
2086 static struct omap_hwmod am33xx_timer1_hwmod = {
2087 .name = "timer1",
2088 .class = &am33xx_timer1ms_hwmod_class,
2089 .clkdm_name = "l4_wkup_clkdm",
2090 .mpu_irqs = am33xx_timer1_irqs,
2091 .main_clk = "timer1_fck",
2092 .prcm = {
2093 .omap4 = {
2094 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2095 .modulemode = MODULEMODE_SWCTRL,
2096 },
2097 },
2098 .slaves = am33xx_timer1_slaves,
2099 .slaves_cnt = ARRAY_SIZE(am33xx_timer1_slaves),
2100 };
2102 /* timer2 */
2103 /* l4 per -> timer2 interface */
2104 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
2105 {
2106 .pa_start = 0x48040000,
2107 .pa_end = 0x48040000 + SZ_1K - 1,
2108 .flags = ADDR_TYPE_RT
2109 },
2110 { }
2111 };
2113 static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = {
2114 .master = &am33xx_l4per_hwmod,
2115 .slave = &am33xx_timer2_hwmod,
2116 .clk = "timer2_ick",
2117 .addr = am33xx_timer2_addr_space,
2118 .user = OCP_USER_MPU,
2119 };
2121 static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = {
2122 &am33xx_l4per__timer2,
2123 };
2125 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
2126 { .irq = 68 },
2127 { .irq = -1 }
2128 };
2130 static struct omap_hwmod am33xx_timer2_hwmod = {
2131 .name = "timer2",
2132 .class = &am33xx_timer_hwmod_class,
2133 .clkdm_name = "l4ls_clkdm",
2134 .mpu_irqs = am33xx_timer2_irqs,
2135 .main_clk = "timer2_fck",
2136 .prcm = {
2137 .omap4 = {
2138 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
2139 .modulemode = MODULEMODE_SWCTRL,
2140 },
2141 },
2142 .slaves = am33xx_timer2_slaves,
2143 .slaves_cnt = ARRAY_SIZE(am33xx_timer2_slaves),
2144 };
2146 /* timer3 */
2147 /* l4 per -> timer3 interface */
2148 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
2149 {
2150 .pa_start = 0x48042000,
2151 .pa_end = 0x48042000 + SZ_1K - 1,
2152 .flags = ADDR_TYPE_RT
2153 },
2154 { }
2155 };
2157 static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = {
2158 .master = &am33xx_l4per_hwmod,
2159 .slave = &am33xx_timer3_hwmod,
2160 .clk = "timer3_ick",
2161 .addr = am33xx_timer3_addr_space,
2162 .user = OCP_USER_MPU,
2163 };
2165 static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = {
2166 &am33xx_l4per__timer3,
2167 };
2169 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
2170 { .irq = 69 },
2171 { .irq = -1 }
2172 };
2174 static struct omap_hwmod am33xx_timer3_hwmod = {
2175 .name = "timer3",
2176 .class = &am33xx_timer_hwmod_class,
2177 .clkdm_name = "l4ls_clkdm",
2178 .mpu_irqs = am33xx_timer3_irqs,
2179 .main_clk = "timer3_fck",
2180 .prcm = {
2181 .omap4 = {
2182 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
2183 .modulemode = MODULEMODE_SWCTRL,
2184 },
2185 },
2186 .slaves = am33xx_timer3_slaves,
2187 .slaves_cnt = ARRAY_SIZE(am33xx_timer3_slaves),
2188 };
2190 /* timer4 */
2191 /* l4 per -> timer4 interface */
2192 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
2193 {
2194 .pa_start = 0x48044000,
2195 .pa_end = 0x48044000 + SZ_1K - 1,
2196 .flags = ADDR_TYPE_RT
2197 },
2198 { }
2199 };
2201 static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = {
2202 .master = &am33xx_l4per_hwmod,
2203 .slave = &am33xx_timer4_hwmod,
2204 .clk = "timer4_ick",
2205 .addr = am33xx_timer4_addr_space,
2206 .user = OCP_USER_MPU,
2207 };
2209 static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = {
2210 &am33xx_l4per__timer4,
2211 };
2213 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
2214 { .irq = 92 },
2215 { .irq = -1 }
2216 };
2218 static struct omap_hwmod am33xx_timer4_hwmod = {
2219 .name = "timer4",
2220 .class = &am33xx_timer_hwmod_class,
2221 .clkdm_name = "l4ls_clkdm",
2222 .mpu_irqs = am33xx_timer4_irqs,
2223 .main_clk = "timer4_fck",
2224 .prcm = {
2225 .omap4 = {
2226 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
2227 .modulemode = MODULEMODE_SWCTRL,
2228 },
2229 },
2230 .slaves = am33xx_timer4_slaves,
2231 .slaves_cnt = ARRAY_SIZE(am33xx_timer4_slaves),
2232 };
2234 /* timer5 */
2235 /* l4 per -> timer5 interface */
2236 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
2237 {
2238 .pa_start = 0x48046000,
2239 .pa_end = 0x48046000 + SZ_1K - 1,
2240 .flags = ADDR_TYPE_RT
2241 },
2242 { }
2243 };
2245 static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = {
2246 .master = &am33xx_l4per_hwmod,
2247 .slave = &am33xx_timer5_hwmod,
2248 .clk = "timer5_ick",
2249 .addr = am33xx_timer5_addr_space,
2250 .user = OCP_USER_MPU,
2251 };
2253 static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = {
2254 &am33xx_l4per__timer5,
2255 };
2257 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
2258 { .irq = 93 },
2259 { .irq = -1 }
2260 };
2262 static struct omap_hwmod am33xx_timer5_hwmod = {
2263 .name = "timer5",
2264 .class = &am33xx_timer_hwmod_class,
2265 .clkdm_name = "l4ls_clkdm",
2266 .mpu_irqs = am33xx_timer5_irqs,
2267 .main_clk = "timer5_fck",
2268 .prcm = {
2269 .omap4 = {
2270 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
2271 .modulemode = MODULEMODE_SWCTRL,
2272 },
2273 },
2274 .slaves = am33xx_timer5_slaves,
2275 .slaves_cnt = ARRAY_SIZE(am33xx_timer5_slaves),
2276 };
2278 /* timer6 */
2279 /* l4 per -> timer6 interface */
2280 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
2281 {
2282 .pa_start = 0x48048000,
2283 .pa_end = 0x48048000 + SZ_1K - 1,
2284 .flags = ADDR_TYPE_RT
2285 },
2286 { }
2287 };
2289 static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = {
2290 .master = &am33xx_l4per_hwmod,
2291 .slave = &am33xx_timer6_hwmod,
2292 .clk = "timer6_ick",
2293 .addr = am33xx_timer6_addr_space,
2294 .user = OCP_USER_MPU,
2295 };
2297 static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = {
2298 &am33xx_l4per__timer6,
2299 };
2301 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
2302 { .irq = 94 },
2303 { .irq = -1 }
2304 };
2306 static struct omap_hwmod am33xx_timer6_hwmod = {
2307 .name = "timer6",
2308 .class = &am33xx_timer_hwmod_class,
2309 .clkdm_name = "l4ls_clkdm",
2310 .mpu_irqs = am33xx_timer6_irqs,
2311 .main_clk = "timer6_fck",
2312 .prcm = {
2313 .omap4 = {
2314 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
2315 .modulemode = MODULEMODE_SWCTRL,
2316 },
2317 },
2318 .slaves = am33xx_timer6_slaves,
2319 .slaves_cnt = ARRAY_SIZE(am33xx_timer6_slaves),
2320 };
2322 /* timer7 */
2323 /* l4 per -> timer7 interface */
2324 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
2325 {
2326 .pa_start = 0x4804A000,
2327 .pa_end = 0x4804A000 + SZ_1K - 1,
2328 .flags = ADDR_TYPE_RT
2329 },
2330 { }
2331 };
2333 static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = {
2334 .master = &am33xx_l4per_hwmod,
2335 .slave = &am33xx_timer7_hwmod,
2336 .clk = "timer7_ick",
2337 .addr = am33xx_timer7_addr_space,
2338 .user = OCP_USER_MPU,
2339 };
2341 static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = {
2342 &am33xx_l4per__timer7,
2343 };
2345 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
2346 { .irq = 95 },
2347 { .irq = -1 }
2348 };
2350 static struct omap_hwmod am33xx_timer7_hwmod = {
2351 .name = "timer7",
2352 .class = &am33xx_timer_hwmod_class,
2353 .clkdm_name = "l4ls_clkdm",
2354 .mpu_irqs = am33xx_timer7_irqs,
2355 .main_clk = "timer7_fck",
2356 .prcm = {
2357 .omap4 = {
2358 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
2359 .modulemode = MODULEMODE_SWCTRL,
2360 },
2361 },
2362 .slaves = am33xx_timer7_slaves,
2363 .slaves_cnt = ARRAY_SIZE(am33xx_timer7_slaves),
2364 };
2366 /* tpcc */
2367 #define AM33XX_TPCC_BASE 0x49000000
2368 #define AM33XX_TPTC0_BASE 0x49800000
2369 #define AM33XX_TPTC1_BASE 0x49900000
2370 #define AM33XX_TPTC2_BASE 0x49a00000
2372 /* 'tpcc' class */
2373 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
2374 .name = "tpcc",
2375 };
2377 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
2378 { .name = "edma0", .irq = 12 },
2379 { .name = "edma0_mperr", .irq = 13, },
2380 { .name = "edma0_err", .irq = 14 },
2381 { .irq = -1 }
2382 };
2384 static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
2385 {
2386 .name = "edma_cc0",
2387 .pa_start = AM33XX_TPCC_BASE,
2388 .pa_end = AM33XX_TPCC_BASE + SZ_32K - 1,
2389 .flags = ADDR_TYPE_RT
2390 },
2391 { }
2392 };
2394 static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
2395 .master = &am33xx_l3_main_hwmod,
2396 .slave = &am33xx_tpcc_hwmod,
2397 .addr = am33xx_tpcc_addr_space,
2398 .user = OCP_USER_MPU,
2399 };
2401 static struct omap_hwmod_ocp_if *am33xx_tpcc_slaves[] = {
2402 &am33xx_l3_main__tpcc,
2403 };
2405 static struct omap_hwmod am33xx_tpcc_hwmod = {
2406 .name = "tpcc",
2407 .class = &am33xx_tpcc_hwmod_class,
2408 .clkdm_name = "l3_clkdm",
2409 .mpu_irqs = am33xx_tpcc_irqs,
2410 .main_clk = "tpcc_ick",
2411 .prcm = {
2412 .omap4 = {
2413 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
2414 .modulemode = MODULEMODE_SWCTRL,
2415 },
2416 },
2417 .slaves = am33xx_tpcc_slaves,
2418 .slaves_cnt = ARRAY_SIZE(am33xx_tpcc_slaves),
2419 };
2421 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
2422 .rev_offs = 0x0,
2423 .sysc_offs = 0x10,
2424 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2425 SYSC_HAS_MIDLEMODE),
2426 .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
2427 .sysc_fields = &omap_hwmod_sysc_type2,
2428 };
2430 /* 'tptc' class */
2431 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
2432 .name = "tptc",
2433 .sysc = &am33xx_tptc_sysc,
2434 };
2436 /* tptc0 */
2437 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
2438 { .irq = 112 },
2439 { .irq = -1 }
2440 };
2442 struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
2443 {
2444 .name = "edma_tc0",
2445 .pa_start = AM33XX_TPTC0_BASE,
2446 .pa_end = AM33XX_TPTC0_BASE + SZ_8K - 1,
2447 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2448 },
2449 { }
2450 };
2452 struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
2453 .master = &am33xx_l3_main_hwmod,
2454 .slave = &am33xx_tptc0_hwmod,
2455 .addr = am33xx_tptc0_addr_space,
2456 .user = OCP_USER_MPU,
2457 };
2459 static struct omap_hwmod_ocp_if *am33xx_tptc0_slaves[] = {
2460 &am33xx_l3_main__tptc0,
2461 };
2463 static struct omap_hwmod am33xx_tptc0_hwmod = {
2464 .name = "tptc0",
2465 .class = &am33xx_tptc_hwmod_class,
2466 .clkdm_name = "l3_clkdm",
2467 .mpu_irqs = am33xx_tptc0_irqs,
2468 .main_clk = "tptc0_ick",
2469 .prcm = {
2470 .omap4 = {
2471 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
2472 .modulemode = MODULEMODE_SWCTRL,
2473 },
2474 },
2475 .slaves = am33xx_tptc0_slaves,
2476 .slaves_cnt = ARRAY_SIZE(am33xx_tptc0_slaves),
2477 };
2479 /* tptc1 */
2480 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
2481 { .irq = 113 },
2482 { .irq = -1 }
2483 };
2485 struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
2486 {
2487 .name = "edma_tc1",
2488 .pa_start = AM33XX_TPTC1_BASE,
2489 .pa_end = AM33XX_TPTC1_BASE + SZ_8K - 1,
2490 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2491 },
2492 { }
2493 };
2495 struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
2496 .master = &am33xx_l3_main_hwmod,
2497 .slave = &am33xx_tptc1_hwmod,
2498 .addr = am33xx_tptc1_addr_space,
2499 .user = OCP_USER_MPU,
2500 };
2502 static struct omap_hwmod_ocp_if *am33xx_tptc1_slaves[] = {
2503 &am33xx_l3_main__tptc1,
2504 };
2506 static struct omap_hwmod am33xx_tptc1_hwmod = {
2507 .name = "tptc1",
2508 .class = &am33xx_tptc_hwmod_class,
2509 .clkdm_name = "l3_clkdm",
2510 .mpu_irqs = am33xx_tptc1_irqs,
2511 .main_clk = "tptc1_ick",
2512 .prcm = {
2513 .omap4 = {
2514 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
2515 .modulemode = MODULEMODE_SWCTRL,
2516 },
2517 },
2518 .slaves = am33xx_tptc1_slaves,
2519 .slaves_cnt = ARRAY_SIZE(am33xx_tptc1_slaves),
2520 };
2522 /* tptc2 */
2523 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
2524 { .irq = 114 },
2525 { .irq = -1 }
2526 };
2528 struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
2529 {
2530 .name = "edma_tc2",
2531 .pa_start = AM33XX_TPTC2_BASE,
2532 .pa_end = AM33XX_TPTC2_BASE + SZ_8K - 1,
2533 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2534 },
2535 { }
2536 };
2538 struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
2539 .master = &am33xx_l3_main_hwmod,
2540 .slave = &am33xx_tptc2_hwmod,
2541 .addr = am33xx_tptc2_addr_space,
2542 .user = OCP_USER_MPU,
2543 };
2545 static struct omap_hwmod_ocp_if *am33xx_tptc2_slaves[] = {
2546 &am33xx_l3_main__tptc2,
2547 };
2549 static struct omap_hwmod am33xx_tptc2_hwmod = {
2550 .name = "tptc2",
2551 .class = &am33xx_tptc_hwmod_class,
2552 .clkdm_name = "l3_clkdm",
2553 .mpu_irqs = am33xx_tptc2_irqs,
2554 .main_clk = "tptc2_ick",
2555 .prcm = {
2556 .omap4 = {
2557 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
2558 .modulemode = MODULEMODE_SWCTRL,
2559 },
2560 },
2561 .slaves = am33xx_tptc2_slaves,
2562 .slaves_cnt = ARRAY_SIZE(am33xx_tptc2_slaves),
2563 };
2565 /* 'uart' class */
2566 static struct omap_hwmod_class_sysconfig uart_sysc = {
2567 .rev_offs = 0x50,
2568 .sysc_offs = 0x54,
2569 .syss_offs = 0x58,
2570 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2571 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2572 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2573 SIDLE_SMART_WKUP),
2574 .sysc_fields = &omap_hwmod_sysc_type1,
2575 };
2577 static struct omap_hwmod_class uart_class = {
2578 .name = "uart",
2579 .sysc = &uart_sysc,
2580 };
2582 /* uart1 */
2583 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
2584 { .name = "tx", .dma_req = 26, },
2585 { .name = "rx", .dma_req = 27, },
2586 { .dma_req = -1 }
2587 };
2589 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
2590 {
2591 .pa_start = 0x44E09000,
2592 .pa_end = 0x44E09000 + SZ_8K - 1,
2593 .flags = ADDR_TYPE_RT,
2594 },
2595 { }
2596 };
2598 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
2599 .master = &am33xx_l4wkup_hwmod,
2600 .slave = &am33xx_uart1_hwmod,
2601 .clk = "uart1_ick",
2602 .addr = am33xx_uart1_addr_space,
2603 .user = OCP_USER_MPU,
2604 };
2606 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
2607 { .irq = 72 },
2608 { .irq = -1 }
2609 };
2611 static struct omap_hwmod_ocp_if *am33xx_uart1_slaves[] = {
2612 &am33xx_l4_wkup__uart1,
2613 };
2615 static struct omap_hwmod am33xx_uart1_hwmod = {
2616 .name = "uart1",
2617 .class = &uart_class,
2618 .clkdm_name = "l4_wkup_clkdm",
2619 .mpu_irqs = am33xx_uart1_irqs,
2620 .main_clk = "uart1_fck",
2621 .sdma_reqs = uart1_edma_reqs,
2622 .prcm = {
2623 .omap4 = {
2624 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
2625 .modulemode = MODULEMODE_SWCTRL,
2626 },
2627 },
2628 .slaves = am33xx_uart1_slaves,
2629 .slaves_cnt = ARRAY_SIZE(am33xx_uart1_slaves),
2630 };
2632 /* uart2 */
2633 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
2634 {
2635 .pa_start = 0x48022000,
2636 .pa_end = 0x48022000 + SZ_8K - 1,
2637 .flags = ADDR_TYPE_RT,
2638 },
2639 { }
2640 };
2642 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
2643 .slave = &am33xx_uart2_hwmod,
2644 .clk = "uart2_ick",
2645 .addr = am33xx_uart2_addr_space,
2646 .user = OCP_USER_MPU,
2647 };
2649 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
2650 { .irq = 73 },
2651 { .irq = -1 }
2652 };
2654 static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = {
2655 &am33xx_l4_ls__uart2,
2656 };
2658 static struct omap_hwmod am33xx_uart2_hwmod = {
2659 .name = "uart2",
2660 .class = &uart_class,
2661 .clkdm_name = "l4ls_clkdm",
2662 .mpu_irqs = am33xx_uart2_irqs,
2663 .main_clk = "uart2_fck",
2664 .sdma_reqs = uart1_edma_reqs,
2665 .prcm = {
2666 .omap4 = {
2667 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
2668 .modulemode = MODULEMODE_SWCTRL,
2669 },
2670 },
2671 .slaves = am33xx_uart2_slaves,
2672 .slaves_cnt = ARRAY_SIZE(am33xx_uart2_slaves),
2673 };
2675 /* uart3 */
2676 static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
2677 { .name = "tx", .dma_req = 30, },
2678 { .name = "rx", .dma_req = 31, },
2679 { .dma_req = -1 }
2680 };
2682 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
2683 {
2684 .pa_start = 0x48024000,
2685 .pa_end = 0x48024000 + SZ_8K - 1,
2686 .flags = ADDR_TYPE_RT,
2687 },
2688 { }
2689 };
2691 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
2692 .slave = &am33xx_uart3_hwmod,
2693 .clk = "uart3_ick",
2694 .addr = am33xx_uart3_addr_space,
2695 .user = OCP_USER_MPU,
2696 };
2698 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2699 { .irq = 74 },
2700 { .irq = -1 }
2701 };
2703 static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = {
2704 &am33xx_l4_ls__uart3,
2705 };
2707 static struct omap_hwmod am33xx_uart3_hwmod = {
2708 .name = "uart3",
2709 .class = &uart_class,
2710 .clkdm_name = "l4ls_clkdm",
2711 .mpu_irqs = am33xx_uart3_irqs,
2712 .main_clk = "uart3_fck",
2713 .sdma_reqs = uart3_edma_reqs,
2714 .prcm = {
2715 .omap4 = {
2716 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
2717 .modulemode = MODULEMODE_SWCTRL,
2718 },
2719 },
2720 .slaves = am33xx_uart3_slaves,
2721 .slaves_cnt = ARRAY_SIZE(am33xx_uart3_slaves),
2722 };
2724 /* uart4 */
2725 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
2726 {
2727 .pa_start = 0x481A6000,
2728 .pa_end = 0x481A6000 + SZ_8K - 1,
2729 .flags = ADDR_TYPE_RT,
2730 },
2731 { }
2732 };
2734 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
2735 .slave = &am33xx_uart4_hwmod,
2736 .clk = "uart4_ick",
2737 .addr = am33xx_uart4_addr_space,
2738 .user = OCP_USER_MPU,
2739 };
2741 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2742 { .irq = 44 },
2743 { .irq = -1 }
2744 };
2746 static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = {
2747 &am33xx_l4_ls__uart4,
2748 };
2750 static struct omap_hwmod am33xx_uart4_hwmod = {
2751 .name = "uart4",
2752 .class = &uart_class,
2753 .mpu_irqs = am33xx_uart4_irqs,
2754 .main_clk = "uart4_fck",
2755 .clkdm_name = "l4ls_clkdm",
2756 .sdma_reqs = uart1_edma_reqs,
2757 .prcm = {
2758 .omap4 = {
2759 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
2760 .modulemode = MODULEMODE_SWCTRL,
2761 },
2762 },
2763 .slaves = am33xx_uart4_slaves,
2764 .slaves_cnt = ARRAY_SIZE(am33xx_uart4_slaves),
2765 };
2767 /* uart5 */
2768 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
2769 {
2770 .pa_start = 0x481A8000,
2771 .pa_end = 0x481A8000 + SZ_8K - 1,
2772 .flags = ADDR_TYPE_RT,
2773 },
2774 { }
2775 };
2777 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
2778 .slave = &am33xx_uart5_hwmod,
2779 .clk = "uart5_ick",
2780 .addr = am33xx_uart5_addr_space,
2781 .user = OCP_USER_MPU,
2782 };
2784 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2785 { .irq = 45 },
2786 { .irq = -1 }
2787 };
2789 static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = {
2790 &am33xx_l4_ls__uart5,
2791 };
2793 static struct omap_hwmod am33xx_uart5_hwmod = {
2794 .name = "uart5",
2795 .class = &uart_class,
2796 .clkdm_name = "l4ls_clkdm",
2797 .mpu_irqs = am33xx_uart5_irqs,
2798 .main_clk = "uart5_fck",
2799 .sdma_reqs = uart1_edma_reqs,
2800 .prcm = {
2801 .omap4 = {
2802 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2803 .modulemode = MODULEMODE_SWCTRL,
2804 },
2805 },
2806 .slaves = am33xx_uart5_slaves,
2807 .slaves_cnt = ARRAY_SIZE(am33xx_uart5_slaves),
2808 };
2810 /* uart6 */
2811 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
2812 {
2813 .pa_start = 0x481AA000,
2814 .pa_end = 0x481AA000 + SZ_8K - 1,
2815 .flags = ADDR_TYPE_RT,
2816 },
2817 { }
2818 };
2820 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
2821 .slave = &am33xx_uart6_hwmod,
2822 .clk = "uart6_ick",
2823 .addr = am33xx_uart6_addr_space,
2824 .user = OCP_USER_MPU,
2825 };
2827 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2828 { .irq = 46 },
2829 { .irq = -1 }
2830 };
2832 static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = {
2833 &am33xx_l4_ls__uart6,
2834 };
2836 static struct omap_hwmod am33xx_uart6_hwmod = {
2837 .name = "uart6",
2838 .class = &uart_class,
2839 .clkdm_name = "l4ls_clkdm",
2840 .mpu_irqs = am33xx_uart6_irqs,
2841 .main_clk = "uart6_fck",
2842 .sdma_reqs = uart1_edma_reqs,
2843 .prcm = {
2844 .omap4 = {
2845 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2846 .modulemode = MODULEMODE_SWCTRL,
2847 },
2848 },
2849 .slaves = am33xx_uart6_slaves,
2850 .slaves_cnt = ARRAY_SIZE(am33xx_uart6_slaves),
2851 };
2853 /* 'wd_timer' class */
2854 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2855 .name = "wd_timer",
2856 };
2858 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
2859 {
2860 .pa_start = 0x44E35000,
2861 .pa_end = 0x44E35000 + SZ_4K - 1,
2862 .flags = ADDR_TYPE_RT
2863 },
2864 { }
2865 };
2867 /* l4_wkup -> wd_timer1 */
2868 static struct omap_hwmod_ocp_if am33xx_l4wkup__wd_timer1 = {
2869 .master = &am33xx_l4wkup_hwmod,
2870 .slave = &am33xx_wd_timer1_hwmod,
2871 .addr = am33xx_wd_timer1_addrs,
2872 .user = OCP_USER_MPU,
2873 };
2875 static struct omap_hwmod_ocp_if *am33xx_wd_timer1_slaves[] = {
2876 &am33xx_l4wkup__wd_timer1,
2877 };
2879 /*
2880 * TODO: device.c file uses hardcoded name for watchdog timer
2881 * driver "wd_timer2, so we are also using same name as of now...
2882 */
2883 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2884 .name = "wd_timer2",
2885 .class = &am33xx_wd_timer_hwmod_class,
2886 .clkdm_name = "l4_wkup_clkdm",
2887 .main_clk = "wdt1_fck",
2888 .prcm = {
2889 .omap4 = {
2890 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2891 .modulemode = MODULEMODE_SWCTRL,
2892 },
2893 },
2894 .slaves = am33xx_wd_timer1_slaves,
2895 .slaves_cnt = ARRAY_SIZE(am33xx_wd_timer1_slaves),
2896 };
2898 /* wkup_m3 */
2899 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
2900 .name = "wkup_m3",
2901 };
2903 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
2904 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
2905 };
2907 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
2908 .name = "wkup_m3",
2909 .class = &am33xx_wkup_m3_hwmod_class,
2910 .clkdm_name = "l4_wkup_aon_clkdm",
2911 .main_clk = "wkup_m3_fck",
2912 .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */
2913 .prcm = {
2914 .omap4 = {
2915 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
2916 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
2917 .modulemode = MODULEMODE_SWCTRL,
2918 },
2919 },
2920 .rst_lines = am33xx_wkup_m3_resets,
2921 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
2922 };
2924 /* usbss */
2925 /* L3 SLOW -> USBSS interface */
2926 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
2927 {
2928 .name = "usbss",
2929 .pa_start = 0x47400000,
2930 .pa_end = 0x47400000 + SZ_4K - 1,
2931 .flags = ADDR_TYPE_RT
2932 },
2933 {
2934 .name = "musb0",
2935 .pa_start = 0x47401000,
2936 .pa_end = 0x47401000 + SZ_2K - 1,
2937 .flags = ADDR_TYPE_RT
2938 },
2939 {
2940 .name = "musb1",
2941 .pa_start = 0x47401800,
2942 .pa_end = 0x47401800 + SZ_2K - 1,
2943 .flags = ADDR_TYPE_RT
2944 },
2945 { }
2946 };
2948 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2949 .rev_offs = 0x0,
2950 .sysc_offs = 0x10,
2951 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
2952 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2953 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2954 .sysc_fields = &omap_hwmod_sysc_type2,
2955 };
2957 static struct omap_hwmod_class am33xx_usbotg_class = {
2958 .name = "usbotg",
2959 .sysc = &am33xx_usbhsotg_sysc,
2960 };
2962 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2963 { .name = "usbss-irq", .irq = 17, },
2964 { .name = "musb0-irq", .irq = 18, },
2965 { .name = "musb1-irq", .irq = 19, },
2966 { .irq = -1, },
2967 };
2969 static struct omap_hwmod_ocp_if am33xx_l3_slow__usbss = {
2970 .master = &am33xx_l3slow_hwmod,
2971 .slave = &am33xx_usbss_hwmod,
2972 .clk = "usbotg_ick",
2973 .addr = am33xx_usbss_addr_space,
2974 .user = OCP_USER_MPU,
2975 .flags = OCPIF_SWSUP_IDLE,
2976 };
2978 static struct omap_hwmod_ocp_if *am33xx_usbss_slaves[] = {
2979 &am33xx_l3_slow__usbss,
2980 };
2982 static struct omap_hwmod am33xx_usbss_hwmod = {
2983 .name = "usb_otg_hs",
2984 .class = &am33xx_usbotg_class,
2985 .clkdm_name = "l3s_clkdm",
2986 .mpu_irqs = am33xx_usbss_mpu_irqs,
2987 .main_clk = "usbotg_fck",
2988 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2989 .prcm = {
2990 .omap4 = {
2991 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2992 .modulemode = MODULEMODE_SWCTRL,
2993 },
2994 },
2995 .slaves = am33xx_usbss_slaves,
2996 .slaves_cnt = ARRAY_SIZE(am33xx_usbss_slaves),
2997 };
2999 /* gfx */
3000 /* Pseudo hwmod for reset control purpose only */
3001 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
3002 .name = "gfx",
3003 };
3005 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
3006 { .name = "gfx", .rst_shift = 0 },
3007 };
3009 static struct omap_hwmod am33xx_gfx_hwmod = {
3010 .name = "gfx",
3011 .class = &am33xx_gfx_hwmod_class,
3012 .clkdm_name = "gfx_l3_clkdm",
3013 .main_clk = "gfx_fclk",
3014 .prcm = {
3015 .omap4 = {
3016 .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
3017 .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
3018 .modulemode = MODULEMODE_SWCTRL,
3019 },
3020 },
3021 .rst_lines = am33xx_gfx_resets,
3022 .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
3023 };
3025 /* PRUSS */
3026 /* Pseudo hwmod for reset control purpose only */
3027 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
3028 .name = "pruss",
3029 };
3031 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
3032 { .name = "pruss", .rst_shift = 1 },
3033 };
3035 static struct omap_hwmod am33xx_pruss_hwmod = {
3036 .name = "pruss",
3037 .class = &am33xx_pruss_hwmod_class,
3038 .clkdm_name = "pruss_ocp_clkdm",
3039 .main_clk = "pruss_uart_gclk",
3040 .prcm = {
3041 .omap4 = {
3042 .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
3043 .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
3044 .modulemode = MODULEMODE_SWCTRL,
3045 },
3046 },
3047 .rst_lines = am33xx_pruss_resets,
3048 .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
3049 };
3051 static __initdata struct omap_hwmod *am33xx_hwmods[] = {
3052 /* l3 class */
3053 &am33xx_l3_instr_hwmod,
3054 &am33xx_l3_main_hwmod,
3055 /* l3s class */
3056 &am33xx_l3slow_hwmod,
3057 /* l4hs class */
3058 &am33xx_l4_hs_hwmod,
3059 /* l4fw class */
3060 &am33xx_l4fw_hwmod,
3061 /* l4ls class */
3062 &am33xx_l4ls_hwmod,
3063 /* l4per class */
3064 &am33xx_l4per_hwmod,
3065 /* l4wkup class */
3066 &am33xx_l4wkup_hwmod,
3067 /* clkdiv32k class */
3068 &am33xx_clkdiv32k_hwmod,
3069 /* mpu class */
3070 &am33xx_mpu_hwmod,
3071 /* adc_tsc class */
3072 &am33xx_adc_tsc_hwmod,
3073 /* aes class */
3074 &am33xx_aes0_hwmod,
3075 /* cefuse class */
3076 &am33xx_cefuse_hwmod,
3077 /* control class */
3078 &am33xx_control_hwmod,
3079 /* dcan class */
3080 &am33xx_dcan0_hwmod,
3081 &am33xx_dcan1_hwmod,
3082 /* debugss class */
3083 &am33xx_debugss_hwmod,
3084 /* elm class */
3085 &am33xx_elm_hwmod,
3086 /* emif_fw class */
3087 &am33xx_emif_fw_hwmod,
3088 /* epwmss class */
3089 &am33xx_epwmss0_hwmod,
3090 &am33xx_epwmss1_hwmod,
3091 &am33xx_epwmss2_hwmod,
3092 /* gpio class */
3093 &am33xx_gpio0_hwmod,
3094 &am33xx_gpio1_hwmod,
3095 &am33xx_gpio2_hwmod,
3096 &am33xx_gpio3_hwmod,
3097 /* gpmc class */
3098 &am33xx_gpmc_hwmod,
3099 /* i2c class */
3100 &am33xx_i2c1_hwmod,
3101 &am33xx_i2c2_hwmod,
3102 &am33xx_i2c3_hwmod,
3103 /* ieee5000 class */
3104 &am33xx_ieee5000_hwmod,
3105 /* mailbox class */
3106 &am33xx_mailbox_hwmod,
3107 /* mcasp class */
3108 &am33xx_mcasp0_hwmod,
3109 &am33xx_mcasp1_hwmod,
3110 /* mmc class */
3111 &am33xx_mmc0_hwmod,
3112 &am33xx_mmc1_hwmod,
3113 &am33xx_mmc2_hwmod,
3114 /* ocmcram class */
3115 &am33xx_ocmcram_hwmod,
3116 /* ocpwp class */
3117 &am33xx_ocpwp_hwmod,
3118 /* rtc class */
3119 &am33xx_rtc_hwmod,
3120 /* sha0 class */
3121 &am33xx_sha0_hwmod,
3122 /* smartreflex class */
3123 &am33xx_smartreflex0_hwmod,
3124 &am33xx_smartreflex1_hwmod,
3125 /* spi class */
3126 &am33xx_spi0_hwmod,
3127 &am33xx_spi1_hwmod,
3128 /* spinlock class */
3129 &am33xx_spinlock_hwmod,
3130 /* uart class */
3131 &am33xx_uart1_hwmod,
3132 &am33xx_uart2_hwmod,
3133 &am33xx_uart3_hwmod,
3134 &am33xx_uart4_hwmod,
3135 &am33xx_uart5_hwmod,
3136 &am33xx_uart6_hwmod,
3137 /* timer class */
3138 &am33xx_timer0_hwmod,
3139 &am33xx_timer1_hwmod,
3140 &am33xx_timer2_hwmod,
3141 &am33xx_timer3_hwmod,
3142 &am33xx_timer4_hwmod,
3143 &am33xx_timer5_hwmod,
3144 &am33xx_timer6_hwmod,
3145 &am33xx_timer7_hwmod,
3146 /* wkup_m3 class */
3147 &am33xx_wkup_m3_hwmod,
3148 /* wd_timer class */
3149 &am33xx_wd_timer1_hwmod,
3150 /* usbss hwmod */
3151 &am33xx_usbss_hwmod,
3152 /* cpgmac0 class */
3153 &am33xx_cpgmac0_hwmod,
3154 /* tptc class */
3155 &am33xx_tptc0_hwmod,
3156 &am33xx_tptc1_hwmod,
3157 &am33xx_tptc2_hwmod,
3158 /* tpcc class */
3159 &am33xx_tpcc_hwmod,
3160 /* LCDC class */
3161 &am33xx_lcdc_hwmod,
3162 /* gfx/sgx */
3163 &am33xx_gfx_hwmod,
3164 /* pruss */
3165 &am33xx_pruss_hwmod,
3166 NULL,
3167 };
3169 int __init am33xx_hwmod_init(void)
3170 {
3171 return omap_hwmod_register(am33xx_hwmods);
3172 }