1 /*
2 * Hardware modules present on the OMAP44xx chips
3 *
4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
21 #include <linux/io.h>
23 #include <plat/omap_hwmod.h>
24 #include <plat/cpu.h>
25 #include <plat/i2c.h>
26 #include <plat/gpio.h>
27 #include <plat/dma.h>
28 #include <plat/mcspi.h>
29 #include <plat/mcbsp.h>
30 #include <plat/mmc.h>
31 #include <plat/i2c.h>
32 #include <plat/dmtimer.h>
33 #include <plat/common.h>
35 #include "omap_hwmod_common_data.h"
37 #include "cm1_44xx.h"
38 #include "cm2_44xx.h"
39 #include "prm44xx.h"
40 #include "prm-regbits-44xx.h"
41 #include "wd_timer.h"
43 /* Base offset for all OMAP4 interrupts external to MPUSS */
44 #define OMAP44XX_IRQ_GIC_START 32
46 /* Base offset for all OMAP4 dma requests */
47 #define OMAP44XX_DMA_REQ_START 1
49 /* Backward references (IPs with Bus Master capability) */
50 static struct omap_hwmod omap44xx_aess_hwmod;
51 static struct omap_hwmod omap44xx_dma_system_hwmod;
52 static struct omap_hwmod omap44xx_dmm_hwmod;
53 static struct omap_hwmod omap44xx_dsp_hwmod;
54 static struct omap_hwmod omap44xx_dss_hwmod;
55 static struct omap_hwmod omap44xx_emif_fw_hwmod;
56 static struct omap_hwmod omap44xx_fdif_hwmod;
57 static struct omap_hwmod omap44xx_hsi_hwmod;
58 static struct omap_hwmod omap44xx_ipu_hwmod;
59 static struct omap_hwmod omap44xx_iss_hwmod;
60 static struct omap_hwmod omap44xx_iva_hwmod;
61 static struct omap_hwmod omap44xx_l3_instr_hwmod;
62 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
63 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
64 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
65 static struct omap_hwmod omap44xx_l4_abe_hwmod;
66 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
67 static struct omap_hwmod omap44xx_l4_per_hwmod;
68 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
69 static struct omap_hwmod omap44xx_mmc1_hwmod;
70 static struct omap_hwmod omap44xx_mmc2_hwmod;
71 static struct omap_hwmod omap44xx_mpu_hwmod;
72 static struct omap_hwmod omap44xx_mpu_private_hwmod;
73 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
74 static struct omap_hwmod omap44xx_usb_host_hs_hwmod;
75 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod;
77 /*
78 * Interconnects omap_hwmod structures
79 * hwmods that compose the global OMAP interconnect
80 */
82 /*
83 * 'dmm' class
84 * instance(s): dmm
85 */
86 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
87 .name = "dmm",
88 };
90 /* dmm */
91 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
92 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
93 { .irq = -1 }
94 };
96 /* l3_main_1 -> dmm */
97 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
98 .master = &omap44xx_l3_main_1_hwmod,
99 .slave = &omap44xx_dmm_hwmod,
100 .clk = "l3_div_ck",
101 .user = OCP_USER_SDMA,
102 };
104 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
105 {
106 .pa_start = 0x4e000000,
107 .pa_end = 0x4e0007ff,
108 .flags = ADDR_TYPE_RT
109 },
110 { }
111 };
113 /* mpu -> dmm */
114 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
115 .master = &omap44xx_mpu_hwmod,
116 .slave = &omap44xx_dmm_hwmod,
117 .clk = "l3_div_ck",
118 .addr = omap44xx_dmm_addrs,
119 .user = OCP_USER_MPU,
120 };
122 /* dmm slave ports */
123 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
124 &omap44xx_l3_main_1__dmm,
125 &omap44xx_mpu__dmm,
126 };
128 static struct omap_hwmod omap44xx_dmm_hwmod = {
129 .name = "dmm",
130 .class = &omap44xx_dmm_hwmod_class,
131 .clkdm_name = "l3_emif_clkdm",
132 .prcm = {
133 .omap4 = {
134 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
135 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
136 },
137 },
138 .slaves = omap44xx_dmm_slaves,
139 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
140 .mpu_irqs = omap44xx_dmm_irqs,
141 };
143 /*
144 * 'emif_fw' class
145 * instance(s): emif_fw
146 */
147 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
148 .name = "emif_fw",
149 };
151 /* emif_fw */
152 /* dmm -> emif_fw */
153 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
154 .master = &omap44xx_dmm_hwmod,
155 .slave = &omap44xx_emif_fw_hwmod,
156 .clk = "l3_div_ck",
157 .user = OCP_USER_MPU | OCP_USER_SDMA,
158 };
160 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
161 {
162 .pa_start = 0x4a20c000,
163 .pa_end = 0x4a20c0ff,
164 .flags = ADDR_TYPE_RT
165 },
166 { }
167 };
169 /* l4_cfg -> emif_fw */
170 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
171 .master = &omap44xx_l4_cfg_hwmod,
172 .slave = &omap44xx_emif_fw_hwmod,
173 .clk = "l4_div_ck",
174 .addr = omap44xx_emif_fw_addrs,
175 .user = OCP_USER_MPU,
176 };
178 /* emif_fw slave ports */
179 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
180 &omap44xx_dmm__emif_fw,
181 &omap44xx_l4_cfg__emif_fw,
182 };
184 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
185 .name = "emif_fw",
186 .class = &omap44xx_emif_fw_hwmod_class,
187 .clkdm_name = "l3_emif_clkdm",
188 .prcm = {
189 .omap4 = {
190 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
191 .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
192 },
193 },
194 .slaves = omap44xx_emif_fw_slaves,
195 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
196 };
198 /*
199 * 'l3' class
200 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
201 */
202 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
203 .name = "l3",
204 };
206 /* l3_instr */
207 /* iva -> l3_instr */
208 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
209 .master = &omap44xx_iva_hwmod,
210 .slave = &omap44xx_l3_instr_hwmod,
211 .clk = "l3_div_ck",
212 .user = OCP_USER_MPU | OCP_USER_SDMA,
213 };
215 /* l3_main_3 -> l3_instr */
216 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
217 .master = &omap44xx_l3_main_3_hwmod,
218 .slave = &omap44xx_l3_instr_hwmod,
219 .clk = "l3_div_ck",
220 .user = OCP_USER_MPU | OCP_USER_SDMA,
221 };
223 /* l3_instr slave ports */
224 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
225 &omap44xx_iva__l3_instr,
226 &omap44xx_l3_main_3__l3_instr,
227 };
229 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
230 .name = "l3_instr",
231 .class = &omap44xx_l3_hwmod_class,
232 .clkdm_name = "l3_instr_clkdm",
233 .prcm = {
234 .omap4 = {
235 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
236 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
237 .modulemode = MODULEMODE_HWCTRL,
238 },
239 },
240 .slaves = omap44xx_l3_instr_slaves,
241 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
242 };
244 /* l3_main_1 */
245 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
246 { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
247 { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
248 { .irq = -1 }
249 };
251 /* dsp -> l3_main_1 */
252 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
253 .master = &omap44xx_dsp_hwmod,
254 .slave = &omap44xx_l3_main_1_hwmod,
255 .clk = "l3_div_ck",
256 .user = OCP_USER_MPU | OCP_USER_SDMA,
257 };
259 /* dss -> l3_main_1 */
260 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
261 .master = &omap44xx_dss_hwmod,
262 .slave = &omap44xx_l3_main_1_hwmod,
263 .clk = "l3_div_ck",
264 .user = OCP_USER_MPU | OCP_USER_SDMA,
265 };
267 /* l3_main_2 -> l3_main_1 */
268 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
269 .master = &omap44xx_l3_main_2_hwmod,
270 .slave = &omap44xx_l3_main_1_hwmod,
271 .clk = "l3_div_ck",
272 .user = OCP_USER_MPU | OCP_USER_SDMA,
273 };
275 /* l4_cfg -> l3_main_1 */
276 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
277 .master = &omap44xx_l4_cfg_hwmod,
278 .slave = &omap44xx_l3_main_1_hwmod,
279 .clk = "l4_div_ck",
280 .user = OCP_USER_MPU | OCP_USER_SDMA,
281 };
283 /* mmc1 -> l3_main_1 */
284 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
285 .master = &omap44xx_mmc1_hwmod,
286 .slave = &omap44xx_l3_main_1_hwmod,
287 .clk = "l3_div_ck",
288 .user = OCP_USER_MPU | OCP_USER_SDMA,
289 };
291 /* mmc2 -> l3_main_1 */
292 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
293 .master = &omap44xx_mmc2_hwmod,
294 .slave = &omap44xx_l3_main_1_hwmod,
295 .clk = "l3_div_ck",
296 .user = OCP_USER_MPU | OCP_USER_SDMA,
297 };
299 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
300 {
301 .pa_start = 0x44000000,
302 .pa_end = 0x44000fff,
303 .flags = ADDR_TYPE_RT
304 },
305 { }
306 };
308 /* mpu -> l3_main_1 */
309 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
310 .master = &omap44xx_mpu_hwmod,
311 .slave = &omap44xx_l3_main_1_hwmod,
312 .clk = "l3_div_ck",
313 .addr = omap44xx_l3_main_1_addrs,
314 .user = OCP_USER_MPU,
315 };
317 /* l3_main_1 slave ports */
318 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
319 &omap44xx_dsp__l3_main_1,
320 &omap44xx_dss__l3_main_1,
321 &omap44xx_l3_main_2__l3_main_1,
322 &omap44xx_l4_cfg__l3_main_1,
323 &omap44xx_mmc1__l3_main_1,
324 &omap44xx_mmc2__l3_main_1,
325 &omap44xx_mpu__l3_main_1,
326 };
328 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
329 .name = "l3_main_1",
330 .class = &omap44xx_l3_hwmod_class,
331 .clkdm_name = "l3_1_clkdm",
332 .mpu_irqs = omap44xx_l3_main_1_irqs,
333 .prcm = {
334 .omap4 = {
335 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
336 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
337 },
338 },
339 .slaves = omap44xx_l3_main_1_slaves,
340 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
341 };
343 /* l3_main_2 */
344 /* dma_system -> l3_main_2 */
345 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
346 .master = &omap44xx_dma_system_hwmod,
347 .slave = &omap44xx_l3_main_2_hwmod,
348 .clk = "l3_div_ck",
349 .user = OCP_USER_MPU | OCP_USER_SDMA,
350 };
352 /* fdif -> l3_main_2 */
353 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
354 .master = &omap44xx_fdif_hwmod,
355 .slave = &omap44xx_l3_main_2_hwmod,
356 .clk = "l3_div_ck",
357 .user = OCP_USER_MPU | OCP_USER_SDMA,
358 };
360 /* hsi -> l3_main_2 */
361 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
362 .master = &omap44xx_hsi_hwmod,
363 .slave = &omap44xx_l3_main_2_hwmod,
364 .clk = "l3_div_ck",
365 .user = OCP_USER_MPU | OCP_USER_SDMA,
366 };
368 /* ipu -> l3_main_2 */
369 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
370 .master = &omap44xx_ipu_hwmod,
371 .slave = &omap44xx_l3_main_2_hwmod,
372 .clk = "l3_div_ck",
373 .user = OCP_USER_MPU | OCP_USER_SDMA,
374 };
376 /* iss -> l3_main_2 */
377 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
378 .master = &omap44xx_iss_hwmod,
379 .slave = &omap44xx_l3_main_2_hwmod,
380 .clk = "l3_div_ck",
381 .user = OCP_USER_MPU | OCP_USER_SDMA,
382 };
384 /* iva -> l3_main_2 */
385 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
386 .master = &omap44xx_iva_hwmod,
387 .slave = &omap44xx_l3_main_2_hwmod,
388 .clk = "l3_div_ck",
389 .user = OCP_USER_MPU | OCP_USER_SDMA,
390 };
392 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
393 {
394 .pa_start = 0x44800000,
395 .pa_end = 0x44801fff,
396 .flags = ADDR_TYPE_RT
397 },
398 { }
399 };
401 /* l3_main_1 -> l3_main_2 */
402 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
403 .master = &omap44xx_l3_main_1_hwmod,
404 .slave = &omap44xx_l3_main_2_hwmod,
405 .clk = "l3_div_ck",
406 .addr = omap44xx_l3_main_2_addrs,
407 .user = OCP_USER_MPU,
408 };
410 /* l4_cfg -> l3_main_2 */
411 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
412 .master = &omap44xx_l4_cfg_hwmod,
413 .slave = &omap44xx_l3_main_2_hwmod,
414 .clk = "l4_div_ck",
415 .user = OCP_USER_MPU | OCP_USER_SDMA,
416 };
418 /* usb_otg_hs -> l3_main_2 */
419 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
420 .master = &omap44xx_usb_otg_hs_hwmod,
421 .slave = &omap44xx_l3_main_2_hwmod,
422 .clk = "l3_div_ck",
423 .user = OCP_USER_MPU | OCP_USER_SDMA,
424 };
426 /* l3_main_2 slave ports */
427 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
428 &omap44xx_dma_system__l3_main_2,
429 &omap44xx_fdif__l3_main_2,
430 &omap44xx_hsi__l3_main_2,
431 &omap44xx_ipu__l3_main_2,
432 &omap44xx_iss__l3_main_2,
433 &omap44xx_iva__l3_main_2,
434 &omap44xx_l3_main_1__l3_main_2,
435 &omap44xx_l4_cfg__l3_main_2,
436 &omap44xx_usb_otg_hs__l3_main_2,
437 };
439 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
440 .name = "l3_main_2",
441 .class = &omap44xx_l3_hwmod_class,
442 .clkdm_name = "l3_2_clkdm",
443 .prcm = {
444 .omap4 = {
445 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
446 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
447 },
448 },
449 .slaves = omap44xx_l3_main_2_slaves,
450 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
451 };
453 /* l3_main_3 */
454 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
455 {
456 .pa_start = 0x45000000,
457 .pa_end = 0x45000fff,
458 .flags = ADDR_TYPE_RT
459 },
460 { }
461 };
463 /* l3_main_1 -> l3_main_3 */
464 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
465 .master = &omap44xx_l3_main_1_hwmod,
466 .slave = &omap44xx_l3_main_3_hwmod,
467 .clk = "l3_div_ck",
468 .addr = omap44xx_l3_main_3_addrs,
469 .user = OCP_USER_MPU,
470 };
472 /* l3_main_2 -> l3_main_3 */
473 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
474 .master = &omap44xx_l3_main_2_hwmod,
475 .slave = &omap44xx_l3_main_3_hwmod,
476 .clk = "l3_div_ck",
477 .user = OCP_USER_MPU | OCP_USER_SDMA,
478 };
480 /* l4_cfg -> l3_main_3 */
481 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
482 .master = &omap44xx_l4_cfg_hwmod,
483 .slave = &omap44xx_l3_main_3_hwmod,
484 .clk = "l4_div_ck",
485 .user = OCP_USER_MPU | OCP_USER_SDMA,
486 };
488 /* l3_main_3 slave ports */
489 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
490 &omap44xx_l3_main_1__l3_main_3,
491 &omap44xx_l3_main_2__l3_main_3,
492 &omap44xx_l4_cfg__l3_main_3,
493 };
495 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
496 .name = "l3_main_3",
497 .class = &omap44xx_l3_hwmod_class,
498 .clkdm_name = "l3_instr_clkdm",
499 .prcm = {
500 .omap4 = {
501 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
502 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
503 .modulemode = MODULEMODE_HWCTRL,
504 },
505 },
506 .slaves = omap44xx_l3_main_3_slaves,
507 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
508 };
510 /*
511 * 'l4' class
512 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
513 */
514 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
515 .name = "l4",
516 };
518 /* l4_abe */
519 /* aess -> l4_abe */
520 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
521 .master = &omap44xx_aess_hwmod,
522 .slave = &omap44xx_l4_abe_hwmod,
523 .clk = "ocp_abe_iclk",
524 .user = OCP_USER_MPU | OCP_USER_SDMA,
525 };
527 /* dsp -> l4_abe */
528 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
529 .master = &omap44xx_dsp_hwmod,
530 .slave = &omap44xx_l4_abe_hwmod,
531 .clk = "ocp_abe_iclk",
532 .user = OCP_USER_MPU | OCP_USER_SDMA,
533 };
535 /* l3_main_1 -> l4_abe */
536 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
537 .master = &omap44xx_l3_main_1_hwmod,
538 .slave = &omap44xx_l4_abe_hwmod,
539 .clk = "l3_div_ck",
540 .user = OCP_USER_MPU | OCP_USER_SDMA,
541 };
543 /* mpu -> l4_abe */
544 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
545 .master = &omap44xx_mpu_hwmod,
546 .slave = &omap44xx_l4_abe_hwmod,
547 .clk = "ocp_abe_iclk",
548 .user = OCP_USER_MPU | OCP_USER_SDMA,
549 };
551 /* l4_abe slave ports */
552 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
553 &omap44xx_aess__l4_abe,
554 &omap44xx_dsp__l4_abe,
555 &omap44xx_l3_main_1__l4_abe,
556 &omap44xx_mpu__l4_abe,
557 };
559 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
560 .name = "l4_abe",
561 .class = &omap44xx_l4_hwmod_class,
562 .clkdm_name = "abe_clkdm",
563 .prcm = {
564 .omap4 = {
565 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
566 },
567 },
568 .slaves = omap44xx_l4_abe_slaves,
569 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
570 };
572 /* l4_cfg */
573 /* l3_main_1 -> l4_cfg */
574 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
575 .master = &omap44xx_l3_main_1_hwmod,
576 .slave = &omap44xx_l4_cfg_hwmod,
577 .clk = "l3_div_ck",
578 .user = OCP_USER_MPU | OCP_USER_SDMA,
579 };
581 /* l4_cfg slave ports */
582 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
583 &omap44xx_l3_main_1__l4_cfg,
584 };
586 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
587 .name = "l4_cfg",
588 .class = &omap44xx_l4_hwmod_class,
589 .clkdm_name = "l4_cfg_clkdm",
590 .prcm = {
591 .omap4 = {
592 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
593 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
594 },
595 },
596 .slaves = omap44xx_l4_cfg_slaves,
597 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
598 };
600 /* l4_per */
601 /* l3_main_2 -> l4_per */
602 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
603 .master = &omap44xx_l3_main_2_hwmod,
604 .slave = &omap44xx_l4_per_hwmod,
605 .clk = "l3_div_ck",
606 .user = OCP_USER_MPU | OCP_USER_SDMA,
607 };
609 /* l4_per slave ports */
610 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
611 &omap44xx_l3_main_2__l4_per,
612 };
614 static struct omap_hwmod omap44xx_l4_per_hwmod = {
615 .name = "l4_per",
616 .class = &omap44xx_l4_hwmod_class,
617 .clkdm_name = "l4_per_clkdm",
618 .prcm = {
619 .omap4 = {
620 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
621 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
622 },
623 },
624 .slaves = omap44xx_l4_per_slaves,
625 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
626 };
628 /* l4_wkup */
629 /* l4_cfg -> l4_wkup */
630 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
631 .master = &omap44xx_l4_cfg_hwmod,
632 .slave = &omap44xx_l4_wkup_hwmod,
633 .clk = "l4_div_ck",
634 .user = OCP_USER_MPU | OCP_USER_SDMA,
635 };
637 /* l4_wkup slave ports */
638 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
639 &omap44xx_l4_cfg__l4_wkup,
640 };
642 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
643 .name = "l4_wkup",
644 .class = &omap44xx_l4_hwmod_class,
645 .clkdm_name = "l4_wkup_clkdm",
646 .prcm = {
647 .omap4 = {
648 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
649 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
650 },
651 },
652 .slaves = omap44xx_l4_wkup_slaves,
653 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
654 };
656 /*
657 * 'mpu_bus' class
658 * instance(s): mpu_private
659 */
660 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
661 .name = "mpu_bus",
662 };
664 /* mpu_private */
665 /* mpu -> mpu_private */
666 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
667 .master = &omap44xx_mpu_hwmod,
668 .slave = &omap44xx_mpu_private_hwmod,
669 .clk = "l3_div_ck",
670 .user = OCP_USER_MPU | OCP_USER_SDMA,
671 };
673 /* mpu_private slave ports */
674 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
675 &omap44xx_mpu__mpu_private,
676 };
678 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
679 .name = "mpu_private",
680 .class = &omap44xx_mpu_bus_hwmod_class,
681 .clkdm_name = "mpuss_clkdm",
682 .slaves = omap44xx_mpu_private_slaves,
683 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
684 };
686 /*
687 * Modules omap_hwmod structures
688 *
689 * The following IPs are excluded for the moment because:
690 * - They do not need an explicit SW control using omap_hwmod API.
691 * - They still need to be validated with the driver
692 * properly adapted to omap_hwmod / omap_device
693 *
694 * c2c
695 * c2c_target_fw
696 * cm_core
697 * cm_core_aon
698 * ctrl_module_core
699 * ctrl_module_pad_core
700 * ctrl_module_pad_wkup
701 * ctrl_module_wkup
702 * debugss
703 * efuse_ctrl_cust
704 * efuse_ctrl_std
705 * elm
706 * emif1
707 * emif2
708 * fdif
709 * gpmc
710 * gpu
711 * hdq1w
712 * mcasp
713 * mpu_c0
714 * mpu_c1
715 * ocmc_ram
716 * ocp2scp_usb_phy
717 * ocp_wp_noc
718 * prcm_mpu
719 * prm
720 * scrm
721 * sl2if
722 * slimbus1
723 * slimbus2
724 * usb_host_fs
725 * usb_host_hs
726 * usb_phy_cm
727 * usb_tll_hs
728 * usim
729 */
731 /*
732 * 'aess' class
733 * audio engine sub system
734 */
736 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
737 .rev_offs = 0x0000,
738 .sysc_offs = 0x0010,
739 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
740 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
741 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
742 MSTANDBY_SMART_WKUP),
743 .sysc_fields = &omap_hwmod_sysc_type2,
744 };
746 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
747 .name = "aess",
748 .sysc = &omap44xx_aess_sysc,
749 };
751 /* aess */
752 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
753 { .irq = 99 + OMAP44XX_IRQ_GIC_START },
754 { .irq = -1 }
755 };
757 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
758 { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
759 { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
760 { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
761 { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
762 { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
763 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
764 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
765 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
766 { .dma_req = -1 }
767 };
769 /* aess master ports */
770 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
771 &omap44xx_aess__l4_abe,
772 };
774 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
775 {
776 .pa_start = 0x401f1000,
777 .pa_end = 0x401f13ff,
778 .flags = ADDR_TYPE_RT
779 },
780 { }
781 };
783 /* l4_abe -> aess */
784 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
785 .master = &omap44xx_l4_abe_hwmod,
786 .slave = &omap44xx_aess_hwmod,
787 .clk = "ocp_abe_iclk",
788 .addr = omap44xx_aess_addrs,
789 .user = OCP_USER_MPU,
790 };
792 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
793 {
794 .pa_start = 0x490f1000,
795 .pa_end = 0x490f13ff,
796 .flags = ADDR_TYPE_RT
797 },
798 { }
799 };
801 /* l4_abe -> aess (dma) */
802 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
803 .master = &omap44xx_l4_abe_hwmod,
804 .slave = &omap44xx_aess_hwmod,
805 .clk = "ocp_abe_iclk",
806 .addr = omap44xx_aess_dma_addrs,
807 .user = OCP_USER_SDMA,
808 };
810 /* aess slave ports */
811 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
812 &omap44xx_l4_abe__aess,
813 &omap44xx_l4_abe__aess_dma,
814 };
816 static struct omap_hwmod omap44xx_aess_hwmod = {
817 .name = "aess",
818 .class = &omap44xx_aess_hwmod_class,
819 .clkdm_name = "abe_clkdm",
820 .mpu_irqs = omap44xx_aess_irqs,
821 .sdma_reqs = omap44xx_aess_sdma_reqs,
822 .main_clk = "aess_fck",
823 .prcm = {
824 .omap4 = {
825 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
826 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
827 .modulemode = MODULEMODE_SWCTRL,
828 },
829 },
830 .slaves = omap44xx_aess_slaves,
831 .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves),
832 .masters = omap44xx_aess_masters,
833 .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters),
834 };
836 /*
837 * 'bandgap' class
838 * bangap reference for ldo regulators
839 */
841 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
842 .name = "bandgap",
843 };
845 /* bandgap */
846 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
847 { .role = "fclk", .clk = "bandgap_fclk" },
848 };
850 static struct omap_hwmod omap44xx_bandgap_hwmod = {
851 .name = "bandgap",
852 .class = &omap44xx_bandgap_hwmod_class,
853 .clkdm_name = "l4_wkup_clkdm",
854 .prcm = {
855 .omap4 = {
856 .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
857 },
858 },
859 .opt_clks = bandgap_opt_clks,
860 .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks),
861 };
863 /*
864 * 'counter' class
865 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
866 */
868 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
869 .rev_offs = 0x0000,
870 .sysc_offs = 0x0004,
871 .sysc_flags = SYSC_HAS_SIDLEMODE,
872 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
873 SIDLE_SMART_WKUP),
874 .sysc_fields = &omap_hwmod_sysc_type1,
875 };
877 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
878 .name = "counter",
879 .sysc = &omap44xx_counter_sysc,
880 };
882 /* counter_32k */
883 static struct omap_hwmod omap44xx_counter_32k_hwmod;
884 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
885 {
886 .pa_start = 0x4a304000,
887 .pa_end = 0x4a30401f,
888 .flags = ADDR_TYPE_RT
889 },
890 { }
891 };
893 /* l4_wkup -> counter_32k */
894 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
895 .master = &omap44xx_l4_wkup_hwmod,
896 .slave = &omap44xx_counter_32k_hwmod,
897 .clk = "l4_wkup_clk_mux_ck",
898 .addr = omap44xx_counter_32k_addrs,
899 .user = OCP_USER_MPU | OCP_USER_SDMA,
900 };
902 /* counter_32k slave ports */
903 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
904 &omap44xx_l4_wkup__counter_32k,
905 };
907 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
908 .name = "counter_32k",
909 .class = &omap44xx_counter_hwmod_class,
910 .clkdm_name = "l4_wkup_clkdm",
911 .flags = HWMOD_SWSUP_SIDLE,
912 .main_clk = "sys_32k_ck",
913 .prcm = {
914 .omap4 = {
915 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
916 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
917 },
918 },
919 .slaves = omap44xx_counter_32k_slaves,
920 .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves),
921 };
923 /*
924 * 'dma' class
925 * dma controller for data exchange between memory to memory (i.e. internal or
926 * external memory) and gp peripherals to memory or memory to gp peripherals
927 */
929 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
930 .rev_offs = 0x0000,
931 .sysc_offs = 0x002c,
932 .syss_offs = 0x0028,
933 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
934 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
935 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
936 SYSS_HAS_RESET_STATUS),
937 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
938 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
939 .sysc_fields = &omap_hwmod_sysc_type1,
940 };
942 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
943 .name = "dma",
944 .sysc = &omap44xx_dma_sysc,
945 };
947 /* dma dev_attr */
948 static struct omap_dma_dev_attr dma_dev_attr = {
949 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
950 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
951 .lch_count = 32,
952 };
954 /* dma_system */
955 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
956 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
957 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
958 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
959 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
960 { .irq = -1 }
961 };
963 /* dma_system master ports */
964 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
965 &omap44xx_dma_system__l3_main_2,
966 };
968 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
969 {
970 .pa_start = 0x4a056000,
971 .pa_end = 0x4a056fff,
972 .flags = ADDR_TYPE_RT
973 },
974 { }
975 };
977 /* l4_cfg -> dma_system */
978 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
979 .master = &omap44xx_l4_cfg_hwmod,
980 .slave = &omap44xx_dma_system_hwmod,
981 .clk = "l4_div_ck",
982 .addr = omap44xx_dma_system_addrs,
983 .user = OCP_USER_MPU | OCP_USER_SDMA,
984 };
986 /* dma_system slave ports */
987 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
988 &omap44xx_l4_cfg__dma_system,
989 };
991 static struct omap_hwmod omap44xx_dma_system_hwmod = {
992 .name = "dma_system",
993 .class = &omap44xx_dma_hwmod_class,
994 .clkdm_name = "l3_dma_clkdm",
995 .mpu_irqs = omap44xx_dma_system_irqs,
996 .main_clk = "l3_div_ck",
997 .prcm = {
998 .omap4 = {
999 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
1000 .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
1001 },
1002 },
1003 .dev_attr = &dma_dev_attr,
1004 .slaves = omap44xx_dma_system_slaves,
1005 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
1006 .masters = omap44xx_dma_system_masters,
1007 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
1008 };
1010 /*
1011 * 'dmic' class
1012 * digital microphone controller
1013 */
1015 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
1016 .rev_offs = 0x0000,
1017 .sysc_offs = 0x0010,
1018 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1019 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1020 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1021 SIDLE_SMART_WKUP),
1022 .sysc_fields = &omap_hwmod_sysc_type2,
1023 };
1025 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
1026 .name = "dmic",
1027 .sysc = &omap44xx_dmic_sysc,
1028 };
1030 /* dmic */
1031 static struct omap_hwmod omap44xx_dmic_hwmod;
1032 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
1033 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
1034 { .irq = -1 }
1035 };
1037 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
1038 { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
1039 { .dma_req = -1 }
1040 };
1042 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
1043 {
1044 .name = "mpu",
1045 .pa_start = 0x4012e000,
1046 .pa_end = 0x4012e07f,
1047 .flags = ADDR_TYPE_RT
1048 },
1049 { }
1050 };
1052 /* l4_abe -> dmic */
1053 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
1054 .master = &omap44xx_l4_abe_hwmod,
1055 .slave = &omap44xx_dmic_hwmod,
1056 .clk = "ocp_abe_iclk",
1057 .addr = omap44xx_dmic_addrs,
1058 .user = OCP_USER_MPU,
1059 };
1061 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
1062 {
1063 .name = "dma",
1064 .pa_start = 0x4902e000,
1065 .pa_end = 0x4902e07f,
1066 .flags = ADDR_TYPE_RT
1067 },
1068 { }
1069 };
1071 /* l4_abe -> dmic (dma) */
1072 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
1073 .master = &omap44xx_l4_abe_hwmod,
1074 .slave = &omap44xx_dmic_hwmod,
1075 .clk = "ocp_abe_iclk",
1076 .addr = omap44xx_dmic_dma_addrs,
1077 .user = OCP_USER_SDMA,
1078 };
1080 /* dmic slave ports */
1081 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
1082 &omap44xx_l4_abe__dmic,
1083 &omap44xx_l4_abe__dmic_dma,
1084 };
1086 static struct omap_hwmod omap44xx_dmic_hwmod = {
1087 .name = "dmic",
1088 .class = &omap44xx_dmic_hwmod_class,
1089 .clkdm_name = "abe_clkdm",
1090 .mpu_irqs = omap44xx_dmic_irqs,
1091 .sdma_reqs = omap44xx_dmic_sdma_reqs,
1092 .main_clk = "dmic_fck",
1093 .prcm = {
1094 .omap4 = {
1095 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
1096 .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
1097 .modulemode = MODULEMODE_SWCTRL,
1098 },
1099 },
1100 .slaves = omap44xx_dmic_slaves,
1101 .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves),
1102 };
1104 /*
1105 * 'dsp' class
1106 * dsp sub-system
1107 */
1109 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1110 .name = "dsp",
1111 };
1113 /* dsp */
1114 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1115 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1116 { .irq = -1 }
1117 };
1119 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1120 { .name = "mmu_cache", .rst_shift = 1 },
1121 };
1123 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1124 { .name = "dsp", .rst_shift = 0 },
1125 };
1127 /* dsp -> iva */
1128 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1129 .master = &omap44xx_dsp_hwmod,
1130 .slave = &omap44xx_iva_hwmod,
1131 .clk = "dpll_iva_m5x2_ck",
1132 };
1134 /* dsp master ports */
1135 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1136 &omap44xx_dsp__l3_main_1,
1137 &omap44xx_dsp__l4_abe,
1138 &omap44xx_dsp__iva,
1139 };
1141 /* l4_cfg -> dsp */
1142 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1143 .master = &omap44xx_l4_cfg_hwmod,
1144 .slave = &omap44xx_dsp_hwmod,
1145 .clk = "l4_div_ck",
1146 .user = OCP_USER_MPU | OCP_USER_SDMA,
1147 };
1149 /* dsp slave ports */
1150 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1151 &omap44xx_l4_cfg__dsp,
1152 };
1154 /* Pseudo hwmod for reset control purpose only */
1155 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1156 .name = "dsp_c0",
1157 .class = &omap44xx_dsp_hwmod_class,
1158 .clkdm_name = "tesla_clkdm",
1159 .flags = HWMOD_INIT_NO_RESET,
1160 .rst_lines = omap44xx_dsp_c0_resets,
1161 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1162 .prcm = {
1163 .omap4 = {
1164 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1165 },
1166 },
1167 };
1169 static struct omap_hwmod omap44xx_dsp_hwmod = {
1170 .name = "dsp",
1171 .class = &omap44xx_dsp_hwmod_class,
1172 .clkdm_name = "tesla_clkdm",
1173 .mpu_irqs = omap44xx_dsp_irqs,
1174 .rst_lines = omap44xx_dsp_resets,
1175 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
1176 .main_clk = "dsp_fck",
1177 .prcm = {
1178 .omap4 = {
1179 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
1180 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1181 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
1182 .modulemode = MODULEMODE_HWCTRL,
1183 },
1184 },
1185 .slaves = omap44xx_dsp_slaves,
1186 .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
1187 .masters = omap44xx_dsp_masters,
1188 .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
1189 };
1191 /*
1192 * 'dss' class
1193 * display sub-system
1194 */
1196 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1197 .rev_offs = 0x0000,
1198 .syss_offs = 0x0014,
1199 .sysc_flags = SYSS_HAS_RESET_STATUS,
1200 };
1202 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1203 .name = "dss",
1204 .sysc = &omap44xx_dss_sysc,
1205 .reset = omap_dss_reset,
1206 };
1208 /* dss */
1209 /* dss master ports */
1210 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1211 &omap44xx_dss__l3_main_1,
1212 };
1214 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1215 {
1216 .pa_start = 0x58000000,
1217 .pa_end = 0x5800007f,
1218 .flags = ADDR_TYPE_RT
1219 },
1220 { }
1221 };
1223 /* l3_main_2 -> dss */
1224 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1225 .master = &omap44xx_l3_main_2_hwmod,
1226 .slave = &omap44xx_dss_hwmod,
1227 .clk = "dss_fck",
1228 .addr = omap44xx_dss_dma_addrs,
1229 .user = OCP_USER_SDMA,
1230 };
1232 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1233 {
1234 .pa_start = 0x48040000,
1235 .pa_end = 0x4804007f,
1236 .flags = ADDR_TYPE_RT
1237 },
1238 { }
1239 };
1241 /* l4_per -> dss */
1242 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1243 .master = &omap44xx_l4_per_hwmod,
1244 .slave = &omap44xx_dss_hwmod,
1245 .clk = "l4_div_ck",
1246 .addr = omap44xx_dss_addrs,
1247 .user = OCP_USER_MPU,
1248 };
1250 /* dss slave ports */
1251 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1252 &omap44xx_l3_main_2__dss,
1253 &omap44xx_l4_per__dss,
1254 };
1256 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1257 { .role = "sys_clk", .clk = "dss_sys_clk" },
1258 { .role = "tv_clk", .clk = "dss_tv_clk" },
1259 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1260 };
1262 static struct omap_hwmod omap44xx_dss_hwmod = {
1263 .name = "dss_core",
1264 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1265 .class = &omap44xx_dss_hwmod_class,
1266 .clkdm_name = "l3_dss_clkdm",
1267 .main_clk = "dss_dss_clk",
1268 .prcm = {
1269 .omap4 = {
1270 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1271 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1272 },
1273 },
1274 .opt_clks = dss_opt_clks,
1275 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1276 .slaves = omap44xx_dss_slaves,
1277 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
1278 .masters = omap44xx_dss_masters,
1279 .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
1280 };
1282 /*
1283 * 'dispc' class
1284 * display controller
1285 */
1287 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1288 .rev_offs = 0x0000,
1289 .sysc_offs = 0x0010,
1290 .syss_offs = 0x0014,
1291 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1292 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1293 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1294 SYSS_HAS_RESET_STATUS),
1295 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1296 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1297 .sysc_fields = &omap_hwmod_sysc_type1,
1298 };
1300 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1301 .name = "dispc",
1302 .sysc = &omap44xx_dispc_sysc,
1303 };
1305 /* dss_dispc */
1306 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1307 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1308 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1309 { .irq = -1 }
1310 };
1312 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1313 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1314 { .dma_req = -1 }
1315 };
1317 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1318 {
1319 .pa_start = 0x58001000,
1320 .pa_end = 0x58001fff,
1321 .flags = ADDR_TYPE_RT
1322 },
1323 { }
1324 };
1326 /* l3_main_2 -> dss_dispc */
1327 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1328 .master = &omap44xx_l3_main_2_hwmod,
1329 .slave = &omap44xx_dss_dispc_hwmod,
1330 .clk = "dss_fck",
1331 .addr = omap44xx_dss_dispc_dma_addrs,
1332 .user = OCP_USER_SDMA,
1333 };
1335 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1336 {
1337 .pa_start = 0x48041000,
1338 .pa_end = 0x48041fff,
1339 .flags = ADDR_TYPE_RT
1340 },
1341 { }
1342 };
1344 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
1345 .manager_count = 3,
1346 .has_framedonetv_irq = 1
1347 };
1349 /* l4_per -> dss_dispc */
1350 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1351 .master = &omap44xx_l4_per_hwmod,
1352 .slave = &omap44xx_dss_dispc_hwmod,
1353 .clk = "l4_div_ck",
1354 .addr = omap44xx_dss_dispc_addrs,
1355 .user = OCP_USER_MPU,
1356 };
1358 /* dss_dispc slave ports */
1359 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1360 &omap44xx_l3_main_2__dss_dispc,
1361 &omap44xx_l4_per__dss_dispc,
1362 };
1364 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1365 .name = "dss_dispc",
1366 .class = &omap44xx_dispc_hwmod_class,
1367 .clkdm_name = "l3_dss_clkdm",
1368 .mpu_irqs = omap44xx_dss_dispc_irqs,
1369 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
1370 .main_clk = "dss_dss_clk",
1371 .prcm = {
1372 .omap4 = {
1373 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1374 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1375 },
1376 },
1377 .slaves = omap44xx_dss_dispc_slaves,
1378 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1379 .dev_attr = &omap44xx_dss_dispc_dev_attr
1380 };
1382 /*
1383 * 'dsi' class
1384 * display serial interface controller
1385 */
1387 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1388 .rev_offs = 0x0000,
1389 .sysc_offs = 0x0010,
1390 .syss_offs = 0x0014,
1391 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1392 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1393 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1394 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1395 .sysc_fields = &omap_hwmod_sysc_type1,
1396 };
1398 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1399 .name = "dsi",
1400 .sysc = &omap44xx_dsi_sysc,
1401 };
1403 /* dss_dsi1 */
1404 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1405 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1406 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1407 { .irq = -1 }
1408 };
1410 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1411 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1412 { .dma_req = -1 }
1413 };
1415 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1416 {
1417 .pa_start = 0x58004000,
1418 .pa_end = 0x580041ff,
1419 .flags = ADDR_TYPE_RT
1420 },
1421 { }
1422 };
1424 /* l3_main_2 -> dss_dsi1 */
1425 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1426 .master = &omap44xx_l3_main_2_hwmod,
1427 .slave = &omap44xx_dss_dsi1_hwmod,
1428 .clk = "dss_fck",
1429 .addr = omap44xx_dss_dsi1_dma_addrs,
1430 .user = OCP_USER_SDMA,
1431 };
1433 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1434 {
1435 .pa_start = 0x48044000,
1436 .pa_end = 0x480441ff,
1437 .flags = ADDR_TYPE_RT
1438 },
1439 { }
1440 };
1442 /* l4_per -> dss_dsi1 */
1443 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1444 .master = &omap44xx_l4_per_hwmod,
1445 .slave = &omap44xx_dss_dsi1_hwmod,
1446 .clk = "l4_div_ck",
1447 .addr = omap44xx_dss_dsi1_addrs,
1448 .user = OCP_USER_MPU,
1449 };
1451 /* dss_dsi1 slave ports */
1452 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1453 &omap44xx_l3_main_2__dss_dsi1,
1454 &omap44xx_l4_per__dss_dsi1,
1455 };
1457 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1458 { .role = "sys_clk", .clk = "dss_sys_clk" },
1459 };
1461 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1462 .name = "dss_dsi1",
1463 .class = &omap44xx_dsi_hwmod_class,
1464 .clkdm_name = "l3_dss_clkdm",
1465 .mpu_irqs = omap44xx_dss_dsi1_irqs,
1466 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
1467 .main_clk = "dss_dss_clk",
1468 .prcm = {
1469 .omap4 = {
1470 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1471 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1472 },
1473 },
1474 .opt_clks = dss_dsi1_opt_clks,
1475 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
1476 .slaves = omap44xx_dss_dsi1_slaves,
1477 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1478 };
1480 /* dss_dsi2 */
1481 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1482 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1483 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1484 { .irq = -1 }
1485 };
1487 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1488 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1489 { .dma_req = -1 }
1490 };
1492 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1493 {
1494 .pa_start = 0x58005000,
1495 .pa_end = 0x580051ff,
1496 .flags = ADDR_TYPE_RT
1497 },
1498 { }
1499 };
1501 /* l3_main_2 -> dss_dsi2 */
1502 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1503 .master = &omap44xx_l3_main_2_hwmod,
1504 .slave = &omap44xx_dss_dsi2_hwmod,
1505 .clk = "dss_fck",
1506 .addr = omap44xx_dss_dsi2_dma_addrs,
1507 .user = OCP_USER_SDMA,
1508 };
1510 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1511 {
1512 .pa_start = 0x48045000,
1513 .pa_end = 0x480451ff,
1514 .flags = ADDR_TYPE_RT
1515 },
1516 { }
1517 };
1519 /* l4_per -> dss_dsi2 */
1520 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1521 .master = &omap44xx_l4_per_hwmod,
1522 .slave = &omap44xx_dss_dsi2_hwmod,
1523 .clk = "l4_div_ck",
1524 .addr = omap44xx_dss_dsi2_addrs,
1525 .user = OCP_USER_MPU,
1526 };
1528 /* dss_dsi2 slave ports */
1529 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1530 &omap44xx_l3_main_2__dss_dsi2,
1531 &omap44xx_l4_per__dss_dsi2,
1532 };
1534 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1535 { .role = "sys_clk", .clk = "dss_sys_clk" },
1536 };
1538 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1539 .name = "dss_dsi2",
1540 .class = &omap44xx_dsi_hwmod_class,
1541 .clkdm_name = "l3_dss_clkdm",
1542 .mpu_irqs = omap44xx_dss_dsi2_irqs,
1543 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
1544 .main_clk = "dss_dss_clk",
1545 .prcm = {
1546 .omap4 = {
1547 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1548 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1549 },
1550 },
1551 .opt_clks = dss_dsi2_opt_clks,
1552 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
1553 .slaves = omap44xx_dss_dsi2_slaves,
1554 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1555 };
1557 /*
1558 * 'hdmi' class
1559 * hdmi controller
1560 */
1562 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1563 .rev_offs = 0x0000,
1564 .sysc_offs = 0x0010,
1565 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1566 SYSC_HAS_SOFTRESET),
1567 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1568 SIDLE_SMART_WKUP),
1569 .sysc_fields = &omap_hwmod_sysc_type2,
1570 };
1572 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1573 .name = "hdmi",
1574 .sysc = &omap44xx_hdmi_sysc,
1575 };
1577 /* dss_hdmi */
1578 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1579 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1580 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1581 { .irq = -1 }
1582 };
1584 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1585 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1586 { .dma_req = -1 }
1587 };
1589 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1590 {
1591 .pa_start = 0x58006000,
1592 .pa_end = 0x58006fff,
1593 .flags = ADDR_TYPE_RT
1594 },
1595 { }
1596 };
1598 /* l3_main_2 -> dss_hdmi */
1599 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1600 .master = &omap44xx_l3_main_2_hwmod,
1601 .slave = &omap44xx_dss_hdmi_hwmod,
1602 .clk = "dss_fck",
1603 .addr = omap44xx_dss_hdmi_dma_addrs,
1604 .user = OCP_USER_SDMA,
1605 };
1607 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1608 {
1609 .pa_start = 0x48046000,
1610 .pa_end = 0x48046fff,
1611 .flags = ADDR_TYPE_RT
1612 },
1613 { }
1614 };
1616 /* l4_per -> dss_hdmi */
1617 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1618 .master = &omap44xx_l4_per_hwmod,
1619 .slave = &omap44xx_dss_hdmi_hwmod,
1620 .clk = "l4_div_ck",
1621 .addr = omap44xx_dss_hdmi_addrs,
1622 .user = OCP_USER_MPU,
1623 };
1625 /* dss_hdmi slave ports */
1626 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1627 &omap44xx_l3_main_2__dss_hdmi,
1628 &omap44xx_l4_per__dss_hdmi,
1629 };
1631 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1632 { .role = "sys_clk", .clk = "dss_sys_clk" },
1633 };
1635 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1636 .name = "dss_hdmi",
1637 .class = &omap44xx_hdmi_hwmod_class,
1638 .clkdm_name = "l3_dss_clkdm",
1639 .mpu_irqs = omap44xx_dss_hdmi_irqs,
1640 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
1641 .main_clk = "dss_48mhz_clk",
1642 .prcm = {
1643 .omap4 = {
1644 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1645 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1646 },
1647 },
1648 .opt_clks = dss_hdmi_opt_clks,
1649 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
1650 .slaves = omap44xx_dss_hdmi_slaves,
1651 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1652 };
1654 /*
1655 * 'rfbi' class
1656 * remote frame buffer interface
1657 */
1659 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1660 .rev_offs = 0x0000,
1661 .sysc_offs = 0x0010,
1662 .syss_offs = 0x0014,
1663 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1664 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1665 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1666 .sysc_fields = &omap_hwmod_sysc_type1,
1667 };
1669 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1670 .name = "rfbi",
1671 .sysc = &omap44xx_rfbi_sysc,
1672 };
1674 /* dss_rfbi */
1675 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1676 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1677 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1678 { .dma_req = -1 }
1679 };
1681 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1682 {
1683 .pa_start = 0x58002000,
1684 .pa_end = 0x580020ff,
1685 .flags = ADDR_TYPE_RT
1686 },
1687 { }
1688 };
1690 /* l3_main_2 -> dss_rfbi */
1691 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1692 .master = &omap44xx_l3_main_2_hwmod,
1693 .slave = &omap44xx_dss_rfbi_hwmod,
1694 .clk = "dss_fck",
1695 .addr = omap44xx_dss_rfbi_dma_addrs,
1696 .user = OCP_USER_SDMA,
1697 };
1699 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1700 {
1701 .pa_start = 0x48042000,
1702 .pa_end = 0x480420ff,
1703 .flags = ADDR_TYPE_RT
1704 },
1705 { }
1706 };
1708 /* l4_per -> dss_rfbi */
1709 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1710 .master = &omap44xx_l4_per_hwmod,
1711 .slave = &omap44xx_dss_rfbi_hwmod,
1712 .clk = "l4_div_ck",
1713 .addr = omap44xx_dss_rfbi_addrs,
1714 .user = OCP_USER_MPU,
1715 };
1717 /* dss_rfbi slave ports */
1718 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1719 &omap44xx_l3_main_2__dss_rfbi,
1720 &omap44xx_l4_per__dss_rfbi,
1721 };
1723 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1724 { .role = "ick", .clk = "dss_fck" },
1725 };
1727 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1728 .name = "dss_rfbi",
1729 .class = &omap44xx_rfbi_hwmod_class,
1730 .clkdm_name = "l3_dss_clkdm",
1731 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
1732 .main_clk = "dss_dss_clk",
1733 .prcm = {
1734 .omap4 = {
1735 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1736 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1737 },
1738 },
1739 .opt_clks = dss_rfbi_opt_clks,
1740 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1741 .slaves = omap44xx_dss_rfbi_slaves,
1742 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1743 };
1745 /*
1746 * 'venc' class
1747 * video encoder
1748 */
1750 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1751 .name = "venc",
1752 };
1754 /* dss_venc */
1755 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1756 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1757 {
1758 .pa_start = 0x58003000,
1759 .pa_end = 0x580030ff,
1760 .flags = ADDR_TYPE_RT
1761 },
1762 { }
1763 };
1765 /* l3_main_2 -> dss_venc */
1766 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1767 .master = &omap44xx_l3_main_2_hwmod,
1768 .slave = &omap44xx_dss_venc_hwmod,
1769 .clk = "dss_fck",
1770 .addr = omap44xx_dss_venc_dma_addrs,
1771 .user = OCP_USER_SDMA,
1772 };
1774 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1775 {
1776 .pa_start = 0x48043000,
1777 .pa_end = 0x480430ff,
1778 .flags = ADDR_TYPE_RT
1779 },
1780 { }
1781 };
1783 /* l4_per -> dss_venc */
1784 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1785 .master = &omap44xx_l4_per_hwmod,
1786 .slave = &omap44xx_dss_venc_hwmod,
1787 .clk = "l4_div_ck",
1788 .addr = omap44xx_dss_venc_addrs,
1789 .user = OCP_USER_MPU,
1790 };
1792 /* dss_venc slave ports */
1793 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1794 &omap44xx_l3_main_2__dss_venc,
1795 &omap44xx_l4_per__dss_venc,
1796 };
1798 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1799 .name = "dss_venc",
1800 .class = &omap44xx_venc_hwmod_class,
1801 .clkdm_name = "l3_dss_clkdm",
1802 .main_clk = "dss_tv_clk",
1803 .prcm = {
1804 .omap4 = {
1805 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1806 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1807 },
1808 },
1809 .slaves = omap44xx_dss_venc_slaves,
1810 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1811 };
1813 /*
1814 * 'fdif' class
1815 * face detection hw accelerator module
1816 */
1818 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1819 .rev_offs = 0x0000,
1820 .sysc_offs = 0x0010,
1821 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1822 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1823 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1824 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1825 .sysc_fields = &omap_hwmod_sysc_type2,
1826 };
1828 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1829 .name = "fdif",
1830 .sysc = &omap44xx_fdif_sysc,
1831 };
1833 /* fdif */
1834 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1835 { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1836 { .irq = -1 }
1837 };
1839 /* fdif master ports */
1840 static struct omap_hwmod_ocp_if *omap44xx_fdif_masters[] = {
1841 &omap44xx_fdif__l3_main_2,
1842 };
1844 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
1845 {
1846 .pa_start = 0x4a10a000,
1847 .pa_end = 0x4a10a1ff,
1848 .flags = ADDR_TYPE_RT
1849 },
1850 { }
1851 };
1853 /* l4_cfg -> fdif */
1854 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
1855 .master = &omap44xx_l4_cfg_hwmod,
1856 .slave = &omap44xx_fdif_hwmod,
1857 .clk = "l4_div_ck",
1858 .addr = omap44xx_fdif_addrs,
1859 .user = OCP_USER_MPU | OCP_USER_SDMA,
1860 };
1862 /* fdif slave ports */
1863 static struct omap_hwmod_ocp_if *omap44xx_fdif_slaves[] = {
1864 &omap44xx_l4_cfg__fdif,
1865 };
1867 static struct omap_hwmod omap44xx_fdif_hwmod = {
1868 .name = "fdif",
1869 .class = &omap44xx_fdif_hwmod_class,
1870 .clkdm_name = "iss_clkdm",
1871 .mpu_irqs = omap44xx_fdif_irqs,
1872 .main_clk = "fdif_fck",
1873 .prcm = {
1874 .omap4 = {
1875 .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1876 .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1877 .modulemode = MODULEMODE_SWCTRL,
1878 },
1879 },
1880 .slaves = omap44xx_fdif_slaves,
1881 .slaves_cnt = ARRAY_SIZE(omap44xx_fdif_slaves),
1882 .masters = omap44xx_fdif_masters,
1883 .masters_cnt = ARRAY_SIZE(omap44xx_fdif_masters),
1884 };
1886 /*
1887 * 'gpio' class
1888 * general purpose io module
1889 */
1891 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1892 .rev_offs = 0x0000,
1893 .sysc_offs = 0x0010,
1894 .syss_offs = 0x0114,
1895 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1896 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1897 SYSS_HAS_RESET_STATUS),
1898 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1899 SIDLE_SMART_WKUP),
1900 .sysc_fields = &omap_hwmod_sysc_type1,
1901 };
1903 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1904 .name = "gpio",
1905 .sysc = &omap44xx_gpio_sysc,
1906 .rev = 2,
1907 };
1909 /* gpio dev_attr */
1910 static struct omap_gpio_dev_attr gpio_dev_attr = {
1911 .bank_width = 32,
1912 .dbck_flag = true,
1913 };
1915 /* gpio1 */
1916 static struct omap_hwmod omap44xx_gpio1_hwmod;
1917 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1918 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1919 { .irq = -1 }
1920 };
1922 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1923 {
1924 .pa_start = 0x4a310000,
1925 .pa_end = 0x4a3101ff,
1926 .flags = ADDR_TYPE_RT
1927 },
1928 { }
1929 };
1931 /* l4_wkup -> gpio1 */
1932 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1933 .master = &omap44xx_l4_wkup_hwmod,
1934 .slave = &omap44xx_gpio1_hwmod,
1935 .clk = "l4_wkup_clk_mux_ck",
1936 .addr = omap44xx_gpio1_addrs,
1937 .user = OCP_USER_MPU | OCP_USER_SDMA,
1938 };
1940 /* gpio1 slave ports */
1941 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1942 &omap44xx_l4_wkup__gpio1,
1943 };
1945 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1946 { .role = "dbclk", .clk = "gpio1_dbclk" },
1947 };
1949 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1950 .name = "gpio1",
1951 .class = &omap44xx_gpio_hwmod_class,
1952 .clkdm_name = "l4_wkup_clkdm",
1953 .mpu_irqs = omap44xx_gpio1_irqs,
1954 .main_clk = "gpio1_ick",
1955 .prcm = {
1956 .omap4 = {
1957 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1958 .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1959 .modulemode = MODULEMODE_HWCTRL,
1960 },
1961 },
1962 .opt_clks = gpio1_opt_clks,
1963 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1964 .dev_attr = &gpio_dev_attr,
1965 .slaves = omap44xx_gpio1_slaves,
1966 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
1967 };
1969 /* gpio2 */
1970 static struct omap_hwmod omap44xx_gpio2_hwmod;
1971 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1972 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1973 { .irq = -1 }
1974 };
1976 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1977 {
1978 .pa_start = 0x48055000,
1979 .pa_end = 0x480551ff,
1980 .flags = ADDR_TYPE_RT
1981 },
1982 { }
1983 };
1985 /* l4_per -> gpio2 */
1986 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1987 .master = &omap44xx_l4_per_hwmod,
1988 .slave = &omap44xx_gpio2_hwmod,
1989 .clk = "l4_div_ck",
1990 .addr = omap44xx_gpio2_addrs,
1991 .user = OCP_USER_MPU | OCP_USER_SDMA,
1992 };
1994 /* gpio2 slave ports */
1995 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1996 &omap44xx_l4_per__gpio2,
1997 };
1999 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
2000 { .role = "dbclk", .clk = "gpio2_dbclk" },
2001 };
2003 static struct omap_hwmod omap44xx_gpio2_hwmod = {
2004 .name = "gpio2",
2005 .class = &omap44xx_gpio_hwmod_class,
2006 .clkdm_name = "l4_per_clkdm",
2007 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2008 .mpu_irqs = omap44xx_gpio2_irqs,
2009 .main_clk = "gpio2_ick",
2010 .prcm = {
2011 .omap4 = {
2012 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
2013 .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
2014 .modulemode = MODULEMODE_HWCTRL,
2015 },
2016 },
2017 .opt_clks = gpio2_opt_clks,
2018 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
2019 .dev_attr = &gpio_dev_attr,
2020 .slaves = omap44xx_gpio2_slaves,
2021 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
2022 };
2024 /* gpio3 */
2025 static struct omap_hwmod omap44xx_gpio3_hwmod;
2026 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
2027 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
2028 { .irq = -1 }
2029 };
2031 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
2032 {
2033 .pa_start = 0x48057000,
2034 .pa_end = 0x480571ff,
2035 .flags = ADDR_TYPE_RT
2036 },
2037 { }
2038 };
2040 /* l4_per -> gpio3 */
2041 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
2042 .master = &omap44xx_l4_per_hwmod,
2043 .slave = &omap44xx_gpio3_hwmod,
2044 .clk = "l4_div_ck",
2045 .addr = omap44xx_gpio3_addrs,
2046 .user = OCP_USER_MPU | OCP_USER_SDMA,
2047 };
2049 /* gpio3 slave ports */
2050 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
2051 &omap44xx_l4_per__gpio3,
2052 };
2054 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
2055 { .role = "dbclk", .clk = "gpio3_dbclk" },
2056 };
2058 static struct omap_hwmod omap44xx_gpio3_hwmod = {
2059 .name = "gpio3",
2060 .class = &omap44xx_gpio_hwmod_class,
2061 .clkdm_name = "l4_per_clkdm",
2062 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2063 .mpu_irqs = omap44xx_gpio3_irqs,
2064 .main_clk = "gpio3_ick",
2065 .prcm = {
2066 .omap4 = {
2067 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
2068 .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
2069 .modulemode = MODULEMODE_HWCTRL,
2070 },
2071 },
2072 .opt_clks = gpio3_opt_clks,
2073 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
2074 .dev_attr = &gpio_dev_attr,
2075 .slaves = omap44xx_gpio3_slaves,
2076 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
2077 };
2079 /* gpio4 */
2080 static struct omap_hwmod omap44xx_gpio4_hwmod;
2081 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
2082 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
2083 { .irq = -1 }
2084 };
2086 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
2087 {
2088 .pa_start = 0x48059000,
2089 .pa_end = 0x480591ff,
2090 .flags = ADDR_TYPE_RT
2091 },
2092 { }
2093 };
2095 /* l4_per -> gpio4 */
2096 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
2097 .master = &omap44xx_l4_per_hwmod,
2098 .slave = &omap44xx_gpio4_hwmod,
2099 .clk = "l4_div_ck",
2100 .addr = omap44xx_gpio4_addrs,
2101 .user = OCP_USER_MPU | OCP_USER_SDMA,
2102 };
2104 /* gpio4 slave ports */
2105 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
2106 &omap44xx_l4_per__gpio4,
2107 };
2109 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2110 { .role = "dbclk", .clk = "gpio4_dbclk" },
2111 };
2113 static struct omap_hwmod omap44xx_gpio4_hwmod = {
2114 .name = "gpio4",
2115 .class = &omap44xx_gpio_hwmod_class,
2116 .clkdm_name = "l4_per_clkdm",
2117 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2118 .mpu_irqs = omap44xx_gpio4_irqs,
2119 .main_clk = "gpio4_ick",
2120 .prcm = {
2121 .omap4 = {
2122 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
2123 .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
2124 .modulemode = MODULEMODE_HWCTRL,
2125 },
2126 },
2127 .opt_clks = gpio4_opt_clks,
2128 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
2129 .dev_attr = &gpio_dev_attr,
2130 .slaves = omap44xx_gpio4_slaves,
2131 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
2132 };
2134 /* gpio5 */
2135 static struct omap_hwmod omap44xx_gpio5_hwmod;
2136 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
2137 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
2138 { .irq = -1 }
2139 };
2141 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
2142 {
2143 .pa_start = 0x4805b000,
2144 .pa_end = 0x4805b1ff,
2145 .flags = ADDR_TYPE_RT
2146 },
2147 { }
2148 };
2150 /* l4_per -> gpio5 */
2151 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
2152 .master = &omap44xx_l4_per_hwmod,
2153 .slave = &omap44xx_gpio5_hwmod,
2154 .clk = "l4_div_ck",
2155 .addr = omap44xx_gpio5_addrs,
2156 .user = OCP_USER_MPU | OCP_USER_SDMA,
2157 };
2159 /* gpio5 slave ports */
2160 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
2161 &omap44xx_l4_per__gpio5,
2162 };
2164 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2165 { .role = "dbclk", .clk = "gpio5_dbclk" },
2166 };
2168 static struct omap_hwmod omap44xx_gpio5_hwmod = {
2169 .name = "gpio5",
2170 .class = &omap44xx_gpio_hwmod_class,
2171 .clkdm_name = "l4_per_clkdm",
2172 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2173 .mpu_irqs = omap44xx_gpio5_irqs,
2174 .main_clk = "gpio5_ick",
2175 .prcm = {
2176 .omap4 = {
2177 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
2178 .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
2179 .modulemode = MODULEMODE_HWCTRL,
2180 },
2181 },
2182 .opt_clks = gpio5_opt_clks,
2183 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2184 .dev_attr = &gpio_dev_attr,
2185 .slaves = omap44xx_gpio5_slaves,
2186 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
2187 };
2189 /* gpio6 */
2190 static struct omap_hwmod omap44xx_gpio6_hwmod;
2191 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2192 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
2193 { .irq = -1 }
2194 };
2196 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
2197 {
2198 .pa_start = 0x4805d000,
2199 .pa_end = 0x4805d1ff,
2200 .flags = ADDR_TYPE_RT
2201 },
2202 { }
2203 };
2205 /* l4_per -> gpio6 */
2206 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2207 .master = &omap44xx_l4_per_hwmod,
2208 .slave = &omap44xx_gpio6_hwmod,
2209 .clk = "l4_div_ck",
2210 .addr = omap44xx_gpio6_addrs,
2211 .user = OCP_USER_MPU | OCP_USER_SDMA,
2212 };
2214 /* gpio6 slave ports */
2215 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2216 &omap44xx_l4_per__gpio6,
2217 };
2219 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2220 { .role = "dbclk", .clk = "gpio6_dbclk" },
2221 };
2223 static struct omap_hwmod omap44xx_gpio6_hwmod = {
2224 .name = "gpio6",
2225 .class = &omap44xx_gpio_hwmod_class,
2226 .clkdm_name = "l4_per_clkdm",
2227 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2228 .mpu_irqs = omap44xx_gpio6_irqs,
2229 .main_clk = "gpio6_ick",
2230 .prcm = {
2231 .omap4 = {
2232 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
2233 .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
2234 .modulemode = MODULEMODE_HWCTRL,
2235 },
2236 },
2237 .opt_clks = gpio6_opt_clks,
2238 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2239 .dev_attr = &gpio_dev_attr,
2240 .slaves = omap44xx_gpio6_slaves,
2241 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
2242 };
2244 /*
2245 * 'hsi' class
2246 * mipi high-speed synchronous serial interface (multichannel and full-duplex
2247 * serial if)
2248 */
2250 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2251 .rev_offs = 0x0000,
2252 .sysc_offs = 0x0010,
2253 .syss_offs = 0x0014,
2254 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2255 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2256 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2257 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2258 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2259 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2260 .sysc_fields = &omap_hwmod_sysc_type1,
2261 };
2263 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2264 .name = "hsi",
2265 .sysc = &omap44xx_hsi_sysc,
2266 };
2268 /* hsi */
2269 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2270 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2271 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2272 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2273 { .irq = -1 }
2274 };
2276 /* hsi master ports */
2277 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2278 &omap44xx_hsi__l3_main_2,
2279 };
2281 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2282 {
2283 .pa_start = 0x4a058000,
2284 .pa_end = 0x4a05bfff,
2285 .flags = ADDR_TYPE_RT
2286 },
2287 { }
2288 };
2290 /* l4_cfg -> hsi */
2291 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2292 .master = &omap44xx_l4_cfg_hwmod,
2293 .slave = &omap44xx_hsi_hwmod,
2294 .clk = "l4_div_ck",
2295 .addr = omap44xx_hsi_addrs,
2296 .user = OCP_USER_MPU | OCP_USER_SDMA,
2297 };
2299 /* hsi slave ports */
2300 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2301 &omap44xx_l4_cfg__hsi,
2302 };
2304 static struct omap_hwmod omap44xx_hsi_hwmod = {
2305 .name = "hsi",
2306 .class = &omap44xx_hsi_hwmod_class,
2307 .clkdm_name = "l3_init_clkdm",
2308 .mpu_irqs = omap44xx_hsi_irqs,
2309 .main_clk = "hsi_fck",
2310 .prcm = {
2311 .omap4 = {
2312 .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
2313 .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
2314 .modulemode = MODULEMODE_HWCTRL,
2315 },
2316 },
2317 .slaves = omap44xx_hsi_slaves,
2318 .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves),
2319 .masters = omap44xx_hsi_masters,
2320 .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters),
2321 };
2323 /*
2324 * 'i2c' class
2325 * multimaster high-speed i2c controller
2326 */
2328 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2329 .sysc_offs = 0x0010,
2330 .syss_offs = 0x0090,
2331 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2332 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2333 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2334 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2335 SIDLE_SMART_WKUP),
2336 .clockact = CLOCKACT_TEST_ICLK,
2337 .sysc_fields = &omap_hwmod_sysc_type1,
2338 };
2340 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2341 .name = "i2c",
2342 .sysc = &omap44xx_i2c_sysc,
2343 .rev = OMAP_I2C_IP_VERSION_2,
2344 .reset = &omap_i2c_reset,
2345 };
2347 static struct omap_i2c_dev_attr i2c_dev_attr = {
2348 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
2349 };
2351 /* i2c1 */
2352 static struct omap_hwmod omap44xx_i2c1_hwmod;
2353 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2354 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2355 { .irq = -1 }
2356 };
2358 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2359 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2360 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2361 { .dma_req = -1 }
2362 };
2364 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2365 {
2366 .pa_start = 0x48070000,
2367 .pa_end = 0x480700ff,
2368 .flags = ADDR_TYPE_RT
2369 },
2370 { }
2371 };
2373 /* l4_per -> i2c1 */
2374 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2375 .master = &omap44xx_l4_per_hwmod,
2376 .slave = &omap44xx_i2c1_hwmod,
2377 .clk = "l4_div_ck",
2378 .addr = omap44xx_i2c1_addrs,
2379 .user = OCP_USER_MPU | OCP_USER_SDMA,
2380 };
2382 /* i2c1 slave ports */
2383 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2384 &omap44xx_l4_per__i2c1,
2385 };
2387 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2388 .name = "i2c1",
2389 .class = &omap44xx_i2c_hwmod_class,
2390 .clkdm_name = "l4_per_clkdm",
2391 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2392 .mpu_irqs = omap44xx_i2c1_irqs,
2393 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
2394 .main_clk = "i2c1_fck",
2395 .prcm = {
2396 .omap4 = {
2397 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
2398 .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
2399 .modulemode = MODULEMODE_SWCTRL,
2400 },
2401 },
2402 .slaves = omap44xx_i2c1_slaves,
2403 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
2404 .dev_attr = &i2c_dev_attr,
2405 };
2407 /* i2c2 */
2408 static struct omap_hwmod omap44xx_i2c2_hwmod;
2409 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2410 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2411 { .irq = -1 }
2412 };
2414 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2415 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2416 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2417 { .dma_req = -1 }
2418 };
2420 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2421 {
2422 .pa_start = 0x48072000,
2423 .pa_end = 0x480720ff,
2424 .flags = ADDR_TYPE_RT
2425 },
2426 { }
2427 };
2429 /* l4_per -> i2c2 */
2430 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2431 .master = &omap44xx_l4_per_hwmod,
2432 .slave = &omap44xx_i2c2_hwmod,
2433 .clk = "l4_div_ck",
2434 .addr = omap44xx_i2c2_addrs,
2435 .user = OCP_USER_MPU | OCP_USER_SDMA,
2436 };
2438 /* i2c2 slave ports */
2439 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2440 &omap44xx_l4_per__i2c2,
2441 };
2443 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2444 .name = "i2c2",
2445 .class = &omap44xx_i2c_hwmod_class,
2446 .clkdm_name = "l4_per_clkdm",
2447 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2448 .mpu_irqs = omap44xx_i2c2_irqs,
2449 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
2450 .main_clk = "i2c2_fck",
2451 .prcm = {
2452 .omap4 = {
2453 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
2454 .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
2455 .modulemode = MODULEMODE_SWCTRL,
2456 },
2457 },
2458 .slaves = omap44xx_i2c2_slaves,
2459 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
2460 .dev_attr = &i2c_dev_attr,
2461 };
2463 /* i2c3 */
2464 static struct omap_hwmod omap44xx_i2c3_hwmod;
2465 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2466 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2467 { .irq = -1 }
2468 };
2470 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2471 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2472 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2473 { .dma_req = -1 }
2474 };
2476 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2477 {
2478 .pa_start = 0x48060000,
2479 .pa_end = 0x480600ff,
2480 .flags = ADDR_TYPE_RT
2481 },
2482 { }
2483 };
2485 /* l4_per -> i2c3 */
2486 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2487 .master = &omap44xx_l4_per_hwmod,
2488 .slave = &omap44xx_i2c3_hwmod,
2489 .clk = "l4_div_ck",
2490 .addr = omap44xx_i2c3_addrs,
2491 .user = OCP_USER_MPU | OCP_USER_SDMA,
2492 };
2494 /* i2c3 slave ports */
2495 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2496 &omap44xx_l4_per__i2c3,
2497 };
2499 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2500 .name = "i2c3",
2501 .class = &omap44xx_i2c_hwmod_class,
2502 .clkdm_name = "l4_per_clkdm",
2503 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2504 .mpu_irqs = omap44xx_i2c3_irqs,
2505 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
2506 .main_clk = "i2c3_fck",
2507 .prcm = {
2508 .omap4 = {
2509 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
2510 .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
2511 .modulemode = MODULEMODE_SWCTRL,
2512 },
2513 },
2514 .slaves = omap44xx_i2c3_slaves,
2515 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
2516 .dev_attr = &i2c_dev_attr,
2517 };
2519 /* i2c4 */
2520 static struct omap_hwmod omap44xx_i2c4_hwmod;
2521 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2522 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2523 { .irq = -1 }
2524 };
2526 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2527 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2528 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2529 { .dma_req = -1 }
2530 };
2532 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2533 {
2534 .pa_start = 0x48350000,
2535 .pa_end = 0x483500ff,
2536 .flags = ADDR_TYPE_RT
2537 },
2538 { }
2539 };
2541 /* l4_per -> i2c4 */
2542 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2543 .master = &omap44xx_l4_per_hwmod,
2544 .slave = &omap44xx_i2c4_hwmod,
2545 .clk = "l4_div_ck",
2546 .addr = omap44xx_i2c4_addrs,
2547 .user = OCP_USER_MPU | OCP_USER_SDMA,
2548 };
2550 /* i2c4 slave ports */
2551 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2552 &omap44xx_l4_per__i2c4,
2553 };
2555 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2556 .name = "i2c4",
2557 .class = &omap44xx_i2c_hwmod_class,
2558 .clkdm_name = "l4_per_clkdm",
2559 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2560 .mpu_irqs = omap44xx_i2c4_irqs,
2561 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
2562 .main_clk = "i2c4_fck",
2563 .prcm = {
2564 .omap4 = {
2565 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
2566 .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
2567 .modulemode = MODULEMODE_SWCTRL,
2568 },
2569 },
2570 .slaves = omap44xx_i2c4_slaves,
2571 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
2572 .dev_attr = &i2c_dev_attr,
2573 };
2575 /*
2576 * 'ipu' class
2577 * imaging processor unit
2578 */
2580 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2581 .name = "ipu",
2582 };
2584 /* ipu */
2585 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2586 { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2587 { .irq = -1 }
2588 };
2590 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2591 { .name = "cpu0", .rst_shift = 0 },
2592 };
2594 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2595 { .name = "cpu1", .rst_shift = 1 },
2596 };
2598 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2599 { .name = "mmu_cache", .rst_shift = 2 },
2600 };
2602 /* ipu master ports */
2603 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2604 &omap44xx_ipu__l3_main_2,
2605 };
2607 /* l3_main_2 -> ipu */
2608 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2609 .master = &omap44xx_l3_main_2_hwmod,
2610 .slave = &omap44xx_ipu_hwmod,
2611 .clk = "l3_div_ck",
2612 .user = OCP_USER_MPU | OCP_USER_SDMA,
2613 };
2615 /* ipu slave ports */
2616 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2617 &omap44xx_l3_main_2__ipu,
2618 };
2620 /* Pseudo hwmod for reset control purpose only */
2621 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2622 .name = "ipu_c0",
2623 .class = &omap44xx_ipu_hwmod_class,
2624 .clkdm_name = "ducati_clkdm",
2625 .flags = HWMOD_INIT_NO_RESET,
2626 .rst_lines = omap44xx_ipu_c0_resets,
2627 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2628 .prcm = {
2629 .omap4 = {
2630 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2631 },
2632 },
2633 };
2635 /* Pseudo hwmod for reset control purpose only */
2636 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2637 .name = "ipu_c1",
2638 .class = &omap44xx_ipu_hwmod_class,
2639 .clkdm_name = "ducati_clkdm",
2640 .flags = HWMOD_INIT_NO_RESET,
2641 .rst_lines = omap44xx_ipu_c1_resets,
2642 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2643 .prcm = {
2644 .omap4 = {
2645 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2646 },
2647 },
2648 };
2650 static struct omap_hwmod omap44xx_ipu_hwmod = {
2651 .name = "ipu",
2652 .class = &omap44xx_ipu_hwmod_class,
2653 .clkdm_name = "ducati_clkdm",
2654 .mpu_irqs = omap44xx_ipu_irqs,
2655 .rst_lines = omap44xx_ipu_resets,
2656 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
2657 .main_clk = "ipu_fck",
2658 .prcm = {
2659 .omap4 = {
2660 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2661 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2662 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2663 .modulemode = MODULEMODE_HWCTRL,
2664 },
2665 },
2666 .slaves = omap44xx_ipu_slaves,
2667 .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves),
2668 .masters = omap44xx_ipu_masters,
2669 .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters),
2670 };
2672 /*
2673 * 'iss' class
2674 * external images sensor pixel data processor
2675 */
2677 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2678 .rev_offs = 0x0000,
2679 .sysc_offs = 0x0010,
2680 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2681 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2682 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2683 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2684 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2685 .sysc_fields = &omap_hwmod_sysc_type2,
2686 };
2688 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2689 .name = "iss",
2690 .sysc = &omap44xx_iss_sysc,
2691 };
2693 /* iss */
2694 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2695 { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2696 { .irq = -1 }
2697 };
2699 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2700 { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2701 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2702 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2703 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2704 { .dma_req = -1 }
2705 };
2707 /* iss master ports */
2708 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2709 &omap44xx_iss__l3_main_2,
2710 };
2712 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2713 {
2714 .pa_start = 0x52000000,
2715 .pa_end = 0x520000ff,
2716 .flags = ADDR_TYPE_RT
2717 },
2718 { }
2719 };
2721 /* l3_main_2 -> iss */
2722 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2723 .master = &omap44xx_l3_main_2_hwmod,
2724 .slave = &omap44xx_iss_hwmod,
2725 .clk = "l3_div_ck",
2726 .addr = omap44xx_iss_addrs,
2727 .user = OCP_USER_MPU | OCP_USER_SDMA,
2728 };
2730 /* iss slave ports */
2731 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2732 &omap44xx_l3_main_2__iss,
2733 };
2735 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2736 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2737 };
2739 static struct omap_hwmod omap44xx_iss_hwmod = {
2740 .name = "iss",
2741 .class = &omap44xx_iss_hwmod_class,
2742 .clkdm_name = "iss_clkdm",
2743 .mpu_irqs = omap44xx_iss_irqs,
2744 .sdma_reqs = omap44xx_iss_sdma_reqs,
2745 .main_clk = "iss_fck",
2746 .prcm = {
2747 .omap4 = {
2748 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
2749 .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
2750 .modulemode = MODULEMODE_SWCTRL,
2751 },
2752 },
2753 .opt_clks = iss_opt_clks,
2754 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
2755 .slaves = omap44xx_iss_slaves,
2756 .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves),
2757 .masters = omap44xx_iss_masters,
2758 .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters),
2759 };
2761 /*
2762 * 'iva' class
2763 * multi-standard video encoder/decoder hardware accelerator
2764 */
2766 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2767 .name = "iva",
2768 };
2770 /* iva */
2771 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2772 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2773 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2774 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2775 { .irq = -1 }
2776 };
2778 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2779 { .name = "logic", .rst_shift = 2 },
2780 };
2782 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2783 { .name = "seq0", .rst_shift = 0 },
2784 };
2786 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2787 { .name = "seq1", .rst_shift = 1 },
2788 };
2790 /* iva master ports */
2791 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2792 &omap44xx_iva__l3_main_2,
2793 &omap44xx_iva__l3_instr,
2794 };
2796 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2797 {
2798 .pa_start = 0x5a000000,
2799 .pa_end = 0x5a07ffff,
2800 .flags = ADDR_TYPE_RT
2801 },
2802 { }
2803 };
2805 /* l3_main_2 -> iva */
2806 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2807 .master = &omap44xx_l3_main_2_hwmod,
2808 .slave = &omap44xx_iva_hwmod,
2809 .clk = "l3_div_ck",
2810 .addr = omap44xx_iva_addrs,
2811 .user = OCP_USER_MPU,
2812 };
2814 /* iva slave ports */
2815 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2816 &omap44xx_dsp__iva,
2817 &omap44xx_l3_main_2__iva,
2818 };
2820 /* Pseudo hwmod for reset control purpose only */
2821 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2822 .name = "iva_seq0",
2823 .class = &omap44xx_iva_hwmod_class,
2824 .clkdm_name = "ivahd_clkdm",
2825 .flags = HWMOD_INIT_NO_RESET,
2826 .rst_lines = omap44xx_iva_seq0_resets,
2827 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2828 .prcm = {
2829 .omap4 = {
2830 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2831 },
2832 },
2833 };
2835 /* Pseudo hwmod for reset control purpose only */
2836 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2837 .name = "iva_seq1",
2838 .class = &omap44xx_iva_hwmod_class,
2839 .clkdm_name = "ivahd_clkdm",
2840 .flags = HWMOD_INIT_NO_RESET,
2841 .rst_lines = omap44xx_iva_seq1_resets,
2842 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2843 .prcm = {
2844 .omap4 = {
2845 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2846 },
2847 },
2848 };
2850 static struct omap_hwmod omap44xx_iva_hwmod = {
2851 .name = "iva",
2852 .class = &omap44xx_iva_hwmod_class,
2853 .clkdm_name = "ivahd_clkdm",
2854 .mpu_irqs = omap44xx_iva_irqs,
2855 .rst_lines = omap44xx_iva_resets,
2856 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
2857 .main_clk = "iva_fck",
2858 .prcm = {
2859 .omap4 = {
2860 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
2861 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2862 .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
2863 .modulemode = MODULEMODE_HWCTRL,
2864 },
2865 },
2866 .slaves = omap44xx_iva_slaves,
2867 .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves),
2868 .masters = omap44xx_iva_masters,
2869 .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters),
2870 };
2872 /*
2873 * 'kbd' class
2874 * keyboard controller
2875 */
2877 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2878 .rev_offs = 0x0000,
2879 .sysc_offs = 0x0010,
2880 .syss_offs = 0x0014,
2881 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2882 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2883 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2884 SYSS_HAS_RESET_STATUS),
2885 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2886 .sysc_fields = &omap_hwmod_sysc_type1,
2887 };
2889 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2890 .name = "kbd",
2891 .sysc = &omap44xx_kbd_sysc,
2892 };
2894 /* kbd */
2895 static struct omap_hwmod omap44xx_kbd_hwmod;
2896 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2897 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2898 { .irq = -1 }
2899 };
2901 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2902 {
2903 .pa_start = 0x4a31c000,
2904 .pa_end = 0x4a31c07f,
2905 .flags = ADDR_TYPE_RT
2906 },
2907 { }
2908 };
2910 /* l4_wkup -> kbd */
2911 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2912 .master = &omap44xx_l4_wkup_hwmod,
2913 .slave = &omap44xx_kbd_hwmod,
2914 .clk = "l4_wkup_clk_mux_ck",
2915 .addr = omap44xx_kbd_addrs,
2916 .user = OCP_USER_MPU | OCP_USER_SDMA,
2917 };
2919 /* kbd slave ports */
2920 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2921 &omap44xx_l4_wkup__kbd,
2922 };
2924 static struct omap_hwmod omap44xx_kbd_hwmod = {
2925 .name = "kbd",
2926 .class = &omap44xx_kbd_hwmod_class,
2927 .clkdm_name = "l4_wkup_clkdm",
2928 .mpu_irqs = omap44xx_kbd_irqs,
2929 .main_clk = "kbd_fck",
2930 .prcm = {
2931 .omap4 = {
2932 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
2933 .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
2934 .modulemode = MODULEMODE_SWCTRL,
2935 },
2936 },
2937 .slaves = omap44xx_kbd_slaves,
2938 .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves),
2939 };
2941 /*
2942 * 'mailbox' class
2943 * mailbox module allowing communication between the on-chip processors using a
2944 * queued mailbox-interrupt mechanism.
2945 */
2947 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2948 .rev_offs = 0x0000,
2949 .sysc_offs = 0x0010,
2950 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2951 SYSC_HAS_SOFTRESET),
2952 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2953 .sysc_fields = &omap_hwmod_sysc_type2,
2954 };
2956 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2957 .name = "mailbox",
2958 .sysc = &omap44xx_mailbox_sysc,
2959 };
2961 /* mailbox */
2962 static struct omap_hwmod omap44xx_mailbox_hwmod;
2963 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2964 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2965 { .irq = -1 }
2966 };
2968 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2969 {
2970 .pa_start = 0x4a0f4000,
2971 .pa_end = 0x4a0f41ff,
2972 .flags = ADDR_TYPE_RT
2973 },
2974 { }
2975 };
2977 /* l4_cfg -> mailbox */
2978 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2979 .master = &omap44xx_l4_cfg_hwmod,
2980 .slave = &omap44xx_mailbox_hwmod,
2981 .clk = "l4_div_ck",
2982 .addr = omap44xx_mailbox_addrs,
2983 .user = OCP_USER_MPU | OCP_USER_SDMA,
2984 };
2986 /* mailbox slave ports */
2987 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2988 &omap44xx_l4_cfg__mailbox,
2989 };
2991 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2992 .name = "mailbox",
2993 .class = &omap44xx_mailbox_hwmod_class,
2994 .clkdm_name = "l4_cfg_clkdm",
2995 .mpu_irqs = omap44xx_mailbox_irqs,
2996 .prcm = {
2997 .omap4 = {
2998 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
2999 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
3000 },
3001 },
3002 .slaves = omap44xx_mailbox_slaves,
3003 .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
3004 };
3006 /*
3007 * 'mcbsp' class
3008 * multi channel buffered serial port controller
3009 */
3011 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
3012 .sysc_offs = 0x008c,
3013 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
3014 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3015 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3016 .sysc_fields = &omap_hwmod_sysc_type1,
3017 };
3019 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
3020 .name = "mcbsp",
3021 .sysc = &omap44xx_mcbsp_sysc,
3022 .rev = MCBSP_CONFIG_TYPE4,
3023 };
3025 /* mcbsp1 */
3026 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
3027 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
3028 { .irq = 17 + OMAP44XX_IRQ_GIC_START },
3029 { .irq = -1 }
3030 };
3032 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
3033 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
3034 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
3035 { .dma_req = -1 }
3036 };
3038 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
3039 {
3040 .name = "mpu",
3041 .pa_start = 0x40122000,
3042 .pa_end = 0x401220ff,
3043 .flags = ADDR_TYPE_RT
3044 },
3045 { }
3046 };
3048 /* l4_abe -> mcbsp1 */
3049 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
3050 .master = &omap44xx_l4_abe_hwmod,
3051 .slave = &omap44xx_mcbsp1_hwmod,
3052 .clk = "ocp_abe_iclk",
3053 .addr = omap44xx_mcbsp1_addrs,
3054 .user = OCP_USER_MPU,
3055 };
3057 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
3058 {
3059 .name = "dma",
3060 .pa_start = 0x49022000,
3061 .pa_end = 0x490220ff,
3062 .flags = ADDR_TYPE_RT
3063 },
3064 { }
3065 };
3067 /* l4_abe -> mcbsp1 (dma) */
3068 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
3069 .master = &omap44xx_l4_abe_hwmod,
3070 .slave = &omap44xx_mcbsp1_hwmod,
3071 .clk = "ocp_abe_iclk",
3072 .addr = omap44xx_mcbsp1_dma_addrs,
3073 .user = OCP_USER_SDMA,
3074 };
3076 /* mcbsp1 slave ports */
3077 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
3078 &omap44xx_l4_abe__mcbsp1,
3079 &omap44xx_l4_abe__mcbsp1_dma,
3080 };
3082 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
3083 .name = "mcbsp1",
3084 .class = &omap44xx_mcbsp_hwmod_class,
3085 .clkdm_name = "abe_clkdm",
3086 .mpu_irqs = omap44xx_mcbsp1_irqs,
3087 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
3088 .main_clk = "mcbsp1_fck",
3089 .prcm = {
3090 .omap4 = {
3091 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
3092 .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
3093 .modulemode = MODULEMODE_SWCTRL,
3094 },
3095 },
3096 .slaves = omap44xx_mcbsp1_slaves,
3097 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
3098 };
3100 /* mcbsp2 */
3101 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
3102 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
3103 { .irq = 22 + OMAP44XX_IRQ_GIC_START },
3104 { .irq = -1 }
3105 };
3107 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
3108 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
3109 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
3110 { .dma_req = -1 }
3111 };
3113 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
3114 {
3115 .name = "mpu",
3116 .pa_start = 0x40124000,
3117 .pa_end = 0x401240ff,
3118 .flags = ADDR_TYPE_RT
3119 },
3120 { }
3121 };
3123 /* l4_abe -> mcbsp2 */
3124 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
3125 .master = &omap44xx_l4_abe_hwmod,
3126 .slave = &omap44xx_mcbsp2_hwmod,
3127 .clk = "ocp_abe_iclk",
3128 .addr = omap44xx_mcbsp2_addrs,
3129 .user = OCP_USER_MPU,
3130 };
3132 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
3133 {
3134 .name = "dma",
3135 .pa_start = 0x49024000,
3136 .pa_end = 0x490240ff,
3137 .flags = ADDR_TYPE_RT
3138 },
3139 { }
3140 };
3142 /* l4_abe -> mcbsp2 (dma) */
3143 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
3144 .master = &omap44xx_l4_abe_hwmod,
3145 .slave = &omap44xx_mcbsp2_hwmod,
3146 .clk = "ocp_abe_iclk",
3147 .addr = omap44xx_mcbsp2_dma_addrs,
3148 .user = OCP_USER_SDMA,
3149 };
3151 /* mcbsp2 slave ports */
3152 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
3153 &omap44xx_l4_abe__mcbsp2,
3154 &omap44xx_l4_abe__mcbsp2_dma,
3155 };
3157 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
3158 .name = "mcbsp2",
3159 .class = &omap44xx_mcbsp_hwmod_class,
3160 .clkdm_name = "abe_clkdm",
3161 .mpu_irqs = omap44xx_mcbsp2_irqs,
3162 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
3163 .main_clk = "mcbsp2_fck",
3164 .prcm = {
3165 .omap4 = {
3166 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
3167 .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
3168 .modulemode = MODULEMODE_SWCTRL,
3169 },
3170 },
3171 .slaves = omap44xx_mcbsp2_slaves,
3172 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
3173 };
3175 /* mcbsp3 */
3176 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
3177 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
3178 { .irq = 23 + OMAP44XX_IRQ_GIC_START },
3179 { .irq = -1 }
3180 };
3182 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
3183 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
3184 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
3185 { .dma_req = -1 }
3186 };
3188 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
3189 {
3190 .name = "mpu",
3191 .pa_start = 0x40126000,
3192 .pa_end = 0x401260ff,
3193 .flags = ADDR_TYPE_RT
3194 },
3195 { }
3196 };
3198 /* l4_abe -> mcbsp3 */
3199 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3200 .master = &omap44xx_l4_abe_hwmod,
3201 .slave = &omap44xx_mcbsp3_hwmod,
3202 .clk = "ocp_abe_iclk",
3203 .addr = omap44xx_mcbsp3_addrs,
3204 .user = OCP_USER_MPU,
3205 };
3207 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
3208 {
3209 .name = "dma",
3210 .pa_start = 0x49026000,
3211 .pa_end = 0x490260ff,
3212 .flags = ADDR_TYPE_RT
3213 },
3214 { }
3215 };
3217 /* l4_abe -> mcbsp3 (dma) */
3218 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
3219 .master = &omap44xx_l4_abe_hwmod,
3220 .slave = &omap44xx_mcbsp3_hwmod,
3221 .clk = "ocp_abe_iclk",
3222 .addr = omap44xx_mcbsp3_dma_addrs,
3223 .user = OCP_USER_SDMA,
3224 };
3226 /* mcbsp3 slave ports */
3227 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
3228 &omap44xx_l4_abe__mcbsp3,
3229 &omap44xx_l4_abe__mcbsp3_dma,
3230 };
3232 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3233 .name = "mcbsp3",
3234 .class = &omap44xx_mcbsp_hwmod_class,
3235 .clkdm_name = "abe_clkdm",
3236 .mpu_irqs = omap44xx_mcbsp3_irqs,
3237 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
3238 .main_clk = "mcbsp3_fck",
3239 .prcm = {
3240 .omap4 = {
3241 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
3242 .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
3243 .modulemode = MODULEMODE_SWCTRL,
3244 },
3245 },
3246 .slaves = omap44xx_mcbsp3_slaves,
3247 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3248 };
3250 /* mcbsp4 */
3251 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3252 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3253 { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3254 { .irq = -1 }
3255 };
3257 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3258 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3259 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3260 { .dma_req = -1 }
3261 };
3263 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3264 {
3265 .pa_start = 0x48096000,
3266 .pa_end = 0x480960ff,
3267 .flags = ADDR_TYPE_RT
3268 },
3269 { }
3270 };
3272 /* l4_per -> mcbsp4 */
3273 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3274 .master = &omap44xx_l4_per_hwmod,
3275 .slave = &omap44xx_mcbsp4_hwmod,
3276 .clk = "l4_div_ck",
3277 .addr = omap44xx_mcbsp4_addrs,
3278 .user = OCP_USER_MPU | OCP_USER_SDMA,
3279 };
3281 /* mcbsp4 slave ports */
3282 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3283 &omap44xx_l4_per__mcbsp4,
3284 };
3286 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3287 .name = "mcbsp4",
3288 .class = &omap44xx_mcbsp_hwmod_class,
3289 .clkdm_name = "l4_per_clkdm",
3290 .mpu_irqs = omap44xx_mcbsp4_irqs,
3291 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
3292 .main_clk = "mcbsp4_fck",
3293 .prcm = {
3294 .omap4 = {
3295 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
3296 .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
3297 .modulemode = MODULEMODE_SWCTRL,
3298 },
3299 },
3300 .slaves = omap44xx_mcbsp4_slaves,
3301 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3302 };
3304 /*
3305 * 'mcpdm' class
3306 * multi channel pdm controller (proprietary interface with phoenix power
3307 * ic)
3308 */
3310 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3311 .rev_offs = 0x0000,
3312 .sysc_offs = 0x0010,
3313 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3314 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3315 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3316 SIDLE_SMART_WKUP),
3317 .sysc_fields = &omap_hwmod_sysc_type2,
3318 };
3320 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3321 .name = "mcpdm",
3322 .sysc = &omap44xx_mcpdm_sysc,
3323 };
3325 /* mcpdm */
3326 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3327 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3328 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3329 { .irq = -1 }
3330 };
3332 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3333 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3334 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3335 { .dma_req = -1 }
3336 };
3338 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3339 {
3340 .pa_start = 0x40132000,
3341 .pa_end = 0x4013207f,
3342 .flags = ADDR_TYPE_RT
3343 },
3344 { }
3345 };
3347 /* l4_abe -> mcpdm */
3348 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3349 .master = &omap44xx_l4_abe_hwmod,
3350 .slave = &omap44xx_mcpdm_hwmod,
3351 .clk = "ocp_abe_iclk",
3352 .addr = omap44xx_mcpdm_addrs,
3353 .user = OCP_USER_MPU,
3354 };
3356 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3357 {
3358 .pa_start = 0x49032000,
3359 .pa_end = 0x4903207f,
3360 .flags = ADDR_TYPE_RT
3361 },
3362 { }
3363 };
3365 /* l4_abe -> mcpdm (dma) */
3366 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3367 .master = &omap44xx_l4_abe_hwmod,
3368 .slave = &omap44xx_mcpdm_hwmod,
3369 .clk = "ocp_abe_iclk",
3370 .addr = omap44xx_mcpdm_dma_addrs,
3371 .user = OCP_USER_SDMA,
3372 };
3374 /* mcpdm slave ports */
3375 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3376 &omap44xx_l4_abe__mcpdm,
3377 &omap44xx_l4_abe__mcpdm_dma,
3378 };
3380 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3381 .name = "mcpdm",
3382 .class = &omap44xx_mcpdm_hwmod_class,
3383 .clkdm_name = "abe_clkdm",
3384 .mpu_irqs = omap44xx_mcpdm_irqs,
3385 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
3386 .main_clk = "mcpdm_fck",
3387 .prcm = {
3388 .omap4 = {
3389 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
3390 .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
3391 .modulemode = MODULEMODE_SWCTRL,
3392 },
3393 },
3394 .slaves = omap44xx_mcpdm_slaves,
3395 .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3396 };
3398 /*
3399 * 'mcspi' class
3400 * multichannel serial port interface (mcspi) / master/slave synchronous serial
3401 * bus
3402 */
3404 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3405 .rev_offs = 0x0000,
3406 .sysc_offs = 0x0010,
3407 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3408 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3409 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3410 SIDLE_SMART_WKUP),
3411 .sysc_fields = &omap_hwmod_sysc_type2,
3412 };
3414 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3415 .name = "mcspi",
3416 .sysc = &omap44xx_mcspi_sysc,
3417 .rev = OMAP4_MCSPI_REV,
3418 };
3420 /* mcspi1 */
3421 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3422 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3423 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3424 { .irq = -1 }
3425 };
3427 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3428 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3429 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3430 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3431 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3432 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3433 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3434 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3435 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3436 { .dma_req = -1 }
3437 };
3439 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3440 {
3441 .pa_start = 0x48098000,
3442 .pa_end = 0x480981ff,
3443 .flags = ADDR_TYPE_RT
3444 },
3445 { }
3446 };
3448 /* l4_per -> mcspi1 */
3449 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3450 .master = &omap44xx_l4_per_hwmod,
3451 .slave = &omap44xx_mcspi1_hwmod,
3452 .clk = "l4_div_ck",
3453 .addr = omap44xx_mcspi1_addrs,
3454 .user = OCP_USER_MPU | OCP_USER_SDMA,
3455 };
3457 /* mcspi1 slave ports */
3458 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3459 &omap44xx_l4_per__mcspi1,
3460 };
3462 /* mcspi1 dev_attr */
3463 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3464 .num_chipselect = 4,
3465 };
3467 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3468 .name = "mcspi1",
3469 .class = &omap44xx_mcspi_hwmod_class,
3470 .clkdm_name = "l4_per_clkdm",
3471 .mpu_irqs = omap44xx_mcspi1_irqs,
3472 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
3473 .main_clk = "mcspi1_fck",
3474 .prcm = {
3475 .omap4 = {
3476 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
3477 .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
3478 .modulemode = MODULEMODE_SWCTRL,
3479 },
3480 },
3481 .dev_attr = &mcspi1_dev_attr,
3482 .slaves = omap44xx_mcspi1_slaves,
3483 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3484 };
3486 /* mcspi2 */
3487 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3488 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3489 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3490 { .irq = -1 }
3491 };
3493 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3494 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3495 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3496 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3497 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3498 { .dma_req = -1 }
3499 };
3501 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3502 {
3503 .pa_start = 0x4809a000,
3504 .pa_end = 0x4809a1ff,
3505 .flags = ADDR_TYPE_RT
3506 },
3507 { }
3508 };
3510 /* l4_per -> mcspi2 */
3511 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3512 .master = &omap44xx_l4_per_hwmod,
3513 .slave = &omap44xx_mcspi2_hwmod,
3514 .clk = "l4_div_ck",
3515 .addr = omap44xx_mcspi2_addrs,
3516 .user = OCP_USER_MPU | OCP_USER_SDMA,
3517 };
3519 /* mcspi2 slave ports */
3520 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3521 &omap44xx_l4_per__mcspi2,
3522 };
3524 /* mcspi2 dev_attr */
3525 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3526 .num_chipselect = 2,
3527 };
3529 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3530 .name = "mcspi2",
3531 .class = &omap44xx_mcspi_hwmod_class,
3532 .clkdm_name = "l4_per_clkdm",
3533 .mpu_irqs = omap44xx_mcspi2_irqs,
3534 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
3535 .main_clk = "mcspi2_fck",
3536 .prcm = {
3537 .omap4 = {
3538 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
3539 .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
3540 .modulemode = MODULEMODE_SWCTRL,
3541 },
3542 },
3543 .dev_attr = &mcspi2_dev_attr,
3544 .slaves = omap44xx_mcspi2_slaves,
3545 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3546 };
3548 /* mcspi3 */
3549 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3550 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3551 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3552 { .irq = -1 }
3553 };
3555 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3556 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3557 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3558 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3559 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3560 { .dma_req = -1 }
3561 };
3563 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3564 {
3565 .pa_start = 0x480b8000,
3566 .pa_end = 0x480b81ff,
3567 .flags = ADDR_TYPE_RT
3568 },
3569 { }
3570 };
3572 /* l4_per -> mcspi3 */
3573 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3574 .master = &omap44xx_l4_per_hwmod,
3575 .slave = &omap44xx_mcspi3_hwmod,
3576 .clk = "l4_div_ck",
3577 .addr = omap44xx_mcspi3_addrs,
3578 .user = OCP_USER_MPU | OCP_USER_SDMA,
3579 };
3581 /* mcspi3 slave ports */
3582 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3583 &omap44xx_l4_per__mcspi3,
3584 };
3586 /* mcspi3 dev_attr */
3587 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3588 .num_chipselect = 2,
3589 };
3591 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3592 .name = "mcspi3",
3593 .class = &omap44xx_mcspi_hwmod_class,
3594 .clkdm_name = "l4_per_clkdm",
3595 .mpu_irqs = omap44xx_mcspi3_irqs,
3596 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
3597 .main_clk = "mcspi3_fck",
3598 .prcm = {
3599 .omap4 = {
3600 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
3601 .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
3602 .modulemode = MODULEMODE_SWCTRL,
3603 },
3604 },
3605 .dev_attr = &mcspi3_dev_attr,
3606 .slaves = omap44xx_mcspi3_slaves,
3607 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3608 };
3610 /* mcspi4 */
3611 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3612 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3613 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3614 { .irq = -1 }
3615 };
3617 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3618 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3619 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3620 { .dma_req = -1 }
3621 };
3623 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3624 {
3625 .pa_start = 0x480ba000,
3626 .pa_end = 0x480ba1ff,
3627 .flags = ADDR_TYPE_RT
3628 },
3629 { }
3630 };
3632 /* l4_per -> mcspi4 */
3633 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3634 .master = &omap44xx_l4_per_hwmod,
3635 .slave = &omap44xx_mcspi4_hwmod,
3636 .clk = "l4_div_ck",
3637 .addr = omap44xx_mcspi4_addrs,
3638 .user = OCP_USER_MPU | OCP_USER_SDMA,
3639 };
3641 /* mcspi4 slave ports */
3642 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3643 &omap44xx_l4_per__mcspi4,
3644 };
3646 /* mcspi4 dev_attr */
3647 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3648 .num_chipselect = 1,
3649 };
3651 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3652 .name = "mcspi4",
3653 .class = &omap44xx_mcspi_hwmod_class,
3654 .clkdm_name = "l4_per_clkdm",
3655 .mpu_irqs = omap44xx_mcspi4_irqs,
3656 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
3657 .main_clk = "mcspi4_fck",
3658 .prcm = {
3659 .omap4 = {
3660 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
3661 .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
3662 .modulemode = MODULEMODE_SWCTRL,
3663 },
3664 },
3665 .dev_attr = &mcspi4_dev_attr,
3666 .slaves = omap44xx_mcspi4_slaves,
3667 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3668 };
3670 /*
3671 * 'mmc' class
3672 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3673 */
3675 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3676 .rev_offs = 0x0000,
3677 .sysc_offs = 0x0010,
3678 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3679 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3680 SYSC_HAS_SOFTRESET),
3681 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3682 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3683 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3684 .sysc_fields = &omap_hwmod_sysc_type2,
3685 };
3687 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3688 .name = "mmc",
3689 .sysc = &omap44xx_mmc_sysc,
3690 };
3692 /* mmc1 */
3693 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3694 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3695 { .irq = -1 }
3696 };
3698 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3699 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3700 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3701 { .dma_req = -1 }
3702 };
3704 /* mmc1 master ports */
3705 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3706 &omap44xx_mmc1__l3_main_1,
3707 };
3709 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3710 {
3711 .pa_start = 0x4809c000,
3712 .pa_end = 0x4809c3ff,
3713 .flags = ADDR_TYPE_RT
3714 },
3715 { }
3716 };
3718 /* l4_per -> mmc1 */
3719 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3720 .master = &omap44xx_l4_per_hwmod,
3721 .slave = &omap44xx_mmc1_hwmod,
3722 .clk = "l4_div_ck",
3723 .addr = omap44xx_mmc1_addrs,
3724 .user = OCP_USER_MPU | OCP_USER_SDMA,
3725 };
3727 /* mmc1 slave ports */
3728 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3729 &omap44xx_l4_per__mmc1,
3730 };
3732 /* mmc1 dev_attr */
3733 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3734 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3735 };
3737 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3738 .name = "mmc1",
3739 .class = &omap44xx_mmc_hwmod_class,
3740 .clkdm_name = "l3_init_clkdm",
3741 .mpu_irqs = omap44xx_mmc1_irqs,
3742 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
3743 .main_clk = "mmc1_fck",
3744 .prcm = {
3745 .omap4 = {
3746 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
3747 .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
3748 .modulemode = MODULEMODE_SWCTRL,
3749 },
3750 },
3751 .dev_attr = &mmc1_dev_attr,
3752 .slaves = omap44xx_mmc1_slaves,
3753 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
3754 .masters = omap44xx_mmc1_masters,
3755 .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters),
3756 };
3758 /* mmc2 */
3759 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3760 { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3761 { .irq = -1 }
3762 };
3764 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3765 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3766 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3767 { .dma_req = -1 }
3768 };
3770 /* mmc2 master ports */
3771 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3772 &omap44xx_mmc2__l3_main_1,
3773 };
3775 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3776 {
3777 .pa_start = 0x480b4000,
3778 .pa_end = 0x480b43ff,
3779 .flags = ADDR_TYPE_RT
3780 },
3781 { }
3782 };
3784 /* l4_per -> mmc2 */
3785 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3786 .master = &omap44xx_l4_per_hwmod,
3787 .slave = &omap44xx_mmc2_hwmod,
3788 .clk = "l4_div_ck",
3789 .addr = omap44xx_mmc2_addrs,
3790 .user = OCP_USER_MPU | OCP_USER_SDMA,
3791 };
3793 /* mmc2 slave ports */
3794 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3795 &omap44xx_l4_per__mmc2,
3796 };
3798 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3799 .name = "mmc2",
3800 .class = &omap44xx_mmc_hwmod_class,
3801 .clkdm_name = "l3_init_clkdm",
3802 .mpu_irqs = omap44xx_mmc2_irqs,
3803 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
3804 .main_clk = "mmc2_fck",
3805 .prcm = {
3806 .omap4 = {
3807 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
3808 .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
3809 .modulemode = MODULEMODE_SWCTRL,
3810 },
3811 },
3812 .slaves = omap44xx_mmc2_slaves,
3813 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves),
3814 .masters = omap44xx_mmc2_masters,
3815 .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters),
3816 };
3818 /* mmc3 */
3819 static struct omap_hwmod omap44xx_mmc3_hwmod;
3820 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3821 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3822 { .irq = -1 }
3823 };
3825 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3826 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3827 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3828 { .dma_req = -1 }
3829 };
3831 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3832 {
3833 .pa_start = 0x480ad000,
3834 .pa_end = 0x480ad3ff,
3835 .flags = ADDR_TYPE_RT
3836 },
3837 { }
3838 };
3840 /* l4_per -> mmc3 */
3841 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3842 .master = &omap44xx_l4_per_hwmod,
3843 .slave = &omap44xx_mmc3_hwmod,
3844 .clk = "l4_div_ck",
3845 .addr = omap44xx_mmc3_addrs,
3846 .user = OCP_USER_MPU | OCP_USER_SDMA,
3847 };
3849 /* mmc3 slave ports */
3850 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3851 &omap44xx_l4_per__mmc3,
3852 };
3854 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3855 .name = "mmc3",
3856 .class = &omap44xx_mmc_hwmod_class,
3857 .clkdm_name = "l4_per_clkdm",
3858 .mpu_irqs = omap44xx_mmc3_irqs,
3859 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
3860 .main_clk = "mmc3_fck",
3861 .prcm = {
3862 .omap4 = {
3863 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
3864 .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
3865 .modulemode = MODULEMODE_SWCTRL,
3866 },
3867 },
3868 .slaves = omap44xx_mmc3_slaves,
3869 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves),
3870 };
3872 /* mmc4 */
3873 static struct omap_hwmod omap44xx_mmc4_hwmod;
3874 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3875 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3876 { .irq = -1 }
3877 };
3879 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3880 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3881 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3882 { .dma_req = -1 }
3883 };
3885 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3886 {
3887 .pa_start = 0x480d1000,
3888 .pa_end = 0x480d13ff,
3889 .flags = ADDR_TYPE_RT
3890 },
3891 { }
3892 };
3894 /* l4_per -> mmc4 */
3895 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3896 .master = &omap44xx_l4_per_hwmod,
3897 .slave = &omap44xx_mmc4_hwmod,
3898 .clk = "l4_div_ck",
3899 .addr = omap44xx_mmc4_addrs,
3900 .user = OCP_USER_MPU | OCP_USER_SDMA,
3901 };
3903 /* mmc4 slave ports */
3904 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3905 &omap44xx_l4_per__mmc4,
3906 };
3908 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3909 .name = "mmc4",
3910 .class = &omap44xx_mmc_hwmod_class,
3911 .clkdm_name = "l4_per_clkdm",
3912 .mpu_irqs = omap44xx_mmc4_irqs,
3914 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
3915 .main_clk = "mmc4_fck",
3916 .prcm = {
3917 .omap4 = {
3918 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
3919 .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
3920 .modulemode = MODULEMODE_SWCTRL,
3921 },
3922 },
3923 .slaves = omap44xx_mmc4_slaves,
3924 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves),
3925 };
3927 /* mmc5 */
3928 static struct omap_hwmod omap44xx_mmc5_hwmod;
3929 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3930 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3931 { .irq = -1 }
3932 };
3934 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3935 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3936 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3937 { .dma_req = -1 }
3938 };
3940 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3941 {
3942 .pa_start = 0x480d5000,
3943 .pa_end = 0x480d53ff,
3944 .flags = ADDR_TYPE_RT
3945 },
3946 { }
3947 };
3949 /* l4_per -> mmc5 */
3950 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3951 .master = &omap44xx_l4_per_hwmod,
3952 .slave = &omap44xx_mmc5_hwmod,
3953 .clk = "l4_div_ck",
3954 .addr = omap44xx_mmc5_addrs,
3955 .user = OCP_USER_MPU | OCP_USER_SDMA,
3956 };
3958 /* mmc5 slave ports */
3959 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3960 &omap44xx_l4_per__mmc5,
3961 };
3963 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3964 .name = "mmc5",
3965 .class = &omap44xx_mmc_hwmod_class,
3966 .clkdm_name = "l4_per_clkdm",
3967 .mpu_irqs = omap44xx_mmc5_irqs,
3968 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
3969 .main_clk = "mmc5_fck",
3970 .prcm = {
3971 .omap4 = {
3972 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
3973 .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
3974 .modulemode = MODULEMODE_SWCTRL,
3975 },
3976 },
3977 .slaves = omap44xx_mmc5_slaves,
3978 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves),
3979 };
3981 /*
3982 * 'mpu' class
3983 * mpu sub-system
3984 */
3986 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3987 .name = "mpu",
3988 };
3990 /* mpu */
3991 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3992 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3993 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3994 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3995 { .irq = -1 }
3996 };
3998 /* mpu master ports */
3999 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
4000 &omap44xx_mpu__l3_main_1,
4001 &omap44xx_mpu__l4_abe,
4002 &omap44xx_mpu__dmm,
4003 };
4005 static struct omap_hwmod omap44xx_mpu_hwmod = {
4006 .name = "mpu",
4007 .class = &omap44xx_mpu_hwmod_class,
4008 .clkdm_name = "mpuss_clkdm",
4009 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
4010 .mpu_irqs = omap44xx_mpu_irqs,
4011 .main_clk = "dpll_mpu_m2_ck",
4012 .prcm = {
4013 .omap4 = {
4014 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
4015 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
4016 },
4017 },
4018 .masters = omap44xx_mpu_masters,
4019 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
4020 };
4022 /*
4023 * 'smartreflex' class
4024 * smartreflex module (monitor silicon performance and outputs a measure of
4025 * performance error)
4026 */
4028 /* The IP is not compliant to type1 / type2 scheme */
4029 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
4030 .sidle_shift = 24,
4031 .enwkup_shift = 26,
4032 };
4034 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
4035 .sysc_offs = 0x0038,
4036 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
4037 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4038 SIDLE_SMART_WKUP),
4039 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
4040 };
4042 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
4043 .name = "smartreflex",
4044 .sysc = &omap44xx_smartreflex_sysc,
4045 .rev = 2,
4046 };
4048 /* smartreflex_core */
4049 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
4050 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
4051 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
4052 { .irq = -1 }
4053 };
4055 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
4056 {
4057 .pa_start = 0x4a0dd000,
4058 .pa_end = 0x4a0dd03f,
4059 .flags = ADDR_TYPE_RT
4060 },
4061 { }
4062 };
4064 /* l4_cfg -> smartreflex_core */
4065 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
4066 .master = &omap44xx_l4_cfg_hwmod,
4067 .slave = &omap44xx_smartreflex_core_hwmod,
4068 .clk = "l4_div_ck",
4069 .addr = omap44xx_smartreflex_core_addrs,
4070 .user = OCP_USER_MPU | OCP_USER_SDMA,
4071 };
4073 /* smartreflex_core slave ports */
4074 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
4075 &omap44xx_l4_cfg__smartreflex_core,
4076 };
4078 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
4079 .name = "smartreflex_core",
4080 .class = &omap44xx_smartreflex_hwmod_class,
4081 .clkdm_name = "l4_ao_clkdm",
4082 .mpu_irqs = omap44xx_smartreflex_core_irqs,
4084 .main_clk = "smartreflex_core_fck",
4085 .vdd_name = "core",
4086 .prcm = {
4087 .omap4 = {
4088 .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
4089 .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
4090 .modulemode = MODULEMODE_SWCTRL,
4091 },
4092 },
4093 .slaves = omap44xx_smartreflex_core_slaves,
4094 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
4095 };
4097 /* smartreflex_iva */
4098 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
4099 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
4100 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
4101 { .irq = -1 }
4102 };
4104 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4105 {
4106 .pa_start = 0x4a0db000,
4107 .pa_end = 0x4a0db03f,
4108 .flags = ADDR_TYPE_RT
4109 },
4110 { }
4111 };
4113 /* l4_cfg -> smartreflex_iva */
4114 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4115 .master = &omap44xx_l4_cfg_hwmod,
4116 .slave = &omap44xx_smartreflex_iva_hwmod,
4117 .clk = "l4_div_ck",
4118 .addr = omap44xx_smartreflex_iva_addrs,
4119 .user = OCP_USER_MPU | OCP_USER_SDMA,
4120 };
4122 /* smartreflex_iva slave ports */
4123 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
4124 &omap44xx_l4_cfg__smartreflex_iva,
4125 };
4127 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
4128 .name = "smartreflex_iva",
4129 .class = &omap44xx_smartreflex_hwmod_class,
4130 .clkdm_name = "l4_ao_clkdm",
4131 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
4132 .main_clk = "smartreflex_iva_fck",
4133 .vdd_name = "iva",
4134 .prcm = {
4135 .omap4 = {
4136 .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
4137 .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
4138 .modulemode = MODULEMODE_SWCTRL,
4139 },
4140 },
4141 .slaves = omap44xx_smartreflex_iva_slaves,
4142 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
4143 };
4145 /* smartreflex_mpu */
4146 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
4147 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
4148 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
4149 { .irq = -1 }
4150 };
4152 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4153 {
4154 .pa_start = 0x4a0d9000,
4155 .pa_end = 0x4a0d903f,
4156 .flags = ADDR_TYPE_RT
4157 },
4158 { }
4159 };
4161 /* l4_cfg -> smartreflex_mpu */
4162 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4163 .master = &omap44xx_l4_cfg_hwmod,
4164 .slave = &omap44xx_smartreflex_mpu_hwmod,
4165 .clk = "l4_div_ck",
4166 .addr = omap44xx_smartreflex_mpu_addrs,
4167 .user = OCP_USER_MPU | OCP_USER_SDMA,
4168 };
4170 /* smartreflex_mpu slave ports */
4171 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
4172 &omap44xx_l4_cfg__smartreflex_mpu,
4173 };
4175 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
4176 .name = "smartreflex_mpu",
4177 .class = &omap44xx_smartreflex_hwmod_class,
4178 .clkdm_name = "l4_ao_clkdm",
4179 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
4180 .main_clk = "smartreflex_mpu_fck",
4181 .vdd_name = "mpu",
4182 .prcm = {
4183 .omap4 = {
4184 .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
4185 .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
4186 .modulemode = MODULEMODE_SWCTRL,
4187 },
4188 },
4189 .slaves = omap44xx_smartreflex_mpu_slaves,
4190 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
4191 };
4193 /*
4194 * 'spinlock' class
4195 * spinlock provides hardware assistance for synchronizing the processes
4196 * running on multiple processors
4197 */
4199 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
4200 .rev_offs = 0x0000,
4201 .sysc_offs = 0x0010,
4202 .syss_offs = 0x0014,
4203 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4204 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
4205 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4206 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4207 SIDLE_SMART_WKUP),
4208 .sysc_fields = &omap_hwmod_sysc_type1,
4209 };
4211 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
4212 .name = "spinlock",
4213 .sysc = &omap44xx_spinlock_sysc,
4214 };
4216 /* spinlock */
4217 static struct omap_hwmod omap44xx_spinlock_hwmod;
4218 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4219 {
4220 .pa_start = 0x4a0f6000,
4221 .pa_end = 0x4a0f6fff,
4222 .flags = ADDR_TYPE_RT
4223 },
4224 { }
4225 };
4227 /* l4_cfg -> spinlock */
4228 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4229 .master = &omap44xx_l4_cfg_hwmod,
4230 .slave = &omap44xx_spinlock_hwmod,
4231 .clk = "l4_div_ck",
4232 .addr = omap44xx_spinlock_addrs,
4233 .user = OCP_USER_MPU | OCP_USER_SDMA,
4234 };
4236 /* spinlock slave ports */
4237 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
4238 &omap44xx_l4_cfg__spinlock,
4239 };
4241 static struct omap_hwmod omap44xx_spinlock_hwmod = {
4242 .name = "spinlock",
4243 .class = &omap44xx_spinlock_hwmod_class,
4244 .clkdm_name = "l4_cfg_clkdm",
4245 .prcm = {
4246 .omap4 = {
4247 .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
4248 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
4249 },
4250 },
4251 .slaves = omap44xx_spinlock_slaves,
4252 .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves),
4253 };
4255 /*
4256 * 'timer' class
4257 * general purpose timer module with accurate 1ms tick
4258 * This class contains several variants: ['timer_1ms', 'timer']
4259 */
4261 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
4262 .rev_offs = 0x0000,
4263 .sysc_offs = 0x0010,
4264 .syss_offs = 0x0014,
4265 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4266 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
4267 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4268 SYSS_HAS_RESET_STATUS),
4269 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
4270 .sysc_fields = &omap_hwmod_sysc_type1,
4271 };
4273 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
4274 .name = "timer",
4275 .sysc = &omap44xx_timer_1ms_sysc,
4276 };
4278 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4279 .rev_offs = 0x0000,
4280 .sysc_offs = 0x0010,
4281 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4282 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4283 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4284 SIDLE_SMART_WKUP),
4285 .sysc_fields = &omap_hwmod_sysc_type2,
4286 };
4288 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4289 .name = "timer",
4290 .sysc = &omap44xx_timer_sysc,
4291 };
4293 /* always-on timers dev attribute */
4294 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
4295 .timer_capability = OMAP_TIMER_ALWON,
4296 };
4298 /* pwm timers dev attribute */
4299 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
4300 .timer_capability = OMAP_TIMER_HAS_PWM,
4301 };
4303 /* timer1 */
4304 static struct omap_hwmod omap44xx_timer1_hwmod;
4305 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4306 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4307 { .irq = -1 }
4308 };
4310 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4311 {
4312 .pa_start = 0x4a318000,
4313 .pa_end = 0x4a31807f,
4314 .flags = ADDR_TYPE_RT
4315 },
4316 { }
4317 };
4319 /* l4_wkup -> timer1 */
4320 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4321 .master = &omap44xx_l4_wkup_hwmod,
4322 .slave = &omap44xx_timer1_hwmod,
4323 .clk = "l4_wkup_clk_mux_ck",
4324 .addr = omap44xx_timer1_addrs,
4325 .user = OCP_USER_MPU | OCP_USER_SDMA,
4326 };
4328 /* timer1 slave ports */
4329 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4330 &omap44xx_l4_wkup__timer1,
4331 };
4333 static struct omap_hwmod omap44xx_timer1_hwmod = {
4334 .name = "timer1",
4335 .class = &omap44xx_timer_1ms_hwmod_class,
4336 .clkdm_name = "l4_wkup_clkdm",
4337 .mpu_irqs = omap44xx_timer1_irqs,
4338 .main_clk = "timer1_fck",
4339 .prcm = {
4340 .omap4 = {
4341 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
4342 .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
4343 .modulemode = MODULEMODE_SWCTRL,
4344 },
4345 },
4346 .dev_attr = &capability_alwon_dev_attr,
4347 .slaves = omap44xx_timer1_slaves,
4348 .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
4349 };
4351 /* timer2 */
4352 static struct omap_hwmod omap44xx_timer2_hwmod;
4353 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4354 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4355 { .irq = -1 }
4356 };
4358 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4359 {
4360 .pa_start = 0x48032000,
4361 .pa_end = 0x4803207f,
4362 .flags = ADDR_TYPE_RT
4363 },
4364 { }
4365 };
4367 /* l4_per -> timer2 */
4368 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4369 .master = &omap44xx_l4_per_hwmod,
4370 .slave = &omap44xx_timer2_hwmod,
4371 .clk = "l4_div_ck",
4372 .addr = omap44xx_timer2_addrs,
4373 .user = OCP_USER_MPU | OCP_USER_SDMA,
4374 };
4376 /* timer2 slave ports */
4377 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4378 &omap44xx_l4_per__timer2,
4379 };
4381 static struct omap_hwmod omap44xx_timer2_hwmod = {
4382 .name = "timer2",
4383 .class = &omap44xx_timer_1ms_hwmod_class,
4384 .clkdm_name = "l4_per_clkdm",
4385 .mpu_irqs = omap44xx_timer2_irqs,
4386 .main_clk = "timer2_fck",
4387 .prcm = {
4388 .omap4 = {
4389 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
4390 .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
4391 .modulemode = MODULEMODE_SWCTRL,
4392 },
4393 },
4394 .dev_attr = &capability_alwon_dev_attr,
4395 .slaves = omap44xx_timer2_slaves,
4396 .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
4397 };
4399 /* timer3 */
4400 static struct omap_hwmod omap44xx_timer3_hwmod;
4401 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4402 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4403 { .irq = -1 }
4404 };
4406 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4407 {
4408 .pa_start = 0x48034000,
4409 .pa_end = 0x4803407f,
4410 .flags = ADDR_TYPE_RT
4411 },
4412 { }
4413 };
4415 /* l4_per -> timer3 */
4416 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4417 .master = &omap44xx_l4_per_hwmod,
4418 .slave = &omap44xx_timer3_hwmod,
4419 .clk = "l4_div_ck",
4420 .addr = omap44xx_timer3_addrs,
4421 .user = OCP_USER_MPU | OCP_USER_SDMA,
4422 };
4424 /* timer3 slave ports */
4425 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4426 &omap44xx_l4_per__timer3,
4427 };
4429 static struct omap_hwmod omap44xx_timer3_hwmod = {
4430 .name = "timer3",
4431 .class = &omap44xx_timer_hwmod_class,
4432 .clkdm_name = "l4_per_clkdm",
4433 .mpu_irqs = omap44xx_timer3_irqs,
4434 .main_clk = "timer3_fck",
4435 .prcm = {
4436 .omap4 = {
4437 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
4438 .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
4439 .modulemode = MODULEMODE_SWCTRL,
4440 },
4441 },
4442 .dev_attr = &capability_alwon_dev_attr,
4443 .slaves = omap44xx_timer3_slaves,
4444 .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
4445 };
4447 /* timer4 */
4448 static struct omap_hwmod omap44xx_timer4_hwmod;
4449 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4450 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4451 { .irq = -1 }
4452 };
4454 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4455 {
4456 .pa_start = 0x48036000,
4457 .pa_end = 0x4803607f,
4458 .flags = ADDR_TYPE_RT
4459 },
4460 { }
4461 };
4463 /* l4_per -> timer4 */
4464 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4465 .master = &omap44xx_l4_per_hwmod,
4466 .slave = &omap44xx_timer4_hwmod,
4467 .clk = "l4_div_ck",
4468 .addr = omap44xx_timer4_addrs,
4469 .user = OCP_USER_MPU | OCP_USER_SDMA,
4470 };
4472 /* timer4 slave ports */
4473 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4474 &omap44xx_l4_per__timer4,
4475 };
4477 static struct omap_hwmod omap44xx_timer4_hwmod = {
4478 .name = "timer4",
4479 .class = &omap44xx_timer_hwmod_class,
4480 .clkdm_name = "l4_per_clkdm",
4481 .mpu_irqs = omap44xx_timer4_irqs,
4482 .main_clk = "timer4_fck",
4483 .prcm = {
4484 .omap4 = {
4485 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
4486 .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
4487 .modulemode = MODULEMODE_SWCTRL,
4488 },
4489 },
4490 .dev_attr = &capability_alwon_dev_attr,
4491 .slaves = omap44xx_timer4_slaves,
4492 .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
4493 };
4495 /* timer5 */
4496 static struct omap_hwmod omap44xx_timer5_hwmod;
4497 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4498 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4499 { .irq = -1 }
4500 };
4502 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4503 {
4504 .pa_start = 0x40138000,
4505 .pa_end = 0x4013807f,
4506 .flags = ADDR_TYPE_RT
4507 },
4508 { }
4509 };
4511 /* l4_abe -> timer5 */
4512 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4513 .master = &omap44xx_l4_abe_hwmod,
4514 .slave = &omap44xx_timer5_hwmod,
4515 .clk = "ocp_abe_iclk",
4516 .addr = omap44xx_timer5_addrs,
4517 .user = OCP_USER_MPU,
4518 };
4520 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4521 {
4522 .pa_start = 0x49038000,
4523 .pa_end = 0x4903807f,
4524 .flags = ADDR_TYPE_RT
4525 },
4526 { }
4527 };
4529 /* l4_abe -> timer5 (dma) */
4530 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4531 .master = &omap44xx_l4_abe_hwmod,
4532 .slave = &omap44xx_timer5_hwmod,
4533 .clk = "ocp_abe_iclk",
4534 .addr = omap44xx_timer5_dma_addrs,
4535 .user = OCP_USER_SDMA,
4536 };
4538 /* timer5 slave ports */
4539 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4540 &omap44xx_l4_abe__timer5,
4541 &omap44xx_l4_abe__timer5_dma,
4542 };
4544 static struct omap_hwmod omap44xx_timer5_hwmod = {
4545 .name = "timer5",
4546 .class = &omap44xx_timer_hwmod_class,
4547 .clkdm_name = "abe_clkdm",
4548 .mpu_irqs = omap44xx_timer5_irqs,
4549 .main_clk = "timer5_fck",
4550 .prcm = {
4551 .omap4 = {
4552 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
4553 .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
4554 .modulemode = MODULEMODE_SWCTRL,
4555 },
4556 },
4557 .dev_attr = &capability_alwon_dev_attr,
4558 .slaves = omap44xx_timer5_slaves,
4559 .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
4560 };
4562 /* timer6 */
4563 static struct omap_hwmod omap44xx_timer6_hwmod;
4564 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4565 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4566 { .irq = -1 }
4567 };
4569 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4570 {
4571 .pa_start = 0x4013a000,
4572 .pa_end = 0x4013a07f,
4573 .flags = ADDR_TYPE_RT
4574 },
4575 { }
4576 };
4578 /* l4_abe -> timer6 */
4579 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4580 .master = &omap44xx_l4_abe_hwmod,
4581 .slave = &omap44xx_timer6_hwmod,
4582 .clk = "ocp_abe_iclk",
4583 .addr = omap44xx_timer6_addrs,
4584 .user = OCP_USER_MPU,
4585 };
4587 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4588 {
4589 .pa_start = 0x4903a000,
4590 .pa_end = 0x4903a07f,
4591 .flags = ADDR_TYPE_RT
4592 },
4593 { }
4594 };
4596 /* l4_abe -> timer6 (dma) */
4597 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4598 .master = &omap44xx_l4_abe_hwmod,
4599 .slave = &omap44xx_timer6_hwmod,
4600 .clk = "ocp_abe_iclk",
4601 .addr = omap44xx_timer6_dma_addrs,
4602 .user = OCP_USER_SDMA,
4603 };
4605 /* timer6 slave ports */
4606 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4607 &omap44xx_l4_abe__timer6,
4608 &omap44xx_l4_abe__timer6_dma,
4609 };
4611 static struct omap_hwmod omap44xx_timer6_hwmod = {
4612 .name = "timer6",
4613 .class = &omap44xx_timer_hwmod_class,
4614 .clkdm_name = "abe_clkdm",
4615 .mpu_irqs = omap44xx_timer6_irqs,
4617 .main_clk = "timer6_fck",
4618 .prcm = {
4619 .omap4 = {
4620 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
4621 .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
4622 .modulemode = MODULEMODE_SWCTRL,
4623 },
4624 },
4625 .dev_attr = &capability_alwon_dev_attr,
4626 .slaves = omap44xx_timer6_slaves,
4627 .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
4628 };
4630 /* timer7 */
4631 static struct omap_hwmod omap44xx_timer7_hwmod;
4632 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4633 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4634 { .irq = -1 }
4635 };
4637 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4638 {
4639 .pa_start = 0x4013c000,
4640 .pa_end = 0x4013c07f,
4641 .flags = ADDR_TYPE_RT
4642 },
4643 { }
4644 };
4646 /* l4_abe -> timer7 */
4647 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4648 .master = &omap44xx_l4_abe_hwmod,
4649 .slave = &omap44xx_timer7_hwmod,
4650 .clk = "ocp_abe_iclk",
4651 .addr = omap44xx_timer7_addrs,
4652 .user = OCP_USER_MPU,
4653 };
4655 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4656 {
4657 .pa_start = 0x4903c000,
4658 .pa_end = 0x4903c07f,
4659 .flags = ADDR_TYPE_RT
4660 },
4661 { }
4662 };
4664 /* l4_abe -> timer7 (dma) */
4665 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4666 .master = &omap44xx_l4_abe_hwmod,
4667 .slave = &omap44xx_timer7_hwmod,
4668 .clk = "ocp_abe_iclk",
4669 .addr = omap44xx_timer7_dma_addrs,
4670 .user = OCP_USER_SDMA,
4671 };
4673 /* timer7 slave ports */
4674 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4675 &omap44xx_l4_abe__timer7,
4676 &omap44xx_l4_abe__timer7_dma,
4677 };
4679 static struct omap_hwmod omap44xx_timer7_hwmod = {
4680 .name = "timer7",
4681 .class = &omap44xx_timer_hwmod_class,
4682 .clkdm_name = "abe_clkdm",
4683 .mpu_irqs = omap44xx_timer7_irqs,
4684 .main_clk = "timer7_fck",
4685 .prcm = {
4686 .omap4 = {
4687 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
4688 .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
4689 .modulemode = MODULEMODE_SWCTRL,
4690 },
4691 },
4692 .dev_attr = &capability_alwon_dev_attr,
4693 .slaves = omap44xx_timer7_slaves,
4694 .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
4695 };
4697 /* timer8 */
4698 static struct omap_hwmod omap44xx_timer8_hwmod;
4699 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4700 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4701 { .irq = -1 }
4702 };
4704 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4705 {
4706 .pa_start = 0x4013e000,
4707 .pa_end = 0x4013e07f,
4708 .flags = ADDR_TYPE_RT
4709 },
4710 { }
4711 };
4713 /* l4_abe -> timer8 */
4714 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4715 .master = &omap44xx_l4_abe_hwmod,
4716 .slave = &omap44xx_timer8_hwmod,
4717 .clk = "ocp_abe_iclk",
4718 .addr = omap44xx_timer8_addrs,
4719 .user = OCP_USER_MPU,
4720 };
4722 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4723 {
4724 .pa_start = 0x4903e000,
4725 .pa_end = 0x4903e07f,
4726 .flags = ADDR_TYPE_RT
4727 },
4728 { }
4729 };
4731 /* l4_abe -> timer8 (dma) */
4732 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4733 .master = &omap44xx_l4_abe_hwmod,
4734 .slave = &omap44xx_timer8_hwmod,
4735 .clk = "ocp_abe_iclk",
4736 .addr = omap44xx_timer8_dma_addrs,
4737 .user = OCP_USER_SDMA,
4738 };
4740 /* timer8 slave ports */
4741 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4742 &omap44xx_l4_abe__timer8,
4743 &omap44xx_l4_abe__timer8_dma,
4744 };
4746 static struct omap_hwmod omap44xx_timer8_hwmod = {
4747 .name = "timer8",
4748 .class = &omap44xx_timer_hwmod_class,
4749 .clkdm_name = "abe_clkdm",
4750 .mpu_irqs = omap44xx_timer8_irqs,
4751 .main_clk = "timer8_fck",
4752 .prcm = {
4753 .omap4 = {
4754 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
4755 .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
4756 .modulemode = MODULEMODE_SWCTRL,
4757 },
4758 },
4759 .dev_attr = &capability_pwm_dev_attr,
4760 .slaves = omap44xx_timer8_slaves,
4761 .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
4762 };
4764 /* timer9 */
4765 static struct omap_hwmod omap44xx_timer9_hwmod;
4766 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4767 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4768 { .irq = -1 }
4769 };
4771 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4772 {
4773 .pa_start = 0x4803e000,
4774 .pa_end = 0x4803e07f,
4775 .flags = ADDR_TYPE_RT
4776 },
4777 { }
4778 };
4780 /* l4_per -> timer9 */
4781 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4782 .master = &omap44xx_l4_per_hwmod,
4783 .slave = &omap44xx_timer9_hwmod,
4784 .clk = "l4_div_ck",
4785 .addr = omap44xx_timer9_addrs,
4786 .user = OCP_USER_MPU | OCP_USER_SDMA,
4787 };
4789 /* timer9 slave ports */
4790 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4791 &omap44xx_l4_per__timer9,
4792 };
4794 static struct omap_hwmod omap44xx_timer9_hwmod = {
4795 .name = "timer9",
4796 .class = &omap44xx_timer_hwmod_class,
4797 .clkdm_name = "l4_per_clkdm",
4798 .mpu_irqs = omap44xx_timer9_irqs,
4799 .main_clk = "timer9_fck",
4800 .prcm = {
4801 .omap4 = {
4802 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
4803 .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
4804 .modulemode = MODULEMODE_SWCTRL,
4805 },
4806 },
4807 .dev_attr = &capability_pwm_dev_attr,
4808 .slaves = omap44xx_timer9_slaves,
4809 .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
4810 };
4812 /* timer10 */
4813 static struct omap_hwmod omap44xx_timer10_hwmod;
4814 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4815 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4816 { .irq = -1 }
4817 };
4819 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4820 {
4821 .pa_start = 0x48086000,
4822 .pa_end = 0x4808607f,
4823 .flags = ADDR_TYPE_RT
4824 },
4825 { }
4826 };
4828 /* l4_per -> timer10 */
4829 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4830 .master = &omap44xx_l4_per_hwmod,
4831 .slave = &omap44xx_timer10_hwmod,
4832 .clk = "l4_div_ck",
4833 .addr = omap44xx_timer10_addrs,
4834 .user = OCP_USER_MPU | OCP_USER_SDMA,
4835 };
4837 /* timer10 slave ports */
4838 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4839 &omap44xx_l4_per__timer10,
4840 };
4842 static struct omap_hwmod omap44xx_timer10_hwmod = {
4843 .name = "timer10",
4844 .class = &omap44xx_timer_1ms_hwmod_class,
4845 .clkdm_name = "l4_per_clkdm",
4846 .mpu_irqs = omap44xx_timer10_irqs,
4847 .main_clk = "timer10_fck",
4848 .prcm = {
4849 .omap4 = {
4850 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
4851 .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
4852 .modulemode = MODULEMODE_SWCTRL,
4853 },
4854 },
4855 .dev_attr = &capability_pwm_dev_attr,
4856 .slaves = omap44xx_timer10_slaves,
4857 .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
4858 };
4860 /* timer11 */
4861 static struct omap_hwmod omap44xx_timer11_hwmod;
4862 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4863 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4864 { .irq = -1 }
4865 };
4867 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4868 {
4869 .pa_start = 0x48088000,
4870 .pa_end = 0x4808807f,
4871 .flags = ADDR_TYPE_RT
4872 },
4873 { }
4874 };
4876 /* l4_per -> timer11 */
4877 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4878 .master = &omap44xx_l4_per_hwmod,
4879 .slave = &omap44xx_timer11_hwmod,
4880 .clk = "l4_div_ck",
4881 .addr = omap44xx_timer11_addrs,
4882 .user = OCP_USER_MPU | OCP_USER_SDMA,
4883 };
4885 /* timer11 slave ports */
4886 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4887 &omap44xx_l4_per__timer11,
4888 };
4890 static struct omap_hwmod omap44xx_timer11_hwmod = {
4891 .name = "timer11",
4892 .class = &omap44xx_timer_hwmod_class,
4893 .clkdm_name = "l4_per_clkdm",
4894 .mpu_irqs = omap44xx_timer11_irqs,
4895 .main_clk = "timer11_fck",
4896 .prcm = {
4897 .omap4 = {
4898 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
4899 .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
4900 .modulemode = MODULEMODE_SWCTRL,
4901 },
4902 },
4903 .dev_attr = &capability_pwm_dev_attr,
4904 .slaves = omap44xx_timer11_slaves,
4905 .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
4906 };
4908 /*
4909 * 'uart' class
4910 * universal asynchronous receiver/transmitter (uart)
4911 */
4913 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4914 .rev_offs = 0x0050,
4915 .sysc_offs = 0x0054,
4916 .syss_offs = 0x0058,
4917 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4918 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4919 SYSS_HAS_RESET_STATUS),
4920 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4921 SIDLE_SMART_WKUP),
4922 .sysc_fields = &omap_hwmod_sysc_type1,
4923 };
4925 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4926 .name = "uart",
4927 .sysc = &omap44xx_uart_sysc,
4928 };
4930 /* uart1 */
4931 static struct omap_hwmod omap44xx_uart1_hwmod;
4932 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4933 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4934 { .irq = -1 }
4935 };
4937 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4938 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4939 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4940 { .dma_req = -1 }
4941 };
4943 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4944 {
4945 .pa_start = 0x4806a000,
4946 .pa_end = 0x4806a0ff,
4947 .flags = ADDR_TYPE_RT
4948 },
4949 { }
4950 };
4952 /* l4_per -> uart1 */
4953 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4954 .master = &omap44xx_l4_per_hwmod,
4955 .slave = &omap44xx_uart1_hwmod,
4956 .clk = "l4_div_ck",
4957 .addr = omap44xx_uart1_addrs,
4958 .user = OCP_USER_MPU | OCP_USER_SDMA,
4959 };
4961 /* uart1 slave ports */
4962 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4963 &omap44xx_l4_per__uart1,
4964 };
4966 static struct omap_hwmod omap44xx_uart1_hwmod = {
4967 .name = "uart1",
4968 .class = &omap44xx_uart_hwmod_class,
4969 .clkdm_name = "l4_per_clkdm",
4970 .mpu_irqs = omap44xx_uart1_irqs,
4971 .sdma_reqs = omap44xx_uart1_sdma_reqs,
4972 .main_clk = "uart1_fck",
4973 .prcm = {
4974 .omap4 = {
4975 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
4976 .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
4977 .modulemode = MODULEMODE_SWCTRL,
4978 },
4979 },
4980 .slaves = omap44xx_uart1_slaves,
4981 .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
4982 };
4984 /* uart2 */
4985 static struct omap_hwmod omap44xx_uart2_hwmod;
4986 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4987 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4988 { .irq = -1 }
4989 };
4991 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4992 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4993 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4994 { .dma_req = -1 }
4995 };
4997 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4998 {
4999 .pa_start = 0x4806c000,
5000 .pa_end = 0x4806c0ff,
5001 .flags = ADDR_TYPE_RT
5002 },
5003 { }
5004 };
5006 /* l4_per -> uart2 */
5007 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
5008 .master = &omap44xx_l4_per_hwmod,
5009 .slave = &omap44xx_uart2_hwmod,
5010 .clk = "l4_div_ck",
5011 .addr = omap44xx_uart2_addrs,
5012 .user = OCP_USER_MPU | OCP_USER_SDMA,
5013 };
5015 /* uart2 slave ports */
5016 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
5017 &omap44xx_l4_per__uart2,
5018 };
5020 static struct omap_hwmod omap44xx_uart2_hwmod = {
5021 .name = "uart2",
5022 .class = &omap44xx_uart_hwmod_class,
5023 .clkdm_name = "l4_per_clkdm",
5024 .mpu_irqs = omap44xx_uart2_irqs,
5025 .sdma_reqs = omap44xx_uart2_sdma_reqs,
5026 .main_clk = "uart2_fck",
5027 .prcm = {
5028 .omap4 = {
5029 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
5030 .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
5031 .modulemode = MODULEMODE_SWCTRL,
5032 },
5033 },
5034 .slaves = omap44xx_uart2_slaves,
5035 .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
5036 };
5038 /* uart3 */
5039 static struct omap_hwmod omap44xx_uart3_hwmod;
5040 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
5041 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
5042 { .irq = -1 }
5043 };
5045 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
5046 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
5047 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
5048 { .dma_req = -1 }
5049 };
5051 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
5052 {
5053 .pa_start = 0x48020000,
5054 .pa_end = 0x480200ff,
5055 .flags = ADDR_TYPE_RT
5056 },
5057 { }
5058 };
5060 /* l4_per -> uart3 */
5061 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
5062 .master = &omap44xx_l4_per_hwmod,
5063 .slave = &omap44xx_uart3_hwmod,
5064 .clk = "l4_div_ck",
5065 .addr = omap44xx_uart3_addrs,
5066 .user = OCP_USER_MPU | OCP_USER_SDMA,
5067 };
5069 /* uart3 slave ports */
5070 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
5071 &omap44xx_l4_per__uart3,
5072 };
5074 static struct omap_hwmod omap44xx_uart3_hwmod = {
5075 .name = "uart3",
5076 .class = &omap44xx_uart_hwmod_class,
5077 .clkdm_name = "l4_per_clkdm",
5078 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
5079 .mpu_irqs = omap44xx_uart3_irqs,
5080 .sdma_reqs = omap44xx_uart3_sdma_reqs,
5081 .main_clk = "uart3_fck",
5082 .prcm = {
5083 .omap4 = {
5084 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
5085 .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
5086 .modulemode = MODULEMODE_SWCTRL,
5087 },
5088 },
5089 .slaves = omap44xx_uart3_slaves,
5090 .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
5091 };
5093 /* uart4 */
5094 static struct omap_hwmod omap44xx_uart4_hwmod;
5095 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
5096 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
5097 { .irq = -1 }
5098 };
5100 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
5101 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
5102 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
5103 { .dma_req = -1 }
5104 };
5106 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5107 {
5108 .pa_start = 0x4806e000,
5109 .pa_end = 0x4806e0ff,
5110 .flags = ADDR_TYPE_RT
5111 },
5112 { }
5113 };
5115 /* l4_per -> uart4 */
5116 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5117 .master = &omap44xx_l4_per_hwmod,
5118 .slave = &omap44xx_uart4_hwmod,
5119 .clk = "l4_div_ck",
5120 .addr = omap44xx_uart4_addrs,
5121 .user = OCP_USER_MPU | OCP_USER_SDMA,
5122 };
5124 /* uart4 slave ports */
5125 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
5126 &omap44xx_l4_per__uart4,
5127 };
5129 static struct omap_hwmod omap44xx_uart4_hwmod = {
5130 .name = "uart4",
5131 .class = &omap44xx_uart_hwmod_class,
5132 .clkdm_name = "l4_per_clkdm",
5133 .mpu_irqs = omap44xx_uart4_irqs,
5134 .sdma_reqs = omap44xx_uart4_sdma_reqs,
5135 .main_clk = "uart4_fck",
5136 .prcm = {
5137 .omap4 = {
5138 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
5139 .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
5140 .modulemode = MODULEMODE_SWCTRL,
5141 },
5142 },
5143 .slaves = omap44xx_uart4_slaves,
5144 .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
5145 };
5147 /*
5148 * 'usb_otg_hs' class
5149 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
5150 */
5152 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
5153 .rev_offs = 0x0400,
5154 .sysc_offs = 0x0404,
5155 .syss_offs = 0x0408,
5156 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
5157 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
5158 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5159 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5160 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5161 MSTANDBY_SMART),
5162 .sysc_fields = &omap_hwmod_sysc_type1,
5163 };
5165 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
5166 .name = "usb_otg_hs",
5167 .sysc = &omap44xx_usb_otg_hs_sysc,
5168 };
5170 /* usb_otg_hs */
5171 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
5172 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
5173 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
5174 { .irq = -1 }
5175 };
5177 /* usb_otg_hs master ports */
5178 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
5179 &omap44xx_usb_otg_hs__l3_main_2,
5180 };
5182 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5183 {
5184 .pa_start = 0x4a0ab000,
5185 .pa_end = 0x4a0ab003,
5186 .flags = ADDR_TYPE_RT
5187 },
5188 { }
5189 };
5191 /* l4_cfg -> usb_otg_hs */
5192 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5193 .master = &omap44xx_l4_cfg_hwmod,
5194 .slave = &omap44xx_usb_otg_hs_hwmod,
5195 .clk = "l4_div_ck",
5196 .addr = omap44xx_usb_otg_hs_addrs,
5197 .user = OCP_USER_MPU | OCP_USER_SDMA,
5198 };
5200 /* usb_otg_hs slave ports */
5201 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
5202 &omap44xx_l4_cfg__usb_otg_hs,
5203 };
5205 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
5206 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
5207 };
5209 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
5210 .name = "usb_otg_hs",
5211 .class = &omap44xx_usb_otg_hs_hwmod_class,
5212 .clkdm_name = "l3_init_clkdm",
5213 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
5214 .mpu_irqs = omap44xx_usb_otg_hs_irqs,
5215 .main_clk = "usb_otg_hs_ick",
5216 .prcm = {
5217 .omap4 = {
5218 .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
5219 .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
5220 .modulemode = MODULEMODE_HWCTRL,
5221 },
5222 },
5223 .opt_clks = usb_otg_hs_opt_clks,
5224 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
5225 .slaves = omap44xx_usb_otg_hs_slaves,
5226 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
5227 .masters = omap44xx_usb_otg_hs_masters,
5228 .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
5229 };
5231 /*
5232 * 'wd_timer' class
5233 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
5234 * overflow condition
5235 */
5237 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
5238 .rev_offs = 0x0000,
5239 .sysc_offs = 0x0010,
5240 .syss_offs = 0x0014,
5241 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
5242 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5243 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5244 SIDLE_SMART_WKUP),
5245 .sysc_fields = &omap_hwmod_sysc_type1,
5246 };
5248 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
5249 .name = "wd_timer",
5250 .sysc = &omap44xx_wd_timer_sysc,
5251 .pre_shutdown = &omap2_wd_timer_disable,
5252 };
5254 /* wd_timer2 */
5255 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
5256 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
5257 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
5258 { .irq = -1 }
5259 };
5261 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5262 {
5263 .pa_start = 0x4a314000,
5264 .pa_end = 0x4a31407f,
5265 .flags = ADDR_TYPE_RT
5266 },
5267 { }
5268 };
5270 /* l4_wkup -> wd_timer2 */
5271 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5272 .master = &omap44xx_l4_wkup_hwmod,
5273 .slave = &omap44xx_wd_timer2_hwmod,
5274 .clk = "l4_wkup_clk_mux_ck",
5275 .addr = omap44xx_wd_timer2_addrs,
5276 .user = OCP_USER_MPU | OCP_USER_SDMA,
5277 };
5279 /* wd_timer2 slave ports */
5280 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
5281 &omap44xx_l4_wkup__wd_timer2,
5282 };
5284 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
5285 .name = "wd_timer2",
5286 .class = &omap44xx_wd_timer_hwmod_class,
5287 .clkdm_name = "l4_wkup_clkdm",
5288 .mpu_irqs = omap44xx_wd_timer2_irqs,
5289 .main_clk = "wd_timer2_fck",
5290 .prcm = {
5291 .omap4 = {
5292 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
5293 .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
5294 .modulemode = MODULEMODE_SWCTRL,
5295 },
5296 },
5297 .slaves = omap44xx_wd_timer2_slaves,
5298 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
5299 };
5301 /* wd_timer3 */
5302 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
5303 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
5304 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
5305 { .irq = -1 }
5306 };
5308 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5309 {
5310 .pa_start = 0x40130000,
5311 .pa_end = 0x4013007f,
5312 .flags = ADDR_TYPE_RT
5313 },
5314 { }
5315 };
5317 /* l4_abe -> wd_timer3 */
5318 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5319 .master = &omap44xx_l4_abe_hwmod,
5320 .slave = &omap44xx_wd_timer3_hwmod,
5321 .clk = "ocp_abe_iclk",
5322 .addr = omap44xx_wd_timer3_addrs,
5323 .user = OCP_USER_MPU,
5324 };
5326 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5327 {
5328 .pa_start = 0x49030000,
5329 .pa_end = 0x4903007f,
5330 .flags = ADDR_TYPE_RT
5331 },
5332 { }
5333 };
5335 /* l4_abe -> wd_timer3 (dma) */
5336 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5337 .master = &omap44xx_l4_abe_hwmod,
5338 .slave = &omap44xx_wd_timer3_hwmod,
5339 .clk = "ocp_abe_iclk",
5340 .addr = omap44xx_wd_timer3_dma_addrs,
5341 .user = OCP_USER_SDMA,
5342 };
5344 /* wd_timer3 slave ports */
5345 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5346 &omap44xx_l4_abe__wd_timer3,
5347 &omap44xx_l4_abe__wd_timer3_dma,
5348 };
5350 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5351 .name = "wd_timer3",
5352 .class = &omap44xx_wd_timer_hwmod_class,
5353 .clkdm_name = "abe_clkdm",
5354 .mpu_irqs = omap44xx_wd_timer3_irqs,
5355 .main_clk = "wd_timer3_fck",
5356 .prcm = {
5357 .omap4 = {
5358 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
5359 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
5360 .modulemode = MODULEMODE_SWCTRL,
5361 },
5362 },
5363 .slaves = omap44xx_wd_timer3_slaves,
5364 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
5365 };
5367 /*
5368 * 'usb_host_hs' class
5369 * high-speed multi-port usb host controller
5370 */
5371 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
5372 .master = &omap44xx_usb_host_hs_hwmod,
5373 .slave = &omap44xx_l3_main_2_hwmod,
5374 .clk = "l3_div_ck",
5375 .user = OCP_USER_MPU | OCP_USER_SDMA,
5376 };
5378 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
5379 .rev_offs = 0x0000,
5380 .sysc_offs = 0x0010,
5381 .syss_offs = 0x0014,
5382 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
5383 SYSC_HAS_SOFTRESET),
5384 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5385 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5386 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
5387 .sysc_fields = &omap_hwmod_sysc_type2,
5388 };
5390 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
5391 .name = "usb_host_hs",
5392 .sysc = &omap44xx_usb_host_hs_sysc,
5393 };
5395 static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = {
5396 &omap44xx_usb_host_hs__l3_main_2,
5397 };
5399 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
5400 {
5401 .name = "uhh",
5402 .pa_start = 0x4a064000,
5403 .pa_end = 0x4a0647ff,
5404 .flags = ADDR_TYPE_RT
5405 },
5406 {
5407 .name = "ohci",
5408 .pa_start = 0x4a064800,
5409 .pa_end = 0x4a064bff,
5410 },
5411 {
5412 .name = "ehci",
5413 .pa_start = 0x4a064c00,
5414 .pa_end = 0x4a064fff,
5415 },
5416 {}
5417 };
5419 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
5420 { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
5421 { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
5422 { .irq = -1 }
5423 };
5425 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5426 .master = &omap44xx_l4_cfg_hwmod,
5427 .slave = &omap44xx_usb_host_hs_hwmod,
5428 .clk = "l4_div_ck",
5429 .addr = omap44xx_usb_host_hs_addrs,
5430 .user = OCP_USER_MPU | OCP_USER_SDMA,
5431 };
5433 static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = {
5434 &omap44xx_l4_cfg__usb_host_hs,
5435 };
5437 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
5438 .name = "usb_host_hs",
5439 .class = &omap44xx_usb_host_hs_hwmod_class,
5440 .clkdm_name = "l3_init_clkdm",
5441 .main_clk = "usb_host_hs_fck",
5442 .prcm = {
5443 .omap4 = {
5444 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
5445 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
5446 .modulemode = MODULEMODE_SWCTRL,
5447 },
5448 },
5449 .mpu_irqs = omap44xx_usb_host_hs_irqs,
5450 .slaves = omap44xx_usb_host_hs_slaves,
5451 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_slaves),
5452 .masters = omap44xx_usb_host_hs_masters,
5453 .masters_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_masters),
5455 /*
5456 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
5457 * id: i660
5458 *
5459 * Description:
5460 * In the following configuration :
5461 * - USBHOST module is set to smart-idle mode
5462 * - PRCM asserts idle_req to the USBHOST module ( This typically
5463 * happens when the system is going to a low power mode : all ports
5464 * have been suspended, the master part of the USBHOST module has
5465 * entered the standby state, and SW has cut the functional clocks)
5466 * - an USBHOST interrupt occurs before the module is able to answer
5467 * idle_ack, typically a remote wakeup IRQ.
5468 * Then the USB HOST module will enter a deadlock situation where it
5469 * is no more accessible nor functional.
5470 *
5471 * Workaround:
5472 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
5473 */
5475 /*
5476 * Errata: USB host EHCI may stall when entering smart-standby mode
5477 * Id: i571
5478 *
5479 * Description:
5480 * When the USBHOST module is set to smart-standby mode, and when it is
5481 * ready to enter the standby state (i.e. all ports are suspended and
5482 * all attached devices are in suspend mode), then it can wrongly assert
5483 * the Mstandby signal too early while there are still some residual OCP
5484 * transactions ongoing. If this condition occurs, the internal state
5485 * machine may go to an undefined state and the USB link may be stuck
5486 * upon the next resume.
5487 *
5488 * Workaround:
5489 * Don't use smart standby; use only force standby,
5490 * hence HWMOD_SWSUP_MSTANDBY
5491 */
5493 /*
5494 * During system boot; If the hwmod framework resets the module
5495 * the module will have smart idle settings; which can lead to deadlock
5496 * (above Errata Id:i660); so, dont reset the module during boot;
5497 * Use HWMOD_INIT_NO_RESET.
5498 */
5500 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
5501 HWMOD_INIT_NO_RESET,
5502 };
5504 /*
5505 * 'usb_tll_hs' class
5506 * usb_tll_hs module is the adapter on the usb_host_hs ports
5507 */
5508 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
5509 .rev_offs = 0x0000,
5510 .sysc_offs = 0x0010,
5511 .syss_offs = 0x0014,
5512 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
5513 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
5514 SYSC_HAS_AUTOIDLE),
5515 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
5516 .sysc_fields = &omap_hwmod_sysc_type1,
5517 };
5519 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
5520 .name = "usb_tll_hs",
5521 .sysc = &omap44xx_usb_tll_hs_sysc,
5522 };
5524 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
5525 { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
5526 { .irq = -1 }
5527 };
5529 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
5530 {
5531 .name = "tll",
5532 .pa_start = 0x4a062000,
5533 .pa_end = 0x4a063fff,
5534 .flags = ADDR_TYPE_RT
5535 },
5536 {}
5537 };
5539 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5540 .master = &omap44xx_l4_cfg_hwmod,
5541 .slave = &omap44xx_usb_tll_hs_hwmod,
5542 .clk = "l4_div_ck",
5543 .addr = omap44xx_usb_tll_hs_addrs,
5544 .user = OCP_USER_MPU | OCP_USER_SDMA,
5545 };
5547 static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = {
5548 &omap44xx_l4_cfg__usb_tll_hs,
5549 };
5551 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
5552 .name = "usb_tll_hs",
5553 .class = &omap44xx_usb_tll_hs_hwmod_class,
5554 .clkdm_name = "l3_init_clkdm",
5555 .main_clk = "usb_tll_hs_ick",
5556 .prcm = {
5557 .omap4 = {
5558 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
5559 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
5560 .modulemode = MODULEMODE_HWCTRL,
5561 },
5562 },
5563 .mpu_irqs = omap44xx_usb_tll_hs_irqs,
5564 .slaves = omap44xx_usb_tll_hs_slaves,
5565 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves),
5566 };
5568 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5570 /* dmm class */
5571 &omap44xx_dmm_hwmod,
5573 /* emif_fw class */
5574 &omap44xx_emif_fw_hwmod,
5576 /* l3 class */
5577 &omap44xx_l3_instr_hwmod,
5578 &omap44xx_l3_main_1_hwmod,
5579 &omap44xx_l3_main_2_hwmod,
5580 &omap44xx_l3_main_3_hwmod,
5582 /* l4 class */
5583 &omap44xx_l4_abe_hwmod,
5584 &omap44xx_l4_cfg_hwmod,
5585 &omap44xx_l4_per_hwmod,
5586 &omap44xx_l4_wkup_hwmod,
5588 /* mpu_bus class */
5589 &omap44xx_mpu_private_hwmod,
5591 /* aess class */
5592 /* &omap44xx_aess_hwmod, */
5594 /* bandgap class */
5595 &omap44xx_bandgap_hwmod,
5597 /* counter class */
5598 /* &omap44xx_counter_32k_hwmod, */
5600 /* dma class */
5601 &omap44xx_dma_system_hwmod,
5603 /* dmic class */
5604 &omap44xx_dmic_hwmod,
5606 /* dsp class */
5607 &omap44xx_dsp_hwmod,
5608 &omap44xx_dsp_c0_hwmod,
5610 /* dss class */
5611 &omap44xx_dss_hwmod,
5612 &omap44xx_dss_dispc_hwmod,
5613 &omap44xx_dss_dsi1_hwmod,
5614 &omap44xx_dss_dsi2_hwmod,
5615 &omap44xx_dss_hdmi_hwmod,
5616 &omap44xx_dss_rfbi_hwmod,
5617 &omap44xx_dss_venc_hwmod,
5619 /* fdif class */
5620 &omap44xx_fdif_hwmod,
5622 /* gpio class */
5623 &omap44xx_gpio1_hwmod,
5624 &omap44xx_gpio2_hwmod,
5625 &omap44xx_gpio3_hwmod,
5626 &omap44xx_gpio4_hwmod,
5627 &omap44xx_gpio5_hwmod,
5628 &omap44xx_gpio6_hwmod,
5630 /* hsi class */
5631 /* &omap44xx_hsi_hwmod, */
5633 /* i2c class */
5634 &omap44xx_i2c1_hwmod,
5635 &omap44xx_i2c2_hwmod,
5636 &omap44xx_i2c3_hwmod,
5637 &omap44xx_i2c4_hwmod,
5639 /* ipu class */
5640 &omap44xx_ipu_hwmod,
5641 &omap44xx_ipu_c0_hwmod,
5642 &omap44xx_ipu_c1_hwmod,
5644 /* iss class */
5645 /* &omap44xx_iss_hwmod, */
5647 /* iva class */
5648 &omap44xx_iva_hwmod,
5649 &omap44xx_iva_seq0_hwmod,
5650 &omap44xx_iva_seq1_hwmod,
5652 /* kbd class */
5653 &omap44xx_kbd_hwmod,
5655 /* mailbox class */
5656 &omap44xx_mailbox_hwmod,
5658 /* mcbsp class */
5659 &omap44xx_mcbsp1_hwmod,
5660 &omap44xx_mcbsp2_hwmod,
5661 &omap44xx_mcbsp3_hwmod,
5662 &omap44xx_mcbsp4_hwmod,
5664 /* mcpdm class */
5665 &omap44xx_mcpdm_hwmod,
5667 /* mcspi class */
5668 &omap44xx_mcspi1_hwmod,
5669 &omap44xx_mcspi2_hwmod,
5670 &omap44xx_mcspi3_hwmod,
5671 &omap44xx_mcspi4_hwmod,
5673 /* mmc class */
5674 &omap44xx_mmc1_hwmod,
5675 &omap44xx_mmc2_hwmod,
5676 &omap44xx_mmc3_hwmod,
5677 &omap44xx_mmc4_hwmod,
5678 &omap44xx_mmc5_hwmod,
5680 /* mpu class */
5681 &omap44xx_mpu_hwmod,
5683 /* smartreflex class */
5684 &omap44xx_smartreflex_core_hwmod,
5685 &omap44xx_smartreflex_iva_hwmod,
5686 &omap44xx_smartreflex_mpu_hwmod,
5688 /* spinlock class */
5689 &omap44xx_spinlock_hwmod,
5691 /* timer class */
5692 &omap44xx_timer1_hwmod,
5693 &omap44xx_timer2_hwmod,
5694 &omap44xx_timer3_hwmod,
5695 &omap44xx_timer4_hwmod,
5696 &omap44xx_timer5_hwmod,
5697 &omap44xx_timer6_hwmod,
5698 &omap44xx_timer7_hwmod,
5699 &omap44xx_timer8_hwmod,
5700 &omap44xx_timer9_hwmod,
5701 &omap44xx_timer10_hwmod,
5702 &omap44xx_timer11_hwmod,
5704 /* uart class */
5705 &omap44xx_uart1_hwmod,
5706 &omap44xx_uart2_hwmod,
5707 &omap44xx_uart3_hwmod,
5708 &omap44xx_uart4_hwmod,
5710 /* usb host class */
5711 &omap44xx_usb_host_hs_hwmod,
5712 &omap44xx_usb_tll_hs_hwmod,
5714 /* usb_otg_hs class */
5715 &omap44xx_usb_otg_hs_hwmod,
5717 /* wd_timer class */
5718 &omap44xx_wd_timer2_hwmod,
5719 &omap44xx_wd_timer3_hwmod,
5720 NULL,
5721 };
5723 int __init omap44xx_hwmod_init(void)
5724 {
5725 return omap_hwmod_register(omap44xx_hwmods);
5726 }