OMAP4: hwmod data: Add modulemode entry in omap_hwmod structure
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / omap_hwmod_44xx_data.c
1 /*
2  * Hardware modules present on the OMAP44xx chips
3  *
4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
5  * Copyright (C) 2009-2010 Nokia Corporation
6  *
7  * Paul Walmsley
8  * Benoit Cousson
9  *
10  * This file is automatically generated from the OMAP hardware databases.
11  * We respectfully ask that any modifications to this file be coordinated
12  * with the public linux-omap@vger.kernel.org mailing list and the
13  * authors above to ensure that the autogeneration scripts are kept
14  * up-to-date with the file contents.
15  *
16  * This program is free software; you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License version 2 as
18  * published by the Free Software Foundation.
19  */
21 #include <linux/io.h>
23 #include <plat/omap_hwmod.h>
24 #include <plat/cpu.h>
25 #include <plat/i2c.h>
26 #include <plat/gpio.h>
27 #include <plat/dma.h>
28 #include <plat/mcspi.h>
29 #include <plat/mcbsp.h>
30 #include <plat/mmc.h>
31 #include <plat/i2c.h>
33 #include "omap_hwmod_common_data.h"
35 #include "cm1_44xx.h"
36 #include "cm2_44xx.h"
37 #include "prm44xx.h"
38 #include "prm-regbits-44xx.h"
39 #include "wd_timer.h"
41 /* Base offset for all OMAP4 interrupts external to MPUSS */
42 #define OMAP44XX_IRQ_GIC_START  32
44 /* Base offset for all OMAP4 dma requests */
45 #define OMAP44XX_DMA_REQ_START  1
47 /* Backward references (IPs with Bus Master capability) */
48 static struct omap_hwmod omap44xx_aess_hwmod;
49 static struct omap_hwmod omap44xx_dma_system_hwmod;
50 static struct omap_hwmod omap44xx_dmm_hwmod;
51 static struct omap_hwmod omap44xx_dsp_hwmod;
52 static struct omap_hwmod omap44xx_dss_hwmod;
53 static struct omap_hwmod omap44xx_emif_fw_hwmod;
54 static struct omap_hwmod omap44xx_hsi_hwmod;
55 static struct omap_hwmod omap44xx_ipu_hwmod;
56 static struct omap_hwmod omap44xx_iss_hwmod;
57 static struct omap_hwmod omap44xx_iva_hwmod;
58 static struct omap_hwmod omap44xx_l3_instr_hwmod;
59 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
60 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
61 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
62 static struct omap_hwmod omap44xx_l4_abe_hwmod;
63 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
64 static struct omap_hwmod omap44xx_l4_per_hwmod;
65 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
66 static struct omap_hwmod omap44xx_mmc1_hwmod;
67 static struct omap_hwmod omap44xx_mmc2_hwmod;
68 static struct omap_hwmod omap44xx_mpu_hwmod;
69 static struct omap_hwmod omap44xx_mpu_private_hwmod;
70 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
72 /*
73  * Interconnects omap_hwmod structures
74  * hwmods that compose the global OMAP interconnect
75  */
77 /*
78  * 'dmm' class
79  * instance(s): dmm
80  */
81 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
82         .name   = "dmm",
83 };
85 /* dmm */
86 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
87         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
88         { .irq = -1 }
89 };
91 /* l3_main_1 -> dmm */
92 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
93         .master         = &omap44xx_l3_main_1_hwmod,
94         .slave          = &omap44xx_dmm_hwmod,
95         .clk            = "l3_div_ck",
96         .user           = OCP_USER_SDMA,
97 };
99 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
100         {
101                 .pa_start       = 0x4e000000,
102                 .pa_end         = 0x4e0007ff,
103                 .flags          = ADDR_TYPE_RT
104         },
105         { }
106 };
108 /* mpu -> dmm */
109 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
110         .master         = &omap44xx_mpu_hwmod,
111         .slave          = &omap44xx_dmm_hwmod,
112         .clk            = "l3_div_ck",
113         .addr           = omap44xx_dmm_addrs,
114         .user           = OCP_USER_MPU,
115 };
117 /* dmm slave ports */
118 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
119         &omap44xx_l3_main_1__dmm,
120         &omap44xx_mpu__dmm,
121 };
123 static struct omap_hwmod omap44xx_dmm_hwmod = {
124         .name           = "dmm",
125         .class          = &omap44xx_dmm_hwmod_class,
126         .clkdm_name     = "l3_emif_clkdm",
127         .prcm = {
128                 .omap4 = {
129                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
130                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
131                 },
132         },
133         .slaves         = omap44xx_dmm_slaves,
134         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
135         .mpu_irqs       = omap44xx_dmm_irqs,
136         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
137 };
139 /*
140  * 'emif_fw' class
141  * instance(s): emif_fw
142  */
143 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
144         .name   = "emif_fw",
145 };
147 /* emif_fw */
148 /* dmm -> emif_fw */
149 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
150         .master         = &omap44xx_dmm_hwmod,
151         .slave          = &omap44xx_emif_fw_hwmod,
152         .clk            = "l3_div_ck",
153         .user           = OCP_USER_MPU | OCP_USER_SDMA,
154 };
156 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
157         {
158                 .pa_start       = 0x4a20c000,
159                 .pa_end         = 0x4a20c0ff,
160                 .flags          = ADDR_TYPE_RT
161         },
162         { }
163 };
165 /* l4_cfg -> emif_fw */
166 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
167         .master         = &omap44xx_l4_cfg_hwmod,
168         .slave          = &omap44xx_emif_fw_hwmod,
169         .clk            = "l4_div_ck",
170         .addr           = omap44xx_emif_fw_addrs,
171         .user           = OCP_USER_MPU,
172 };
174 /* emif_fw slave ports */
175 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
176         &omap44xx_dmm__emif_fw,
177         &omap44xx_l4_cfg__emif_fw,
178 };
180 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
181         .name           = "emif_fw",
182         .class          = &omap44xx_emif_fw_hwmod_class,
183         .clkdm_name     = "l3_emif_clkdm",
184         .prcm = {
185                 .omap4 = {
186                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
187                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
188                 },
189         },
190         .slaves         = omap44xx_emif_fw_slaves,
191         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
192         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
193 };
195 /*
196  * 'l3' class
197  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
198  */
199 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
200         .name   = "l3",
201 };
203 /* l3_instr */
204 /* iva -> l3_instr */
205 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
206         .master         = &omap44xx_iva_hwmod,
207         .slave          = &omap44xx_l3_instr_hwmod,
208         .clk            = "l3_div_ck",
209         .user           = OCP_USER_MPU | OCP_USER_SDMA,
210 };
212 /* l3_main_3 -> l3_instr */
213 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
214         .master         = &omap44xx_l3_main_3_hwmod,
215         .slave          = &omap44xx_l3_instr_hwmod,
216         .clk            = "l3_div_ck",
217         .user           = OCP_USER_MPU | OCP_USER_SDMA,
218 };
220 /* l3_instr slave ports */
221 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
222         &omap44xx_iva__l3_instr,
223         &omap44xx_l3_main_3__l3_instr,
224 };
226 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
227         .name           = "l3_instr",
228         .class          = &omap44xx_l3_hwmod_class,
229         .clkdm_name     = "l3_instr_clkdm",
230         .prcm = {
231                 .omap4 = {
232                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
233                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
234                         .modulemode   = MODULEMODE_HWCTRL,
235                 },
236         },
237         .slaves         = omap44xx_l3_instr_slaves,
238         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
239         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
240 };
242 /* l3_main_1 */
243 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
244         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
245         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
246         { .irq = -1 }
247 };
249 /* dsp -> l3_main_1 */
250 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
251         .master         = &omap44xx_dsp_hwmod,
252         .slave          = &omap44xx_l3_main_1_hwmod,
253         .clk            = "l3_div_ck",
254         .user           = OCP_USER_MPU | OCP_USER_SDMA,
255 };
257 /* dss -> l3_main_1 */
258 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
259         .master         = &omap44xx_dss_hwmod,
260         .slave          = &omap44xx_l3_main_1_hwmod,
261         .clk            = "l3_div_ck",
262         .user           = OCP_USER_MPU | OCP_USER_SDMA,
263 };
265 /* l3_main_2 -> l3_main_1 */
266 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
267         .master         = &omap44xx_l3_main_2_hwmod,
268         .slave          = &omap44xx_l3_main_1_hwmod,
269         .clk            = "l3_div_ck",
270         .user           = OCP_USER_MPU | OCP_USER_SDMA,
271 };
273 /* l4_cfg -> l3_main_1 */
274 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
275         .master         = &omap44xx_l4_cfg_hwmod,
276         .slave          = &omap44xx_l3_main_1_hwmod,
277         .clk            = "l4_div_ck",
278         .user           = OCP_USER_MPU | OCP_USER_SDMA,
279 };
281 /* mmc1 -> l3_main_1 */
282 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
283         .master         = &omap44xx_mmc1_hwmod,
284         .slave          = &omap44xx_l3_main_1_hwmod,
285         .clk            = "l3_div_ck",
286         .user           = OCP_USER_MPU | OCP_USER_SDMA,
287 };
289 /* mmc2 -> l3_main_1 */
290 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
291         .master         = &omap44xx_mmc2_hwmod,
292         .slave          = &omap44xx_l3_main_1_hwmod,
293         .clk            = "l3_div_ck",
294         .user           = OCP_USER_MPU | OCP_USER_SDMA,
295 };
297 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
298         {
299                 .pa_start       = 0x44000000,
300                 .pa_end         = 0x44000fff,
301                 .flags          = ADDR_TYPE_RT
302         },
303         { }
304 };
306 /* mpu -> l3_main_1 */
307 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
308         .master         = &omap44xx_mpu_hwmod,
309         .slave          = &omap44xx_l3_main_1_hwmod,
310         .clk            = "l3_div_ck",
311         .addr           = omap44xx_l3_main_1_addrs,
312         .user           = OCP_USER_MPU,
313 };
315 /* l3_main_1 slave ports */
316 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
317         &omap44xx_dsp__l3_main_1,
318         &omap44xx_dss__l3_main_1,
319         &omap44xx_l3_main_2__l3_main_1,
320         &omap44xx_l4_cfg__l3_main_1,
321         &omap44xx_mmc1__l3_main_1,
322         &omap44xx_mmc2__l3_main_1,
323         &omap44xx_mpu__l3_main_1,
324 };
326 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
327         .name           = "l3_main_1",
328         .class          = &omap44xx_l3_hwmod_class,
329         .clkdm_name     = "l3_1_clkdm",
330         .mpu_irqs       = omap44xx_l3_main_1_irqs,
331         .prcm = {
332                 .omap4 = {
333                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
334                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
335                 },
336         },
337         .slaves         = omap44xx_l3_main_1_slaves,
338         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
339         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
340 };
342 /* l3_main_2 */
343 /* dma_system -> l3_main_2 */
344 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
345         .master         = &omap44xx_dma_system_hwmod,
346         .slave          = &omap44xx_l3_main_2_hwmod,
347         .clk            = "l3_div_ck",
348         .user           = OCP_USER_MPU | OCP_USER_SDMA,
349 };
351 /* hsi -> l3_main_2 */
352 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
353         .master         = &omap44xx_hsi_hwmod,
354         .slave          = &omap44xx_l3_main_2_hwmod,
355         .clk            = "l3_div_ck",
356         .user           = OCP_USER_MPU | OCP_USER_SDMA,
357 };
359 /* ipu -> l3_main_2 */
360 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
361         .master         = &omap44xx_ipu_hwmod,
362         .slave          = &omap44xx_l3_main_2_hwmod,
363         .clk            = "l3_div_ck",
364         .user           = OCP_USER_MPU | OCP_USER_SDMA,
365 };
367 /* iss -> l3_main_2 */
368 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
369         .master         = &omap44xx_iss_hwmod,
370         .slave          = &omap44xx_l3_main_2_hwmod,
371         .clk            = "l3_div_ck",
372         .user           = OCP_USER_MPU | OCP_USER_SDMA,
373 };
375 /* iva -> l3_main_2 */
376 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
377         .master         = &omap44xx_iva_hwmod,
378         .slave          = &omap44xx_l3_main_2_hwmod,
379         .clk            = "l3_div_ck",
380         .user           = OCP_USER_MPU | OCP_USER_SDMA,
381 };
383 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
384         {
385                 .pa_start       = 0x44800000,
386                 .pa_end         = 0x44801fff,
387                 .flags          = ADDR_TYPE_RT
388         },
389         { }
390 };
392 /* l3_main_1 -> l3_main_2 */
393 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
394         .master         = &omap44xx_l3_main_1_hwmod,
395         .slave          = &omap44xx_l3_main_2_hwmod,
396         .clk            = "l3_div_ck",
397         .addr           = omap44xx_l3_main_2_addrs,
398         .user           = OCP_USER_MPU,
399 };
401 /* l4_cfg -> l3_main_2 */
402 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
403         .master         = &omap44xx_l4_cfg_hwmod,
404         .slave          = &omap44xx_l3_main_2_hwmod,
405         .clk            = "l4_div_ck",
406         .user           = OCP_USER_MPU | OCP_USER_SDMA,
407 };
409 /* usb_otg_hs -> l3_main_2 */
410 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
411         .master         = &omap44xx_usb_otg_hs_hwmod,
412         .slave          = &omap44xx_l3_main_2_hwmod,
413         .clk            = "l3_div_ck",
414         .user           = OCP_USER_MPU | OCP_USER_SDMA,
415 };
417 /* l3_main_2 slave ports */
418 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
419         &omap44xx_dma_system__l3_main_2,
420         &omap44xx_hsi__l3_main_2,
421         &omap44xx_ipu__l3_main_2,
422         &omap44xx_iss__l3_main_2,
423         &omap44xx_iva__l3_main_2,
424         &omap44xx_l3_main_1__l3_main_2,
425         &omap44xx_l4_cfg__l3_main_2,
426         &omap44xx_usb_otg_hs__l3_main_2,
427 };
429 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
430         .name           = "l3_main_2",
431         .class          = &omap44xx_l3_hwmod_class,
432         .clkdm_name     = "l3_2_clkdm",
433         .prcm = {
434                 .omap4 = {
435                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
436                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
437                 },
438         },
439         .slaves         = omap44xx_l3_main_2_slaves,
440         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
441         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
442 };
444 /* l3_main_3 */
445 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
446         {
447                 .pa_start       = 0x45000000,
448                 .pa_end         = 0x45000fff,
449                 .flags          = ADDR_TYPE_RT
450         },
451         { }
452 };
454 /* l3_main_1 -> l3_main_3 */
455 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
456         .master         = &omap44xx_l3_main_1_hwmod,
457         .slave          = &omap44xx_l3_main_3_hwmod,
458         .clk            = "l3_div_ck",
459         .addr           = omap44xx_l3_main_3_addrs,
460         .user           = OCP_USER_MPU,
461 };
463 /* l3_main_2 -> l3_main_3 */
464 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
465         .master         = &omap44xx_l3_main_2_hwmod,
466         .slave          = &omap44xx_l3_main_3_hwmod,
467         .clk            = "l3_div_ck",
468         .user           = OCP_USER_MPU | OCP_USER_SDMA,
469 };
471 /* l4_cfg -> l3_main_3 */
472 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
473         .master         = &omap44xx_l4_cfg_hwmod,
474         .slave          = &omap44xx_l3_main_3_hwmod,
475         .clk            = "l4_div_ck",
476         .user           = OCP_USER_MPU | OCP_USER_SDMA,
477 };
479 /* l3_main_3 slave ports */
480 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
481         &omap44xx_l3_main_1__l3_main_3,
482         &omap44xx_l3_main_2__l3_main_3,
483         &omap44xx_l4_cfg__l3_main_3,
484 };
486 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
487         .name           = "l3_main_3",
488         .class          = &omap44xx_l3_hwmod_class,
489         .clkdm_name     = "l3_instr_clkdm",
490         .prcm = {
491                 .omap4 = {
492                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
493                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
494                         .modulemode   = MODULEMODE_HWCTRL,
495                 },
496         },
497         .slaves         = omap44xx_l3_main_3_slaves,
498         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
499         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
500 };
502 /*
503  * 'l4' class
504  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
505  */
506 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
507         .name   = "l4",
508 };
510 /* l4_abe */
511 /* aess -> l4_abe */
512 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
513         .master         = &omap44xx_aess_hwmod,
514         .slave          = &omap44xx_l4_abe_hwmod,
515         .clk            = "ocp_abe_iclk",
516         .user           = OCP_USER_MPU | OCP_USER_SDMA,
517 };
519 /* dsp -> l4_abe */
520 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
521         .master         = &omap44xx_dsp_hwmod,
522         .slave          = &omap44xx_l4_abe_hwmod,
523         .clk            = "ocp_abe_iclk",
524         .user           = OCP_USER_MPU | OCP_USER_SDMA,
525 };
527 /* l3_main_1 -> l4_abe */
528 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
529         .master         = &omap44xx_l3_main_1_hwmod,
530         .slave          = &omap44xx_l4_abe_hwmod,
531         .clk            = "l3_div_ck",
532         .user           = OCP_USER_MPU | OCP_USER_SDMA,
533 };
535 /* mpu -> l4_abe */
536 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
537         .master         = &omap44xx_mpu_hwmod,
538         .slave          = &omap44xx_l4_abe_hwmod,
539         .clk            = "ocp_abe_iclk",
540         .user           = OCP_USER_MPU | OCP_USER_SDMA,
541 };
543 /* l4_abe slave ports */
544 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
545         &omap44xx_aess__l4_abe,
546         &omap44xx_dsp__l4_abe,
547         &omap44xx_l3_main_1__l4_abe,
548         &omap44xx_mpu__l4_abe,
549 };
551 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
552         .name           = "l4_abe",
553         .class          = &omap44xx_l4_hwmod_class,
554         .clkdm_name     = "abe_clkdm",
555         .prcm = {
556                 .omap4 = {
557                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
558                 },
559         },
560         .slaves         = omap44xx_l4_abe_slaves,
561         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
562         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
563 };
565 /* l4_cfg */
566 /* l3_main_1 -> l4_cfg */
567 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
568         .master         = &omap44xx_l3_main_1_hwmod,
569         .slave          = &omap44xx_l4_cfg_hwmod,
570         .clk            = "l3_div_ck",
571         .user           = OCP_USER_MPU | OCP_USER_SDMA,
572 };
574 /* l4_cfg slave ports */
575 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
576         &omap44xx_l3_main_1__l4_cfg,
577 };
579 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
580         .name           = "l4_cfg",
581         .class          = &omap44xx_l4_hwmod_class,
582         .clkdm_name     = "l4_cfg_clkdm",
583         .prcm = {
584                 .omap4 = {
585                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
586                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
587                 },
588         },
589         .slaves         = omap44xx_l4_cfg_slaves,
590         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
591         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
592 };
594 /* l4_per */
595 /* l3_main_2 -> l4_per */
596 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
597         .master         = &omap44xx_l3_main_2_hwmod,
598         .slave          = &omap44xx_l4_per_hwmod,
599         .clk            = "l3_div_ck",
600         .user           = OCP_USER_MPU | OCP_USER_SDMA,
601 };
603 /* l4_per slave ports */
604 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
605         &omap44xx_l3_main_2__l4_per,
606 };
608 static struct omap_hwmod omap44xx_l4_per_hwmod = {
609         .name           = "l4_per",
610         .class          = &omap44xx_l4_hwmod_class,
611         .clkdm_name     = "l4_per_clkdm",
612         .prcm = {
613                 .omap4 = {
614                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
615                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
616                 },
617         },
618         .slaves         = omap44xx_l4_per_slaves,
619         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
620         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
621 };
623 /* l4_wkup */
624 /* l4_cfg -> l4_wkup */
625 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
626         .master         = &omap44xx_l4_cfg_hwmod,
627         .slave          = &omap44xx_l4_wkup_hwmod,
628         .clk            = "l4_div_ck",
629         .user           = OCP_USER_MPU | OCP_USER_SDMA,
630 };
632 /* l4_wkup slave ports */
633 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
634         &omap44xx_l4_cfg__l4_wkup,
635 };
637 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
638         .name           = "l4_wkup",
639         .class          = &omap44xx_l4_hwmod_class,
640         .clkdm_name     = "l4_wkup_clkdm",
641         .prcm = {
642                 .omap4 = {
643                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
644                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
645                 },
646         },
647         .slaves         = omap44xx_l4_wkup_slaves,
648         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
649         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
650 };
652 /*
653  * 'mpu_bus' class
654  * instance(s): mpu_private
655  */
656 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
657         .name   = "mpu_bus",
658 };
660 /* mpu_private */
661 /* mpu -> mpu_private */
662 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
663         .master         = &omap44xx_mpu_hwmod,
664         .slave          = &omap44xx_mpu_private_hwmod,
665         .clk            = "l3_div_ck",
666         .user           = OCP_USER_MPU | OCP_USER_SDMA,
667 };
669 /* mpu_private slave ports */
670 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
671         &omap44xx_mpu__mpu_private,
672 };
674 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
675         .name           = "mpu_private",
676         .class          = &omap44xx_mpu_bus_hwmod_class,
677         .clkdm_name     = "mpuss_clkdm",
678         .slaves         = omap44xx_mpu_private_slaves,
679         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
680         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
681 };
683 /*
684  * Modules omap_hwmod structures
685  *
686  * The following IPs are excluded for the moment because:
687  * - They do not need an explicit SW control using omap_hwmod API.
688  * - They still need to be validated with the driver
689  *   properly adapted to omap_hwmod / omap_device
690  *
691  *  c2c
692  *  c2c_target_fw
693  *  cm_core
694  *  cm_core_aon
695  *  ctrl_module_core
696  *  ctrl_module_pad_core
697  *  ctrl_module_pad_wkup
698  *  ctrl_module_wkup
699  *  debugss
700  *  efuse_ctrl_cust
701  *  efuse_ctrl_std
702  *  elm
703  *  emif1
704  *  emif2
705  *  fdif
706  *  gpmc
707  *  gpu
708  *  hdq1w
709  *  mcasp
710  *  mpu_c0
711  *  mpu_c1
712  *  ocmc_ram
713  *  ocp2scp_usb_phy
714  *  ocp_wp_noc
715  *  prcm_mpu
716  *  prm
717  *  scrm
718  *  sl2if
719  *  slimbus1
720  *  slimbus2
721  *  usb_host_fs
722  *  usb_host_hs
723  *  usb_phy_cm
724  *  usb_tll_hs
725  *  usim
726  */
728 /*
729  * 'aess' class
730  * audio engine sub system
731  */
733 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
734         .rev_offs       = 0x0000,
735         .sysc_offs      = 0x0010,
736         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
737         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
738                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
739                            MSTANDBY_SMART_WKUP),
740         .sysc_fields    = &omap_hwmod_sysc_type2,
741 };
743 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
744         .name   = "aess",
745         .sysc   = &omap44xx_aess_sysc,
746 };
748 /* aess */
749 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
750         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
751         { .irq = -1 }
752 };
754 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
755         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
756         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
757         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
758         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
759         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
760         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
761         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
762         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
763         { .dma_req = -1 }
764 };
766 /* aess master ports */
767 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
768         &omap44xx_aess__l4_abe,
769 };
771 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
772         {
773                 .pa_start       = 0x401f1000,
774                 .pa_end         = 0x401f13ff,
775                 .flags          = ADDR_TYPE_RT
776         },
777         { }
778 };
780 /* l4_abe -> aess */
781 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
782         .master         = &omap44xx_l4_abe_hwmod,
783         .slave          = &omap44xx_aess_hwmod,
784         .clk            = "ocp_abe_iclk",
785         .addr           = omap44xx_aess_addrs,
786         .user           = OCP_USER_MPU,
787 };
789 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
790         {
791                 .pa_start       = 0x490f1000,
792                 .pa_end         = 0x490f13ff,
793                 .flags          = ADDR_TYPE_RT
794         },
795         { }
796 };
798 /* l4_abe -> aess (dma) */
799 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
800         .master         = &omap44xx_l4_abe_hwmod,
801         .slave          = &omap44xx_aess_hwmod,
802         .clk            = "ocp_abe_iclk",
803         .addr           = omap44xx_aess_dma_addrs,
804         .user           = OCP_USER_SDMA,
805 };
807 /* aess slave ports */
808 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
809         &omap44xx_l4_abe__aess,
810         &omap44xx_l4_abe__aess_dma,
811 };
813 static struct omap_hwmod omap44xx_aess_hwmod = {
814         .name           = "aess",
815         .class          = &omap44xx_aess_hwmod_class,
816         .clkdm_name     = "abe_clkdm",
817         .mpu_irqs       = omap44xx_aess_irqs,
818         .sdma_reqs      = omap44xx_aess_sdma_reqs,
819         .main_clk       = "aess_fck",
820         .prcm = {
821                 .omap4 = {
822                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
823                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
824                         .modulemode   = MODULEMODE_SWCTRL,
825                 },
826         },
827         .slaves         = omap44xx_aess_slaves,
828         .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
829         .masters        = omap44xx_aess_masters,
830         .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
831         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
832 };
834 /*
835  * 'bandgap' class
836  * bangap reference for ldo regulators
837  */
839 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
840         .name   = "bandgap",
841 };
843 /* bandgap */
844 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
845         { .role = "fclk", .clk = "bandgap_fclk" },
846 };
848 static struct omap_hwmod omap44xx_bandgap_hwmod = {
849         .name           = "bandgap",
850         .class          = &omap44xx_bandgap_hwmod_class,
851         .clkdm_name     = "l4_wkup_clkdm",
852         .prcm = {
853                 .omap4 = {
854                         .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
855                 },
856         },
857         .opt_clks       = bandgap_opt_clks,
858         .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
859         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
860 };
862 /*
863  * 'counter' class
864  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
865  */
867 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
868         .rev_offs       = 0x0000,
869         .sysc_offs      = 0x0004,
870         .sysc_flags     = SYSC_HAS_SIDLEMODE,
871         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
872                            SIDLE_SMART_WKUP),
873         .sysc_fields    = &omap_hwmod_sysc_type1,
874 };
876 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
877         .name   = "counter",
878         .sysc   = &omap44xx_counter_sysc,
879 };
881 /* counter_32k */
882 static struct omap_hwmod omap44xx_counter_32k_hwmod;
883 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
884         {
885                 .pa_start       = 0x4a304000,
886                 .pa_end         = 0x4a30401f,
887                 .flags          = ADDR_TYPE_RT
888         },
889         { }
890 };
892 /* l4_wkup -> counter_32k */
893 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
894         .master         = &omap44xx_l4_wkup_hwmod,
895         .slave          = &omap44xx_counter_32k_hwmod,
896         .clk            = "l4_wkup_clk_mux_ck",
897         .addr           = omap44xx_counter_32k_addrs,
898         .user           = OCP_USER_MPU | OCP_USER_SDMA,
899 };
901 /* counter_32k slave ports */
902 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
903         &omap44xx_l4_wkup__counter_32k,
904 };
906 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
907         .name           = "counter_32k",
908         .class          = &omap44xx_counter_hwmod_class,
909         .clkdm_name     = "l4_wkup_clkdm",
910         .flags          = HWMOD_SWSUP_SIDLE,
911         .main_clk       = "sys_32k_ck",
912         .prcm = {
913                 .omap4 = {
914                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
915                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
916                 },
917         },
918         .slaves         = omap44xx_counter_32k_slaves,
919         .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
920         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
921 };
923 /*
924  * 'dma' class
925  * dma controller for data exchange between memory to memory (i.e. internal or
926  * external memory) and gp peripherals to memory or memory to gp peripherals
927  */
929 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
930         .rev_offs       = 0x0000,
931         .sysc_offs      = 0x002c,
932         .syss_offs      = 0x0028,
933         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
934                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
935                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
936                            SYSS_HAS_RESET_STATUS),
937         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
938                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
939         .sysc_fields    = &omap_hwmod_sysc_type1,
940 };
942 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
943         .name   = "dma",
944         .sysc   = &omap44xx_dma_sysc,
945 };
947 /* dma dev_attr */
948 static struct omap_dma_dev_attr dma_dev_attr = {
949         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
950                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
951         .lch_count      = 32,
952 };
954 /* dma_system */
955 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
956         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
957         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
958         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
959         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
960         { .irq = -1 }
961 };
963 /* dma_system master ports */
964 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
965         &omap44xx_dma_system__l3_main_2,
966 };
968 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
969         {
970                 .pa_start       = 0x4a056000,
971                 .pa_end         = 0x4a056fff,
972                 .flags          = ADDR_TYPE_RT
973         },
974         { }
975 };
977 /* l4_cfg -> dma_system */
978 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
979         .master         = &omap44xx_l4_cfg_hwmod,
980         .slave          = &omap44xx_dma_system_hwmod,
981         .clk            = "l4_div_ck",
982         .addr           = omap44xx_dma_system_addrs,
983         .user           = OCP_USER_MPU | OCP_USER_SDMA,
984 };
986 /* dma_system slave ports */
987 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
988         &omap44xx_l4_cfg__dma_system,
989 };
991 static struct omap_hwmod omap44xx_dma_system_hwmod = {
992         .name           = "dma_system",
993         .class          = &omap44xx_dma_hwmod_class,
994         .clkdm_name     = "l3_dma_clkdm",
995         .mpu_irqs       = omap44xx_dma_system_irqs,
996         .main_clk       = "l3_div_ck",
997         .prcm = {
998                 .omap4 = {
999                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
1000                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
1001                 },
1002         },
1003         .dev_attr       = &dma_dev_attr,
1004         .slaves         = omap44xx_dma_system_slaves,
1005         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
1006         .masters        = omap44xx_dma_system_masters,
1007         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
1008         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1009 };
1011 /*
1012  * 'dmic' class
1013  * digital microphone controller
1014  */
1016 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
1017         .rev_offs       = 0x0000,
1018         .sysc_offs      = 0x0010,
1019         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1020                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1021         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1022                            SIDLE_SMART_WKUP),
1023         .sysc_fields    = &omap_hwmod_sysc_type2,
1024 };
1026 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
1027         .name   = "dmic",
1028         .sysc   = &omap44xx_dmic_sysc,
1029 };
1031 /* dmic */
1032 static struct omap_hwmod omap44xx_dmic_hwmod;
1033 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
1034         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
1035         { .irq = -1 }
1036 };
1038 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
1039         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
1040         { .dma_req = -1 }
1041 };
1043 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
1044         {
1045                 .pa_start       = 0x4012e000,
1046                 .pa_end         = 0x4012e07f,
1047                 .flags          = ADDR_TYPE_RT
1048         },
1049         { }
1050 };
1052 /* l4_abe -> dmic */
1053 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
1054         .master         = &omap44xx_l4_abe_hwmod,
1055         .slave          = &omap44xx_dmic_hwmod,
1056         .clk            = "ocp_abe_iclk",
1057         .addr           = omap44xx_dmic_addrs,
1058         .user           = OCP_USER_MPU,
1059 };
1061 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
1062         {
1063                 .pa_start       = 0x4902e000,
1064                 .pa_end         = 0x4902e07f,
1065                 .flags          = ADDR_TYPE_RT
1066         },
1067         { }
1068 };
1070 /* l4_abe -> dmic (dma) */
1071 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
1072         .master         = &omap44xx_l4_abe_hwmod,
1073         .slave          = &omap44xx_dmic_hwmod,
1074         .clk            = "ocp_abe_iclk",
1075         .addr           = omap44xx_dmic_dma_addrs,
1076         .user           = OCP_USER_SDMA,
1077 };
1079 /* dmic slave ports */
1080 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
1081         &omap44xx_l4_abe__dmic,
1082         &omap44xx_l4_abe__dmic_dma,
1083 };
1085 static struct omap_hwmod omap44xx_dmic_hwmod = {
1086         .name           = "dmic",
1087         .class          = &omap44xx_dmic_hwmod_class,
1088         .clkdm_name     = "abe_clkdm",
1089         .mpu_irqs       = omap44xx_dmic_irqs,
1090         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
1091         .main_clk       = "dmic_fck",
1092         .prcm = {
1093                 .omap4 = {
1094                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
1095                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
1096                         .modulemode   = MODULEMODE_SWCTRL,
1097                 },
1098         },
1099         .slaves         = omap44xx_dmic_slaves,
1100         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
1101         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1102 };
1104 /*
1105  * 'dsp' class
1106  * dsp sub-system
1107  */
1109 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1110         .name   = "dsp",
1111 };
1113 /* dsp */
1114 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1115         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1116         { .irq = -1 }
1117 };
1119 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1120         { .name = "mmu_cache", .rst_shift = 1 },
1121 };
1123 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1124         { .name = "dsp", .rst_shift = 0 },
1125 };
1127 /* dsp -> iva */
1128 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1129         .master         = &omap44xx_dsp_hwmod,
1130         .slave          = &omap44xx_iva_hwmod,
1131         .clk            = "dpll_iva_m5x2_ck",
1132 };
1134 /* dsp master ports */
1135 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1136         &omap44xx_dsp__l3_main_1,
1137         &omap44xx_dsp__l4_abe,
1138         &omap44xx_dsp__iva,
1139 };
1141 /* l4_cfg -> dsp */
1142 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1143         .master         = &omap44xx_l4_cfg_hwmod,
1144         .slave          = &omap44xx_dsp_hwmod,
1145         .clk            = "l4_div_ck",
1146         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1147 };
1149 /* dsp slave ports */
1150 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1151         &omap44xx_l4_cfg__dsp,
1152 };
1154 /* Pseudo hwmod for reset control purpose only */
1155 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1156         .name           = "dsp_c0",
1157         .class          = &omap44xx_dsp_hwmod_class,
1158         .clkdm_name     = "tesla_clkdm",
1159         .flags          = HWMOD_INIT_NO_RESET,
1160         .rst_lines      = omap44xx_dsp_c0_resets,
1161         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1162         .prcm = {
1163                 .omap4 = {
1164                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1165                 },
1166         },
1167         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1168 };
1170 static struct omap_hwmod omap44xx_dsp_hwmod = {
1171         .name           = "dsp",
1172         .class          = &omap44xx_dsp_hwmod_class,
1173         .clkdm_name     = "tesla_clkdm",
1174         .mpu_irqs       = omap44xx_dsp_irqs,
1175         .rst_lines      = omap44xx_dsp_resets,
1176         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
1177         .main_clk       = "dsp_fck",
1178         .prcm = {
1179                 .omap4 = {
1180                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
1181                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1182                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
1183                         .modulemode   = MODULEMODE_HWCTRL,
1184                 },
1185         },
1186         .slaves         = omap44xx_dsp_slaves,
1187         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
1188         .masters        = omap44xx_dsp_masters,
1189         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
1190         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1191 };
1193 /*
1194  * 'dss' class
1195  * display sub-system
1196  */
1198 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1199         .rev_offs       = 0x0000,
1200         .syss_offs      = 0x0014,
1201         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1202 };
1204 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1205         .name   = "dss",
1206         .sysc   = &omap44xx_dss_sysc,
1207 };
1209 /* dss */
1210 /* dss master ports */
1211 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1212         &omap44xx_dss__l3_main_1,
1213 };
1215 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1216         {
1217                 .pa_start       = 0x58000000,
1218                 .pa_end         = 0x5800007f,
1219                 .flags          = ADDR_TYPE_RT
1220         },
1221         { }
1222 };
1224 /* l3_main_2 -> dss */
1225 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1226         .master         = &omap44xx_l3_main_2_hwmod,
1227         .slave          = &omap44xx_dss_hwmod,
1228         .clk            = "dss_fck",
1229         .addr           = omap44xx_dss_dma_addrs,
1230         .user           = OCP_USER_SDMA,
1231 };
1233 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1234         {
1235                 .pa_start       = 0x48040000,
1236                 .pa_end         = 0x4804007f,
1237                 .flags          = ADDR_TYPE_RT
1238         },
1239         { }
1240 };
1242 /* l4_per -> dss */
1243 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1244         .master         = &omap44xx_l4_per_hwmod,
1245         .slave          = &omap44xx_dss_hwmod,
1246         .clk            = "l4_div_ck",
1247         .addr           = omap44xx_dss_addrs,
1248         .user           = OCP_USER_MPU,
1249 };
1251 /* dss slave ports */
1252 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1253         &omap44xx_l3_main_2__dss,
1254         &omap44xx_l4_per__dss,
1255 };
1257 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1258         { .role = "sys_clk", .clk = "dss_sys_clk" },
1259         { .role = "tv_clk", .clk = "dss_tv_clk" },
1260         { .role = "dss_clk", .clk = "dss_dss_clk" },
1261         { .role = "video_clk", .clk = "dss_48mhz_clk" },
1262 };
1264 static struct omap_hwmod omap44xx_dss_hwmod = {
1265         .name           = "dss_core",
1266         .class          = &omap44xx_dss_hwmod_class,
1267         .clkdm_name     = "l3_dss_clkdm",
1268         .main_clk       = "dss_dss_clk",
1269         .prcm = {
1270                 .omap4 = {
1271                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1272                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1273                 },
1274         },
1275         .opt_clks       = dss_opt_clks,
1276         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
1277         .slaves         = omap44xx_dss_slaves,
1278         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
1279         .masters        = omap44xx_dss_masters,
1280         .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
1281         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1282 };
1284 /*
1285  * 'dispc' class
1286  * display controller
1287  */
1289 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1290         .rev_offs       = 0x0000,
1291         .sysc_offs      = 0x0010,
1292         .syss_offs      = 0x0014,
1293         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1294                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1295                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1296                            SYSS_HAS_RESET_STATUS),
1297         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1298                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1299         .sysc_fields    = &omap_hwmod_sysc_type1,
1300 };
1302 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1303         .name   = "dispc",
1304         .sysc   = &omap44xx_dispc_sysc,
1305 };
1307 /* dss_dispc */
1308 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1309 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1310         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1311         { .irq = -1 }
1312 };
1314 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1315         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1316         { .dma_req = -1 }
1317 };
1319 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1320         {
1321                 .pa_start       = 0x58001000,
1322                 .pa_end         = 0x58001fff,
1323                 .flags          = ADDR_TYPE_RT
1324         },
1325         { }
1326 };
1328 /* l3_main_2 -> dss_dispc */
1329 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1330         .master         = &omap44xx_l3_main_2_hwmod,
1331         .slave          = &omap44xx_dss_dispc_hwmod,
1332         .clk            = "dss_fck",
1333         .addr           = omap44xx_dss_dispc_dma_addrs,
1334         .user           = OCP_USER_SDMA,
1335 };
1337 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1338         {
1339                 .pa_start       = 0x48041000,
1340                 .pa_end         = 0x48041fff,
1341                 .flags          = ADDR_TYPE_RT
1342         },
1343         { }
1344 };
1346 /* l4_per -> dss_dispc */
1347 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1348         .master         = &omap44xx_l4_per_hwmod,
1349         .slave          = &omap44xx_dss_dispc_hwmod,
1350         .clk            = "l4_div_ck",
1351         .addr           = omap44xx_dss_dispc_addrs,
1352         .user           = OCP_USER_MPU,
1353 };
1355 /* dss_dispc slave ports */
1356 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1357         &omap44xx_l3_main_2__dss_dispc,
1358         &omap44xx_l4_per__dss_dispc,
1359 };
1361 static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
1362         { .role = "sys_clk", .clk = "dss_sys_clk" },
1363         { .role = "tv_clk", .clk = "dss_tv_clk" },
1364         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1365 };
1367 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1368         .name           = "dss_dispc",
1369         .class          = &omap44xx_dispc_hwmod_class,
1370         .clkdm_name     = "l3_dss_clkdm",
1371         .mpu_irqs       = omap44xx_dss_dispc_irqs,
1372         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
1373         .main_clk       = "dss_dss_clk",
1374         .prcm = {
1375                 .omap4 = {
1376                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1377                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1378                 },
1379         },
1380         .opt_clks       = dss_dispc_opt_clks,
1381         .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
1382         .slaves         = omap44xx_dss_dispc_slaves,
1383         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1384         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1385 };
1387 /*
1388  * 'dsi' class
1389  * display serial interface controller
1390  */
1392 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1393         .rev_offs       = 0x0000,
1394         .sysc_offs      = 0x0010,
1395         .syss_offs      = 0x0014,
1396         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1397                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1398                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1399         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1400         .sysc_fields    = &omap_hwmod_sysc_type1,
1401 };
1403 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1404         .name   = "dsi",
1405         .sysc   = &omap44xx_dsi_sysc,
1406 };
1408 /* dss_dsi1 */
1409 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1410 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1411         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1412         { .irq = -1 }
1413 };
1415 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1416         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1417         { .dma_req = -1 }
1418 };
1420 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1421         {
1422                 .pa_start       = 0x58004000,
1423                 .pa_end         = 0x580041ff,
1424                 .flags          = ADDR_TYPE_RT
1425         },
1426         { }
1427 };
1429 /* l3_main_2 -> dss_dsi1 */
1430 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1431         .master         = &omap44xx_l3_main_2_hwmod,
1432         .slave          = &omap44xx_dss_dsi1_hwmod,
1433         .clk            = "dss_fck",
1434         .addr           = omap44xx_dss_dsi1_dma_addrs,
1435         .user           = OCP_USER_SDMA,
1436 };
1438 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1439         {
1440                 .pa_start       = 0x48044000,
1441                 .pa_end         = 0x480441ff,
1442                 .flags          = ADDR_TYPE_RT
1443         },
1444         { }
1445 };
1447 /* l4_per -> dss_dsi1 */
1448 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1449         .master         = &omap44xx_l4_per_hwmod,
1450         .slave          = &omap44xx_dss_dsi1_hwmod,
1451         .clk            = "l4_div_ck",
1452         .addr           = omap44xx_dss_dsi1_addrs,
1453         .user           = OCP_USER_MPU,
1454 };
1456 /* dss_dsi1 slave ports */
1457 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1458         &omap44xx_l3_main_2__dss_dsi1,
1459         &omap44xx_l4_per__dss_dsi1,
1460 };
1462 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1463         { .role = "sys_clk", .clk = "dss_sys_clk" },
1464 };
1466 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1467         .name           = "dss_dsi1",
1468         .class          = &omap44xx_dsi_hwmod_class,
1469         .clkdm_name     = "l3_dss_clkdm",
1470         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
1471         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
1472         .main_clk       = "dss_dss_clk",
1473         .prcm = {
1474                 .omap4 = {
1475                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1476                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1477                 },
1478         },
1479         .opt_clks       = dss_dsi1_opt_clks,
1480         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
1481         .slaves         = omap44xx_dss_dsi1_slaves,
1482         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1483         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1484 };
1486 /* dss_dsi2 */
1487 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1488 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1489         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1490         { .irq = -1 }
1491 };
1493 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1494         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1495         { .dma_req = -1 }
1496 };
1498 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1499         {
1500                 .pa_start       = 0x58005000,
1501                 .pa_end         = 0x580051ff,
1502                 .flags          = ADDR_TYPE_RT
1503         },
1504         { }
1505 };
1507 /* l3_main_2 -> dss_dsi2 */
1508 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1509         .master         = &omap44xx_l3_main_2_hwmod,
1510         .slave          = &omap44xx_dss_dsi2_hwmod,
1511         .clk            = "dss_fck",
1512         .addr           = omap44xx_dss_dsi2_dma_addrs,
1513         .user           = OCP_USER_SDMA,
1514 };
1516 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1517         {
1518                 .pa_start       = 0x48045000,
1519                 .pa_end         = 0x480451ff,
1520                 .flags          = ADDR_TYPE_RT
1521         },
1522         { }
1523 };
1525 /* l4_per -> dss_dsi2 */
1526 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1527         .master         = &omap44xx_l4_per_hwmod,
1528         .slave          = &omap44xx_dss_dsi2_hwmod,
1529         .clk            = "l4_div_ck",
1530         .addr           = omap44xx_dss_dsi2_addrs,
1531         .user           = OCP_USER_MPU,
1532 };
1534 /* dss_dsi2 slave ports */
1535 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1536         &omap44xx_l3_main_2__dss_dsi2,
1537         &omap44xx_l4_per__dss_dsi2,
1538 };
1540 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1541         { .role = "sys_clk", .clk = "dss_sys_clk" },
1542 };
1544 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1545         .name           = "dss_dsi2",
1546         .class          = &omap44xx_dsi_hwmod_class,
1547         .clkdm_name     = "l3_dss_clkdm",
1548         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
1549         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
1550         .main_clk       = "dss_dss_clk",
1551         .prcm = {
1552                 .omap4 = {
1553                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1554                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1555                 },
1556         },
1557         .opt_clks       = dss_dsi2_opt_clks,
1558         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
1559         .slaves         = omap44xx_dss_dsi2_slaves,
1560         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1561         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1562 };
1564 /*
1565  * 'hdmi' class
1566  * hdmi controller
1567  */
1569 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1570         .rev_offs       = 0x0000,
1571         .sysc_offs      = 0x0010,
1572         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1573                            SYSC_HAS_SOFTRESET),
1574         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1575                            SIDLE_SMART_WKUP),
1576         .sysc_fields    = &omap_hwmod_sysc_type2,
1577 };
1579 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1580         .name   = "hdmi",
1581         .sysc   = &omap44xx_hdmi_sysc,
1582 };
1584 /* dss_hdmi */
1585 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1586 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1587         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1588         { .irq = -1 }
1589 };
1591 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1592         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1593         { .dma_req = -1 }
1594 };
1596 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1597         {
1598                 .pa_start       = 0x58006000,
1599                 .pa_end         = 0x58006fff,
1600                 .flags          = ADDR_TYPE_RT
1601         },
1602         { }
1603 };
1605 /* l3_main_2 -> dss_hdmi */
1606 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1607         .master         = &omap44xx_l3_main_2_hwmod,
1608         .slave          = &omap44xx_dss_hdmi_hwmod,
1609         .clk            = "dss_fck",
1610         .addr           = omap44xx_dss_hdmi_dma_addrs,
1611         .user           = OCP_USER_SDMA,
1612 };
1614 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1615         {
1616                 .pa_start       = 0x48046000,
1617                 .pa_end         = 0x48046fff,
1618                 .flags          = ADDR_TYPE_RT
1619         },
1620         { }
1621 };
1623 /* l4_per -> dss_hdmi */
1624 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1625         .master         = &omap44xx_l4_per_hwmod,
1626         .slave          = &omap44xx_dss_hdmi_hwmod,
1627         .clk            = "l4_div_ck",
1628         .addr           = omap44xx_dss_hdmi_addrs,
1629         .user           = OCP_USER_MPU,
1630 };
1632 /* dss_hdmi slave ports */
1633 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1634         &omap44xx_l3_main_2__dss_hdmi,
1635         &omap44xx_l4_per__dss_hdmi,
1636 };
1638 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1639         { .role = "sys_clk", .clk = "dss_sys_clk" },
1640 };
1642 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1643         .name           = "dss_hdmi",
1644         .class          = &omap44xx_hdmi_hwmod_class,
1645         .clkdm_name     = "l3_dss_clkdm",
1646         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
1647         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
1648         .main_clk       = "dss_dss_clk",
1649         .prcm = {
1650                 .omap4 = {
1651                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1652                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1653                 },
1654         },
1655         .opt_clks       = dss_hdmi_opt_clks,
1656         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
1657         .slaves         = omap44xx_dss_hdmi_slaves,
1658         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1659         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1660 };
1662 /*
1663  * 'rfbi' class
1664  * remote frame buffer interface
1665  */
1667 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1668         .rev_offs       = 0x0000,
1669         .sysc_offs      = 0x0010,
1670         .syss_offs      = 0x0014,
1671         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1672                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1673         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1674         .sysc_fields    = &omap_hwmod_sysc_type1,
1675 };
1677 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1678         .name   = "rfbi",
1679         .sysc   = &omap44xx_rfbi_sysc,
1680 };
1682 /* dss_rfbi */
1683 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1684 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1685         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1686         { .dma_req = -1 }
1687 };
1689 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1690         {
1691                 .pa_start       = 0x58002000,
1692                 .pa_end         = 0x580020ff,
1693                 .flags          = ADDR_TYPE_RT
1694         },
1695         { }
1696 };
1698 /* l3_main_2 -> dss_rfbi */
1699 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1700         .master         = &omap44xx_l3_main_2_hwmod,
1701         .slave          = &omap44xx_dss_rfbi_hwmod,
1702         .clk            = "dss_fck",
1703         .addr           = omap44xx_dss_rfbi_dma_addrs,
1704         .user           = OCP_USER_SDMA,
1705 };
1707 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1708         {
1709                 .pa_start       = 0x48042000,
1710                 .pa_end         = 0x480420ff,
1711                 .flags          = ADDR_TYPE_RT
1712         },
1713         { }
1714 };
1716 /* l4_per -> dss_rfbi */
1717 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1718         .master         = &omap44xx_l4_per_hwmod,
1719         .slave          = &omap44xx_dss_rfbi_hwmod,
1720         .clk            = "l4_div_ck",
1721         .addr           = omap44xx_dss_rfbi_addrs,
1722         .user           = OCP_USER_MPU,
1723 };
1725 /* dss_rfbi slave ports */
1726 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1727         &omap44xx_l3_main_2__dss_rfbi,
1728         &omap44xx_l4_per__dss_rfbi,
1729 };
1731 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1732         { .role = "ick", .clk = "dss_fck" },
1733 };
1735 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1736         .name           = "dss_rfbi",
1737         .class          = &omap44xx_rfbi_hwmod_class,
1738         .clkdm_name     = "l3_dss_clkdm",
1739         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
1740         .main_clk       = "dss_dss_clk",
1741         .prcm = {
1742                 .omap4 = {
1743                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1744                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1745                 },
1746         },
1747         .opt_clks       = dss_rfbi_opt_clks,
1748         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
1749         .slaves         = omap44xx_dss_rfbi_slaves,
1750         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1751         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1752 };
1754 /*
1755  * 'venc' class
1756  * video encoder
1757  */
1759 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1760         .name   = "venc",
1761 };
1763 /* dss_venc */
1764 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1765 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1766         {
1767                 .pa_start       = 0x58003000,
1768                 .pa_end         = 0x580030ff,
1769                 .flags          = ADDR_TYPE_RT
1770         },
1771         { }
1772 };
1774 /* l3_main_2 -> dss_venc */
1775 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1776         .master         = &omap44xx_l3_main_2_hwmod,
1777         .slave          = &omap44xx_dss_venc_hwmod,
1778         .clk            = "dss_fck",
1779         .addr           = omap44xx_dss_venc_dma_addrs,
1780         .user           = OCP_USER_SDMA,
1781 };
1783 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1784         {
1785                 .pa_start       = 0x48043000,
1786                 .pa_end         = 0x480430ff,
1787                 .flags          = ADDR_TYPE_RT
1788         },
1789         { }
1790 };
1792 /* l4_per -> dss_venc */
1793 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1794         .master         = &omap44xx_l4_per_hwmod,
1795         .slave          = &omap44xx_dss_venc_hwmod,
1796         .clk            = "l4_div_ck",
1797         .addr           = omap44xx_dss_venc_addrs,
1798         .user           = OCP_USER_MPU,
1799 };
1801 /* dss_venc slave ports */
1802 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1803         &omap44xx_l3_main_2__dss_venc,
1804         &omap44xx_l4_per__dss_venc,
1805 };
1807 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1808         .name           = "dss_venc",
1809         .class          = &omap44xx_venc_hwmod_class,
1810         .clkdm_name     = "l3_dss_clkdm",
1811         .main_clk       = "dss_dss_clk",
1812         .prcm = {
1813                 .omap4 = {
1814                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1815                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1816                 },
1817         },
1818         .slaves         = omap44xx_dss_venc_slaves,
1819         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1820         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1821 };
1823 /*
1824  * 'gpio' class
1825  * general purpose io module
1826  */
1828 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1829         .rev_offs       = 0x0000,
1830         .sysc_offs      = 0x0010,
1831         .syss_offs      = 0x0114,
1832         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1833                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1834                            SYSS_HAS_RESET_STATUS),
1835         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1836                            SIDLE_SMART_WKUP),
1837         .sysc_fields    = &omap_hwmod_sysc_type1,
1838 };
1840 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1841         .name   = "gpio",
1842         .sysc   = &omap44xx_gpio_sysc,
1843         .rev    = 2,
1844 };
1846 /* gpio dev_attr */
1847 static struct omap_gpio_dev_attr gpio_dev_attr = {
1848         .bank_width     = 32,
1849         .dbck_flag      = true,
1850 };
1852 /* gpio1 */
1853 static struct omap_hwmod omap44xx_gpio1_hwmod;
1854 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1855         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1856         { .irq = -1 }
1857 };
1859 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1860         {
1861                 .pa_start       = 0x4a310000,
1862                 .pa_end         = 0x4a3101ff,
1863                 .flags          = ADDR_TYPE_RT
1864         },
1865         { }
1866 };
1868 /* l4_wkup -> gpio1 */
1869 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1870         .master         = &omap44xx_l4_wkup_hwmod,
1871         .slave          = &omap44xx_gpio1_hwmod,
1872         .clk            = "l4_wkup_clk_mux_ck",
1873         .addr           = omap44xx_gpio1_addrs,
1874         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1875 };
1877 /* gpio1 slave ports */
1878 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1879         &omap44xx_l4_wkup__gpio1,
1880 };
1882 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1883         { .role = "dbclk", .clk = "gpio1_dbclk" },
1884 };
1886 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1887         .name           = "gpio1",
1888         .class          = &omap44xx_gpio_hwmod_class,
1889         .clkdm_name     = "l4_wkup_clkdm",
1890         .mpu_irqs       = omap44xx_gpio1_irqs,
1891         .main_clk       = "gpio1_ick",
1892         .prcm = {
1893                 .omap4 = {
1894                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1895                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1896                         .modulemode   = MODULEMODE_HWCTRL,
1897                 },
1898         },
1899         .opt_clks       = gpio1_opt_clks,
1900         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1901         .dev_attr       = &gpio_dev_attr,
1902         .slaves         = omap44xx_gpio1_slaves,
1903         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1904         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1905 };
1907 /* gpio2 */
1908 static struct omap_hwmod omap44xx_gpio2_hwmod;
1909 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1910         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1911         { .irq = -1 }
1912 };
1914 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1915         {
1916                 .pa_start       = 0x48055000,
1917                 .pa_end         = 0x480551ff,
1918                 .flags          = ADDR_TYPE_RT
1919         },
1920         { }
1921 };
1923 /* l4_per -> gpio2 */
1924 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1925         .master         = &omap44xx_l4_per_hwmod,
1926         .slave          = &omap44xx_gpio2_hwmod,
1927         .clk            = "l4_div_ck",
1928         .addr           = omap44xx_gpio2_addrs,
1929         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1930 };
1932 /* gpio2 slave ports */
1933 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1934         &omap44xx_l4_per__gpio2,
1935 };
1937 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1938         { .role = "dbclk", .clk = "gpio2_dbclk" },
1939 };
1941 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1942         .name           = "gpio2",
1943         .class          = &omap44xx_gpio_hwmod_class,
1944         .clkdm_name     = "l4_per_clkdm",
1945         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1946         .mpu_irqs       = omap44xx_gpio2_irqs,
1947         .main_clk       = "gpio2_ick",
1948         .prcm = {
1949                 .omap4 = {
1950                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1951                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1952                         .modulemode   = MODULEMODE_HWCTRL,
1953                 },
1954         },
1955         .opt_clks       = gpio2_opt_clks,
1956         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1957         .dev_attr       = &gpio_dev_attr,
1958         .slaves         = omap44xx_gpio2_slaves,
1959         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1960         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1961 };
1963 /* gpio3 */
1964 static struct omap_hwmod omap44xx_gpio3_hwmod;
1965 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1966         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1967         { .irq = -1 }
1968 };
1970 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1971         {
1972                 .pa_start       = 0x48057000,
1973                 .pa_end         = 0x480571ff,
1974                 .flags          = ADDR_TYPE_RT
1975         },
1976         { }
1977 };
1979 /* l4_per -> gpio3 */
1980 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1981         .master         = &omap44xx_l4_per_hwmod,
1982         .slave          = &omap44xx_gpio3_hwmod,
1983         .clk            = "l4_div_ck",
1984         .addr           = omap44xx_gpio3_addrs,
1985         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1986 };
1988 /* gpio3 slave ports */
1989 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1990         &omap44xx_l4_per__gpio3,
1991 };
1993 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1994         { .role = "dbclk", .clk = "gpio3_dbclk" },
1995 };
1997 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1998         .name           = "gpio3",
1999         .class          = &omap44xx_gpio_hwmod_class,
2000         .clkdm_name     = "l4_per_clkdm",
2001         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2002         .mpu_irqs       = omap44xx_gpio3_irqs,
2003         .main_clk       = "gpio3_ick",
2004         .prcm = {
2005                 .omap4 = {
2006                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
2007                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
2008                         .modulemode   = MODULEMODE_HWCTRL,
2009                 },
2010         },
2011         .opt_clks       = gpio3_opt_clks,
2012         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
2013         .dev_attr       = &gpio_dev_attr,
2014         .slaves         = omap44xx_gpio3_slaves,
2015         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
2016         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2017 };
2019 /* gpio4 */
2020 static struct omap_hwmod omap44xx_gpio4_hwmod;
2021 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
2022         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
2023         { .irq = -1 }
2024 };
2026 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
2027         {
2028                 .pa_start       = 0x48059000,
2029                 .pa_end         = 0x480591ff,
2030                 .flags          = ADDR_TYPE_RT
2031         },
2032         { }
2033 };
2035 /* l4_per -> gpio4 */
2036 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
2037         .master         = &omap44xx_l4_per_hwmod,
2038         .slave          = &omap44xx_gpio4_hwmod,
2039         .clk            = "l4_div_ck",
2040         .addr           = omap44xx_gpio4_addrs,
2041         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2042 };
2044 /* gpio4 slave ports */
2045 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
2046         &omap44xx_l4_per__gpio4,
2047 };
2049 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2050         { .role = "dbclk", .clk = "gpio4_dbclk" },
2051 };
2053 static struct omap_hwmod omap44xx_gpio4_hwmod = {
2054         .name           = "gpio4",
2055         .class          = &omap44xx_gpio_hwmod_class,
2056         .clkdm_name     = "l4_per_clkdm",
2057         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2058         .mpu_irqs       = omap44xx_gpio4_irqs,
2059         .main_clk       = "gpio4_ick",
2060         .prcm = {
2061                 .omap4 = {
2062                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
2063                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
2064                         .modulemode   = MODULEMODE_HWCTRL,
2065                 },
2066         },
2067         .opt_clks       = gpio4_opt_clks,
2068         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
2069         .dev_attr       = &gpio_dev_attr,
2070         .slaves         = omap44xx_gpio4_slaves,
2071         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
2072         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2073 };
2075 /* gpio5 */
2076 static struct omap_hwmod omap44xx_gpio5_hwmod;
2077 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
2078         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
2079         { .irq = -1 }
2080 };
2082 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
2083         {
2084                 .pa_start       = 0x4805b000,
2085                 .pa_end         = 0x4805b1ff,
2086                 .flags          = ADDR_TYPE_RT
2087         },
2088         { }
2089 };
2091 /* l4_per -> gpio5 */
2092 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
2093         .master         = &omap44xx_l4_per_hwmod,
2094         .slave          = &omap44xx_gpio5_hwmod,
2095         .clk            = "l4_div_ck",
2096         .addr           = omap44xx_gpio5_addrs,
2097         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2098 };
2100 /* gpio5 slave ports */
2101 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
2102         &omap44xx_l4_per__gpio5,
2103 };
2105 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2106         { .role = "dbclk", .clk = "gpio5_dbclk" },
2107 };
2109 static struct omap_hwmod omap44xx_gpio5_hwmod = {
2110         .name           = "gpio5",
2111         .class          = &omap44xx_gpio_hwmod_class,
2112         .clkdm_name     = "l4_per_clkdm",
2113         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2114         .mpu_irqs       = omap44xx_gpio5_irqs,
2115         .main_clk       = "gpio5_ick",
2116         .prcm = {
2117                 .omap4 = {
2118                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
2119                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
2120                         .modulemode   = MODULEMODE_HWCTRL,
2121                 },
2122         },
2123         .opt_clks       = gpio5_opt_clks,
2124         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2125         .dev_attr       = &gpio_dev_attr,
2126         .slaves         = omap44xx_gpio5_slaves,
2127         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
2128         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2129 };
2131 /* gpio6 */
2132 static struct omap_hwmod omap44xx_gpio6_hwmod;
2133 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2134         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
2135         { .irq = -1 }
2136 };
2138 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
2139         {
2140                 .pa_start       = 0x4805d000,
2141                 .pa_end         = 0x4805d1ff,
2142                 .flags          = ADDR_TYPE_RT
2143         },
2144         { }
2145 };
2147 /* l4_per -> gpio6 */
2148 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2149         .master         = &omap44xx_l4_per_hwmod,
2150         .slave          = &omap44xx_gpio6_hwmod,
2151         .clk            = "l4_div_ck",
2152         .addr           = omap44xx_gpio6_addrs,
2153         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2154 };
2156 /* gpio6 slave ports */
2157 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2158         &omap44xx_l4_per__gpio6,
2159 };
2161 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2162         { .role = "dbclk", .clk = "gpio6_dbclk" },
2163 };
2165 static struct omap_hwmod omap44xx_gpio6_hwmod = {
2166         .name           = "gpio6",
2167         .class          = &omap44xx_gpio_hwmod_class,
2168         .clkdm_name     = "l4_per_clkdm",
2169         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2170         .mpu_irqs       = omap44xx_gpio6_irqs,
2171         .main_clk       = "gpio6_ick",
2172         .prcm = {
2173                 .omap4 = {
2174                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
2175                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
2176                         .modulemode   = MODULEMODE_HWCTRL,
2177                 },
2178         },
2179         .opt_clks       = gpio6_opt_clks,
2180         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2181         .dev_attr       = &gpio_dev_attr,
2182         .slaves         = omap44xx_gpio6_slaves,
2183         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
2184         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2185 };
2187 /*
2188  * 'hsi' class
2189  * mipi high-speed synchronous serial interface (multichannel and full-duplex
2190  * serial if)
2191  */
2193 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2194         .rev_offs       = 0x0000,
2195         .sysc_offs      = 0x0010,
2196         .syss_offs      = 0x0014,
2197         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2198                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2199                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2200         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2201                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2202                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2203         .sysc_fields    = &omap_hwmod_sysc_type1,
2204 };
2206 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2207         .name   = "hsi",
2208         .sysc   = &omap44xx_hsi_sysc,
2209 };
2211 /* hsi */
2212 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2213         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2214         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2215         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2216         { .irq = -1 }
2217 };
2219 /* hsi master ports */
2220 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2221         &omap44xx_hsi__l3_main_2,
2222 };
2224 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2225         {
2226                 .pa_start       = 0x4a058000,
2227                 .pa_end         = 0x4a05bfff,
2228                 .flags          = ADDR_TYPE_RT
2229         },
2230         { }
2231 };
2233 /* l4_cfg -> hsi */
2234 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2235         .master         = &omap44xx_l4_cfg_hwmod,
2236         .slave          = &omap44xx_hsi_hwmod,
2237         .clk            = "l4_div_ck",
2238         .addr           = omap44xx_hsi_addrs,
2239         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2240 };
2242 /* hsi slave ports */
2243 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2244         &omap44xx_l4_cfg__hsi,
2245 };
2247 static struct omap_hwmod omap44xx_hsi_hwmod = {
2248         .name           = "hsi",
2249         .class          = &omap44xx_hsi_hwmod_class,
2250         .clkdm_name     = "l3_init_clkdm",
2251         .mpu_irqs       = omap44xx_hsi_irqs,
2252         .main_clk       = "hsi_fck",
2253         .prcm = {
2254                 .omap4 = {
2255                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
2256                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
2257                         .modulemode   = MODULEMODE_HWCTRL,
2258                 },
2259         },
2260         .slaves         = omap44xx_hsi_slaves,
2261         .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
2262         .masters        = omap44xx_hsi_masters,
2263         .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
2264         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2265 };
2267 /*
2268  * 'i2c' class
2269  * multimaster high-speed i2c controller
2270  */
2272 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2273         .sysc_offs      = 0x0010,
2274         .syss_offs      = 0x0090,
2275         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2276                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2277                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2278         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2279                            SIDLE_SMART_WKUP),
2280         .sysc_fields    = &omap_hwmod_sysc_type1,
2281 };
2283 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2284         .name   = "i2c",
2285         .sysc   = &omap44xx_i2c_sysc,
2286         .rev    = OMAP_I2C_IP_VERSION_2,
2287         .reset  = &omap_i2c_reset,
2288 };
2290 static struct omap_i2c_dev_attr i2c_dev_attr = {
2291         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
2292 };
2294 /* i2c1 */
2295 static struct omap_hwmod omap44xx_i2c1_hwmod;
2296 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2297         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2298         { .irq = -1 }
2299 };
2301 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2302         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2303         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2304         { .dma_req = -1 }
2305 };
2307 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2308         {
2309                 .pa_start       = 0x48070000,
2310                 .pa_end         = 0x480700ff,
2311                 .flags          = ADDR_TYPE_RT
2312         },
2313         { }
2314 };
2316 /* l4_per -> i2c1 */
2317 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2318         .master         = &omap44xx_l4_per_hwmod,
2319         .slave          = &omap44xx_i2c1_hwmod,
2320         .clk            = "l4_div_ck",
2321         .addr           = omap44xx_i2c1_addrs,
2322         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2323 };
2325 /* i2c1 slave ports */
2326 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2327         &omap44xx_l4_per__i2c1,
2328 };
2330 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2331         .name           = "i2c1",
2332         .class          = &omap44xx_i2c_hwmod_class,
2333         .clkdm_name     = "l4_per_clkdm",
2334         .flags          = HWMOD_16BIT_REG,
2335         .mpu_irqs       = omap44xx_i2c1_irqs,
2336         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
2337         .main_clk       = "i2c1_fck",
2338         .prcm = {
2339                 .omap4 = {
2340                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
2341                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
2342                         .modulemode   = MODULEMODE_SWCTRL,
2343                 },
2344         },
2345         .slaves         = omap44xx_i2c1_slaves,
2346         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
2347         .dev_attr       = &i2c_dev_attr,
2348         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2349 };
2351 /* i2c2 */
2352 static struct omap_hwmod omap44xx_i2c2_hwmod;
2353 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2354         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2355         { .irq = -1 }
2356 };
2358 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2359         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2360         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2361         { .dma_req = -1 }
2362 };
2364 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2365         {
2366                 .pa_start       = 0x48072000,
2367                 .pa_end         = 0x480720ff,
2368                 .flags          = ADDR_TYPE_RT
2369         },
2370         { }
2371 };
2373 /* l4_per -> i2c2 */
2374 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2375         .master         = &omap44xx_l4_per_hwmod,
2376         .slave          = &omap44xx_i2c2_hwmod,
2377         .clk            = "l4_div_ck",
2378         .addr           = omap44xx_i2c2_addrs,
2379         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2380 };
2382 /* i2c2 slave ports */
2383 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2384         &omap44xx_l4_per__i2c2,
2385 };
2387 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2388         .name           = "i2c2",
2389         .class          = &omap44xx_i2c_hwmod_class,
2390         .clkdm_name     = "l4_per_clkdm",
2391         .flags          = HWMOD_16BIT_REG,
2392         .mpu_irqs       = omap44xx_i2c2_irqs,
2393         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
2394         .main_clk       = "i2c2_fck",
2395         .prcm = {
2396                 .omap4 = {
2397                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
2398                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
2399                         .modulemode   = MODULEMODE_SWCTRL,
2400                 },
2401         },
2402         .slaves         = omap44xx_i2c2_slaves,
2403         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
2404         .dev_attr       = &i2c_dev_attr,
2405         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2406 };
2408 /* i2c3 */
2409 static struct omap_hwmod omap44xx_i2c3_hwmod;
2410 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2411         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2412         { .irq = -1 }
2413 };
2415 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2416         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2417         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2418         { .dma_req = -1 }
2419 };
2421 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2422         {
2423                 .pa_start       = 0x48060000,
2424                 .pa_end         = 0x480600ff,
2425                 .flags          = ADDR_TYPE_RT
2426         },
2427         { }
2428 };
2430 /* l4_per -> i2c3 */
2431 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2432         .master         = &omap44xx_l4_per_hwmod,
2433         .slave          = &omap44xx_i2c3_hwmod,
2434         .clk            = "l4_div_ck",
2435         .addr           = omap44xx_i2c3_addrs,
2436         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2437 };
2439 /* i2c3 slave ports */
2440 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2441         &omap44xx_l4_per__i2c3,
2442 };
2444 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2445         .name           = "i2c3",
2446         .class          = &omap44xx_i2c_hwmod_class,
2447         .clkdm_name     = "l4_per_clkdm",
2448         .flags          = HWMOD_16BIT_REG,
2449         .mpu_irqs       = omap44xx_i2c3_irqs,
2450         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
2451         .main_clk       = "i2c3_fck",
2452         .prcm = {
2453                 .omap4 = {
2454                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
2455                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
2456                         .modulemode   = MODULEMODE_SWCTRL,
2457                 },
2458         },
2459         .slaves         = omap44xx_i2c3_slaves,
2460         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
2461         .dev_attr       = &i2c_dev_attr,
2462         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2463 };
2465 /* i2c4 */
2466 static struct omap_hwmod omap44xx_i2c4_hwmod;
2467 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2468         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2469         { .irq = -1 }
2470 };
2472 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2473         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2474         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2475         { .dma_req = -1 }
2476 };
2478 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2479         {
2480                 .pa_start       = 0x48350000,
2481                 .pa_end         = 0x483500ff,
2482                 .flags          = ADDR_TYPE_RT
2483         },
2484         { }
2485 };
2487 /* l4_per -> i2c4 */
2488 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2489         .master         = &omap44xx_l4_per_hwmod,
2490         .slave          = &omap44xx_i2c4_hwmod,
2491         .clk            = "l4_div_ck",
2492         .addr           = omap44xx_i2c4_addrs,
2493         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2494 };
2496 /* i2c4 slave ports */
2497 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2498         &omap44xx_l4_per__i2c4,
2499 };
2501 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2502         .name           = "i2c4",
2503         .class          = &omap44xx_i2c_hwmod_class,
2504         .clkdm_name     = "l4_per_clkdm",
2505         .flags          = HWMOD_16BIT_REG,
2506         .mpu_irqs       = omap44xx_i2c4_irqs,
2507         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
2508         .main_clk       = "i2c4_fck",
2509         .prcm = {
2510                 .omap4 = {
2511                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
2512                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
2513                         .modulemode   = MODULEMODE_SWCTRL,
2514                 },
2515         },
2516         .slaves         = omap44xx_i2c4_slaves,
2517         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
2518         .dev_attr       = &i2c_dev_attr,
2519         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2520 };
2522 /*
2523  * 'ipu' class
2524  * imaging processor unit
2525  */
2527 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2528         .name   = "ipu",
2529 };
2531 /* ipu */
2532 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2533         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2534         { .irq = -1 }
2535 };
2537 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2538         { .name = "cpu0", .rst_shift = 0 },
2539 };
2541 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2542         { .name = "cpu1", .rst_shift = 1 },
2543 };
2545 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2546         { .name = "mmu_cache", .rst_shift = 2 },
2547 };
2549 /* ipu master ports */
2550 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2551         &omap44xx_ipu__l3_main_2,
2552 };
2554 /* l3_main_2 -> ipu */
2555 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2556         .master         = &omap44xx_l3_main_2_hwmod,
2557         .slave          = &omap44xx_ipu_hwmod,
2558         .clk            = "l3_div_ck",
2559         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2560 };
2562 /* ipu slave ports */
2563 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2564         &omap44xx_l3_main_2__ipu,
2565 };
2567 /* Pseudo hwmod for reset control purpose only */
2568 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2569         .name           = "ipu_c0",
2570         .class          = &omap44xx_ipu_hwmod_class,
2571         .clkdm_name     = "ducati_clkdm",
2572         .flags          = HWMOD_INIT_NO_RESET,
2573         .rst_lines      = omap44xx_ipu_c0_resets,
2574         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2575         .prcm = {
2576                 .omap4 = {
2577                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2578                 },
2579         },
2580         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2581 };
2583 /* Pseudo hwmod for reset control purpose only */
2584 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2585         .name           = "ipu_c1",
2586         .class          = &omap44xx_ipu_hwmod_class,
2587         .clkdm_name     = "ducati_clkdm",
2588         .flags          = HWMOD_INIT_NO_RESET,
2589         .rst_lines      = omap44xx_ipu_c1_resets,
2590         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2591         .prcm = {
2592                 .omap4 = {
2593                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2594                 },
2595         },
2596         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2597 };
2599 static struct omap_hwmod omap44xx_ipu_hwmod = {
2600         .name           = "ipu",
2601         .class          = &omap44xx_ipu_hwmod_class,
2602         .clkdm_name     = "ducati_clkdm",
2603         .mpu_irqs       = omap44xx_ipu_irqs,
2604         .rst_lines      = omap44xx_ipu_resets,
2605         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
2606         .main_clk       = "ipu_fck",
2607         .prcm = {
2608                 .omap4 = {
2609                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2610                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2611                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2612                         .modulemode   = MODULEMODE_HWCTRL,
2613                 },
2614         },
2615         .slaves         = omap44xx_ipu_slaves,
2616         .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
2617         .masters        = omap44xx_ipu_masters,
2618         .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
2619         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2620 };
2622 /*
2623  * 'iss' class
2624  * external images sensor pixel data processor
2625  */
2627 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2628         .rev_offs       = 0x0000,
2629         .sysc_offs      = 0x0010,
2630         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2631                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2632         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2633                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2634                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2635         .sysc_fields    = &omap_hwmod_sysc_type2,
2636 };
2638 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2639         .name   = "iss",
2640         .sysc   = &omap44xx_iss_sysc,
2641 };
2643 /* iss */
2644 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2645         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2646         { .irq = -1 }
2647 };
2649 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2650         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2651         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2652         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2653         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2654         { .dma_req = -1 }
2655 };
2657 /* iss master ports */
2658 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2659         &omap44xx_iss__l3_main_2,
2660 };
2662 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2663         {
2664                 .pa_start       = 0x52000000,
2665                 .pa_end         = 0x520000ff,
2666                 .flags          = ADDR_TYPE_RT
2667         },
2668         { }
2669 };
2671 /* l3_main_2 -> iss */
2672 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2673         .master         = &omap44xx_l3_main_2_hwmod,
2674         .slave          = &omap44xx_iss_hwmod,
2675         .clk            = "l3_div_ck",
2676         .addr           = omap44xx_iss_addrs,
2677         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2678 };
2680 /* iss slave ports */
2681 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2682         &omap44xx_l3_main_2__iss,
2683 };
2685 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2686         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2687 };
2689 static struct omap_hwmod omap44xx_iss_hwmod = {
2690         .name           = "iss",
2691         .class          = &omap44xx_iss_hwmod_class,
2692         .clkdm_name     = "iss_clkdm",
2693         .mpu_irqs       = omap44xx_iss_irqs,
2694         .sdma_reqs      = omap44xx_iss_sdma_reqs,
2695         .main_clk       = "iss_fck",
2696         .prcm = {
2697                 .omap4 = {
2698                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
2699                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
2700                         .modulemode   = MODULEMODE_SWCTRL,
2701                 },
2702         },
2703         .opt_clks       = iss_opt_clks,
2704         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
2705         .slaves         = omap44xx_iss_slaves,
2706         .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
2707         .masters        = omap44xx_iss_masters,
2708         .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
2709         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2710 };
2712 /*
2713  * 'iva' class
2714  * multi-standard video encoder/decoder hardware accelerator
2715  */
2717 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2718         .name   = "iva",
2719 };
2721 /* iva */
2722 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2723         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2724         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2725         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2726         { .irq = -1 }
2727 };
2729 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2730         { .name = "logic", .rst_shift = 2 },
2731 };
2733 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2734         { .name = "seq0", .rst_shift = 0 },
2735 };
2737 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2738         { .name = "seq1", .rst_shift = 1 },
2739 };
2741 /* iva master ports */
2742 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2743         &omap44xx_iva__l3_main_2,
2744         &omap44xx_iva__l3_instr,
2745 };
2747 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2748         {
2749                 .pa_start       = 0x5a000000,
2750                 .pa_end         = 0x5a07ffff,
2751                 .flags          = ADDR_TYPE_RT
2752         },
2753         { }
2754 };
2756 /* l3_main_2 -> iva */
2757 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2758         .master         = &omap44xx_l3_main_2_hwmod,
2759         .slave          = &omap44xx_iva_hwmod,
2760         .clk            = "l3_div_ck",
2761         .addr           = omap44xx_iva_addrs,
2762         .user           = OCP_USER_MPU,
2763 };
2765 /* iva slave ports */
2766 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2767         &omap44xx_dsp__iva,
2768         &omap44xx_l3_main_2__iva,
2769 };
2771 /* Pseudo hwmod for reset control purpose only */
2772 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2773         .name           = "iva_seq0",
2774         .class          = &omap44xx_iva_hwmod_class,
2775         .clkdm_name     = "ivahd_clkdm",
2776         .flags          = HWMOD_INIT_NO_RESET,
2777         .rst_lines      = omap44xx_iva_seq0_resets,
2778         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2779         .prcm = {
2780                 .omap4 = {
2781                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2782                 },
2783         },
2784         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2785 };
2787 /* Pseudo hwmod for reset control purpose only */
2788 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2789         .name           = "iva_seq1",
2790         .class          = &omap44xx_iva_hwmod_class,
2791         .clkdm_name     = "ivahd_clkdm",
2792         .flags          = HWMOD_INIT_NO_RESET,
2793         .rst_lines      = omap44xx_iva_seq1_resets,
2794         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2795         .prcm = {
2796                 .omap4 = {
2797                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2798                 },
2799         },
2800         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2801 };
2803 static struct omap_hwmod omap44xx_iva_hwmod = {
2804         .name           = "iva",
2805         .class          = &omap44xx_iva_hwmod_class,
2806         .clkdm_name     = "ivahd_clkdm",
2807         .mpu_irqs       = omap44xx_iva_irqs,
2808         .rst_lines      = omap44xx_iva_resets,
2809         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
2810         .main_clk       = "iva_fck",
2811         .prcm = {
2812                 .omap4 = {
2813                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
2814                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2815                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
2816                         .modulemode   = MODULEMODE_HWCTRL,
2817                 },
2818         },
2819         .slaves         = omap44xx_iva_slaves,
2820         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
2821         .masters        = omap44xx_iva_masters,
2822         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
2823         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2824 };
2826 /*
2827  * 'kbd' class
2828  * keyboard controller
2829  */
2831 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2832         .rev_offs       = 0x0000,
2833         .sysc_offs      = 0x0010,
2834         .syss_offs      = 0x0014,
2835         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2836                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2837                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2838                            SYSS_HAS_RESET_STATUS),
2839         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2840         .sysc_fields    = &omap_hwmod_sysc_type1,
2841 };
2843 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2844         .name   = "kbd",
2845         .sysc   = &omap44xx_kbd_sysc,
2846 };
2848 /* kbd */
2849 static struct omap_hwmod omap44xx_kbd_hwmod;
2850 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2851         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2852         { .irq = -1 }
2853 };
2855 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2856         {
2857                 .pa_start       = 0x4a31c000,
2858                 .pa_end         = 0x4a31c07f,
2859                 .flags          = ADDR_TYPE_RT
2860         },
2861         { }
2862 };
2864 /* l4_wkup -> kbd */
2865 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2866         .master         = &omap44xx_l4_wkup_hwmod,
2867         .slave          = &omap44xx_kbd_hwmod,
2868         .clk            = "l4_wkup_clk_mux_ck",
2869         .addr           = omap44xx_kbd_addrs,
2870         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2871 };
2873 /* kbd slave ports */
2874 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2875         &omap44xx_l4_wkup__kbd,
2876 };
2878 static struct omap_hwmod omap44xx_kbd_hwmod = {
2879         .name           = "kbd",
2880         .class          = &omap44xx_kbd_hwmod_class,
2881         .clkdm_name     = "l4_wkup_clkdm",
2882         .mpu_irqs       = omap44xx_kbd_irqs,
2883         .main_clk       = "kbd_fck",
2884         .prcm = {
2885                 .omap4 = {
2886                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
2887                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
2888                         .modulemode   = MODULEMODE_SWCTRL,
2889                 },
2890         },
2891         .slaves         = omap44xx_kbd_slaves,
2892         .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
2893         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2894 };
2896 /*
2897  * 'mailbox' class
2898  * mailbox module allowing communication between the on-chip processors using a
2899  * queued mailbox-interrupt mechanism.
2900  */
2902 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2903         .rev_offs       = 0x0000,
2904         .sysc_offs      = 0x0010,
2905         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2906                            SYSC_HAS_SOFTRESET),
2907         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2908         .sysc_fields    = &omap_hwmod_sysc_type2,
2909 };
2911 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2912         .name   = "mailbox",
2913         .sysc   = &omap44xx_mailbox_sysc,
2914 };
2916 /* mailbox */
2917 static struct omap_hwmod omap44xx_mailbox_hwmod;
2918 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2919         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2920         { .irq = -1 }
2921 };
2923 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2924         {
2925                 .pa_start       = 0x4a0f4000,
2926                 .pa_end         = 0x4a0f41ff,
2927                 .flags          = ADDR_TYPE_RT
2928         },
2929         { }
2930 };
2932 /* l4_cfg -> mailbox */
2933 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2934         .master         = &omap44xx_l4_cfg_hwmod,
2935         .slave          = &omap44xx_mailbox_hwmod,
2936         .clk            = "l4_div_ck",
2937         .addr           = omap44xx_mailbox_addrs,
2938         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2939 };
2941 /* mailbox slave ports */
2942 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2943         &omap44xx_l4_cfg__mailbox,
2944 };
2946 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2947         .name           = "mailbox",
2948         .class          = &omap44xx_mailbox_hwmod_class,
2949         .clkdm_name     = "l4_cfg_clkdm",
2950         .mpu_irqs       = omap44xx_mailbox_irqs,
2951         .prcm = {
2952                 .omap4 = {
2953                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
2954                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
2955                 },
2956         },
2957         .slaves         = omap44xx_mailbox_slaves,
2958         .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
2959         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2960 };
2962 /*
2963  * 'mcbsp' class
2964  * multi channel buffered serial port controller
2965  */
2967 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2968         .sysc_offs      = 0x008c,
2969         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2970                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2971         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2972         .sysc_fields    = &omap_hwmod_sysc_type1,
2973 };
2975 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2976         .name   = "mcbsp",
2977         .sysc   = &omap44xx_mcbsp_sysc,
2978         .rev    = MCBSP_CONFIG_TYPE4,
2979 };
2981 /* mcbsp1 */
2982 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2983 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2984         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2985         { .irq = -1 }
2986 };
2988 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2989         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2990         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2991         { .dma_req = -1 }
2992 };
2994 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2995         {
2996                 .name           = "mpu",
2997                 .pa_start       = 0x40122000,
2998                 .pa_end         = 0x401220ff,
2999                 .flags          = ADDR_TYPE_RT
3000         },
3001         { }
3002 };
3004 /* l4_abe -> mcbsp1 */
3005 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
3006         .master         = &omap44xx_l4_abe_hwmod,
3007         .slave          = &omap44xx_mcbsp1_hwmod,
3008         .clk            = "ocp_abe_iclk",
3009         .addr           = omap44xx_mcbsp1_addrs,
3010         .user           = OCP_USER_MPU,
3011 };
3013 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
3014         {
3015                 .name           = "dma",
3016                 .pa_start       = 0x49022000,
3017                 .pa_end         = 0x490220ff,
3018                 .flags          = ADDR_TYPE_RT
3019         },
3020         { }
3021 };
3023 /* l4_abe -> mcbsp1 (dma) */
3024 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
3025         .master         = &omap44xx_l4_abe_hwmod,
3026         .slave          = &omap44xx_mcbsp1_hwmod,
3027         .clk            = "ocp_abe_iclk",
3028         .addr           = omap44xx_mcbsp1_dma_addrs,
3029         .user           = OCP_USER_SDMA,
3030 };
3032 /* mcbsp1 slave ports */
3033 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
3034         &omap44xx_l4_abe__mcbsp1,
3035         &omap44xx_l4_abe__mcbsp1_dma,
3036 };