d68ef2ce6f1c86ffd49481686b0fa71b02b63602
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / omap_hwmod_44xx_data.c
1 /*
2  * Hardware modules present on the OMAP44xx chips
3  *
4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
5  * Copyright (C) 2009-2010 Nokia Corporation
6  *
7  * Paul Walmsley
8  * Benoit Cousson
9  *
10  * This file is automatically generated from the OMAP hardware databases.
11  * We respectfully ask that any modifications to this file be coordinated
12  * with the public linux-omap@vger.kernel.org mailing list and the
13  * authors above to ensure that the autogeneration scripts are kept
14  * up-to-date with the file contents.
15  *
16  * This program is free software; you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License version 2 as
18  * published by the Free Software Foundation.
19  */
21 #include <linux/io.h>
23 #include <plat/omap_hwmod.h>
24 #include <plat/cpu.h>
25 #include <plat/i2c.h>
26 #include <plat/gpio.h>
27 #include <plat/dma.h>
28 #include <plat/mcspi.h>
29 #include <plat/mcbsp.h>
30 #include <plat/mmc.h>
31 #include <plat/i2c.h>
33 #include "omap_hwmod_common_data.h"
35 #include "cm1_44xx.h"
36 #include "cm2_44xx.h"
37 #include "prm44xx.h"
38 #include "prm-regbits-44xx.h"
39 #include "wd_timer.h"
41 /* Base offset for all OMAP4 interrupts external to MPUSS */
42 #define OMAP44XX_IRQ_GIC_START  32
44 /* Base offset for all OMAP4 dma requests */
45 #define OMAP44XX_DMA_REQ_START  1
47 /* Backward references (IPs with Bus Master capability) */
48 static struct omap_hwmod omap44xx_aess_hwmod;
49 static struct omap_hwmod omap44xx_dma_system_hwmod;
50 static struct omap_hwmod omap44xx_dmm_hwmod;
51 static struct omap_hwmod omap44xx_dsp_hwmod;
52 static struct omap_hwmod omap44xx_dss_hwmod;
53 static struct omap_hwmod omap44xx_emif_fw_hwmod;
54 static struct omap_hwmod omap44xx_hsi_hwmod;
55 static struct omap_hwmod omap44xx_ipu_hwmod;
56 static struct omap_hwmod omap44xx_iss_hwmod;
57 static struct omap_hwmod omap44xx_iva_hwmod;
58 static struct omap_hwmod omap44xx_l3_instr_hwmod;
59 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
60 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
61 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
62 static struct omap_hwmod omap44xx_l4_abe_hwmod;
63 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
64 static struct omap_hwmod omap44xx_l4_per_hwmod;
65 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
66 static struct omap_hwmod omap44xx_mmc1_hwmod;
67 static struct omap_hwmod omap44xx_mmc2_hwmod;
68 static struct omap_hwmod omap44xx_mpu_hwmod;
69 static struct omap_hwmod omap44xx_mpu_private_hwmod;
70 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
72 /*
73  * Interconnects omap_hwmod structures
74  * hwmods that compose the global OMAP interconnect
75  */
77 /*
78  * 'dmm' class
79  * instance(s): dmm
80  */
81 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
82         .name   = "dmm",
83 };
85 /* dmm */
86 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
87         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
88         { .irq = -1 }
89 };
91 /* l3_main_1 -> dmm */
92 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
93         .master         = &omap44xx_l3_main_1_hwmod,
94         .slave          = &omap44xx_dmm_hwmod,
95         .clk            = "l3_div_ck",
96         .user           = OCP_USER_SDMA,
97 };
99 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
100         {
101                 .pa_start       = 0x4e000000,
102                 .pa_end         = 0x4e0007ff,
103                 .flags          = ADDR_TYPE_RT
104         },
105         { }
106 };
108 /* mpu -> dmm */
109 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
110         .master         = &omap44xx_mpu_hwmod,
111         .slave          = &omap44xx_dmm_hwmod,
112         .clk            = "l3_div_ck",
113         .addr           = omap44xx_dmm_addrs,
114         .user           = OCP_USER_MPU,
115 };
117 /* dmm slave ports */
118 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
119         &omap44xx_l3_main_1__dmm,
120         &omap44xx_mpu__dmm,
121 };
123 static struct omap_hwmod omap44xx_dmm_hwmod = {
124         .name           = "dmm",
125         .class          = &omap44xx_dmm_hwmod_class,
126         .clkdm_name     = "l3_emif_clkdm",
127         .prcm = {
128                 .omap4 = {
129                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
130                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
131                 },
132         },
133         .slaves         = omap44xx_dmm_slaves,
134         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
135         .mpu_irqs       = omap44xx_dmm_irqs,
136         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
137 };
139 /*
140  * 'emif_fw' class
141  * instance(s): emif_fw
142  */
143 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
144         .name   = "emif_fw",
145 };
147 /* emif_fw */
148 /* dmm -> emif_fw */
149 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
150         .master         = &omap44xx_dmm_hwmod,
151         .slave          = &omap44xx_emif_fw_hwmod,
152         .clk            = "l3_div_ck",
153         .user           = OCP_USER_MPU | OCP_USER_SDMA,
154 };
156 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
157         {
158                 .pa_start       = 0x4a20c000,
159                 .pa_end         = 0x4a20c0ff,
160                 .flags          = ADDR_TYPE_RT
161         },
162         { }
163 };
165 /* l4_cfg -> emif_fw */
166 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
167         .master         = &omap44xx_l4_cfg_hwmod,
168         .slave          = &omap44xx_emif_fw_hwmod,
169         .clk            = "l4_div_ck",
170         .addr           = omap44xx_emif_fw_addrs,
171         .user           = OCP_USER_MPU,
172 };
174 /* emif_fw slave ports */
175 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
176         &omap44xx_dmm__emif_fw,
177         &omap44xx_l4_cfg__emif_fw,
178 };
180 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
181         .name           = "emif_fw",
182         .class          = &omap44xx_emif_fw_hwmod_class,
183         .clkdm_name     = "l3_emif_clkdm",
184         .prcm = {
185                 .omap4 = {
186                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
187                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
188                 },
189         },
190         .slaves         = omap44xx_emif_fw_slaves,
191         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
192         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
193 };
195 /*
196  * 'l3' class
197  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
198  */
199 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
200         .name   = "l3",
201 };
203 /* l3_instr */
204 /* iva -> l3_instr */
205 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
206         .master         = &omap44xx_iva_hwmod,
207         .slave          = &omap44xx_l3_instr_hwmod,
208         .clk            = "l3_div_ck",
209         .user           = OCP_USER_MPU | OCP_USER_SDMA,
210 };
212 /* l3_main_3 -> l3_instr */
213 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
214         .master         = &omap44xx_l3_main_3_hwmod,
215         .slave          = &omap44xx_l3_instr_hwmod,
216         .clk            = "l3_div_ck",
217         .user           = OCP_USER_MPU | OCP_USER_SDMA,
218 };
220 /* l3_instr slave ports */
221 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
222         &omap44xx_iva__l3_instr,
223         &omap44xx_l3_main_3__l3_instr,
224 };
226 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
227         .name           = "l3_instr",
228         .class          = &omap44xx_l3_hwmod_class,
229         .clkdm_name     = "l3_instr_clkdm",
230         .prcm = {
231                 .omap4 = {
232                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
233                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
234                 },
235         },
236         .slaves         = omap44xx_l3_instr_slaves,
237         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
238         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
239 };
241 /* l3_main_1 */
242 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
243         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
244         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
245         { .irq = -1 }
246 };
248 /* dsp -> l3_main_1 */
249 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
250         .master         = &omap44xx_dsp_hwmod,
251         .slave          = &omap44xx_l3_main_1_hwmod,
252         .clk            = "l3_div_ck",
253         .user           = OCP_USER_MPU | OCP_USER_SDMA,
254 };
256 /* dss -> l3_main_1 */
257 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
258         .master         = &omap44xx_dss_hwmod,
259         .slave          = &omap44xx_l3_main_1_hwmod,
260         .clk            = "l3_div_ck",
261         .user           = OCP_USER_MPU | OCP_USER_SDMA,
262 };
264 /* l3_main_2 -> l3_main_1 */
265 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
266         .master         = &omap44xx_l3_main_2_hwmod,
267         .slave          = &omap44xx_l3_main_1_hwmod,
268         .clk            = "l3_div_ck",
269         .user           = OCP_USER_MPU | OCP_USER_SDMA,
270 };
272 /* l4_cfg -> l3_main_1 */
273 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
274         .master         = &omap44xx_l4_cfg_hwmod,
275         .slave          = &omap44xx_l3_main_1_hwmod,
276         .clk            = "l4_div_ck",
277         .user           = OCP_USER_MPU | OCP_USER_SDMA,
278 };
280 /* mmc1 -> l3_main_1 */
281 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
282         .master         = &omap44xx_mmc1_hwmod,
283         .slave          = &omap44xx_l3_main_1_hwmod,
284         .clk            = "l3_div_ck",
285         .user           = OCP_USER_MPU | OCP_USER_SDMA,
286 };
288 /* mmc2 -> l3_main_1 */
289 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
290         .master         = &omap44xx_mmc2_hwmod,
291         .slave          = &omap44xx_l3_main_1_hwmod,
292         .clk            = "l3_div_ck",
293         .user           = OCP_USER_MPU | OCP_USER_SDMA,
294 };
296 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
297         {
298                 .pa_start       = 0x44000000,
299                 .pa_end         = 0x44000fff,
300                 .flags          = ADDR_TYPE_RT
301         },
302         { }
303 };
305 /* mpu -> l3_main_1 */
306 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
307         .master         = &omap44xx_mpu_hwmod,
308         .slave          = &omap44xx_l3_main_1_hwmod,
309         .clk            = "l3_div_ck",
310         .addr           = omap44xx_l3_main_1_addrs,
311         .user           = OCP_USER_MPU,
312 };
314 /* l3_main_1 slave ports */
315 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
316         &omap44xx_dsp__l3_main_1,
317         &omap44xx_dss__l3_main_1,
318         &omap44xx_l3_main_2__l3_main_1,
319         &omap44xx_l4_cfg__l3_main_1,
320         &omap44xx_mmc1__l3_main_1,
321         &omap44xx_mmc2__l3_main_1,
322         &omap44xx_mpu__l3_main_1,
323 };
325 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
326         .name           = "l3_main_1",
327         .class          = &omap44xx_l3_hwmod_class,
328         .clkdm_name     = "l3_1_clkdm",
329         .mpu_irqs       = omap44xx_l3_main_1_irqs,
330         .prcm = {
331                 .omap4 = {
332                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
333                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
334                 },
335         },
336         .slaves         = omap44xx_l3_main_1_slaves,
337         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
338         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
339 };
341 /* l3_main_2 */
342 /* dma_system -> l3_main_2 */
343 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
344         .master         = &omap44xx_dma_system_hwmod,
345         .slave          = &omap44xx_l3_main_2_hwmod,
346         .clk            = "l3_div_ck",
347         .user           = OCP_USER_MPU | OCP_USER_SDMA,
348 };
350 /* hsi -> l3_main_2 */
351 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
352         .master         = &omap44xx_hsi_hwmod,
353         .slave          = &omap44xx_l3_main_2_hwmod,
354         .clk            = "l3_div_ck",
355         .user           = OCP_USER_MPU | OCP_USER_SDMA,
356 };
358 /* ipu -> l3_main_2 */
359 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
360         .master         = &omap44xx_ipu_hwmod,
361         .slave          = &omap44xx_l3_main_2_hwmod,
362         .clk            = "l3_div_ck",
363         .user           = OCP_USER_MPU | OCP_USER_SDMA,
364 };
366 /* iss -> l3_main_2 */
367 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
368         .master         = &omap44xx_iss_hwmod,
369         .slave          = &omap44xx_l3_main_2_hwmod,
370         .clk            = "l3_div_ck",
371         .user           = OCP_USER_MPU | OCP_USER_SDMA,
372 };
374 /* iva -> l3_main_2 */
375 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
376         .master         = &omap44xx_iva_hwmod,
377         .slave          = &omap44xx_l3_main_2_hwmod,
378         .clk            = "l3_div_ck",
379         .user           = OCP_USER_MPU | OCP_USER_SDMA,
380 };
382 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
383         {
384                 .pa_start       = 0x44800000,
385                 .pa_end         = 0x44801fff,
386                 .flags          = ADDR_TYPE_RT
387         },
388         { }
389 };
391 /* l3_main_1 -> l3_main_2 */
392 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
393         .master         = &omap44xx_l3_main_1_hwmod,
394         .slave          = &omap44xx_l3_main_2_hwmod,
395         .clk            = "l3_div_ck",
396         .addr           = omap44xx_l3_main_2_addrs,
397         .user           = OCP_USER_MPU,
398 };
400 /* l4_cfg -> l3_main_2 */
401 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
402         .master         = &omap44xx_l4_cfg_hwmod,
403         .slave          = &omap44xx_l3_main_2_hwmod,
404         .clk            = "l4_div_ck",
405         .user           = OCP_USER_MPU | OCP_USER_SDMA,
406 };
408 /* usb_otg_hs -> l3_main_2 */
409 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
410         .master         = &omap44xx_usb_otg_hs_hwmod,
411         .slave          = &omap44xx_l3_main_2_hwmod,
412         .clk            = "l3_div_ck",
413         .user           = OCP_USER_MPU | OCP_USER_SDMA,
414 };
416 /* l3_main_2 slave ports */
417 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
418         &omap44xx_dma_system__l3_main_2,
419         &omap44xx_hsi__l3_main_2,
420         &omap44xx_ipu__l3_main_2,
421         &omap44xx_iss__l3_main_2,
422         &omap44xx_iva__l3_main_2,
423         &omap44xx_l3_main_1__l3_main_2,
424         &omap44xx_l4_cfg__l3_main_2,
425         &omap44xx_usb_otg_hs__l3_main_2,
426 };
428 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
429         .name           = "l3_main_2",
430         .class          = &omap44xx_l3_hwmod_class,
431         .clkdm_name     = "l3_2_clkdm",
432         .prcm = {
433                 .omap4 = {
434                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
435                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
436                 },
437         },
438         .slaves         = omap44xx_l3_main_2_slaves,
439         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
440         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
441 };
443 /* l3_main_3 */
444 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
445         {
446                 .pa_start       = 0x45000000,
447                 .pa_end         = 0x45000fff,
448                 .flags          = ADDR_TYPE_RT
449         },
450         { }
451 };
453 /* l3_main_1 -> l3_main_3 */
454 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
455         .master         = &omap44xx_l3_main_1_hwmod,
456         .slave          = &omap44xx_l3_main_3_hwmod,
457         .clk            = "l3_div_ck",
458         .addr           = omap44xx_l3_main_3_addrs,
459         .user           = OCP_USER_MPU,
460 };
462 /* l3_main_2 -> l3_main_3 */
463 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
464         .master         = &omap44xx_l3_main_2_hwmod,
465         .slave          = &omap44xx_l3_main_3_hwmod,
466         .clk            = "l3_div_ck",
467         .user           = OCP_USER_MPU | OCP_USER_SDMA,
468 };
470 /* l4_cfg -> l3_main_3 */
471 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
472         .master         = &omap44xx_l4_cfg_hwmod,
473         .slave          = &omap44xx_l3_main_3_hwmod,
474         .clk            = "l4_div_ck",
475         .user           = OCP_USER_MPU | OCP_USER_SDMA,
476 };
478 /* l3_main_3 slave ports */
479 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
480         &omap44xx_l3_main_1__l3_main_3,
481         &omap44xx_l3_main_2__l3_main_3,
482         &omap44xx_l4_cfg__l3_main_3,
483 };
485 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
486         .name           = "l3_main_3",
487         .class          = &omap44xx_l3_hwmod_class,
488         .clkdm_name     = "l3_instr_clkdm",
489         .prcm = {
490                 .omap4 = {
491                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
492                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
493                 },
494         },
495         .slaves         = omap44xx_l3_main_3_slaves,
496         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
497         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
498 };
500 /*
501  * 'l4' class
502  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
503  */
504 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
505         .name   = "l4",
506 };
508 /* l4_abe */
509 /* aess -> l4_abe */
510 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
511         .master         = &omap44xx_aess_hwmod,
512         .slave          = &omap44xx_l4_abe_hwmod,
513         .clk            = "ocp_abe_iclk",
514         .user           = OCP_USER_MPU | OCP_USER_SDMA,
515 };
517 /* dsp -> l4_abe */
518 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
519         .master         = &omap44xx_dsp_hwmod,
520         .slave          = &omap44xx_l4_abe_hwmod,
521         .clk            = "ocp_abe_iclk",
522         .user           = OCP_USER_MPU | OCP_USER_SDMA,
523 };
525 /* l3_main_1 -> l4_abe */
526 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
527         .master         = &omap44xx_l3_main_1_hwmod,
528         .slave          = &omap44xx_l4_abe_hwmod,
529         .clk            = "l3_div_ck",
530         .user           = OCP_USER_MPU | OCP_USER_SDMA,
531 };
533 /* mpu -> l4_abe */
534 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
535         .master         = &omap44xx_mpu_hwmod,
536         .slave          = &omap44xx_l4_abe_hwmod,
537         .clk            = "ocp_abe_iclk",
538         .user           = OCP_USER_MPU | OCP_USER_SDMA,
539 };
541 /* l4_abe slave ports */
542 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
543         &omap44xx_aess__l4_abe,
544         &omap44xx_dsp__l4_abe,
545         &omap44xx_l3_main_1__l4_abe,
546         &omap44xx_mpu__l4_abe,
547 };
549 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
550         .name           = "l4_abe",
551         .class          = &omap44xx_l4_hwmod_class,
552         .clkdm_name     = "abe_clkdm",
553         .prcm = {
554                 .omap4 = {
555                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
556                 },
557         },
558         .slaves         = omap44xx_l4_abe_slaves,
559         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
560         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
561 };
563 /* l4_cfg */
564 /* l3_main_1 -> l4_cfg */
565 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
566         .master         = &omap44xx_l3_main_1_hwmod,
567         .slave          = &omap44xx_l4_cfg_hwmod,
568         .clk            = "l3_div_ck",
569         .user           = OCP_USER_MPU | OCP_USER_SDMA,
570 };
572 /* l4_cfg slave ports */
573 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
574         &omap44xx_l3_main_1__l4_cfg,
575 };
577 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
578         .name           = "l4_cfg",
579         .class          = &omap44xx_l4_hwmod_class,
580         .clkdm_name     = "l4_cfg_clkdm",
581         .prcm = {
582                 .omap4 = {
583                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
584                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
585                 },
586         },
587         .slaves         = omap44xx_l4_cfg_slaves,
588         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
589         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
590 };
592 /* l4_per */
593 /* l3_main_2 -> l4_per */
594 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
595         .master         = &omap44xx_l3_main_2_hwmod,
596         .slave          = &omap44xx_l4_per_hwmod,
597         .clk            = "l3_div_ck",
598         .user           = OCP_USER_MPU | OCP_USER_SDMA,
599 };
601 /* l4_per slave ports */
602 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
603         &omap44xx_l3_main_2__l4_per,
604 };
606 static struct omap_hwmod omap44xx_l4_per_hwmod = {
607         .name           = "l4_per",
608         .class          = &omap44xx_l4_hwmod_class,
609         .clkdm_name     = "l4_per_clkdm",
610         .prcm = {
611                 .omap4 = {
612                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
613                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
614                 },
615         },
616         .slaves         = omap44xx_l4_per_slaves,
617         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
618         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
619 };
621 /* l4_wkup */
622 /* l4_cfg -> l4_wkup */
623 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
624         .master         = &omap44xx_l4_cfg_hwmod,
625         .slave          = &omap44xx_l4_wkup_hwmod,
626         .clk            = "l4_div_ck",
627         .user           = OCP_USER_MPU | OCP_USER_SDMA,
628 };
630 /* l4_wkup slave ports */
631 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
632         &omap44xx_l4_cfg__l4_wkup,
633 };
635 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
636         .name           = "l4_wkup",
637         .class          = &omap44xx_l4_hwmod_class,
638         .clkdm_name     = "l4_wkup_clkdm",
639         .prcm = {
640                 .omap4 = {
641                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
642                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
643                 },
644         },
645         .slaves         = omap44xx_l4_wkup_slaves,
646         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
647         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
648 };
650 /*
651  * 'mpu_bus' class
652  * instance(s): mpu_private
653  */
654 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
655         .name   = "mpu_bus",
656 };
658 /* mpu_private */
659 /* mpu -> mpu_private */
660 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
661         .master         = &omap44xx_mpu_hwmod,
662         .slave          = &omap44xx_mpu_private_hwmod,
663         .clk            = "l3_div_ck",
664         .user           = OCP_USER_MPU | OCP_USER_SDMA,
665 };
667 /* mpu_private slave ports */
668 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
669         &omap44xx_mpu__mpu_private,
670 };
672 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
673         .name           = "mpu_private",
674         .class          = &omap44xx_mpu_bus_hwmod_class,
675         .clkdm_name     = "mpuss_clkdm",
676         .slaves         = omap44xx_mpu_private_slaves,
677         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
678         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
679 };
681 /*
682  * Modules omap_hwmod structures
683  *
684  * The following IPs are excluded for the moment because:
685  * - They do not need an explicit SW control using omap_hwmod API.
686  * - They still need to be validated with the driver
687  *   properly adapted to omap_hwmod / omap_device
688  *
689  *  c2c
690  *  c2c_target_fw
691  *  cm_core
692  *  cm_core_aon
693  *  ctrl_module_core
694  *  ctrl_module_pad_core
695  *  ctrl_module_pad_wkup
696  *  ctrl_module_wkup
697  *  debugss
698  *  efuse_ctrl_cust
699  *  efuse_ctrl_std
700  *  elm
701  *  emif1
702  *  emif2
703  *  fdif
704  *  gpmc
705  *  gpu
706  *  hdq1w
707  *  mcasp
708  *  mpu_c0
709  *  mpu_c1
710  *  ocmc_ram
711  *  ocp2scp_usb_phy
712  *  ocp_wp_noc
713  *  prcm_mpu
714  *  prm
715  *  scrm
716  *  sl2if
717  *  slimbus1
718  *  slimbus2
719  *  usb_host_fs
720  *  usb_host_hs
721  *  usb_phy_cm
722  *  usb_tll_hs
723  *  usim
724  */
726 /*
727  * 'aess' class
728  * audio engine sub system
729  */
731 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
732         .rev_offs       = 0x0000,
733         .sysc_offs      = 0x0010,
734         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
735         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
736                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
737                            MSTANDBY_SMART_WKUP),
738         .sysc_fields    = &omap_hwmod_sysc_type2,
739 };
741 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
742         .name   = "aess",
743         .sysc   = &omap44xx_aess_sysc,
744 };
746 /* aess */
747 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
748         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
749         { .irq = -1 }
750 };
752 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
753         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
754         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
755         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
756         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
757         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
758         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
759         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
760         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
761         { .dma_req = -1 }
762 };
764 /* aess master ports */
765 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
766         &omap44xx_aess__l4_abe,
767 };
769 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
770         {
771                 .pa_start       = 0x401f1000,
772                 .pa_end         = 0x401f13ff,
773                 .flags          = ADDR_TYPE_RT
774         },
775         { }
776 };
778 /* l4_abe -> aess */
779 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
780         .master         = &omap44xx_l4_abe_hwmod,
781         .slave          = &omap44xx_aess_hwmod,
782         .clk            = "ocp_abe_iclk",
783         .addr           = omap44xx_aess_addrs,
784         .user           = OCP_USER_MPU,
785 };
787 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
788         {
789                 .pa_start       = 0x490f1000,
790                 .pa_end         = 0x490f13ff,
791                 .flags          = ADDR_TYPE_RT
792         },
793         { }
794 };
796 /* l4_abe -> aess (dma) */
797 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
798         .master         = &omap44xx_l4_abe_hwmod,
799         .slave          = &omap44xx_aess_hwmod,
800         .clk            = "ocp_abe_iclk",
801         .addr           = omap44xx_aess_dma_addrs,
802         .user           = OCP_USER_SDMA,
803 };
805 /* aess slave ports */
806 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
807         &omap44xx_l4_abe__aess,
808         &omap44xx_l4_abe__aess_dma,
809 };
811 static struct omap_hwmod omap44xx_aess_hwmod = {
812         .name           = "aess",
813         .class          = &omap44xx_aess_hwmod_class,
814         .clkdm_name     = "abe_clkdm",
815         .mpu_irqs       = omap44xx_aess_irqs,
816         .sdma_reqs      = omap44xx_aess_sdma_reqs,
817         .main_clk       = "aess_fck",
818         .prcm = {
819                 .omap4 = {
820                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
821                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
822                 },
823         },
824         .slaves         = omap44xx_aess_slaves,
825         .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
826         .masters        = omap44xx_aess_masters,
827         .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
828         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
829 };
831 /*
832  * 'bandgap' class
833  * bangap reference for ldo regulators
834  */
836 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
837         .name   = "bandgap",
838 };
840 /* bandgap */
841 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
842         { .role = "fclk", .clk = "bandgap_fclk" },
843 };
845 static struct omap_hwmod omap44xx_bandgap_hwmod = {
846         .name           = "bandgap",
847         .class          = &omap44xx_bandgap_hwmod_class,
848         .clkdm_name     = "l4_wkup_clkdm",
849         .prcm = {
850                 .omap4 = {
851                         .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
852                 },
853         },
854         .opt_clks       = bandgap_opt_clks,
855         .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
856         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
857 };
859 /*
860  * 'counter' class
861  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
862  */
864 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
865         .rev_offs       = 0x0000,
866         .sysc_offs      = 0x0004,
867         .sysc_flags     = SYSC_HAS_SIDLEMODE,
868         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
869                            SIDLE_SMART_WKUP),
870         .sysc_fields    = &omap_hwmod_sysc_type1,
871 };
873 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
874         .name   = "counter",
875         .sysc   = &omap44xx_counter_sysc,
876 };
878 /* counter_32k */
879 static struct omap_hwmod omap44xx_counter_32k_hwmod;
880 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
881         {
882                 .pa_start       = 0x4a304000,
883                 .pa_end         = 0x4a30401f,
884                 .flags          = ADDR_TYPE_RT
885         },
886         { }
887 };
889 /* l4_wkup -> counter_32k */
890 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
891         .master         = &omap44xx_l4_wkup_hwmod,
892         .slave          = &omap44xx_counter_32k_hwmod,
893         .clk            = "l4_wkup_clk_mux_ck",
894         .addr           = omap44xx_counter_32k_addrs,
895         .user           = OCP_USER_MPU | OCP_USER_SDMA,
896 };
898 /* counter_32k slave ports */
899 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
900         &omap44xx_l4_wkup__counter_32k,
901 };
903 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
904         .name           = "counter_32k",
905         .class          = &omap44xx_counter_hwmod_class,
906         .clkdm_name     = "l4_wkup_clkdm",
907         .flags          = HWMOD_SWSUP_SIDLE,
908         .main_clk       = "sys_32k_ck",
909         .prcm = {
910                 .omap4 = {
911                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
912                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
913                 },
914         },
915         .slaves         = omap44xx_counter_32k_slaves,
916         .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
917         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
918 };
920 /*
921  * 'dma' class
922  * dma controller for data exchange between memory to memory (i.e. internal or
923  * external memory) and gp peripherals to memory or memory to gp peripherals
924  */
926 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
927         .rev_offs       = 0x0000,
928         .sysc_offs      = 0x002c,
929         .syss_offs      = 0x0028,
930         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
931                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
932                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
933                            SYSS_HAS_RESET_STATUS),
934         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
935                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
936         .sysc_fields    = &omap_hwmod_sysc_type1,
937 };
939 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
940         .name   = "dma",
941         .sysc   = &omap44xx_dma_sysc,
942 };
944 /* dma dev_attr */
945 static struct omap_dma_dev_attr dma_dev_attr = {
946         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
947                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
948         .lch_count      = 32,
949 };
951 /* dma_system */
952 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
953         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
954         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
955         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
956         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
957         { .irq = -1 }
958 };
960 /* dma_system master ports */
961 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
962         &omap44xx_dma_system__l3_main_2,
963 };
965 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
966         {
967                 .pa_start       = 0x4a056000,
968                 .pa_end         = 0x4a056fff,
969                 .flags          = ADDR_TYPE_RT
970         },
971         { }
972 };
974 /* l4_cfg -> dma_system */
975 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
976         .master         = &omap44xx_l4_cfg_hwmod,
977         .slave          = &omap44xx_dma_system_hwmod,
978         .clk            = "l4_div_ck",
979         .addr           = omap44xx_dma_system_addrs,
980         .user           = OCP_USER_MPU | OCP_USER_SDMA,
981 };
983 /* dma_system slave ports */
984 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
985         &omap44xx_l4_cfg__dma_system,
986 };
988 static struct omap_hwmod omap44xx_dma_system_hwmod = {
989         .name           = "dma_system",
990         .class          = &omap44xx_dma_hwmod_class,
991         .clkdm_name     = "l3_dma_clkdm",
992         .mpu_irqs       = omap44xx_dma_system_irqs,
993         .main_clk       = "l3_div_ck",
994         .prcm = {
995                 .omap4 = {
996                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
997                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
998                 },
999         },
1000         .dev_attr       = &dma_dev_attr,
1001         .slaves         = omap44xx_dma_system_slaves,
1002         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
1003         .masters        = omap44xx_dma_system_masters,
1004         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
1005         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1006 };
1008 /*
1009  * 'dmic' class
1010  * digital microphone controller
1011  */
1013 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
1014         .rev_offs       = 0x0000,
1015         .sysc_offs      = 0x0010,
1016         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1017                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1018         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1019                            SIDLE_SMART_WKUP),
1020         .sysc_fields    = &omap_hwmod_sysc_type2,
1021 };
1023 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
1024         .name   = "dmic",
1025         .sysc   = &omap44xx_dmic_sysc,
1026 };
1028 /* dmic */
1029 static struct omap_hwmod omap44xx_dmic_hwmod;
1030 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
1031         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
1032         { .irq = -1 }
1033 };
1035 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
1036         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
1037         { .dma_req = -1 }
1038 };
1040 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
1041         {
1042                 .pa_start       = 0x4012e000,
1043                 .pa_end         = 0x4012e07f,
1044                 .flags          = ADDR_TYPE_RT
1045         },
1046         { }
1047 };
1049 /* l4_abe -> dmic */
1050 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
1051         .master         = &omap44xx_l4_abe_hwmod,
1052         .slave          = &omap44xx_dmic_hwmod,
1053         .clk            = "ocp_abe_iclk",
1054         .addr           = omap44xx_dmic_addrs,
1055         .user           = OCP_USER_MPU,
1056 };
1058 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
1059         {
1060                 .pa_start       = 0x4902e000,
1061                 .pa_end         = 0x4902e07f,
1062                 .flags          = ADDR_TYPE_RT
1063         },
1064         { }
1065 };
1067 /* l4_abe -> dmic (dma) */
1068 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
1069         .master         = &omap44xx_l4_abe_hwmod,
1070         .slave          = &omap44xx_dmic_hwmod,
1071         .clk            = "ocp_abe_iclk",
1072         .addr           = omap44xx_dmic_dma_addrs,
1073         .user           = OCP_USER_SDMA,
1074 };
1076 /* dmic slave ports */
1077 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
1078         &omap44xx_l4_abe__dmic,
1079         &omap44xx_l4_abe__dmic_dma,
1080 };
1082 static struct omap_hwmod omap44xx_dmic_hwmod = {
1083         .name           = "dmic",
1084         .class          = &omap44xx_dmic_hwmod_class,
1085         .clkdm_name     = "abe_clkdm",
1086         .mpu_irqs       = omap44xx_dmic_irqs,
1087         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
1088         .main_clk       = "dmic_fck",
1089         .prcm = {
1090                 .omap4 = {
1091                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
1092                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
1093                 },
1094         },
1095         .slaves         = omap44xx_dmic_slaves,
1096         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
1097         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1098 };
1100 /*
1101  * 'dsp' class
1102  * dsp sub-system
1103  */
1105 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1106         .name   = "dsp",
1107 };
1109 /* dsp */
1110 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1111         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1112         { .irq = -1 }
1113 };
1115 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1116         { .name = "mmu_cache", .rst_shift = 1 },
1117 };
1119 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1120         { .name = "dsp", .rst_shift = 0 },
1121 };
1123 /* dsp -> iva */
1124 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1125         .master         = &omap44xx_dsp_hwmod,
1126         .slave          = &omap44xx_iva_hwmod,
1127         .clk            = "dpll_iva_m5x2_ck",
1128 };
1130 /* dsp master ports */
1131 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1132         &omap44xx_dsp__l3_main_1,
1133         &omap44xx_dsp__l4_abe,
1134         &omap44xx_dsp__iva,
1135 };
1137 /* l4_cfg -> dsp */
1138 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1139         .master         = &omap44xx_l4_cfg_hwmod,
1140         .slave          = &omap44xx_dsp_hwmod,
1141         .clk            = "l4_div_ck",
1142         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1143 };
1145 /* dsp slave ports */
1146 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1147         &omap44xx_l4_cfg__dsp,
1148 };
1150 /* Pseudo hwmod for reset control purpose only */
1151 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1152         .name           = "dsp_c0",
1153         .class          = &omap44xx_dsp_hwmod_class,
1154         .clkdm_name     = "tesla_clkdm",
1155         .flags          = HWMOD_INIT_NO_RESET,
1156         .rst_lines      = omap44xx_dsp_c0_resets,
1157         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1158         .prcm = {
1159                 .omap4 = {
1160                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1161                 },
1162         },
1163         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1164 };
1166 static struct omap_hwmod omap44xx_dsp_hwmod = {
1167         .name           = "dsp",
1168         .class          = &omap44xx_dsp_hwmod_class,
1169         .clkdm_name     = "tesla_clkdm",
1170         .mpu_irqs       = omap44xx_dsp_irqs,
1171         .rst_lines      = omap44xx_dsp_resets,
1172         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
1173         .main_clk       = "dsp_fck",
1174         .prcm = {
1175                 .omap4 = {
1176                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
1177                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1178                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
1179                 },
1180         },
1181         .slaves         = omap44xx_dsp_slaves,
1182         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
1183         .masters        = omap44xx_dsp_masters,
1184         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
1185         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1186 };
1188 /*
1189  * 'dss' class
1190  * display sub-system
1191  */
1193 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1194         .rev_offs       = 0x0000,
1195         .syss_offs      = 0x0014,
1196         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1197 };
1199 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1200         .name   = "dss",
1201         .sysc   = &omap44xx_dss_sysc,
1202 };
1204 /* dss */
1205 /* dss master ports */
1206 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1207         &omap44xx_dss__l3_main_1,
1208 };
1210 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1211         {
1212                 .pa_start       = 0x58000000,
1213                 .pa_end         = 0x5800007f,
1214                 .flags          = ADDR_TYPE_RT
1215         },
1216         { }
1217 };
1219 /* l3_main_2 -> dss */
1220 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1221         .master         = &omap44xx_l3_main_2_hwmod,
1222         .slave          = &omap44xx_dss_hwmod,
1223         .clk            = "dss_fck",
1224         .addr           = omap44xx_dss_dma_addrs,
1225         .user           = OCP_USER_SDMA,
1226 };
1228 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1229         {
1230                 .pa_start       = 0x48040000,
1231                 .pa_end         = 0x4804007f,
1232                 .flags          = ADDR_TYPE_RT
1233         },
1234         { }
1235 };
1237 /* l4_per -> dss */
1238 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1239         .master         = &omap44xx_l4_per_hwmod,
1240         .slave          = &omap44xx_dss_hwmod,
1241         .clk            = "l4_div_ck",
1242         .addr           = omap44xx_dss_addrs,
1243         .user           = OCP_USER_MPU,
1244 };
1246 /* dss slave ports */
1247 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1248         &omap44xx_l3_main_2__dss,
1249         &omap44xx_l4_per__dss,
1250 };
1252 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1253         { .role = "sys_clk", .clk = "dss_sys_clk" },
1254         { .role = "tv_clk", .clk = "dss_tv_clk" },
1255         { .role = "dss_clk", .clk = "dss_dss_clk" },
1256         { .role = "video_clk", .clk = "dss_48mhz_clk" },
1257 };
1259 static struct omap_hwmod omap44xx_dss_hwmod = {
1260         .name           = "dss_core",
1261         .class          = &omap44xx_dss_hwmod_class,
1262         .clkdm_name     = "l3_dss_clkdm",
1263         .main_clk       = "dss_dss_clk",
1264         .prcm = {
1265                 .omap4 = {
1266                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1267                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1268                 },
1269         },
1270         .opt_clks       = dss_opt_clks,
1271         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
1272         .slaves         = omap44xx_dss_slaves,
1273         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
1274         .masters        = omap44xx_dss_masters,
1275         .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
1276         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1277 };
1279 /*
1280  * 'dispc' class
1281  * display controller
1282  */
1284 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1285         .rev_offs       = 0x0000,
1286         .sysc_offs      = 0x0010,
1287         .syss_offs      = 0x0014,
1288         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1289                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1290                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1291                            SYSS_HAS_RESET_STATUS),
1292         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1293                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1294         .sysc_fields    = &omap_hwmod_sysc_type1,
1295 };
1297 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1298         .name   = "dispc",
1299         .sysc   = &omap44xx_dispc_sysc,
1300 };
1302 /* dss_dispc */
1303 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1304 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1305         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1306         { .irq = -1 }
1307 };
1309 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1310         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1311         { .dma_req = -1 }
1312 };
1314 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1315         {
1316                 .pa_start       = 0x58001000,
1317                 .pa_end         = 0x58001fff,
1318                 .flags          = ADDR_TYPE_RT
1319         },
1320         { }
1321 };
1323 /* l3_main_2 -> dss_dispc */
1324 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1325         .master         = &omap44xx_l3_main_2_hwmod,
1326         .slave          = &omap44xx_dss_dispc_hwmod,
1327         .clk            = "dss_fck",
1328         .addr           = omap44xx_dss_dispc_dma_addrs,
1329         .user           = OCP_USER_SDMA,
1330 };
1332 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1333         {
1334                 .pa_start       = 0x48041000,
1335                 .pa_end         = 0x48041fff,
1336                 .flags          = ADDR_TYPE_RT
1337         },
1338         { }
1339 };
1341 /* l4_per -> dss_dispc */
1342 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1343         .master         = &omap44xx_l4_per_hwmod,
1344         .slave          = &omap44xx_dss_dispc_hwmod,
1345         .clk            = "l4_div_ck",
1346         .addr           = omap44xx_dss_dispc_addrs,
1347         .user           = OCP_USER_MPU,
1348 };
1350 /* dss_dispc slave ports */
1351 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1352         &omap44xx_l3_main_2__dss_dispc,
1353         &omap44xx_l4_per__dss_dispc,
1354 };
1356 static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
1357         { .role = "sys_clk", .clk = "dss_sys_clk" },
1358         { .role = "tv_clk", .clk = "dss_tv_clk" },
1359         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1360 };
1362 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1363         .name           = "dss_dispc",
1364         .class          = &omap44xx_dispc_hwmod_class,
1365         .clkdm_name     = "l3_dss_clkdm",
1366         .mpu_irqs       = omap44xx_dss_dispc_irqs,
1367         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
1368         .main_clk       = "dss_dss_clk",
1369         .prcm = {
1370                 .omap4 = {
1371                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1372                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1373                 },
1374         },
1375         .opt_clks       = dss_dispc_opt_clks,
1376         .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
1377         .slaves         = omap44xx_dss_dispc_slaves,
1378         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1379         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1380 };
1382 /*
1383  * 'dsi' class
1384  * display serial interface controller
1385  */
1387 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1388         .rev_offs       = 0x0000,
1389         .sysc_offs      = 0x0010,
1390         .syss_offs      = 0x0014,
1391         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1392                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1393                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1394         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1395         .sysc_fields    = &omap_hwmod_sysc_type1,
1396 };
1398 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1399         .name   = "dsi",
1400         .sysc   = &omap44xx_dsi_sysc,
1401 };
1403 /* dss_dsi1 */
1404 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1405 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1406         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1407         { .irq = -1 }
1408 };
1410 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1411         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1412         { .dma_req = -1 }
1413 };
1415 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1416         {
1417                 .pa_start       = 0x58004000,
1418                 .pa_end         = 0x580041ff,
1419                 .flags          = ADDR_TYPE_RT
1420         },
1421         { }
1422 };
1424 /* l3_main_2 -> dss_dsi1 */
1425 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1426         .master         = &omap44xx_l3_main_2_hwmod,
1427         .slave          = &omap44xx_dss_dsi1_hwmod,
1428         .clk            = "dss_fck",
1429         .addr           = omap44xx_dss_dsi1_dma_addrs,
1430         .user           = OCP_USER_SDMA,
1431 };
1433 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1434         {
1435                 .pa_start       = 0x48044000,
1436                 .pa_end         = 0x480441ff,
1437                 .flags          = ADDR_TYPE_RT
1438         },
1439         { }
1440 };
1442 /* l4_per -> dss_dsi1 */
1443 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1444         .master         = &omap44xx_l4_per_hwmod,
1445         .slave          = &omap44xx_dss_dsi1_hwmod,
1446         .clk            = "l4_div_ck",
1447         .addr           = omap44xx_dss_dsi1_addrs,
1448         .user           = OCP_USER_MPU,
1449 };
1451 /* dss_dsi1 slave ports */
1452 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1453         &omap44xx_l3_main_2__dss_dsi1,
1454         &omap44xx_l4_per__dss_dsi1,
1455 };
1457 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1458         { .role = "sys_clk", .clk = "dss_sys_clk" },
1459 };
1461 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1462         .name           = "dss_dsi1",
1463         .class          = &omap44xx_dsi_hwmod_class,
1464         .clkdm_name     = "l3_dss_clkdm",
1465         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
1466         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
1467         .main_clk       = "dss_dss_clk",
1468         .prcm = {
1469                 .omap4 = {
1470                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1471                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1472                 },
1473         },
1474         .opt_clks       = dss_dsi1_opt_clks,
1475         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
1476         .slaves         = omap44xx_dss_dsi1_slaves,
1477         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1478         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1479 };
1481 /* dss_dsi2 */
1482 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1483 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1484         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1485         { .irq = -1 }
1486 };
1488 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1489         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1490         { .dma_req = -1 }
1491 };
1493 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1494         {
1495                 .pa_start       = 0x58005000,
1496                 .pa_end         = 0x580051ff,
1497                 .flags          = ADDR_TYPE_RT
1498         },
1499         { }
1500 };
1502 /* l3_main_2 -> dss_dsi2 */
1503 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1504         .master         = &omap44xx_l3_main_2_hwmod,
1505         .slave          = &omap44xx_dss_dsi2_hwmod,
1506         .clk            = "dss_fck",
1507         .addr           = omap44xx_dss_dsi2_dma_addrs,
1508         .user           = OCP_USER_SDMA,
1509 };
1511 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1512         {
1513                 .pa_start       = 0x48045000,
1514                 .pa_end         = 0x480451ff,
1515                 .flags          = ADDR_TYPE_RT
1516         },
1517         { }
1518 };
1520 /* l4_per -> dss_dsi2 */
1521 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1522         .master         = &omap44xx_l4_per_hwmod,
1523         .slave          = &omap44xx_dss_dsi2_hwmod,
1524         .clk            = "l4_div_ck",
1525         .addr           = omap44xx_dss_dsi2_addrs,
1526         .user           = OCP_USER_MPU,
1527 };
1529 /* dss_dsi2 slave ports */
1530 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1531         &omap44xx_l3_main_2__dss_dsi2,
1532         &omap44xx_l4_per__dss_dsi2,
1533 };
1535 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1536         { .role = "sys_clk", .clk = "dss_sys_clk" },
1537 };
1539 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1540         .name           = "dss_dsi2",
1541         .class          = &omap44xx_dsi_hwmod_class,
1542         .clkdm_name     = "l3_dss_clkdm",
1543         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
1544         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
1545         .main_clk       = "dss_dss_clk",
1546         .prcm = {
1547                 .omap4 = {
1548                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1549                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1550                 },
1551         },
1552         .opt_clks       = dss_dsi2_opt_clks,
1553         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
1554         .slaves         = omap44xx_dss_dsi2_slaves,
1555         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1556         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1557 };
1559 /*
1560  * 'hdmi' class
1561  * hdmi controller
1562  */
1564 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1565         .rev_offs       = 0x0000,
1566         .sysc_offs      = 0x0010,
1567         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1568                            SYSC_HAS_SOFTRESET),
1569         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1570                            SIDLE_SMART_WKUP),
1571         .sysc_fields    = &omap_hwmod_sysc_type2,
1572 };
1574 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1575         .name   = "hdmi",
1576         .sysc   = &omap44xx_hdmi_sysc,
1577 };
1579 /* dss_hdmi */
1580 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1581 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1582         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1583         { .irq = -1 }
1584 };
1586 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1587         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1588         { .dma_req = -1 }
1589 };
1591 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1592         {
1593                 .pa_start       = 0x58006000,
1594                 .pa_end         = 0x58006fff,
1595                 .flags          = ADDR_TYPE_RT
1596         },
1597         { }
1598 };
1600 /* l3_main_2 -> dss_hdmi */
1601 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1602         .master         = &omap44xx_l3_main_2_hwmod,
1603         .slave          = &omap44xx_dss_hdmi_hwmod,
1604         .clk            = "dss_fck",
1605         .addr           = omap44xx_dss_hdmi_dma_addrs,
1606         .user           = OCP_USER_SDMA,
1607 };
1609 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1610         {
1611                 .pa_start       = 0x48046000,
1612                 .pa_end         = 0x48046fff,
1613                 .flags          = ADDR_TYPE_RT
1614         },
1615         { }
1616 };
1618 /* l4_per -> dss_hdmi */
1619 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1620         .master         = &omap44xx_l4_per_hwmod,
1621         .slave          = &omap44xx_dss_hdmi_hwmod,
1622         .clk            = "l4_div_ck",
1623         .addr           = omap44xx_dss_hdmi_addrs,
1624         .user           = OCP_USER_MPU,
1625 };
1627 /* dss_hdmi slave ports */
1628 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1629         &omap44xx_l3_main_2__dss_hdmi,
1630         &omap44xx_l4_per__dss_hdmi,
1631 };
1633 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1634         { .role = "sys_clk", .clk = "dss_sys_clk" },
1635 };
1637 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1638         .name           = "dss_hdmi",
1639         .class          = &omap44xx_hdmi_hwmod_class,
1640         .clkdm_name     = "l3_dss_clkdm",
1641         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
1642         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
1643         .main_clk       = "dss_dss_clk",
1644         .prcm = {
1645                 .omap4 = {
1646                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1647                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1648                 },
1649         },
1650         .opt_clks       = dss_hdmi_opt_clks,
1651         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
1652         .slaves         = omap44xx_dss_hdmi_slaves,
1653         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1654         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1655 };
1657 /*
1658  * 'rfbi' class
1659  * remote frame buffer interface
1660  */
1662 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1663         .rev_offs       = 0x0000,
1664         .sysc_offs      = 0x0010,
1665         .syss_offs      = 0x0014,
1666         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1667                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1668         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1669         .sysc_fields    = &omap_hwmod_sysc_type1,
1670 };
1672 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1673         .name   = "rfbi",
1674         .sysc   = &omap44xx_rfbi_sysc,
1675 };
1677 /* dss_rfbi */
1678 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1679 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1680         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1681         { .dma_req = -1 }
1682 };
1684 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1685         {
1686                 .pa_start       = 0x58002000,
1687                 .pa_end         = 0x580020ff,
1688                 .flags          = ADDR_TYPE_RT
1689         },
1690         { }
1691 };
1693 /* l3_main_2 -> dss_rfbi */
1694 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1695         .master         = &omap44xx_l3_main_2_hwmod,
1696         .slave          = &omap44xx_dss_rfbi_hwmod,
1697         .clk            = "dss_fck",
1698         .addr           = omap44xx_dss_rfbi_dma_addrs,
1699         .user           = OCP_USER_SDMA,
1700 };
1702 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1703         {
1704                 .pa_start       = 0x48042000,
1705                 .pa_end         = 0x480420ff,
1706                 .flags          = ADDR_TYPE_RT
1707         },
1708         { }
1709 };
1711 /* l4_per -> dss_rfbi */
1712 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1713         .master         = &omap44xx_l4_per_hwmod,
1714         .slave          = &omap44xx_dss_rfbi_hwmod,
1715         .clk            = "l4_div_ck",
1716         .addr           = omap44xx_dss_rfbi_addrs,
1717         .user           = OCP_USER_MPU,
1718 };
1720 /* dss_rfbi slave ports */
1721 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1722         &omap44xx_l3_main_2__dss_rfbi,
1723         &omap44xx_l4_per__dss_rfbi,
1724 };
1726 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1727         { .role = "ick", .clk = "dss_fck" },
1728 };
1730 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1731         .name           = "dss_rfbi",
1732         .class          = &omap44xx_rfbi_hwmod_class,
1733         .clkdm_name     = "l3_dss_clkdm",
1734         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
1735         .main_clk       = "dss_dss_clk",
1736         .prcm = {
1737                 .omap4 = {
1738                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1739                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1740                 },
1741         },
1742         .opt_clks       = dss_rfbi_opt_clks,
1743         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
1744         .slaves         = omap44xx_dss_rfbi_slaves,
1745         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1746         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1747 };
1749 /*
1750  * 'venc' class
1751  * video encoder
1752  */
1754 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1755         .name   = "venc",
1756 };
1758 /* dss_venc */
1759 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1760 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1761         {
1762                 .pa_start       = 0x58003000,
1763                 .pa_end         = 0x580030ff,
1764                 .flags          = ADDR_TYPE_RT
1765         },
1766         { }
1767 };
1769 /* l3_main_2 -> dss_venc */
1770 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1771         .master         = &omap44xx_l3_main_2_hwmod,
1772         .slave          = &omap44xx_dss_venc_hwmod,
1773         .clk            = "dss_fck",
1774         .addr           = omap44xx_dss_venc_dma_addrs,
1775         .user           = OCP_USER_SDMA,
1776 };
1778 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1779         {
1780                 .pa_start       = 0x48043000,
1781                 .pa_end         = 0x480430ff,
1782                 .flags          = ADDR_TYPE_RT
1783         },
1784         { }
1785 };
1787 /* l4_per -> dss_venc */
1788 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1789         .master         = &omap44xx_l4_per_hwmod,
1790         .slave          = &omap44xx_dss_venc_hwmod,
1791         .clk            = "l4_div_ck",
1792         .addr           = omap44xx_dss_venc_addrs,
1793         .user           = OCP_USER_MPU,
1794 };
1796 /* dss_venc slave ports */
1797 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1798         &omap44xx_l3_main_2__dss_venc,
1799         &omap44xx_l4_per__dss_venc,
1800 };
1802 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1803         .name           = "dss_venc",
1804         .class          = &omap44xx_venc_hwmod_class,
1805         .clkdm_name     = "l3_dss_clkdm",
1806         .main_clk       = "dss_dss_clk",
1807         .prcm = {
1808                 .omap4 = {
1809                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1810                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1811                 },
1812         },
1813         .slaves         = omap44xx_dss_venc_slaves,
1814         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1815         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1816 };
1818 /*
1819  * 'gpio' class
1820  * general purpose io module
1821  */
1823 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1824         .rev_offs       = 0x0000,
1825         .sysc_offs      = 0x0010,
1826         .syss_offs      = 0x0114,
1827         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1828                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1829                            SYSS_HAS_RESET_STATUS),
1830         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1831                            SIDLE_SMART_WKUP),
1832         .sysc_fields    = &omap_hwmod_sysc_type1,
1833 };
1835 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1836         .name   = "gpio",
1837         .sysc   = &omap44xx_gpio_sysc,
1838         .rev    = 2,
1839 };
1841 /* gpio dev_attr */
1842 static struct omap_gpio_dev_attr gpio_dev_attr = {
1843         .bank_width     = 32,
1844         .dbck_flag      = true,
1845 };
1847 /* gpio1 */
1848 static struct omap_hwmod omap44xx_gpio1_hwmod;
1849 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1850         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1851         { .irq = -1 }
1852 };
1854 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1855         {
1856                 .pa_start       = 0x4a310000,
1857                 .pa_end         = 0x4a3101ff,
1858                 .flags          = ADDR_TYPE_RT
1859         },
1860         { }
1861 };
1863 /* l4_wkup -> gpio1 */
1864 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1865         .master         = &omap44xx_l4_wkup_hwmod,
1866         .slave          = &omap44xx_gpio1_hwmod,
1867         .clk            = "l4_wkup_clk_mux_ck",
1868         .addr           = omap44xx_gpio1_addrs,
1869         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1870 };
1872 /* gpio1 slave ports */
1873 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1874         &omap44xx_l4_wkup__gpio1,
1875 };
1877 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1878         { .role = "dbclk", .clk = "gpio1_dbclk" },
1879 };
1881 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1882         .name           = "gpio1",
1883         .class          = &omap44xx_gpio_hwmod_class,
1884         .clkdm_name     = "l4_wkup_clkdm",
1885         .mpu_irqs       = omap44xx_gpio1_irqs,
1886         .main_clk       = "gpio1_ick",
1887         .prcm = {
1888                 .omap4 = {
1889                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1890                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1891                 },
1892         },
1893         .opt_clks       = gpio1_opt_clks,
1894         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1895         .dev_attr       = &gpio_dev_attr,
1896         .slaves         = omap44xx_gpio1_slaves,
1897         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1898         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1899 };
1901 /* gpio2 */
1902 static struct omap_hwmod omap44xx_gpio2_hwmod;
1903 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1904         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1905         { .irq = -1 }
1906 };
1908 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1909         {
1910                 .pa_start       = 0x48055000,
1911                 .pa_end         = 0x480551ff,
1912                 .flags          = ADDR_TYPE_RT
1913         },
1914         { }
1915 };
1917 /* l4_per -> gpio2 */
1918 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1919         .master         = &omap44xx_l4_per_hwmod,
1920         .slave          = &omap44xx_gpio2_hwmod,
1921         .clk            = "l4_div_ck",
1922         .addr           = omap44xx_gpio2_addrs,
1923         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1924 };
1926 /* gpio2 slave ports */
1927 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1928         &omap44xx_l4_per__gpio2,
1929 };
1931 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1932         { .role = "dbclk", .clk = "gpio2_dbclk" },
1933 };
1935 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1936         .name           = "gpio2",
1937         .class          = &omap44xx_gpio_hwmod_class,
1938         .clkdm_name     = "l4_per_clkdm",
1939         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1940         .mpu_irqs       = omap44xx_gpio2_irqs,
1941         .main_clk       = "gpio2_ick",
1942         .prcm = {
1943                 .omap4 = {
1944                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1945                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1946                 },
1947         },
1948         .opt_clks       = gpio2_opt_clks,
1949         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1950         .dev_attr       = &gpio_dev_attr,
1951         .slaves         = omap44xx_gpio2_slaves,
1952         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1953         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1954 };
1956 /* gpio3 */
1957 static struct omap_hwmod omap44xx_gpio3_hwmod;
1958 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1959         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1960         { .irq = -1 }
1961 };
1963 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1964         {
1965                 .pa_start       = 0x48057000,
1966                 .pa_end         = 0x480571ff,
1967                 .flags          = ADDR_TYPE_RT
1968         },
1969         { }
1970 };
1972 /* l4_per -> gpio3 */
1973 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1974         .master         = &omap44xx_l4_per_hwmod,
1975         .slave          = &omap44xx_gpio3_hwmod,
1976         .clk            = "l4_div_ck",
1977         .addr           = omap44xx_gpio3_addrs,
1978         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1979 };
1981 /* gpio3 slave ports */
1982 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1983         &omap44xx_l4_per__gpio3,
1984 };
1986 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1987         { .role = "dbclk", .clk = "gpio3_dbclk" },
1988 };
1990 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1991         .name           = "gpio3",
1992         .class          = &omap44xx_gpio_hwmod_class,
1993         .clkdm_name     = "l4_per_clkdm",
1994         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1995         .mpu_irqs       = omap44xx_gpio3_irqs,
1996         .main_clk       = "gpio3_ick",
1997         .prcm = {
1998                 .omap4 = {
1999                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
2000                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
2001                 },
2002         },
2003         .opt_clks       = gpio3_opt_clks,
2004         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
2005         .dev_attr       = &gpio_dev_attr,
2006         .slaves         = omap44xx_gpio3_slaves,
2007         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
2008         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2009 };
2011 /* gpio4 */
2012 static struct omap_hwmod omap44xx_gpio4_hwmod;
2013 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
2014         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
2015         { .irq = -1 }
2016 };
2018 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
2019         {
2020                 .pa_start       = 0x48059000,
2021                 .pa_end         = 0x480591ff,
2022                 .flags          = ADDR_TYPE_RT
2023         },
2024         { }
2025 };
2027 /* l4_per -> gpio4 */
2028 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
2029         .master         = &omap44xx_l4_per_hwmod,
2030         .slave          = &omap44xx_gpio4_hwmod,
2031         .clk            = "l4_div_ck",
2032         .addr           = omap44xx_gpio4_addrs,
2033         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2034 };
2036 /* gpio4 slave ports */
2037 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
2038         &omap44xx_l4_per__gpio4,
2039 };
2041 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2042         { .role = "dbclk", .clk = "gpio4_dbclk" },
2043 };
2045 static struct omap_hwmod omap44xx_gpio4_hwmod = {
2046         .name           = "gpio4",
2047         .class          = &omap44xx_gpio_hwmod_class,
2048         .clkdm_name     = "l4_per_clkdm",
2049         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2050         .mpu_irqs       = omap44xx_gpio4_irqs,
2051         .main_clk       = "gpio4_ick",
2052         .prcm = {
2053                 .omap4 = {
2054                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
2055                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
2056                 },
2057         },
2058         .opt_clks       = gpio4_opt_clks,
2059         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
2060         .dev_attr       = &gpio_dev_attr,
2061         .slaves         = omap44xx_gpio4_slaves,
2062         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
2063         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2064 };
2066 /* gpio5 */
2067 static struct omap_hwmod omap44xx_gpio5_hwmod;
2068 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
2069         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
2070         { .irq = -1 }
2071 };
2073 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
2074         {
2075                 .pa_start       = 0x4805b000,
2076                 .pa_end         = 0x4805b1ff,
2077                 .flags          = ADDR_TYPE_RT
2078         },
2079         { }
2080 };
2082 /* l4_per -> gpio5 */
2083 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
2084         .master         = &omap44xx_l4_per_hwmod,
2085         .slave          = &omap44xx_gpio5_hwmod,
2086         .clk            = "l4_div_ck",
2087         .addr           = omap44xx_gpio5_addrs,
2088         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2089 };
2091 /* gpio5 slave ports */
2092 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
2093         &omap44xx_l4_per__gpio5,
2094 };
2096 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2097         { .role = "dbclk", .clk = "gpio5_dbclk" },
2098 };
2100 static struct omap_hwmod omap44xx_gpio5_hwmod = {
2101         .name           = "gpio5",
2102         .class          = &omap44xx_gpio_hwmod_class,
2103         .clkdm_name     = "l4_per_clkdm",
2104         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2105         .mpu_irqs       = omap44xx_gpio5_irqs,
2106         .main_clk       = "gpio5_ick",
2107         .prcm = {
2108                 .omap4 = {
2109                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
2110                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
2111                 },
2112         },
2113         .opt_clks       = gpio5_opt_clks,
2114         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2115         .dev_attr       = &gpio_dev_attr,
2116         .slaves         = omap44xx_gpio5_slaves,
2117         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
2118         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2119 };
2121 /* gpio6 */
2122 static struct omap_hwmod omap44xx_gpio6_hwmod;
2123 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2124         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
2125         { .irq = -1 }
2126 };
2128 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
2129         {
2130                 .pa_start       = 0x4805d000,
2131                 .pa_end         = 0x4805d1ff,
2132                 .flags          = ADDR_TYPE_RT
2133         },
2134         { }
2135 };
2137 /* l4_per -> gpio6 */
2138 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2139         .master         = &omap44xx_l4_per_hwmod,
2140         .slave          = &omap44xx_gpio6_hwmod,
2141         .clk            = "l4_div_ck",
2142         .addr           = omap44xx_gpio6_addrs,
2143         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2144 };
2146 /* gpio6 slave ports */
2147 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2148         &omap44xx_l4_per__gpio6,
2149 };
2151 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2152         { .role = "dbclk", .clk = "gpio6_dbclk" },
2153 };
2155 static struct omap_hwmod omap44xx_gpio6_hwmod = {
2156         .name           = "gpio6",
2157         .class          = &omap44xx_gpio_hwmod_class,
2158         .clkdm_name     = "l4_per_clkdm",
2159         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2160         .mpu_irqs       = omap44xx_gpio6_irqs,
2161         .main_clk       = "gpio6_ick",
2162         .prcm = {
2163                 .omap4 = {
2164                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
2165                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
2166                 },
2167         },
2168         .opt_clks       = gpio6_opt_clks,
2169         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2170         .dev_attr       = &gpio_dev_attr,
2171         .slaves         = omap44xx_gpio6_slaves,
2172         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
2173         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2174 };
2176 /*
2177  * 'hsi' class
2178  * mipi high-speed synchronous serial interface (multichannel and full-duplex
2179  * serial if)
2180  */
2182 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2183         .rev_offs       = 0x0000,
2184         .sysc_offs      = 0x0010,
2185         .syss_offs      = 0x0014,
2186         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2187                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2188                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2189         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2190                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2191                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2192         .sysc_fields    = &omap_hwmod_sysc_type1,
2193 };
2195 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2196         .name   = "hsi",
2197         .sysc   = &omap44xx_hsi_sysc,
2198 };
2200 /* hsi */
2201 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2202         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2203         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2204         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2205         { .irq = -1 }
2206 };
2208 /* hsi master ports */
2209 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2210         &omap44xx_hsi__l3_main_2,
2211 };
2213 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2214         {
2215                 .pa_start       = 0x4a058000,
2216                 .pa_end         = 0x4a05bfff,
2217                 .flags          = ADDR_TYPE_RT
2218         },
2219         { }
2220 };
2222 /* l4_cfg -> hsi */
2223 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2224         .master         = &omap44xx_l4_cfg_hwmod,
2225         .slave          = &omap44xx_hsi_hwmod,
2226         .clk            = "l4_div_ck",
2227         .addr           = omap44xx_hsi_addrs,
2228         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2229 };
2231 /* hsi slave ports */
2232 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2233         &omap44xx_l4_cfg__hsi,
2234 };
2236 static struct omap_hwmod omap44xx_hsi_hwmod = {
2237         .name           = "hsi",
2238         .class          = &omap44xx_hsi_hwmod_class,
2239         .clkdm_name     = "l3_init_clkdm",
2240         .mpu_irqs       = omap44xx_hsi_irqs,
2241         .main_clk       = "hsi_fck",
2242         .prcm = {
2243                 .omap4 = {
2244                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
2245                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
2246                 },
2247         },
2248         .slaves         = omap44xx_hsi_slaves,
2249         .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
2250         .masters        = omap44xx_hsi_masters,
2251         .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
2252         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2253 };
2255 /*
2256  * 'i2c' class
2257  * multimaster high-speed i2c controller
2258  */
2260 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2261         .sysc_offs      = 0x0010,
2262         .syss_offs      = 0x0090,
2263         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2264                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2265                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2266         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2267                            SIDLE_SMART_WKUP),
2268         .sysc_fields    = &omap_hwmod_sysc_type1,
2269 };
2271 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2272         .name   = "i2c",
2273         .sysc   = &omap44xx_i2c_sysc,
2274         .rev    = OMAP_I2C_IP_VERSION_2,
2275         .reset  = &omap_i2c_reset,
2276 };
2278 static struct omap_i2c_dev_attr i2c_dev_attr = {
2279         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
2280 };
2282 /* i2c1 */
2283 static struct omap_hwmod omap44xx_i2c1_hwmod;
2284 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2285         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2286         { .irq = -1 }
2287 };
2289 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2290         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2291         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2292         { .dma_req = -1 }
2293 };
2295 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2296         {
2297                 .pa_start       = 0x48070000,
2298                 .pa_end         = 0x480700ff,
2299                 .flags          = ADDR_TYPE_RT
2300         },
2301         { }
2302 };
2304 /* l4_per -> i2c1 */
2305 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2306         .master         = &omap44xx_l4_per_hwmod,
2307         .slave          = &omap44xx_i2c1_hwmod,
2308         .clk            = "l4_div_ck",
2309         .addr           = omap44xx_i2c1_addrs,
2310         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2311 };
2313 /* i2c1 slave ports */
2314 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2315         &omap44xx_l4_per__i2c1,
2316 };
2318 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2319         .name           = "i2c1",
2320         .class          = &omap44xx_i2c_hwmod_class,
2321         .clkdm_name     = "l4_per_clkdm",
2322         .flags          = HWMOD_16BIT_REG,
2323         .mpu_irqs       = omap44xx_i2c1_irqs,
2324         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
2325         .main_clk       = "i2c1_fck",
2326         .prcm = {
2327                 .omap4 = {
2328                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
2329                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
2330                 },
2331         },
2332         .slaves         = omap44xx_i2c1_slaves,
2333         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
2334         .dev_attr       = &i2c_dev_attr,
2335         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2336 };
2338 /* i2c2 */
2339 static struct omap_hwmod omap44xx_i2c2_hwmod;
2340 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2341         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2342         { .irq = -1 }
2343 };
2345 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2346         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2347         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2348         { .dma_req = -1 }
2349 };
2351 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2352         {
2353                 .pa_start       = 0x48072000,
2354                 .pa_end         = 0x480720ff,
2355                 .flags          = ADDR_TYPE_RT
2356         },
2357         { }
2358 };
2360 /* l4_per -> i2c2 */
2361 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2362         .master         = &omap44xx_l4_per_hwmod,
2363         .slave          = &omap44xx_i2c2_hwmod,
2364         .clk            = "l4_div_ck",
2365         .addr           = omap44xx_i2c2_addrs,
2366         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2367 };
2369 /* i2c2 slave ports */
2370 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2371         &omap44xx_l4_per__i2c2,
2372 };
2374 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2375         .name           = "i2c2",
2376         .class          = &omap44xx_i2c_hwmod_class,
2377         .clkdm_name     = "l4_per_clkdm",
2378         .flags          = HWMOD_16BIT_REG,
2379         .mpu_irqs       = omap44xx_i2c2_irqs,
2380         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
2381         .main_clk       = "i2c2_fck",
2382         .prcm = {
2383                 .omap4 = {
2384                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
2385                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
2386                 },
2387         },
2388         .slaves         = omap44xx_i2c2_slaves,
2389         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
2390         .dev_attr       = &i2c_dev_attr,
2391         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2392 };
2394 /* i2c3 */
2395 static struct omap_hwmod omap44xx_i2c3_hwmod;
2396 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2397         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2398         { .irq = -1 }
2399 };
2401 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2402         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2403         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2404         { .dma_req = -1 }
2405 };
2407 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2408         {
2409                 .pa_start       = 0x48060000,
2410                 .pa_end         = 0x480600ff,
2411                 .flags          = ADDR_TYPE_RT
2412         },
2413         { }
2414 };
2416 /* l4_per -> i2c3 */
2417 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2418         .master         = &omap44xx_l4_per_hwmod,
2419         .slave          = &omap44xx_i2c3_hwmod,
2420         .clk            = "l4_div_ck",
2421         .addr           = omap44xx_i2c3_addrs,
2422         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2423 };
2425 /* i2c3 slave ports */
2426 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2427         &omap44xx_l4_per__i2c3,
2428 };
2430 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2431         .name           = "i2c3",
2432         .class          = &omap44xx_i2c_hwmod_class,
2433         .clkdm_name     = "l4_per_clkdm",
2434         .flags          = HWMOD_16BIT_REG,
2435         .mpu_irqs       = omap44xx_i2c3_irqs,
2436         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
2437         .main_clk       = "i2c3_fck",
2438         .prcm = {
2439                 .omap4 = {
2440                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
2441                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
2442                 },
2443         },
2444         .slaves         = omap44xx_i2c3_slaves,
2445         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
2446         .dev_attr       = &i2c_dev_attr,
2447         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2448 };
2450 /* i2c4 */
2451 static struct omap_hwmod omap44xx_i2c4_hwmod;
2452 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2453         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2454         { .irq = -1 }
2455 };
2457 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2458         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2459         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2460         { .dma_req = -1 }
2461 };
2463 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2464         {
2465                 .pa_start       = 0x48350000,
2466                 .pa_end         = 0x483500ff,
2467                 .flags          = ADDR_TYPE_RT
2468         },
2469         { }
2470 };
2472 /* l4_per -> i2c4 */
2473 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2474         .master         = &omap44xx_l4_per_hwmod,
2475         .slave          = &omap44xx_i2c4_hwmod,
2476         .clk            = "l4_div_ck",
2477         .addr           = omap44xx_i2c4_addrs,
2478         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2479 };
2481 /* i2c4 slave ports */
2482 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2483         &omap44xx_l4_per__i2c4,
2484 };
2486 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2487         .name           = "i2c4",
2488         .class          = &omap44xx_i2c_hwmod_class,
2489         .clkdm_name     = "l4_per_clkdm",
2490         .flags          = HWMOD_16BIT_REG,
2491         .mpu_irqs       = omap44xx_i2c4_irqs,
2492         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
2493         .main_clk       = "i2c4_fck",
2494         .prcm = {
2495                 .omap4 = {
2496                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
2497                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
2498                 },
2499         },
2500         .slaves         = omap44xx_i2c4_slaves,
2501         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
2502         .dev_attr       = &i2c_dev_attr,
2503         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2504 };
2506 /*
2507  * 'ipu' class
2508  * imaging processor unit
2509  */
2511 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2512         .name   = "ipu",
2513 };
2515 /* ipu */
2516 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2517         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2518         { .irq = -1 }
2519 };
2521 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2522         { .name = "cpu0", .rst_shift = 0 },
2523 };
2525 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2526         { .name = "cpu1", .rst_shift = 1 },
2527 };
2529 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2530         { .name = "mmu_cache", .rst_shift = 2 },
2531 };
2533 /* ipu master ports */
2534 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2535         &omap44xx_ipu__l3_main_2,
2536 };
2538 /* l3_main_2 -> ipu */
2539 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2540         .master         = &omap44xx_l3_main_2_hwmod,
2541         .slave          = &omap44xx_ipu_hwmod,
2542         .clk            = "l3_div_ck",
2543         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2544 };
2546 /* ipu slave ports */
2547 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2548         &omap44xx_l3_main_2__ipu,
2549 };
2551 /* Pseudo hwmod for reset control purpose only */
2552 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2553         .name           = "ipu_c0",
2554         .class          = &omap44xx_ipu_hwmod_class,
2555         .clkdm_name     = "ducati_clkdm",
2556         .flags          = HWMOD_INIT_NO_RESET,
2557         .rst_lines      = omap44xx_ipu_c0_resets,
2558         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2559         .prcm = {
2560                 .omap4 = {
2561                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2562                 },
2563         },
2564         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2565 };
2567 /* Pseudo hwmod for reset control purpose only */
2568 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2569         .name           = "ipu_c1",
2570         .class          = &omap44xx_ipu_hwmod_class,
2571         .clkdm_name     = "ducati_clkdm",
2572         .flags          = HWMOD_INIT_NO_RESET,
2573         .rst_lines      = omap44xx_ipu_c1_resets,
2574         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2575         .prcm = {
2576                 .omap4 = {
2577                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2578                 },
2579         },
2580         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2581 };
2583 static struct omap_hwmod omap44xx_ipu_hwmod = {
2584         .name           = "ipu",
2585         .class          = &omap44xx_ipu_hwmod_class,
2586         .clkdm_name     = "ducati_clkdm",
2587         .mpu_irqs       = omap44xx_ipu_irqs,
2588         .rst_lines      = omap44xx_ipu_resets,
2589         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
2590         .main_clk       = "ipu_fck",
2591         .prcm = {
2592                 .omap4 = {
2593                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2594                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2595                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2596                 },
2597         },
2598         .slaves         = omap44xx_ipu_slaves,
2599         .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
2600         .masters        = omap44xx_ipu_masters,
2601         .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
2602         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2603 };
2605 /*
2606  * 'iss' class
2607  * external images sensor pixel data processor
2608  */
2610 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2611         .rev_offs       = 0x0000,
2612         .sysc_offs      = 0x0010,
2613         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2614                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2615         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2616                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2617                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2618         .sysc_fields    = &omap_hwmod_sysc_type2,
2619 };
2621 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2622         .name   = "iss",
2623         .sysc   = &omap44xx_iss_sysc,
2624 };
2626 /* iss */
2627 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2628         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2629         { .irq = -1 }
2630 };
2632 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2633         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2634         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2635         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2636         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2637         { .dma_req = -1 }
2638 };
2640 /* iss master ports */
2641 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2642         &omap44xx_iss__l3_main_2,
2643 };
2645 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2646         {
2647                 .pa_start       = 0x52000000,
2648                 .pa_end         = 0x520000ff,
2649                 .flags          = ADDR_TYPE_RT
2650         },
2651         { }
2652 };
2654 /* l3_main_2 -> iss */
2655 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2656         .master         = &omap44xx_l3_main_2_hwmod,
2657         .slave          = &omap44xx_iss_hwmod,
2658         .clk            = "l3_div_ck",
2659         .addr           = omap44xx_iss_addrs,
2660         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2661 };
2663 /* iss slave ports */
2664 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2665         &omap44xx_l3_main_2__iss,
2666 };
2668 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2669         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2670 };
2672 static struct omap_hwmod omap44xx_iss_hwmod = {
2673         .name           = "iss",
2674         .class          = &omap44xx_iss_hwmod_class,
2675         .clkdm_name     = "iss_clkdm",
2676         .mpu_irqs       = omap44xx_iss_irqs,
2677         .sdma_reqs      = omap44xx_iss_sdma_reqs,
2678         .main_clk       = "iss_fck",
2679         .prcm = {
2680                 .omap4 = {
2681                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
2682                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
2683                 },
2684         },
2685         .opt_clks       = iss_opt_clks,
2686         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
2687         .slaves         = omap44xx_iss_slaves,
2688         .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
2689         .masters        = omap44xx_iss_masters,
2690         .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
2691         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2692 };
2694 /*
2695  * 'iva' class
2696  * multi-standard video encoder/decoder hardware accelerator
2697  */
2699 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2700         .name   = "iva",
2701 };
2703 /* iva */
2704 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2705         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2706         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2707         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2708         { .irq = -1 }
2709 };
2711 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2712         { .name = "logic", .rst_shift = 2 },
2713 };
2715 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2716         { .name = "seq0", .rst_shift = 0 },
2717 };
2719 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2720         { .name = "seq1", .rst_shift = 1 },
2721 };
2723 /* iva master ports */
2724 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2725         &omap44xx_iva__l3_main_2,
2726         &omap44xx_iva__l3_instr,
2727 };
2729 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2730         {
2731                 .pa_start       = 0x5a000000,
2732                 .pa_end         = 0x5a07ffff,
2733                 .flags          = ADDR_TYPE_RT
2734         },
2735         { }
2736 };
2738 /* l3_main_2 -> iva */
2739 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2740         .master         = &omap44xx_l3_main_2_hwmod,
2741         .slave          = &omap44xx_iva_hwmod,
2742         .clk            = "l3_div_ck",
2743         .addr           = omap44xx_iva_addrs,
2744         .user           = OCP_USER_MPU,
2745 };
2747 /* iva slave ports */
2748 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2749         &omap44xx_dsp__iva,
2750         &omap44xx_l3_main_2__iva,
2751 };
2753 /* Pseudo hwmod for reset control purpose only */
2754 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2755         .name           = "iva_seq0",
2756         .class          = &omap44xx_iva_hwmod_class,
2757         .clkdm_name     = "ivahd_clkdm",
2758         .flags          = HWMOD_INIT_NO_RESET,
2759         .rst_lines      = omap44xx_iva_seq0_resets,
2760         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2761         .prcm = {
2762                 .omap4 = {
2763                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2764                 },
2765         },
2766         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2767 };
2769 /* Pseudo hwmod for reset control purpose only */
2770 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2771         .name           = "iva_seq1",
2772         .class          = &omap44xx_iva_hwmod_class,
2773         .clkdm_name     = "ivahd_clkdm",
2774         .flags          = HWMOD_INIT_NO_RESET,
2775         .rst_lines      = omap44xx_iva_seq1_resets,
2776         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2777         .prcm = {
2778                 .omap4 = {
2779                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2780                 },
2781         },
2782         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2783 };
2785 static struct omap_hwmod omap44xx_iva_hwmod = {
2786         .name           = "iva",
2787         .class          = &omap44xx_iva_hwmod_class,
2788         .clkdm_name     = "ivahd_clkdm",
2789         .mpu_irqs       = omap44xx_iva_irqs,
2790         .rst_lines      = omap44xx_iva_resets,
2791         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
2792         .main_clk       = "iva_fck",
2793         .prcm = {
2794                 .omap4 = {
2795                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
2796                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2797                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
2798                 },
2799         },
2800         .slaves         = omap44xx_iva_slaves,
2801         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
2802         .masters        = omap44xx_iva_masters,
2803         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
2804         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2805 };
2807 /*
2808  * 'kbd' class
2809  * keyboard controller
2810  */
2812 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2813         .rev_offs       = 0x0000,
2814         .sysc_offs      = 0x0010,
2815         .syss_offs      = 0x0014,
2816         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2817                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2818                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2819                            SYSS_HAS_RESET_STATUS),
2820         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2821         .sysc_fields    = &omap_hwmod_sysc_type1,
2822 };
2824 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2825         .name   = "kbd",
2826         .sysc   = &omap44xx_kbd_sysc,
2827 };
2829 /* kbd */
2830 static struct omap_hwmod omap44xx_kbd_hwmod;
2831 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2832         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2833         { .irq = -1 }
2834 };
2836 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2837         {
2838                 .pa_start       = 0x4a31c000,
2839                 .pa_end         = 0x4a31c07f,
2840                 .flags          = ADDR_TYPE_RT
2841         },
2842         { }
2843 };
2845 /* l4_wkup -> kbd */
2846 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2847         .master         = &omap44xx_l4_wkup_hwmod,
2848         .slave          = &omap44xx_kbd_hwmod,
2849         .clk            = "l4_wkup_clk_mux_ck",
2850         .addr           = omap44xx_kbd_addrs,
2851         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2852 };
2854 /* kbd slave ports */
2855 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2856         &omap44xx_l4_wkup__kbd,
2857 };
2859 static struct omap_hwmod omap44xx_kbd_hwmod = {
2860         .name           = "kbd",
2861         .class          = &omap44xx_kbd_hwmod_class,
2862         .clkdm_name     = "l4_wkup_clkdm",
2863         .mpu_irqs       = omap44xx_kbd_irqs,
2864         .main_clk       = "kbd_fck",
2865         .prcm = {
2866                 .omap4 = {
2867                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
2868                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
2869                 },
2870         },
2871         .slaves         = omap44xx_kbd_slaves,
2872         .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
2873         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2874 };
2876 /*
2877  * 'mailbox' class
2878  * mailbox module allowing communication between the on-chip processors using a
2879  * queued mailbox-interrupt mechanism.
2880  */
2882 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2883         .rev_offs       = 0x0000,
2884         .sysc_offs      = 0x0010,
2885         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2886                            SYSC_HAS_SOFTRESET),
2887         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2888         .sysc_fields    = &omap_hwmod_sysc_type2,
2889 };
2891 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2892         .name   = "mailbox",
2893         .sysc   = &omap44xx_mailbox_sysc,
2894 };
2896 /* mailbox */
2897 static struct omap_hwmod omap44xx_mailbox_hwmod;
2898 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2899         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2900         { .irq = -1 }
2901 };
2903 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2904         {
2905                 .pa_start       = 0x4a0f4000,
2906                 .pa_end         = 0x4a0f41ff,
2907                 .flags          = ADDR_TYPE_RT
2908         },
2909         { }
2910 };
2912 /* l4_cfg -> mailbox */
2913 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2914         .master         = &omap44xx_l4_cfg_hwmod,
2915         .slave          = &omap44xx_mailbox_hwmod,
2916         .clk            = "l4_div_ck",
2917         .addr           = omap44xx_mailbox_addrs,
2918         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2919 };
2921 /* mailbox slave ports */
2922 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2923         &omap44xx_l4_cfg__mailbox,
2924 };
2926 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2927         .name           = "mailbox",
2928         .class          = &omap44xx_mailbox_hwmod_class,
2929         .clkdm_name     = "l4_cfg_clkdm",
2930         .mpu_irqs       = omap44xx_mailbox_irqs,
2931         .prcm = {
2932                 .omap4 = {
2933                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
2934                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
2935                 },
2936         },
2937         .slaves         = omap44xx_mailbox_slaves,
2938         .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
2939         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2940 };
2942 /*
2943  * 'mcbsp' class
2944  * multi channel buffered serial port controller
2945  */
2947 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2948         .sysc_offs      = 0x008c,
2949         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2950                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2951         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2952         .sysc_fields    = &omap_hwmod_sysc_type1,
2953 };
2955 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2956         .name   = "mcbsp",
2957         .sysc   = &omap44xx_mcbsp_sysc,
2958         .rev    = MCBSP_CONFIG_TYPE4,
2959 };
2961 /* mcbsp1 */
2962 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2963 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2964         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2965         { .irq = -1 }
2966 };
2968 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2969         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2970         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2971         { .dma_req = -1 }
2972 };
2974 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2975         {
2976                 .name           = "mpu",
2977                 .pa_start       = 0x40122000,
2978                 .pa_end         = 0x401220ff,
2979                 .flags          = ADDR_TYPE_RT
2980         },
2981         { }
2982 };
2984 /* l4_abe -> mcbsp1 */
2985 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2986         .master         = &omap44xx_l4_abe_hwmod,
2987         .slave          = &omap44xx_mcbsp1_hwmod,
2988         .clk            = "ocp_abe_iclk",
2989         .addr           = omap44xx_mcbsp1_addrs,
2990         .user           = OCP_USER_MPU,
2991 };
2993 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2994         {
2995                 .name           = "dma",
2996                 .pa_start       = 0x49022000,
2997                 .pa_end         = 0x490220ff,
2998                 .flags          = ADDR_TYPE_RT
2999         },
3000         { }
3001 };
3003 /* l4_abe -> mcbsp1 (dma) */
3004 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
3005         .master         = &omap44xx_l4_abe_hwmod,
3006         .slave          = &omap44xx_mcbsp1_hwmod,
3007         .clk            = "ocp_abe_iclk",
3008         .addr           = omap44xx_mcbsp1_dma_addrs,
3009         .user           = OCP_USER_SDMA,
3010 };
3012 /* mcbsp1 slave ports */
3013 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
3014         &omap44xx_l4_abe__mcbsp1,
3015         &omap44xx_l4_abe__mcbsp1_dma,
3016 };
3018 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
3019         .name           = "mcbsp1",
3020         .class          = &omap44xx_mcbsp_hwmod_class,
3021         .clkdm_name     = "abe_clkdm",
3022         .mpu_irqs       = omap44xx_mcbsp1_irqs,
3023         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
3024         .main_clk       = "mcbsp1_fck",
3025         .prcm = {
3026                 .omap4 = {
3027                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
3028                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
3029                 },
3030         },
3031         .slaves         = omap44xx_mcbsp1_slaves,
3032         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
3033         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3034 };
3036 /* mcbsp2 */
3037 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
3038 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
3039         { .irq = 22 + OMAP44XX_IRQ_GIC_START },
3040         { .irq = -1 }
3041 };
3043 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
3044         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
3045         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
3046         { .dma_req = -1 }
3047 };
3049 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
3050         {
3051                 .name           = "mpu",
3052                 .pa_start       = 0x40124000,
3053                 .pa_end         = 0x401240ff,
3054                 .flags          = ADDR_TYPE_RT
3055         },
3056         { }
3057 };
3059 /* l4_abe -> mcbsp2 */
3060 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
3061         .master         = &omap44xx_l4_abe_hwmod,
3062         .slave          = &omap44xx_mcbsp2_hwmod,
3063         .clk            = "ocp_abe_iclk",
3064         .addr           = omap44xx_mcbsp2_addrs,
3065         .user           = OCP_USER_MPU,
3066 };
3068 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
3069         {
3070                 .name           = "dma",
3071                 .pa_start       = 0x49024000,
3072                 .pa_end         = 0x490240ff,
3073                 .flags          = ADDR_TYPE_RT
3074         },
3075         { }
3076 };
3078 /* l4_abe -> mcbsp2 (dma) */
3079 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
3080         .master         = &omap44xx_l4_abe_hwmod,
3081         .slave          = &omap44xx_mcbsp2_hwmod,
3082         .clk            = "ocp_abe_iclk",
3083         .addr           = omap44xx_mcbsp2_dma_addrs,
3084         .user           = OCP_USER_SDMA,
3085 };
3087 /* mcbsp2 slave ports */
3088 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
3089         &omap44xx_l4_abe__mcbsp2,
3090         &omap44xx_l4_abe__mcbsp2_dma,
3091 };
3093 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
3094         .name           = "mcbsp2",
3095         .class          = &omap44xx_mcbsp_hwmod_class,
3096         .clkdm_name     = "abe_clkdm",
3097         .mpu_irqs       = omap44xx_mcbsp2_irqs,
3098         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
3099         .main_clk       = "mcbsp2_fck",
3100         .prcm = {
3101                 .omap4 = {
3102                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
3103                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
3104                 },
3105         },
3106         .slaves         = omap44xx_mcbsp2_slaves,
3107         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
3108         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3109 };
3111 /* mcbsp3 */
3112 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
3113 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
3114         { .irq = 23 + OMAP44XX_IRQ_GIC_START },
3115         { .irq = -1 }
3116 };
3118 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
3119         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
3120         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
3121         { .dma_req = -1 }
3122 };
3124 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
3125         {
3126                 .name           = "mpu",
3127                 .pa_start       = 0x40126000,
3128                 .pa_end         = 0x401260ff,
3129                 .flags          = ADDR_TYPE_RT
3130         },
3131         { }
3132 };
3134 /* l4_abe -> mcbsp3 */
3135 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3136         .master         = &omap44xx_l4_abe_hwmod,
3137         .slave          = &omap44xx_mcbsp3_hwmod,
3138         .clk            = "ocp_abe_iclk",
3139         .addr           = omap44xx_mcbsp3_addrs,
3140         .user           = OCP_USER_MPU,
3141 };
3143 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
3144         {
3145                 .name           = "dma",
3146                 .pa_start       = 0x49026000,
3147                 .pa_end         = 0x490260ff,
3148                 .flags          = ADDR_TYPE_RT
3149         },
3150         { }
3151 };
3153 /* l4_abe -> mcbsp3 (dma) */
3154 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
3155         .master         = &omap44xx_l4_abe_hwmod,
3156         .slave          = &omap44xx_mcbsp3_hwmod,
3157         .clk            = "ocp_abe_iclk",
3158         .addr           = omap44xx_mcbsp3_dma_addrs,
3159         .user           = OCP_USER_SDMA,
3160 };
3162 /* mcbsp3 slave ports */
3163 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
3164         &omap44xx_l4_abe__mcbsp3,
3165         &omap44xx_l4_abe__mcbsp3_dma,
3166 };
3168 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3169         .name           = "mcbsp3",
3170         .class          = &omap44xx_mcbsp_hwmod_class,
3171         .clkdm_name     = "abe_clkdm",
3172         .mpu_irqs       = omap44xx_mcbsp3_irqs,
3173         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
3174         .main_clk       = "mcbsp3_fck",
3175         .prcm = {
3176                 .omap4 = {
3177                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
3178                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
3179                 },
3180         },
3181         .slaves         = omap44xx_mcbsp3_slaves,
3182         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3183         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3184 };
3186 /* mcbsp4 */
3187 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3188 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3189         { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3190         { .irq = -1 }
3191 };
3193 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3194         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3195         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3196         { .dma_req = -1 }
3197 };
3199 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3200         {
3201                 .pa_start       = 0x48096000,
3202                 .pa_end         = 0x480960ff,
3203                 .flags          = ADDR_TYPE_RT
3204         },
3205         { }
3206 };
3208 /* l4_per -> mcbsp4 */
3209 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3210         .master         = &omap44xx_l4_per_hwmod,
3211         .slave          = &omap44xx_mcbsp4_hwmod,
3212         .clk            = "l4_div_ck",
3213         .addr           = omap44xx_mcbsp4_addrs,
3214         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3215 };
3217 /* mcbsp4 slave ports */
3218 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3219         &omap44xx_l4_per__mcbsp4,
3220 };
3222 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3223         .name           = "mcbsp4",
3224         .class          = &omap44xx_mcbsp_hwmod_class,
3225         .clkdm_name     = "l4_per_clkdm",
3226         .mpu_irqs       = omap44xx_mcbsp4_irqs,
3227         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
3228         .main_clk       = "mcbsp4_fck",
3229         .prcm = {
3230                 .omap4 = {
3231                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
3232                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
3233                 },
3234         },
3235         .slaves         = omap44xx_mcbsp4_slaves,
3236         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3237         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3238 };
3240 /*
3241  * 'mcpdm' class
3242  * multi channel pdm controller (proprietary interface with phoenix power
3243  * ic)
3244  */
3246 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3247         .rev_offs       = 0x0000,
3248         .sysc_offs      = 0x0010,
3249         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3250                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3251         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3252                            SIDLE_SMART_WKUP),
3253         .sysc_fields    = &omap_hwmod_sysc_type2,
3254 };
3256 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3257         .name   = "mcpdm",
3258         .sysc   = &omap44xx_mcpdm_sysc,
3259 };
3261 /* mcpdm */
3262 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3263 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3264         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3265         { .irq = -1 }
3266 };
3268 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3269         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3270         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3271         { .dma_req = -1 }
3272 };
3274 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3275         {
3276                 .pa_start       = 0x40132000,
3277                 .pa_end         = 0x4013207f,
3278                 .flags          = ADDR_TYPE_RT
3279         },
3280         { }
3281 };
3283 /* l4_abe -> mcpdm */
3284 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3285         .master         = &omap44xx_l4_abe_hwmod,
3286         .slave          = &omap44xx_mcpdm_hwmod,
3287         .clk            = "ocp_abe_iclk",
3288         .addr           = omap44xx_mcpdm_addrs,
3289         .user           = OCP_USER_MPU,
3290 };
3292 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3293         {
3294                 .pa_start       = 0x49032000,
3295                 .pa_end         = 0x4903207f,
3296                 .flags          = ADDR_TYPE_RT
3297         },
3298         { }
3299 };
3301 /* l4_abe -> mcpdm (dma) */
3302 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3303         .master         = &omap44xx_l4_abe_hwmod,
3304         .slave          = &omap44xx_mcpdm_hwmod,
3305         .clk            = "ocp_abe_iclk",
3306         .addr           = omap44xx_mcpdm_dma_addrs,
3307         .user           = OCP_USER_SDMA,
3308 };
3310 /* mcpdm slave ports */
3311 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3312         &omap44xx_l4_abe__mcpdm,
3313         &omap44xx_l4_abe__mcpdm_dma,
3314 };
3316 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3317         .name           = "mcpdm",
3318         .class          = &omap44xx_mcpdm_hwmod_class,
3319         .clkdm_name     = "abe_clkdm",
3320         .mpu_irqs       = omap44xx_mcpdm_irqs,
3321         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
3322         .main_clk       = "mcpdm_fck",
3323         .prcm = {
3324                 .omap4 = {
3325                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
3326                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
3327                 },
3328         },
3329         .slaves         = omap44xx_mcpdm_slaves,
3330         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3331         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3332 };
3334 /*
3335  * 'mcspi' class
3336  * multichannel serial port interface (mcspi) / master/slave synchronous serial
3337  * bus
3338  */
3340 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3341         .rev_offs       = 0x0000,
3342         .sysc_offs      = 0x0010,
3343         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3344                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3345         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3346                            SIDLE_SMART_WKUP),
3347         .sysc_fields    = &omap_hwmod_sysc_type2,
3348 };
3350 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3351         .name   = "mcspi",
3352         .sysc   = &omap44xx_mcspi_sysc,
3353         .rev    = OMAP4_MCSPI_REV,
3354 };
3356 /* mcspi1 */
3357 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3358 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3359         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3360         { .irq = -1 }
3361 };
3363 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3364         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3365         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3366         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3367         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3368         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3369         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3370         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3371         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3372         { .dma_req = -1 }
3373 };
3375 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3376         {
3377                 .pa_start       = 0x48098000,
3378                 .pa_end         = 0x480981ff,
3379                 .flags          = ADDR_TYPE_RT
3380         },
3381         { }
3382 };
3384 /* l4_per -> mcspi1 */
3385 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3386         .master         = &omap44xx_l4_per_hwmod,
3387         .slave          = &omap44xx_mcspi1_hwmod,
3388         .clk            = "l4_div_ck",
3389         .addr           = omap44xx_mcspi1_addrs,
3390         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3391 };
3393 /* mcspi1 slave ports */
3394 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3395         &omap44xx_l4_per__mcspi1,
3396 };
3398 /* mcspi1 dev_attr */
3399 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3400         .num_chipselect = 4,
3401 };
3403 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3404         .name           = "mcspi1",
3405         .class          = &omap44xx_mcspi_hwmod_class,
3406         .clkdm_name     = "l4_per_clkdm",
3407         .mpu_irqs       = omap44xx_mcspi1_irqs,
3408         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
3409         .main_clk       = "mcspi1_fck",
3410         .prcm = {
3411                 .omap4 = {
3412                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
3413                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
3414                 },
3415         },
3416         .dev_attr       = &mcspi1_dev_attr,
3417         .slaves         = omap44xx_mcspi1_slaves,
3418         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3419         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3420 };
3422 /* mcspi2 */
3423 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3424 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3425         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3426         { .irq = -1 }
3427 };
3429 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3430         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3431         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3432         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3433         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3434         { .dma_req = -1 }
3435 };
3437 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3438         {
3439                 .pa_start       = 0x4809a000,
3440                 .pa_end         = 0x4809a1ff,
3441                 .flags          = ADDR_TYPE_RT
3442         },
3443         { }
3444 };
3446 /* l4_per -> mcspi2 */
3447 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3448         .master         = &omap44xx_l4_per_hwmod,
3449         .slave          = &omap44xx_mcspi2_hwmod,
3450         .clk            = "l4_div_ck",
3451         .addr           = omap44xx_mcspi2_addrs,
3452         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3453 };
3455 /* mcspi2 slave ports */
3456 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3457         &omap44xx_l4_per__mcspi2,
3458 };
3460 /* mcspi2 dev_attr */
3461 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3462         .num_chipselect = 2,
3463 };
3465 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3466         .name           = "mcspi2",
3467         .class          = &omap44xx_mcspi_hwmod_class,
3468         .clkdm_name     = "l4_per_clkdm",
3469         .mpu_irqs       = omap44xx_mcspi2_irqs,
3470         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
3471         .main_clk       = "mcspi2_fck",
3472         .prcm = {
3473                 .omap4 = {
3474                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
3475                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
3476                 },
3477         },
3478         .dev_attr       = &mcspi2_dev_attr,
3479         .slaves         = omap44xx_mcspi2_slaves,
3480         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3481         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3482 };
3484 /* mcspi3 */
3485 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3486 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3487         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3488      &