arch/arm/mach-omap2/omap_twl.c

   1 /**
   2  * OMAP and TWL PMIC specific intializations.
   3  *
   4  * Copyright (C) 2010 Texas Instruments Incorporated.
   5  * Thara Gopinath
   6  * Copyright (C) 2009 Texas Instruments Incorporated.
   7  * Nishanth Menon
   8  * Copyright (C) 2009 Nokia Corporation
   9  * Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/kernel.h>
  19 #include <linux/i2c/twl.h>
  20
  21 #include "voltage.h"
  22
  23 #include "pm.h"
  24
  25 #define OMAP3_SRI2C_SLAVE_ADDR          0x12
  26 #define OMAP3_VDD_MPU_SR_CONTROL_REG    0x00
  27 #define OMAP3_VDD_CORE_SR_CONTROL_REG   0x01
  28 #define OMAP3_VP_CONFIG_ERROROFFSET     0x00
  29 #define OMAP3_VP_VSTEPMIN_VSTEPMIN      0x1
  30 #define OMAP3_VP_VSTEPMAX_VSTEPMAX      0x04
  31 #define OMAP3_VP_VLIMITTO_TIMEOUT_US    200
  32
  33 #define OMAP3430_VP1_VLIMITTO_VDDMIN    0x14
  34 #define OMAP3430_VP1_VLIMITTO_VDDMAX    0x42
  35 #define OMAP3430_VP2_VLIMITTO_VDDMIN    0x18
  36 #define OMAP3430_VP2_VLIMITTO_VDDMAX    0x2c
  37
  38 #define OMAP3630_VP1_VLIMITTO_VDDMIN    0x18
  39 #define OMAP3630_VP1_VLIMITTO_VDDMAX    0x3c
  40 #define OMAP3630_VP2_VLIMITTO_VDDMIN    0x18
  41 #define OMAP3630_VP2_VLIMITTO_VDDMAX    0x30
  42
  43 #define OMAP4_SRI2C_SLAVE_ADDR          0x12
  44 #define OMAP4_VDD_MPU_SR_VOLT_REG       0x55
  45 #define OMAP4_VDD_MPU_SR_CMD_REG        0x56
  46 #define OMAP4_VDD_IVA_SR_VOLT_REG       0x5B
  47 #define OMAP4_VDD_IVA_SR_CMD_REG        0x5C
  48 #define OMAP4_VDD_CORE_SR_VOLT_REG      0x61
  49 #define OMAP4_VDD_CORE_SR_CMD_REG       0x62
  50
  51 #define OMAP4_VP_CONFIG_ERROROFFSET     0x00
  52 #define OMAP4_VP_VSTEPMIN_VSTEPMIN      0x01
  53 #define OMAP4_VP_VSTEPMAX_VSTEPMAX      0x04
  54 #define OMAP4_VP_VLIMITTO_TIMEOUT_US    200
  55
  56 #define OMAP4_VP_MPU_VLIMITTO_VDDMIN    0xA
  57 #define OMAP4_VP_MPU_VLIMITTO_VDDMAX    0x39
  58 #define OMAP4_VP_IVA_VLIMITTO_VDDMIN    0xA
  59 #define OMAP4_VP_IVA_VLIMITTO_VDDMAX    0x2D
  60 #define OMAP4_VP_CORE_VLIMITTO_VDDMIN   0xA
  61 #define OMAP4_VP_CORE_VLIMITTO_VDDMAX   0x28
  62
  63 static bool is_offset_valid;
  64 static u8 smps_offset;
  65 /*
  66  * Flag to ensure Smartreflex bit in TWL
  67  * being cleared in board file is not overwritten.
  68  */
  69 static bool __initdata twl_sr_enable_autoinit;
  70
  71 #define TWL4030_DCDC_GLOBAL_CFG        0x06
  72 #define REG_SMPS_OFFSET         0xE0
  73 #define SMARTREFLEX_ENABLE     BIT(3)
  74
  75 static unsigned long twl4030_vsel_to_uv(const u8 vsel)
  76 {
  77         return (((vsel * 125) + 6000)) * 100;
  78 }
  79
  80 static u8 twl4030_uv_to_vsel(unsigned long uv)
  81 {
  82         return DIV_ROUND_UP(uv - 600000, 12500);
  83 }
  84
  85 static unsigned long twl6030_vsel_to_uv(const u8 vsel)
  86 {
  87         /*
  88          * In TWL6030 depending on the value of SMPS_OFFSET
  89          * efuse register the voltage range supported in
  90          * standard mode can be either between 0.6V - 1.3V or
  91          * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
  92          * is programmed to all 0's where as starting from
  93          * TWL6030 ES1.1 the efuse is programmed to 1
  94          */
  95         if (!is_offset_valid) {
  96                 twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
  97                                 REG_SMPS_OFFSET);
  98                 is_offset_valid = true;
  99         }
 100
 101         if (!vsel)
 102                 return 0;
 103         /*
 104          * There is no specific formula for voltage to vsel
 105          * conversion above 1.3V. There are special hardcoded
 106          * values for voltages above 1.3V. Currently we are
 107          * hardcoding only for 1.35 V which is used for 1GH OPP for
 108          * OMAP4430.
 109          */
 110         if (vsel == 0x3A)
 111                 return 1350000;
 112
 113         if (smps_offset & 0x8)
 114                 return ((((vsel - 1) * 1266) + 70900)) * 10;
 115         else
 116                 return ((((vsel - 1) * 1266) + 60770)) * 10;
 117 }
 118
 119 static u8 twl6030_uv_to_vsel(unsigned long uv)
 120 {
 121         /*
 122          * In TWL6030 depending on the value of SMPS_OFFSET
 123          * efuse register the voltage range supported in
 124          * standard mode can be either between 0.6V - 1.3V or
 125          * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
 126          * is programmed to all 0's where as starting from
 127          * TWL6030 ES1.1 the efuse is programmed to 1
 128          */
 129         if (!is_offset_valid) {
 130                 twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
 131                                 REG_SMPS_OFFSET);
 132                 is_offset_valid = true;
 133         }
 134
 135         if (!uv)
 136                 return 0x00;
 137         /*
 138          * There is no specific formula for voltage to vsel
 139          * conversion above 1.3V. There are special hardcoded
 140          * values for voltages above 1.3V. Currently we are
 141          * hardcoding only for 1.35 V which is used for 1GH OPP for
 142          * OMAP4430.
 143          */
 144         if (uv > twl6030_vsel_to_uv(0x39)) {
 145                 if (uv == 1350000)
 146                         return 0x3A;
 147                 pr_err("%s:OUT OF RANGE! non mapped vsel for %ld Vs max %ld\n",
 148                         __func__, uv, twl6030_vsel_to_uv(0x39));
 149                 return 0x3A;
 150         }
 151
 152         if (smps_offset & 0x8)
 153                 return DIV_ROUND_UP(uv - 709000, 12660) + 1;
 154         else
 155                 return DIV_ROUND_UP(uv - 607700, 12660) + 1;
 156 }
 157
 158 static struct omap_voltdm_pmic omap3_mpu_pmic = {
 159         .slew_rate              = 4000,
 160         .step_size              = 12500,
 161         .on_volt                = 1200000,
 162         .onlp_volt              = 1000000,
 163         .ret_volt               = 975000,
 164         .off_volt               = 600000,
 165         .volt_setup_time        = 0xfff,
 166         .vp_erroroffset         = OMAP3_VP_CONFIG_ERROROFFSET,
 167         .vp_vstepmin            = OMAP3_VP_VSTEPMIN_VSTEPMIN,
 168         .vp_vstepmax            = OMAP3_VP_VSTEPMAX_VSTEPMAX,
 169         .vp_vddmin              = OMAP3430_VP1_VLIMITTO_VDDMIN,
 170         .vp_vddmax              = OMAP3430_VP1_VLIMITTO_VDDMAX,
 171         .vp_timeout_us          = OMAP3_VP_VLIMITTO_TIMEOUT_US,
 172         .i2c_slave_addr         = OMAP3_SRI2C_SLAVE_ADDR,
 173         .volt_reg_addr          = OMAP3_VDD_MPU_SR_CONTROL_REG,
 174         .i2c_high_speed         = true,
 175         .vsel_to_uv             = twl4030_vsel_to_uv,
 176         .uv_to_vsel             = twl4030_uv_to_vsel,
 177 };
 178
 179 static struct omap_voltdm_pmic omap3_core_pmic = {
 180         .slew_rate              = 4000,
 181         .step_size              = 12500,
 182         .on_volt                = 1200000,
 183         .onlp_volt              = 1000000,
 184         .ret_volt               = 975000,
 185         .off_volt               = 600000,
 186         .volt_setup_time        = 0xfff,
 187         .vp_erroroffset         = OMAP3_VP_CONFIG_ERROROFFSET,
 188         .vp_vstepmin            = OMAP3_VP_VSTEPMIN_VSTEPMIN,
 189         .vp_vstepmax            = OMAP3_VP_VSTEPMAX_VSTEPMAX,
 190         .vp_vddmin              = OMAP3430_VP2_VLIMITTO_VDDMIN,
 191         .vp_vddmax              = OMAP3430_VP2_VLIMITTO_VDDMAX,
 192         .vp_timeout_us          = OMAP3_VP_VLIMITTO_TIMEOUT_US,
 193         .i2c_slave_addr         = OMAP3_SRI2C_SLAVE_ADDR,
 194         .volt_reg_addr          = OMAP3_VDD_CORE_SR_CONTROL_REG,
 195         .i2c_high_speed         = true,
 196         .vsel_to_uv             = twl4030_vsel_to_uv,
 197         .uv_to_vsel             = twl4030_uv_to_vsel,
 198 };
 199
 200 static struct omap_voltdm_pmic omap4_mpu_pmic = {
 201         .slew_rate              = 4000,
 202         .step_size              = 12660,
 203         .on_volt                = 1375000,
 204         .onlp_volt              = 1375000,
 205         .ret_volt               = 830000,
 206         .off_volt               = 0,
 207         .volt_setup_time        = 0,
 208         .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
 209         .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
 210         .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
 211         .vp_vddmin              = OMAP4_VP_MPU_VLIMITTO_VDDMIN,
 212         .vp_vddmax              = OMAP4_VP_MPU_VLIMITTO_VDDMAX,
 213         .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
 214         .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
 215         .volt_reg_addr          = OMAP4_VDD_MPU_SR_VOLT_REG,
 216         .cmd_reg_addr           = OMAP4_VDD_MPU_SR_CMD_REG,
 217         .i2c_high_speed         = true,
 218         .vsel_to_uv             = twl6030_vsel_to_uv,
 219         .uv_to_vsel             = twl6030_uv_to_vsel,
 220 };
 221
 222 static struct omap_voltdm_pmic omap4_iva_pmic = {
 223         .slew_rate              = 4000,
 224         .step_size              = 12660,
 225         .on_volt                = 1188000,
 226         .onlp_volt              = 1188000,
 227         .ret_volt               = 830000,
 228         .off_volt               = 0,
 229         .volt_setup_time        = 0,
 230         .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
 231         .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
 232         .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
 233         .vp_vddmin              = OMAP4_VP_IVA_VLIMITTO_VDDMIN,
 234         .vp_vddmax              = OMAP4_VP_IVA_VLIMITTO_VDDMAX,
 235         .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
 236         .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
 237         .volt_reg_addr          = OMAP4_VDD_IVA_SR_VOLT_REG,
 238         .cmd_reg_addr           = OMAP4_VDD_IVA_SR_CMD_REG,
 239         .i2c_high_speed         = true,
 240         .vsel_to_uv             = twl6030_vsel_to_uv,
 241         .uv_to_vsel             = twl6030_uv_to_vsel,
 242 };
 243
 244 static struct omap_voltdm_pmic omap4_core_pmic = {
 245         .slew_rate              = 4000,
 246         .step_size              = 12660,
 247         .on_volt                = 1200000,
 248         .onlp_volt              = 1200000,
 249         .ret_volt               = 830000,
 250         .off_volt               = 0,
 251         .volt_setup_time        = 0,
 252         .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
 253         .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
 254         .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
 255         .vp_vddmin              = OMAP4_VP_CORE_VLIMITTO_VDDMIN,
 256         .vp_vddmax              = OMAP4_VP_CORE_VLIMITTO_VDDMAX,
 257         .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
 258         .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
 259         .volt_reg_addr          = OMAP4_VDD_CORE_SR_VOLT_REG,
 260         .cmd_reg_addr           = OMAP4_VDD_CORE_SR_CMD_REG,
 261         .vsel_to_uv             = twl6030_vsel_to_uv,
 262         .uv_to_vsel             = twl6030_uv_to_vsel,
 263 };
 264
 265 int __init omap4_twl_init(void)
 266 {
 267         struct voltagedomain *voltdm;
 268
 269         if (!cpu_is_omap44xx())
 270                 return -ENODEV;
 271
 272         voltdm = voltdm_lookup("mpu");
 273         omap_voltage_register_pmic(voltdm, &omap4_mpu_pmic);
 274
 275         voltdm = voltdm_lookup("iva");
 276         omap_voltage_register_pmic(voltdm, &omap4_iva_pmic);
 277
 278         voltdm = voltdm_lookup("core");
 279         omap_voltage_register_pmic(voltdm, &omap4_core_pmic);
 280
 281         return 0;
 282 }
 283
 284 int __init omap3_twl_init(void)
 285 {
 286         struct voltagedomain *voltdm;
 287
 288         if (!cpu_is_omap34xx() || cpu_is_am33xx())
 289                 return -ENODEV;
 290
 291         if (cpu_is_omap3630()) {
 292                 omap3_mpu_pmic.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
 293                 omap3_mpu_pmic.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
 294                 omap3_core_pmic.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
 295                 omap3_core_pmic.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
 296         }
 297
 298         /*
 299          * The smartreflex bit on twl4030 specifies if the setting of voltage
 300          * is done over the I2C_SR path. Since this setting is independent of
 301          * the actual usage of smartreflex AVS module, we enable TWL SR bit
 302          * by default irrespective of whether smartreflex AVS module is enabled
 303          * on the OMAP side or not. This is because without this bit enabled,
 304          * the voltage scaling through vp forceupdate/bypass mechanism of
 305          * voltage scaling will not function on TWL over I2C_SR.
 306          */
 307         if (!twl_sr_enable_autoinit)
 308                 omap3_twl_set_sr_bit(true);
 309
 310         voltdm = voltdm_lookup("mpu_iva");
 311         omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic);
 312
 313         voltdm = voltdm_lookup("core");
 314         omap_voltage_register_pmic(voltdm, &omap3_core_pmic);
 315
 316         return 0;
 317 }
 318
 319 /**
 320  * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL
 321  * @enable: enable SR mode in twl or not
 322  *
 323  * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure
 324  * voltage scaling through OMAP SR works. Else, the smartreflex bit
 325  * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but
 326  * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct
 327  * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
 328  * in those scenarios this bit is to be cleared (enable = false).
 329  *
 330  * Returns 0 on success, error is returned if I2C read/write fails.
 331  */
 332 int __init omap3_twl_set_sr_bit(bool enable)
 333 {
 334         u8 temp;
 335         int ret;
 336         if (twl_sr_enable_autoinit)
 337                 pr_warning("%s: unexpected multiple calls\n", __func__);
 338
 339         ret = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &temp,
 340                                         TWL4030_DCDC_GLOBAL_CFG);
 341         if (ret)
 342                 goto err;
 343
 344         if (enable)
 345                 temp |= SMARTREFLEX_ENABLE;
 346         else
 347                 temp &= ~SMARTREFLEX_ENABLE;
 348
 349         ret = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
 350                                 TWL4030_DCDC_GLOBAL_CFG);
 351         if (!ret) {
 352                 twl_sr_enable_autoinit = true;
 353                 return 0;
 354         }
 355 err:
 356         pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret);
 357         return ret;
 358 }