27bf641544328bf0cd15548df92fe4861ebe3f12
1 /*
2 * AM33XX Power Management Routines
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/clk.h>
19 #include <linux/console.h>
20 #include <linux/err.h>
21 #include <linux/firmware.h>
22 #include <linux/io.h>
23 #include <linux/platform_device.h>
24 #include <linux/sched.h>
25 #include <linux/suspend.h>
27 #include <plat/prcm.h>
28 #include <plat/mailbox.h>
29 #include <plat/sram.h>
30 #include <plat/omap_hwmod.h>
31 #include <plat/omap_device.h>
33 #include <asm/suspend.h>
34 #include <asm/proc-fns.h>
35 #include <asm/sizes.h>
37 #include "pm.h"
39 static int m3_state;
40 static struct device *mpu_dev;
41 struct omap_mbox *m3_mbox;
42 void __iomem *ipc_regs;
43 void __iomem *m3_eoi;
44 void __iomem *m3_code;
46 bool enable_deep_sleep = true;
48 struct a8_wkup_m3_ipc_data {
49 int resume_addr;
50 int sleep_mode;
51 int ipc_data1;
52 int ipc_data2;
53 } am33xx_lp_ipc;
55 static int am33xx_set_low_power_state(struct a8_wkup_m3_ipc_data *);
56 void (*am33xx_do_wfi_sram)(void);
58 #define DS_RESUME_ADDR 0x40300010
59 #define DS_MODE 0x5
60 #define DS_IPC_DEFAULT 0xffffffff
62 #define A8_M3_IPC_REGS 0x44E11328
63 #define M3_TXEV_EOI 0x44E11324
65 #ifdef CONFIG_SUSPEND
66 static suspend_state_t suspend_state = PM_SUSPEND_ON;
68 static int am33xx_do_sram_idle(long unsigned int state)
69 {
70 am33xx_do_wfi_sram();
71 return 0;
72 }
74 static inline bool is_suspending(void)
75 {
76 return (suspend_state != PM_SUSPEND_ON) && console_suspend_enabled;
77 }
79 static int am33xx_pm_suspend(void)
80 {
81 int ret = 0;
83 /* Block console output in case it is on one of the OMAP UARTs */
84 if (!is_suspending()) {
85 if (!console_trylock()) {
86 ret = -EAGAIN;
87 goto err;
88 }
89 }
91 ret = cpu_suspend(0, am33xx_do_sram_idle);
92 if (ret)
93 pr_err("Could not suspend\n");
94 else
95 goto done;
97 err:
98 pr_err("Console still active\n");
99 done:
100 return ret;
101 }
103 static int am33xx_pm_enter(suspend_state_t unused)
104 {
105 int ret = 0;
107 switch (suspend_state) {
108 case PM_SUSPEND_STANDBY:
109 case PM_SUSPEND_MEM:
110 ret = am33xx_pm_suspend();
111 break;
112 default:
113 ret = -EINVAL;
114 }
116 return ret;
117 }
119 static int am33xx_pm_begin(suspend_state_t state)
120 {
121 int ret = 0;
123 am33xx_lp_ipc.resume_addr = DS_RESUME_ADDR;
124 am33xx_lp_ipc.sleep_mode = DS_MODE;
125 am33xx_lp_ipc.ipc_data1 = DS_IPC_DEFAULT;
126 am33xx_lp_ipc.ipc_data2 = DS_IPC_DEFAULT;
128 am33xx_set_low_power_state(&am33xx_lp_ipc);
130 ret = omap_mbox_msg_send(m3_mbox, 0xABCDABCD);
131 if (!ret) {
132 pr_info("Message sent\n");
133 omap_mbox_msg_rx_flush(m3_mbox);
134 }
136 omap_mbox_disable_irq(m3_mbox, IRQ_RX);
138 disable_hlt();
139 suspend_state = state;
141 return ret;
142 }
144 static void am33xx_pm_end(void)
145 {
146 suspend_state = PM_SUSPEND_ON;
148 if (!is_suspending())
149 console_unlock();
151 omap_mbox_enable_irq(m3_mbox, IRQ_RX);
152 return;
153 }
155 static const struct platform_suspend_ops am33xx_pm_ops = {
156 .begin = am33xx_pm_begin,
157 .end = am33xx_pm_end,
158 .enter = am33xx_pm_enter,
159 .valid = suspend_valid_only_mem,
160 };
161 #endif /* CONFIG_SUSPEND */
163 /*
164 * Push the minimal suspend-resume code to SRAM
165 */
166 void am33xx_push_sram_idle(void)
167 {
168 am33xx_do_wfi_sram = omap_sram_push(am33xx_do_wfi, am33xx_do_wfi_sz);
169 }
171 int am33xx_set_low_power_state(struct a8_wkup_m3_ipc_data *data)
172 {
173 __raw_writel(data->resume_addr, ipc_regs);
174 __raw_writel(data->sleep_mode, ipc_regs + 0x4);
175 __raw_writel(data->ipc_data1, ipc_regs + 0x8);
176 __raw_writel(data->ipc_data2, ipc_regs + 0xc);
178 return 0;
179 }
181 /*
182 * Dummy notifier for the mailbox
183 * TODO: Can this be completely removed?
184 */
185 int wkup_m3_mbox_msg(struct notifier_block *self, unsigned long len, void *msg)
186 {
187 return 0;
188 }
190 static struct notifier_block wkup_m3_mbox_notifier = {
191 .notifier_call = wkup_m3_mbox_msg,
192 };
194 /* Interrupt from M3 to A8 */
195 static irqreturn_t wkup_m3_txev_handler(int irq, void *unused)
196 {
197 m3_state++;
199 if (m3_eoi) {
200 __raw_writel(0x1, m3_eoi);
201 __raw_writel(0x0, m3_eoi);
202 return IRQ_HANDLED;
203 } else {
204 pr_err("%s unexpected interrupt. "
205 "Something is seriously wrong\n", __func__);
206 return IRQ_NONE;
207 }
208 }
210 /* Initiliaze WKUP_M3, load the binary blob and let it run */
211 static int wkup_m3_init(void)
212 {
213 struct clk *m3_clk;
214 struct omap_hwmod *wkup_m3_oh;
215 const struct firmware *firmware;
216 int ret = 0;
218 wkup_m3_oh = omap_hwmod_lookup("wkup_m3");
220 if (!wkup_m3_oh) {
221 pr_err("%s: could not find omap_hwmod\n", __func__);
222 ret = -ENODEV;
223 goto exit;
224 }
226 ipc_regs = ioremap(A8_M3_IPC_REGS, 0x4*8);
227 if (!ipc_regs) {
228 pr_err("Could not ioremap the IPC area\b");
229 ret = -ENOMEM;
230 goto exit;
231 }
233 m3_eoi = ioremap(M3_TXEV_EOI, 0x4);
234 if (!m3_eoi) {
235 pr_err("Could not ioremap the EOI register\n");
236 ret = -ENOMEM;
237 goto err1;
238 }
240 /* Reserve the MBOX for sending messages to M3 */
241 m3_mbox = omap_mbox_get("wkup_m3", &wkup_m3_mbox_notifier);
242 if (IS_ERR(m3_mbox)) {
243 pr_err("Could not reserve mailbox for A8->M3 IPC\n");
244 ret = -ENODEV;
245 goto err2;
246 }
248 /* Enable access to the M3 code and data area from A8 */
249 m3_clk = clk_get(NULL, "wkup_m3_fck");
250 if (IS_ERR(m3_clk)) {
251 pr_err("%s failed to enable WKUP_M3 clock\n", __func__);
252 goto err3;
253 }
255 if (clk_enable(m3_clk)) {
256 pr_err("%s WKUP_M3: clock enable Failed\n", __func__);
257 goto err4;
258 }
260 m3_code = ioremap(0x44D00000, SZ_16K);
261 if (!m3_code) {
262 pr_err("%s Could not ioremap M3 code space\n", __func__);
263 ret = -ENOMEM;
264 goto err5;
265 }
267 /* Now try to load the firware */
268 ret = request_firmware(&firmware, "cm3-firmware.bin", mpu_dev);
269 if (ret < 0) {
270 dev_err(mpu_dev, "request_firmware failed\n");
271 goto err6;
272 } else {
273 memcpy(m3_code, firmware->data, firmware->size);
274 pr_info("Copied the M3 firmware to UMEM\n");
275 }
277 ret = omap_hwmod_deassert_hardreset(wkup_m3_oh, "wkup_m3");
278 if (ret) {
279 pr_err("Could not deassert the reset for WKUP_M3\n");
280 goto err6;
281 }
283 ret = request_irq(AM33XX_IRQ_M3_M3SP_TXEV, wkup_m3_txev_handler,
284 IRQF_DISABLED, "wkup_m3_txev", NULL);
285 if (ret)
286 pr_err("%s request_irq failed for 0x%x\n", __func__,
287 AM33XX_IRQ_M3_M3SP_TXEV);
288 else
289 return 0;
291 err6:
292 release_firmware(firmware);
293 iounmap(m3_code);
294 err5:
295 clk_disable(m3_clk);
296 err4:
297 clk_put(m3_clk);
298 err3:
299 omap_mbox_put(m3_mbox, &wkup_m3_mbox_notifier);
300 err2:
301 iounmap(m3_eoi);
302 err1:
303 iounmap(ipc_regs);
304 exit:
305 return ret;
306 }
309 static int __init am33xx_pm_init(void)
310 {
311 int ret;
313 if (!cpu_is_am33xx())
314 return -ENODEV;
316 pr_info("Power Management for AM33XX family\n");
318 mpu_dev = omap_device_get_by_hwmod_name("mpu");
320 if (!mpu_dev) {
321 pr_warning("%s: unable to get the mpu device\n", __func__);
322 return -EINVAL;
323 }
325 ret = wkup_m3_init();
327 if (ret) {
328 pr_err("Could not initialise WKUP_M3."
329 "Power management will be compromised\n");
330 enable_deep_sleep = false;
331 }
333 #ifdef CONFIG_SUSPEND
334 if (enable_deep_sleep)
335 suspend_set_ops(&am33xx_pm_ops);
336 #endif /* CONFIG_SUSPEND */
338 return ret;
339 }
340 late_initcall(am33xx_pm_init);