arch/arm/mach-omap2/pm33xx.c

   1 /*
   2  * AM33XX Power Management Routines
   3  *
   4  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/clk.h>
  19 #include <linux/console.h>
  20 #include <linux/err.h>
  21 #include <linux/firmware.h>
  22 #include <linux/io.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/sched.h>
  25 #include <linux/suspend.h>
  26 #include <linux/completion.h>
  27 #include <linux/regulator/consumer.h>
  28 #include <linux/pm_runtime.h>
  29
  30 #include <plat/prcm.h>
  31 #include <plat/mailbox.h>
  32 #include <plat/sram.h>
  33 #include <plat/omap_hwmod.h>
  34 #include <plat/omap_device.h>
  35
  36 #include <asm/suspend.h>
  37 #include <asm/proc-fns.h>
  38 #include <asm/sizes.h>
  39
  40 #include "pm.h"
  41 #include "pm33xx.h"
  42 #include "control.h"
  43 #include "clockdomain.h"
  44 #include "powerdomain.h"
  45
  46 void (*am33xx_do_wfi_sram)(void);
  47
  48 #define DS_MODE         DS0_ID  /* DS0/1_ID */
  49
  50 #ifdef CONFIG_SUSPEND
  51
  52 void __iomem *ipc_regs;
  53 void __iomem *m3_eoi;
  54 void __iomem *m3_code;
  55
  56 bool enable_deep_sleep = true;
  57 static suspend_state_t suspend_state = PM_SUSPEND_ON;
  58
  59 static struct device *mpu_dev;
  60 static struct device *i2c_dev;
  61 static struct omap_mbox *m3_mbox;
  62 static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm;
  63 static struct clockdomain *gfx_l3_clkdm, *gfx_l4ls_clkdm;
  64
  65 static struct am33xx_padconf lp_padconf;
  66 static int gmii_sel;
  67
  68 static int core_suspend_stat = -1;
  69 static int m3_state = M3_STATE_UNKNOWN;
  70
  71 static int am33xx_ipc_cmd(struct a8_wkup_m3_ipc_data *);
  72 static int am33xx_verify_lp_state(void);
  73 static void am33xx_m3_state_machine_reset(void);
  74
  75 static DECLARE_COMPLETION(a8_m3_sync);
  76
  77 #define VOLT_TOLERANCE  12500 /* 12.5mV */
  78
  79 struct suspend_opp_change {
  80         char *clk_name;
  81         char *reg_name;
  82         unsigned long freq1;    /* Frequency in suspend mode */
  83         unsigned long freq2;    /* Frequency in active mode */
  84         unsigned int volt1;     /* Voltage in suspend mode */
  85         unsigned int volt2;     /* Voltage in active mode */
  86         struct clk *clk;
  87         struct regulator *reg;
  88 };
  89
  90 static struct suspend_opp_change opp[] = {
  91         {
  92                 .clk_name       = "dpll_mpu_ck",
  93                 .reg_name       = "vdd_mpu",
  94                 .freq1          = 275000000,
  95                 .volt1          = 965000,
  96         },
  97 };
  98
  99 static void save_padconf(void)
 100 {
 101         lp_padconf.mii1_col     = readl(AM33XX_CTRL_REGADDR(0x0908));
 102         lp_padconf.mii1_crs     = readl(AM33XX_CTRL_REGADDR(0x090c));
 103         lp_padconf.mii1_rxerr   = readl(AM33XX_CTRL_REGADDR(0x0910));
 104         lp_padconf.mii1_txen    = readl(AM33XX_CTRL_REGADDR(0x0914));
 105         lp_padconf.mii1_rxdv    = readl(AM33XX_CTRL_REGADDR(0x0918));
 106         lp_padconf.mii1_txd3    = readl(AM33XX_CTRL_REGADDR(0x091c));
 107         lp_padconf.mii1_txd2    = readl(AM33XX_CTRL_REGADDR(0x0920));
 108         lp_padconf.mii1_txd1    = readl(AM33XX_CTRL_REGADDR(0x0924));
 109         lp_padconf.mii1_txd0    = readl(AM33XX_CTRL_REGADDR(0x0928));
 110         lp_padconf.mii1_txclk   = readl(AM33XX_CTRL_REGADDR(0x092c));
 111         lp_padconf.mii1_rxclk   = readl(AM33XX_CTRL_REGADDR(0x0930));
 112         lp_padconf.mii1_rxd3    = readl(AM33XX_CTRL_REGADDR(0x0934));
 113         lp_padconf.mii1_rxd2    = readl(AM33XX_CTRL_REGADDR(0x0938));
 114         lp_padconf.mii1_rxd1    = readl(AM33XX_CTRL_REGADDR(0x093c));
 115         lp_padconf.mii1_rxd0    = readl(AM33XX_CTRL_REGADDR(0x0940));
 116         lp_padconf.rmii1_refclk = readl(AM33XX_CTRL_REGADDR(0x0944));
 117         lp_padconf.mdio_data    = readl(AM33XX_CTRL_REGADDR(0x0948));
 118         lp_padconf.mdio_clk     = readl(AM33XX_CTRL_REGADDR(0x094c));
 119         gmii_sel                = readl(AM33XX_CTRL_REGADDR(0x0650));
 120 }
 121
 122 static void restore_padconf(void)
 123 {
 124         writel(lp_padconf.mii1_col, AM33XX_CTRL_REGADDR(0x0908));
 125         writel(lp_padconf.mii1_crs, AM33XX_CTRL_REGADDR(0x090c));
 126         writel(lp_padconf.mii1_rxerr, AM33XX_CTRL_REGADDR(0x0910));
 127         writel(lp_padconf.mii1_txen, AM33XX_CTRL_REGADDR(0x0914));
 128         writel(lp_padconf.mii1_rxdv, AM33XX_CTRL_REGADDR(0x0918));
 129         writel(lp_padconf.mii1_txd3, AM33XX_CTRL_REGADDR(0x091c));
 130         writel(lp_padconf.mii1_txd2, AM33XX_CTRL_REGADDR(0x0920));
 131         writel(lp_padconf.mii1_txd1, AM33XX_CTRL_REGADDR(0x0924));
 132         writel(lp_padconf.mii1_txd0, AM33XX_CTRL_REGADDR(0x0928));
 133         writel(lp_padconf.mii1_txclk, AM33XX_CTRL_REGADDR(0x092c));
 134         writel(lp_padconf.mii1_rxclk, AM33XX_CTRL_REGADDR(0x0930));
 135         writel(lp_padconf.mii1_rxd3, AM33XX_CTRL_REGADDR(0x0934));
 136         writel(lp_padconf.mii1_rxd2, AM33XX_CTRL_REGADDR(0x0938));
 137         writel(lp_padconf.mii1_rxd1, AM33XX_CTRL_REGADDR(0x093c));
 138         writel(lp_padconf.mii1_rxd0, AM33XX_CTRL_REGADDR(0x0940));
 139         writel(lp_padconf.rmii1_refclk, AM33XX_CTRL_REGADDR(0x0944));
 140         writel(lp_padconf.mdio_data, AM33XX_CTRL_REGADDR(0x0948));
 141         writel(lp_padconf.mdio_clk, AM33XX_CTRL_REGADDR(0x094c));
 142         writel(gmii_sel, AM33XX_CTRL_REGADDR(0x0650));
 143 }
 144
 145
 146 static int am33xx_pm_prepare_late(void)
 147 {
 148         int ret = 0;
 149
 150         save_padconf();
 151
 152         if(!opp[0].clk || !opp[0].reg || !i2c_dev) {
 153                 pr_debug("Not attempting OPP change in suspend\n");
 154                 return ret;
 155         }
 156
 157         opp[0].freq2 = clk_get_rate(opp[0].clk);
 158         ret = clk_set_rate(opp[0].clk, opp[0].freq1);
 159         if (ret) {
 160                 pr_debug("Failed to set %s frequency to %luMHz\n",
 161                                         opp[0].clk_name, opp[0].freq1/1000000);
 162         } else {
 163                 opp[0].volt2 = regulator_get_voltage(opp[0].reg);
 164                 ret = regulator_set_voltage(opp[0].reg, opp[0].volt1,
 165                                         opp[0].volt1 + VOLT_TOLERANCE);
 166                 if (ret)
 167                         pr_debug("Failed to set %s voltage to %dmV\n",
 168                                         opp[0].reg_name, opp[0].volt1/1000);
 169         }
 170
 171         return ret;
 172 }
 173
 174 static void am33xx_pm_finish(void)
 175 {
 176         int ret = 0;
 177
 178         if(!opp[0].clk || !opp[0].reg || !i2c_dev) {
 179                 pr_debug("Not attempting OPP change in resume\n");
 180                 goto padconf;
 181         }
 182
 183         ret = regulator_set_voltage(opp[0].reg, opp[0].volt2,
 184                                         opp[0].volt2 + VOLT_TOLERANCE);
 185         if (ret) {
 186                 pr_warning("Failed to restore %s voltage to %dmV\n",
 187                                         opp[0].reg_name, opp[0].volt2/1000);
 188         } else {
 189                 ret = clk_set_rate(opp[0].clk, opp[0].freq2);
 190                 if (ret)
 191                         pr_warning("Failed to restore %s frequency to %luMHz\n",
 192                                         opp[0].clk_name, opp[0].freq2/1000000);
 193         }
 194
 195 padconf:
 196         restore_padconf();
 197 }
 198
 199 static int am33xx_do_sram_idle(long unsigned int state)
 200 {
 201         am33xx_do_wfi_sram();
 202         return 0;
 203 }
 204
 205 static int am33xx_pm_suspend(void)
 206 {
 207         int state, ret = 0;
 208
 209         struct omap_hwmod *cpgmac_oh, *gpmc_oh, *usb_oh;
 210
 211         cpgmac_oh       = omap_hwmod_lookup("cpgmac0");
 212         usb_oh          = omap_hwmod_lookup("usb_otg_hs");
 213         gpmc_oh         = omap_hwmod_lookup("gpmc");
 214
 215         omap_hwmod_enable(cpgmac_oh);
 216         omap_hwmod_enable(usb_oh);
 217         omap_hwmod_enable(gpmc_oh);
 218
 219         omap_hwmod_idle(cpgmac_oh);
 220         omap_hwmod_idle(usb_oh);
 221         omap_hwmod_idle(gpmc_oh);
 222
 223         if(gfx_l3_clkdm && gfx_l4ls_clkdm) {
 224                 clkdm_sleep(gfx_l3_clkdm);
 225                 clkdm_sleep(gfx_l4ls_clkdm);
 226         }
 227
 228         /* Try to put GFX to sleep */
 229         if (gfx_pwrdm)
 230                 pwrdm_set_next_pwrst(gfx_pwrdm, PWRDM_POWER_OFF);
 231         else
 232                 pr_err("Could not program GFX to low power state\n");
 233
 234         ret = cpu_suspend(0, am33xx_do_sram_idle);
 235
 236         if (gfx_pwrdm) {
 237                 state = pwrdm_read_pwrst(gfx_pwrdm);
 238                 if (state != PWRDM_POWER_OFF)
 239                         pr_err("GFX domain did not transition to low power state\n");
 240                 else
 241                         pr_info("GFX domain entered low power state\n");
 242         }
 243
 244         /* XXX: Why do we need to wakeup the clockdomains? */
 245         if(gfx_l3_clkdm && gfx_l4ls_clkdm) {
 246                 clkdm_wakeup(gfx_l3_clkdm);
 247                 clkdm_wakeup(gfx_l4ls_clkdm);
 248         }
 249
 250         core_suspend_stat = ret;
 251
 252         return ret;
 253 }
 254
 255 static int am33xx_pm_enter(suspend_state_t unused)
 256 {
 257         int ret = 0;
 258
 259         switch (suspend_state) {
 260         case PM_SUSPEND_STANDBY:
 261         case PM_SUSPEND_MEM:
 262                 ret = am33xx_pm_suspend();
 263                 break;
 264         default:
 265                 ret = -EINVAL;
 266         }
 267
 268         return ret;
 269 }
 270
 271 static int am33xx_pm_begin(suspend_state_t state)
 272 {
 273         int ret = 0;
 274
 275         disable_hlt();
 276
 277         if(i2c_dev)
 278                 pm_runtime_forbid(i2c_dev);
 279
 280         am33xx_lp_ipc.resume_addr = DS_RESUME_ADDR;
 281         am33xx_lp_ipc.sleep_mode  = DS_MODE;
 282         am33xx_lp_ipc.ipc_data1   = DS_IPC_DEFAULT;
 283         am33xx_lp_ipc.ipc_data2   = DS_IPC_DEFAULT;
 284
 285         am33xx_ipc_cmd(&am33xx_lp_ipc);
 286
 287         m3_state = M3_STATE_MSG_FOR_LP;
 288
 289         omap_mbox_enable_irq(m3_mbox, IRQ_RX);
 290
 291         ret = omap_mbox_msg_send(m3_mbox, 0xABCDABCD);
 292         if (ret) {
 293                 pr_err("A8<->CM3 MSG for LP failed\n");
 294                 am33xx_m3_state_machine_reset();
 295                 ret = -1;
 296         }
 297
 298         if (!wait_for_completion_timeout(&a8_m3_sync, msecs_to_jiffies(5000))) {
 299                 pr_err("A8<->CM3 sync failure\n");
 300                 am33xx_m3_state_machine_reset();
 301                 ret = -1;
 302         } else {
 303                 pr_debug("Message sent for entering %s\n",
 304                         (DS_MODE == DS0_ID ? "DS0" : "DS1"));
 305                 omap_mbox_disable_irq(m3_mbox, IRQ_RX);
 306         }
 307
 308         suspend_state = state;
 309         return ret;
 310 }
 311
 312 static void am33xx_m3_state_machine_reset(void)
 313 {
 314         int ret = 0;
 315
 316         am33xx_lp_ipc.resume_addr = 0x0;
 317         am33xx_lp_ipc.sleep_mode  = 0xe;
 318         am33xx_lp_ipc.ipc_data1   = DS_IPC_DEFAULT;
 319         am33xx_lp_ipc.ipc_data2   = DS_IPC_DEFAULT;
 320
 321         am33xx_ipc_cmd(&am33xx_lp_ipc);
 322
 323         m3_state = M3_STATE_MSG_FOR_RESET;
 324
 325         ret = omap_mbox_msg_send(m3_mbox, 0xABCDABCD);
 326         if (!ret) {
 327                 pr_debug("Message sent for resetting M3 state machine\n");
 328                 if (!wait_for_completion_timeout(&a8_m3_sync, msecs_to_jiffies(5000)))
 329                         pr_err("A8<->CM3 sync failure\n");
 330         } else {
 331                 pr_debug("Could not reset M3 state machine!!!\n");
 332                 m3_state = M3_STATE_UNKNOWN;
 333         }
 334 }
 335
 336 static void am33xx_pm_end(void)
 337 {
 338         int ret;
 339
 340         suspend_state = PM_SUSPEND_ON;
 341
 342         ret = am33xx_verify_lp_state();
 343
 344         omap_mbox_enable_irq(m3_mbox, IRQ_RX);
 345
 346         am33xx_m3_state_machine_reset();
 347
 348         if(i2c_dev)
 349                 pm_runtime_allow(i2c_dev);
 350
 351         enable_hlt();
 352
 353         return;
 354 }
 355
 356 static const struct platform_suspend_ops am33xx_pm_ops = {
 357         .begin          = am33xx_pm_begin,
 358         .end            = am33xx_pm_end,
 359         .enter          = am33xx_pm_enter,
 360         .valid          = suspend_valid_only_mem,
 361         .prepare        = am33xx_pm_prepare_late,
 362         .finish         = am33xx_pm_finish,
 363 };
 364
 365 int am33xx_ipc_cmd(struct a8_wkup_m3_ipc_data *data)
 366 {
 367         writel(data->resume_addr, ipc_regs);
 368         writel(data->sleep_mode, ipc_regs + 0x4);
 369         writel(data->ipc_data1, ipc_regs + 0x8);
 370         writel(data->ipc_data2, ipc_regs + 0xc);
 371
 372         return 0;
 373 }
 374
 375 /* return 0 if no reset M3 needed, 1 otherwise */
 376 static int am33xx_verify_lp_state(void)
 377 {
 378         int status, ret = 0;
 379
 380         if (core_suspend_stat) {
 381                 pr_err("Kernel core reported suspend failure\n");
 382                 ret = -1;
 383                 goto clear_old_status;
 384         }
 385
 386         status = readl(ipc_regs + 0x4);
 387         status &= 0xffff0000;
 388
 389         if (status == 0x0) {
 390                 pr_info("Successfully transitioned all domains to low power state\n");
 391                 goto clear_old_status;
 392         } else if (status == 0x10000) {
 393                 pr_info("Could not enter low power state\n"
 394                         "Please check for active clocks in PER domain\n");
 395                 ret = -1;
 396                 goto clear_old_status;
 397         } else {
 398                 pr_info("Something went wrong :(\nStatus = %0x\n", status);
 399                 ret = -1;
 400         }
 401
 402 clear_old_status:
 403         /* After decoding write back the bad status */
 404         status = readl(ipc_regs + 0x4);
 405         status &= 0xffff0000;
 406         status |= 0x10000;
 407         writel(status, ipc_regs + 0x4);
 408
 409         return ret;
 410 }
 411
 412 /*
 413  * Dummy notifier for the mailbox
 414  * TODO: Can this be completely removed?
 415  */
 416 int wkup_m3_mbox_msg(struct notifier_block *self, unsigned long len, void *msg)
 417 {
 418         return 0;
 419 }
 420
 421 static struct notifier_block wkup_m3_mbox_notifier = {
 422         .notifier_call = wkup_m3_mbox_msg,
 423 };
 424
 425 /* Interrupt from M3 to A8 */
 426 static irqreturn_t wkup_m3_txev_handler(int irq, void *unused)
 427 {
 428         writel(0x1, m3_eoi);
 429
 430         if (m3_state == M3_STATE_RESET) {
 431                 m3_state = M3_STATE_INITED;
 432         } else if (m3_state == M3_STATE_MSG_FOR_RESET) {
 433                 m3_state = M3_STATE_INITED;
 434                 omap_mbox_msg_rx_flush(m3_mbox);
 435                 if (m3_mbox->ops->ack_irq)
 436                         m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX);
 437                 complete(&a8_m3_sync);
 438         } else if (m3_state == M3_STATE_MSG_FOR_LP) {
 439                 /* Read back the MBOX and disable the interrupt to M3 since we are going down */
 440                 omap_mbox_msg_rx_flush(m3_mbox);
 441                 if (m3_mbox->ops->ack_irq)
 442                         m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX);
 443                 complete(&a8_m3_sync);
 444         } else if (m3_state == M3_STATE_UNKNOWN) {
 445                 pr_err("IRQ %d with CM3 in unknown state\n", irq);
 446                 omap_mbox_msg_rx_flush(m3_mbox);
 447                 if (m3_mbox->ops->ack_irq)
 448                         m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX);
 449                 return IRQ_NONE;
 450         }
 451
 452         writel(0x0, m3_eoi);
 453
 454         return IRQ_HANDLED;
 455 }
 456
 457 /* Initiliaze WKUP_M3, load the binary blob and let it run */
 458 static int wkup_m3_init(void)
 459 {
 460         struct clk *m3_clk;
 461         struct omap_hwmod *wkup_m3_oh;
 462         const struct firmware *firmware;
 463         int ret = 0;
 464
 465         wkup_m3_oh = omap_hwmod_lookup("wkup_m3");
 466
 467         if (!wkup_m3_oh) {
 468                 pr_err("%s: could not find omap_hwmod\n", __func__);
 469                 ret = -ENODEV;
 470                 goto exit;
 471         }
 472
 473         ipc_regs = ioremap(A8_M3_IPC_REGS, 0x4*8);
 474         if (!ipc_regs) {
 475                 pr_err("Could not ioremap the IPC area\b");
 476                 ret = -ENOMEM;
 477                 goto exit;
 478         }
 479
 480         m3_eoi = ioremap(M3_TXEV_EOI, 0x4);
 481         if (!m3_eoi) {
 482                 pr_err("Could not ioremap the EOI register\n");
 483                 ret = -ENOMEM;
 484                 goto err1;
 485         }
 486
 487         /* Reserve the MBOX for sending messages to M3 */
 488         m3_mbox = omap_mbox_get("wkup_m3", &wkup_m3_mbox_notifier);
 489         if (IS_ERR(m3_mbox)) {
 490                 pr_err("Could not reserve mailbox for A8->M3 IPC\n");
 491                 ret = -ENODEV;
 492                 goto err2;
 493         }
 494
 495         /* Enable access to the M3 code and data area from A8 */
 496         m3_clk = clk_get(NULL, "wkup_m3_fck");
 497         if (IS_ERR(m3_clk)) {
 498                 pr_err("%s failed to enable WKUP_M3 clock\n", __func__);
 499                 goto err3;
 500         }
 501
 502         if (clk_enable(m3_clk)) {
 503                 pr_err("%s WKUP_M3: clock enable Failed\n", __func__);
 504                 goto err4;
 505         }
 506
 507         m3_code = ioremap(M3_UMEM, SZ_16K);
 508         if (!m3_code) {
 509                 pr_err("%s Could not ioremap M3 code space\n", __func__);
 510                 ret = -ENOMEM;
 511                 goto err5;
 512         }
 513
 514         pr_info("Trying to load am335x-pm-firmware.bin\n");
 515
 516         /* Now try to load the firware */
 517         ret = request_firmware(&firmware, "am335x-pm-firmware.bin", mpu_dev);
 518         if (ret < 0) {
 519                 dev_err(mpu_dev, "request_firmware failed\n");
 520                 goto err6;
 521         } else {
 522                 memcpy(m3_code, firmware->data, firmware->size);
 523                 pr_info("Copied the M3 firmware to UMEM\n");
 524         }
 525
 526         /* Request the IRQ before M3 is released from reset */
 527         ret = request_irq(AM33XX_IRQ_M3_M3SP_TXEV, wkup_m3_txev_handler,
 528                           IRQF_DISABLED, "wkup_m3_txev", NULL);
 529         if (ret) {
 530                 pr_err("%s request_irq failed for 0x%x\n", __func__,
 531                         AM33XX_IRQ_M3_M3SP_TXEV);
 532                 goto err6;
 533         }
 534
 535         m3_state = M3_STATE_RESET;
 536
 537         ret = omap_hwmod_deassert_hardreset(wkup_m3_oh, "wkup_m3");
 538         if (ret) {
 539                 pr_err("Could not deassert the reset for WKUP_M3\n");
 540                 goto err6;
 541         } else {
 542                 return 0;
 543         }
 544
 545 err6:
 546         release_firmware(firmware);
 547         iounmap(m3_code);
 548 err5:
 549         clk_disable(m3_clk);
 550 err4:
 551         clk_put(m3_clk);
 552 err3:
 553         omap_mbox_put(m3_mbox, &wkup_m3_mbox_notifier);
 554 err2:
 555         iounmap(m3_eoi);
 556 err1:
 557         iounmap(ipc_regs);
 558 exit:
 559         return ret;
 560 }
 561
 562 /*
 563  * Enable hardware supervised mode for all clockdomains if it's
 564  * supported. Initiate sleep transition for other clockdomains, if
 565  * they are not used
 566  */
 567 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 568 {
 569         if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 570                         atomic_read(&clkdm->usecount) == 0)
 571                 clkdm_sleep(clkdm);
 572         return 0;
 573 }
 574 #endif /* CONFIG_SUSPEND */
 575
 576 /*
 577  * Push the minimal suspend-resume code to SRAM
 578  */
 579 void am33xx_push_sram_idle(void)
 580 {
 581         am33xx_do_wfi_sram = omap_sram_push(am33xx_do_wfi, am33xx_do_wfi_sz);
 582 }
 583
 584 static int __init am33xx_pm_init(void)
 585 {
 586         int ret, i;
 587
 588         if (!cpu_is_am33xx())
 589                 return -ENODEV;
 590
 591         pr_info("Power Management for AM33XX family\n");
 592
 593 #ifdef CONFIG_SUSPEND
 594         (void) clkdm_for_each(clkdms_setup, NULL);
 595
 596         /* CEFUSE domain should be turned off post bootup */
 597         cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm");
 598         if (cefuse_pwrdm == NULL)
 599                 printk(KERN_ERR "Failed to get cefuse_pwrdm\n");
 600         else
 601                 pwrdm_set_next_pwrst(cefuse_pwrdm, PWRDM_POWER_OFF);
 602
 603         gfx_pwrdm = pwrdm_lookup("gfx_pwrdm");
 604         if (gfx_pwrdm == NULL)
 605                 printk(KERN_ERR "Failed to get gfx_pwrdm\n");
 606
 607         gfx_l3_clkdm = clkdm_lookup("gfx_l3_clkdm");
 608         if (gfx_l3_clkdm == NULL)
 609                 printk(KERN_ERR "Failed to get gfx_l3_clkdm\n");
 610
 611         gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm");
 612         if (gfx_l4ls_clkdm == NULL)
 613                 printk(KERN_ERR "Failed to get gfx_l4ls_gfx_clkdm\n");
 614
 615         mpu_dev = omap_device_get_by_hwmod_name("mpu");
 616
 617         if (!mpu_dev) {
 618                 pr_warning("%s: unable to get the mpu device\n", __func__);
 619                 return -EINVAL;
 620         }
 621
 622         i2c_dev = omap_device_get_by_hwmod_name("i2c1");
 623
 624         if (!i2c_dev) {
 625                 pr_warning("%s: unable to get the i2c device\n", __func__);
 626                 return -EINVAL;
 627         }
 628
 629         for (i = 0; i < ARRAY_SIZE(opp); i++) {
 630                 opp[i].clk = clk_get(NULL, opp[i].clk_name);
 631                 if (IS_ERR(opp[i].clk))
 632                         pr_warning("Could not get %s clock\n", opp[i].clk_name);
 633
 634                 if (opp[i].reg_name) {
 635                         opp[i].reg = regulator_get(NULL, opp[i].reg_name);
 636                         if (IS_ERR(opp[i].reg))
 637                                 pr_warning("Could not get %s regulator\n",
 638                                                         opp[i].reg_name);
 639                 }
 640         }
 641
 642         ret = wkup_m3_init();
 643
 644         if (ret) {
 645                 pr_err("Could not initialise WKUP_M3. "
 646                         "Power management will be compromised\n");
 647                 enable_deep_sleep = false;
 648         }
 649
 650         if (enable_deep_sleep)
 651                 suspend_set_ops(&am33xx_pm_ops);
 652 #endif /* CONFIG_SUSPEND */
 653
 654         return ret;
 655 }
 656 late_initcall(am33xx_pm_init);