arch/arm/mach-omap2/pm33xx.h

   1 /*
   2  * AM33XX Power Management Routines
   3  *
   4  * Copyright (C) 2012 Texas Instruments Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #ifndef __ARCH_ARM_MACH_OMAP2_PM33XX_H
  12 #define __ARCH_ARM_MACH_OMAP2_PM33XX_H
  13
  14 #include <mach/hardware.h>      /* XXX Is this the right one to include? */
  15
  16 #ifndef __ASSEMBLER__
  17 extern void __iomem *am33xx_get_ram_base(void);
  18 #endif /* ASSEMBLER */
  19
  20 #define M3_TXEV_EOI                     (AM33XX_CTRL_BASE + 0x1324)
  21 #define A8_M3_IPC_REGS                  (AM33XX_CTRL_BASE + 0x1328)
  22 #define DS_RESUME_ADDR                  0x403000A0
  23 #define DS_IPC_DEFAULT                  0xffffffff
  24 #define M3_UMEM                         0x44D00000
  25
  26 #define DS0_ID                          0x3
  27 #define DS1_ID                          0x5
  28
  29 /* DDR offsets */
  30 #define DDR_CMD0_IOCTRL                 (AM33XX_CTRL_BASE + 0x1404)
  31 #define DDR_CMD1_IOCTRL                 (AM33XX_CTRL_BASE + 0x1408)
  32 #define DDR_CMD2_IOCTRL                 (AM33XX_CTRL_BASE + 0x140C)
  33 #define DDR_DATA0_IOCTRL                (AM33XX_CTRL_BASE + 0x1440)
  34 #define DDR_DATA1_IOCTRL                (AM33XX_CTRL_BASE + 0x1444)
  35
  36 #define DDR_IO_CTRL                     (AM33XX_CTRL_BASE + 0x0E04)
  37 #define VTP0_CTRL_REG                   (AM33XX_CTRL_BASE + 0x0E0C)
  38 #define DDR_CKE_CTRL                    (AM33XX_CTRL_BASE + 0x131C)
  39 #define DDR_PHY_BASE_ADDR               (AM33XX_CTRL_BASE + 0x2000)
  40
  41 #define CMD0_CTRL_SLAVE_RATIO_0         (DDR_PHY_BASE_ADDR + 0x01C)
  42 #define CMD0_CTRL_SLAVE_FORCE_0         (DDR_PHY_BASE_ADDR + 0x020)
  43 #define CMD0_CTRL_SLAVE_DELAY_0         (DDR_PHY_BASE_ADDR + 0x024)
  44 #define CMD0_DLL_LOCK_DIFF_0            (DDR_PHY_BASE_ADDR + 0x028)
  45 #define CMD0_INVERT_CLKOUT_0            (DDR_PHY_BASE_ADDR + 0x02C)
  46
  47 #define CMD1_CTRL_SLAVE_RATIO_0         (DDR_PHY_BASE_ADDR + 0x050)
  48 #define CMD1_CTRL_SLAVE_FORCE_0         (DDR_PHY_BASE_ADDR + 0x054)
  49 #define CMD1_CTRL_SLAVE_DELAY_0         (DDR_PHY_BASE_ADDR + 0x058)
  50 #define CMD1_DLL_LOCK_DIFF_0            (DDR_PHY_BASE_ADDR + 0x05C)
  51 #define CMD1_INVERT_CLKOUT_0            (DDR_PHY_BASE_ADDR + 0x060)
  52
  53 #define CMD2_CTRL_SLAVE_RATIO_0         (DDR_PHY_BASE_ADDR + 0x084)
  54 #define CMD2_CTRL_SLAVE_FORCE_0         (DDR_PHY_BASE_ADDR + 0x088)
  55 #define CMD2_CTRL_SLAVE_DELAY_0         (DDR_PHY_BASE_ADDR + 0x08C)
  56 #define CMD2_DLL_LOCK_DIFF_0            (DDR_PHY_BASE_ADDR + 0x090)
  57 #define CMD2_INVERT_CLKOUT_0            (DDR_PHY_BASE_ADDR + 0x094)
  58
  59 #define DATA0_RD_DQS_SLAVE_RATIO_0      (DDR_PHY_BASE_ADDR + 0x0C8)
  60 #define DATA0_RD_DQS_SLAVE_RATIO_1      (DDR_PHY_BASE_ADDR + 0x0CC)
  61
  62 #define DATA0_WR_DQS_SLAVE_RATIO_0      (DDR_PHY_BASE_ADDR + 0x0DC)
  63 #define DATA0_WR_DQS_SLAVE_RATIO_1      (DDR_PHY_BASE_ADDR + 0x0E0)
  64
  65 #define DATA0_WRLVL_INIT_RATIO_0        (DDR_PHY_BASE_ADDR + 0x0F0)
  66 #define DATA0_WRLVL_INIT_RATIO_1        (DDR_PHY_BASE_ADDR + 0x0F4)
  67
  68 #define DATA0_GATELVL_INIT_RATIO_0      (DDR_PHY_BASE_ADDR + 0x0FC)
  69 #define DATA0_GATELVL_INIT_RATIO_1      (DDR_PHY_BASE_ADDR + 0x100)
  70
  71 #define DATA0_FIFO_WE_SLAVE_RATIO_0     (DDR_PHY_BASE_ADDR + 0x108)
  72 #define DATA0_FIFO_WE_SLAVE_RATIO_1     (DDR_PHY_BASE_ADDR + 0x10C)
  73
  74 #define DATA0_WR_DATA_SLAVE_RATIO_0     (DDR_PHY_BASE_ADDR + 0x120)
  75 #define DATA0_WR_DATA_SLAVE_RATIO_1     (DDR_PHY_BASE_ADDR + 0x124)
  76
  77 #define DATA0_DLL_LOCK_DIFF_0           (DDR_PHY_BASE_ADDR + 0x138)
  78
  79 #define DATA0_RANK0_DELAYS_0            (DDR_PHY_BASE_ADDR + 0x134)
  80 #define DATA1_RANK0_DELAYS_0            (DDR_PHY_BASE_ADDR + 0x1D8)
  81
  82 /* Temp placeholder for the values we want in the registers */
  83 #define EMIF_READ_LATENCY       0x04
  84 #define EMIF_TIM1               0x0666B3D6
  85 #define EMIF_TIM2               0x143731DA
  86 #define EMIF_TIM3               0x00000347
  87 #define EMIF_SDCFG              0x43805332
  88 #define EMIF_SDREF              0x0000081a
  89 #define EMIF_SDMGT              0x80000000
  90 #define EMIF_SDRAM              0x00004650
  91 #define EMIF_PHYCFG             0x2
  92
  93 #define DDR2_DLL_LOCK_DIFF      0x0
  94 #define DDR2_RD_DQS             0x12
  95 #define DDR2_PHY_FIFO_WE        0x80
  96
  97 #define DDR_PHY_RESET           (0x1 << 10)
  98 #define DDR_PHY_READY           (0x1 << 2)
  99 #define DDR2_RATIO              0x80
 100 #define CMD_FORCE               0x00
 101 #define CMD_DELAY               0x00
 102
 103 #define DDR2_INVERT_CLKOUT      0x00
 104 #define DDR2_WR_DQS             0x00
 105 #define DDR2_PHY_WRLVL          0x00
 106 #define DDR2_PHY_GATELVL        0x00
 107 #define DDR2_PHY_WR_DATA        0x40
 108 #define PHY_RANK0_DELAY         0x01
 109 #define PHY_DLL_LOCK_DIFF       0x0
 110 #define DDR_IOCTRL_VALUE        0x18B
 111
 112 #define VTP_CTRL_READY          (0x1 << 5)
 113 #define VTP_CTRL_ENABLE         (0x1 << 6)
 114 #define VTP_CTRL_LOCK_EN        (0x1 << 4)
 115 #define VTP_CTRL_START_EN       (0x1)
 116
 117 #endif