1 /*
2 * AM33XX Power Management Routines
3 *
4 * Copyright (C) 2012 Texas Instruments Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
11 #ifndef __ARCH_ARM_MACH_OMAP2_PM33XX_H
12 #define __ARCH_ARM_MACH_OMAP2_PM33XX_H
14 #include <mach/hardware.h> /* XXX Is this the right one to include? */
16 #ifndef __ASSEMBLER__
17 extern void __iomem *am33xx_get_ram_base(void);
19 struct a8_wkup_m3_ipc_data {
20 int resume_addr;
21 int sleep_mode;
22 int ipc_data1;
23 int ipc_data2;
24 } am33xx_lp_ipc;
26 struct am33xx_padconf {
27 int mii1_col;
28 int mii1_crs;
29 int mii1_rxerr;
30 int mii1_txen;
31 int mii1_rxdv;
32 int mii1_txd3;
33 int mii1_txd2;
34 int mii1_txd1;
35 int mii1_txd0;
36 int mii1_txclk;
37 int mii1_rxclk;
38 int mii1_rxd3;
39 int mii1_rxd2;
40 int mii1_rxd1;
41 int mii1_rxd0;
42 int rmii1_refclk;
43 int mdio_data;
44 int mdio_clk;
45 };
46 #endif /* ASSEMBLER */
48 #define M3_TXEV_EOI (AM33XX_CTRL_BASE + 0x1324)
49 #define A8_M3_IPC_REGS (AM33XX_CTRL_BASE + 0x1328)
50 #define DS_RESUME_ADDR 0x40300340
51 #define DS_IPC_DEFAULT 0xffffffff
52 #define M3_UMEM 0x44D00000
54 #define DS0_ID 0x3
55 #define DS1_ID 0x5
57 #define M3_STATE_UNKNOWN -1
58 #define M3_STATE_RESET 0
59 #define M3_STATE_INITED 1
60 #define M3_STATE_MSG_FOR_LP 2
61 #define M3_STATE_MSG_FOR_RESET 3
63 /* DDR offsets */
64 #define DDR_CMD0_IOCTRL (AM33XX_CTRL_BASE + 0x1404)
65 #define DDR_CMD1_IOCTRL (AM33XX_CTRL_BASE + 0x1408)
66 #define DDR_CMD2_IOCTRL (AM33XX_CTRL_BASE + 0x140C)
67 #define DDR_DATA0_IOCTRL (AM33XX_CTRL_BASE + 0x1440)
68 #define DDR_DATA1_IOCTRL (AM33XX_CTRL_BASE + 0x1444)
70 #define DDR_IO_CTRL (AM33XX_CTRL_BASE + 0x0E04)
71 #define VTP0_CTRL_REG (AM33XX_CTRL_BASE + 0x0E0C)
72 #define DDR_CKE_CTRL (AM33XX_CTRL_BASE + 0x131C)
73 #define DDR_PHY_BASE_ADDR (AM33XX_CTRL_BASE + 0x2000)
75 #define CMD0_CTRL_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x01C)
76 #define CMD0_CTRL_SLAVE_FORCE_0 (DDR_PHY_BASE_ADDR + 0x020)
77 #define CMD0_CTRL_SLAVE_DELAY_0 (DDR_PHY_BASE_ADDR + 0x024)
78 #define CMD0_DLL_LOCK_DIFF_0 (DDR_PHY_BASE_ADDR + 0x028)
79 #define CMD0_INVERT_CLKOUT_0 (DDR_PHY_BASE_ADDR + 0x02C)
81 #define CMD1_CTRL_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x050)
82 #define CMD1_CTRL_SLAVE_FORCE_0 (DDR_PHY_BASE_ADDR + 0x054)
83 #define CMD1_CTRL_SLAVE_DELAY_0 (DDR_PHY_BASE_ADDR + 0x058)
84 #define CMD1_DLL_LOCK_DIFF_0 (DDR_PHY_BASE_ADDR + 0x05C)
85 #define CMD1_INVERT_CLKOUT_0 (DDR_PHY_BASE_ADDR + 0x060)
87 #define CMD2_CTRL_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x084)
88 #define CMD2_CTRL_SLAVE_FORCE_0 (DDR_PHY_BASE_ADDR + 0x088)
89 #define CMD2_CTRL_SLAVE_DELAY_0 (DDR_PHY_BASE_ADDR + 0x08C)
90 #define CMD2_DLL_LOCK_DIFF_0 (DDR_PHY_BASE_ADDR + 0x090)
91 #define CMD2_INVERT_CLKOUT_0 (DDR_PHY_BASE_ADDR + 0x094)
93 #define DATA0_RD_DQS_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x0C8)
94 #define DATA0_RD_DQS_SLAVE_RATIO_1 (DDR_PHY_BASE_ADDR + 0x0CC)
96 #define DATA0_WR_DQS_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x0DC)
97 #define DATA0_WR_DQS_SLAVE_RATIO_1 (DDR_PHY_BASE_ADDR + 0x0E0)
99 #define DATA0_WRLVL_INIT_RATIO_0 (DDR_PHY_BASE_ADDR + 0x0F0)
100 #define DATA0_WRLVL_INIT_RATIO_1 (DDR_PHY_BASE_ADDR + 0x0F4)
102 #define DATA0_GATELVL_INIT_RATIO_0 (DDR_PHY_BASE_ADDR + 0x0FC)
103 #define DATA0_GATELVL_INIT_RATIO_1 (DDR_PHY_BASE_ADDR + 0x100)
105 #define DATA0_FIFO_WE_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x108)
106 #define DATA0_FIFO_WE_SLAVE_RATIO_1 (DDR_PHY_BASE_ADDR + 0x10C)
108 #define DATA0_WR_DATA_SLAVE_RATIO_0 (DDR_PHY_BASE_ADDR + 0x120)
109 #define DATA0_WR_DATA_SLAVE_RATIO_1 (DDR_PHY_BASE_ADDR + 0x124)
111 #define DATA0_DLL_LOCK_DIFF_0 (DDR_PHY_BASE_ADDR + 0x138)
113 #define DATA0_RANK0_DELAYS_0 (DDR_PHY_BASE_ADDR + 0x134)
114 #define DATA1_RANK0_DELAYS_0 (DDR_PHY_BASE_ADDR + 0x1D8)
116 /* Temp placeholder for the values we want in the registers */
117 #define EMIF_READ_LATENCY 0x04
118 #define EMIF_TIM1 0x0666B3D6
119 #define EMIF_TIM2 0x143731DA
120 #define EMIF_TIM3 0x00000347
121 #define EMIF_SDCFG 0x43805332
122 #define EMIF_SDREF 0x0000081a
123 #define EMIF_SDMGT 0x80000000
124 #define EMIF_SDRAM 0x00004650
125 #define EMIF_PHYCFG 0x2
127 #define DDR2_DLL_LOCK_DIFF 0x0
128 #define DDR2_RD_DQS 0x12
129 #define DDR2_PHY_FIFO_WE 0x80
131 #define DDR_PHY_RESET (0x1 << 10)
132 #define DDR_PHY_READY (0x1 << 2)
133 #define DDR2_RATIO 0x80
134 #define CMD_FORCE 0x00
135 #define CMD_DELAY 0x00
137 #define DDR2_INVERT_CLKOUT 0x00
138 #define DDR2_WR_DQS 0x00
139 #define DDR2_PHY_WRLVL 0x00
140 #define DDR2_PHY_GATELVL 0x00
141 #define DDR2_PHY_WR_DATA 0x40
142 #define PHY_RANK0_DELAY 0x01
143 #define PHY_DLL_LOCK_DIFF 0x0
144 #define DDR_IOCTRL_VALUE 0x18B
146 #define VTP_CTRL_READY (0x1 << 5)
147 #define VTP_CTRL_ENABLE (0x1 << 6)
148 #define VTP_CTRL_LOCK_EN (0x1 << 4)
149 #define VTP_CTRL_START_EN (0x1)
151 #endif