ARM: AM335X: Split hwmod data accessible only on GP devices
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / pm33xx.h
1 /*
2  * AM33XX Power Management Routines
3  *
4  * Copyright (C) 2012 Texas Instruments Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
11 #ifndef __ARCH_ARM_MACH_OMAP2_PM33XX_H
12 #define __ARCH_ARM_MACH_OMAP2_PM33XX_H
14 #include <mach/hardware.h>      /* XXX Is this the right one to include? */
15 #include "control.h"
16 #include "mux33xx.h"
18 #ifndef __ASSEMBLER__
19 extern void __iomem *am33xx_get_ram_base(void);
21 /*
22  * This enum is used to index the array passed to suspend routine with
23  * parameters that vary across DDR2 and DDR3 sleep sequence.
24  *
25  * Since these are used to load into registers by suspend code,
26  * entries here must always be in sync with the suspend code
27  * in arm/mach-omap2/sleep33xx.S
28  */
29 enum suspend_cfg_params {
30         MEMORY_TYPE = 0,
31         SUSP_VTP_CTRL_VAL,
32         EVM_ID,
33         SUSPEND_CFG_PARAMS_END /* Must be the last entry */
34 };
36 struct a8_wkup_m3_ipc_data {
37         int resume_addr;
38         int sleep_mode;
39         int ipc_data1;
40         int ipc_data2;
41 } am33xx_lp_ipc;
43 struct am33xx_padconf_regs {
44         u16 offset;
45         u32 val;
46 };
48 #ifdef CONFIG_SUSPEND
49 static struct am33xx_padconf_regs am33xx_lp_padconf[] = {
50         {.offset = AM33XX_CONTROL_GMII_SEL_OFFSET},
51         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A0_OFFSET},
52         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A1_OFFSET},
53         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A2_OFFSET},
54         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A3_OFFSET},
55         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A4_OFFSET},
56         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A5_OFFSET},
57         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A6_OFFSET},
58         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A7_OFFSET},
59         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A8_OFFSET},
60         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A9_OFFSET},
61         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A10_OFFSET},
62         {.offset = AM33XX_CONTROL_PADCONF_GPMC_A11_OFFSET},
63         {.offset = AM33XX_CONTROL_PADCONF_GPMC_WAIT0_OFFSET},
64         {.offset = AM33XX_CONTROL_PADCONF_GPMC_WPN_OFFSET},
65         {.offset = AM33XX_CONTROL_PADCONF_GPMC_BEN1_OFFSET},
66         {.offset = AM33XX_CONTROL_PADCONF_MII1_COL_OFFSET},
67         {.offset = AM33XX_CONTROL_PADCONF_MII1_CRS_OFFSET},
68         {.offset = AM33XX_CONTROL_PADCONF_MII1_RXERR_OFFSET},
69         {.offset = AM33XX_CONTROL_PADCONF_MII1_TXEN_OFFSET},
70         {.offset = AM33XX_CONTROL_PADCONF_MII1_RXDV_OFFSET},
71         {.offset = AM33XX_CONTROL_PADCONF_MII1_TXD3_OFFSET},
72         {.offset = AM33XX_CONTROL_PADCONF_MII1_TXD2_OFFSET},
73         {.offset = AM33XX_CONTROL_PADCONF_MII1_TXD1_OFFSET},
74         {.offset = AM33XX_CONTROL_PADCONF_MII1_TXD0_OFFSET},
75         {.offset = AM33XX_CONTROL_PADCONF_MII1_TXCLK_OFFSET},
76         {.offset = AM33XX_CONTROL_PADCONF_MII1_RXCLK_OFFSET},
77         {.offset = AM33XX_CONTROL_PADCONF_MII1_RXD3_OFFSET},
78         {.offset = AM33XX_CONTROL_PADCONF_MII1_RXD2_OFFSET},
79         {.offset = AM33XX_CONTROL_PADCONF_MII1_RXD1_OFFSET},
80         {.offset = AM33XX_CONTROL_PADCONF_MII1_RXD0_OFFSET},
81         {.offset = AM33XX_CONTROL_PADCONF_MII1_REFCLK_OFFSET},
82         {.offset = AM33XX_CONTROL_PADCONF_MDIO_DATA_OFFSET},
83         {.offset = AM33XX_CONTROL_PADCONF_MDIO_CLK_OFFSET},
84 };
85 #endif /* CONFIG_SUSPEND */
86 #endif /* ASSEMBLER */
88 #define M3_TXEV_EOI                     (AM33XX_CTRL_BASE + 0x1324)
89 #define A8_M3_IPC_REGS                  (AM33XX_CTRL_BASE + 0x1328)
90 #define DS_RESUME_BASE                  0x40300000
91 #define DS_IPC_DEFAULT                  0xffffffff
92 #define M3_UMEM                         0x44D00000
94 #define DS0_ID                          0x3
95 #define DS1_ID                          0x5
97 #define M3_STATE_UNKNOWN                -1
98 #define M3_STATE_RESET                  0
99 #define M3_STATE_INITED                 1
100 #define M3_STATE_MSG_FOR_LP             2
101 #define M3_STATE_MSG_FOR_RESET          3
103 #define VTP_CTRL_READY          (0x1 << 5)
104 #define VTP_CTRL_ENABLE         (0x1 << 6)
105 #define VTP_CTRL_LOCK_EN        (0x1 << 4)
106 #define VTP_CTRL_START_EN       (0x1)
108 #define DDR_IO_CTRL             (AM33XX_CTRL_BASE + 0x0E04)
109 #define VTP0_CTRL_REG           (AM33XX_CTRL_BASE + 0x0E0C)
110 #define DDR_CMD0_IOCTRL         (AM33XX_CTRL_BASE + 0x1404)
111 #define DDR_CMD1_IOCTRL         (AM33XX_CTRL_BASE + 0x1408)
112 #define DDR_CMD2_IOCTRL         (AM33XX_CTRL_BASE + 0x140C)
113 #define DDR_DATA0_IOCTRL        (AM33XX_CTRL_BASE + 0x1440)
114 #define DDR_DATA1_IOCTRL        (AM33XX_CTRL_BASE + 0x1444)
116 #define MEM_TYPE_DDR2           2
118 #define SUSP_VTP_CTRL_DDR2      0x10117
119 #define SUSP_VTP_CTRL_DDR3      0x0
121 #endif