ARM: OMAP: AM33XX: Yet one more DS0 update
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / pm33xx.h
1 /*
2  * AM33XX Power Management Routines
3  *
4  * Copyright (C) 2012 Texas Instruments Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
11 #ifndef __ARCH_ARM_MACH_OMAP2_PM33XX_H
12 #define __ARCH_ARM_MACH_OMAP2_PM33XX_H
14 #include <mach/hardware.h>      /* XXX Is this the right one to include? */
16 #ifndef __ASSEMBLER__
17 extern void __iomem *am33xx_get_ram_base(void);
19 struct a8_wkup_m3_ipc_data {
20         int resume_addr;
21         int sleep_mode;
22         int ipc_data1;
23         int ipc_data2;
24 } am33xx_lp_ipc;
25 #endif /* ASSEMBLER */
27 #define M3_TXEV_EOI                     (AM33XX_CTRL_BASE + 0x1324)
28 #define A8_M3_IPC_REGS                  (AM33XX_CTRL_BASE + 0x1328)
29 #define DS_RESUME_ADDR                  0x40300220
30 #define DS_IPC_DEFAULT                  0xffffffff
31 #define M3_UMEM                         0x44D00000
33 #define DS0_ID                          0x3
34 #define DS1_ID                          0x5
36 #define M3_STATE_UNKNOWN                -1
37 #define M3_STATE_RESET                  0
38 #define M3_STATE_INITED                 1
39 #define M3_STATE_MSG_FOR_LP             2
40 #define M3_STATE_MSG_FOR_RESET          3
42 /* DDR offsets */
43 #define DDR_CMD0_IOCTRL                 (AM33XX_CTRL_BASE + 0x1404)
44 #define DDR_CMD1_IOCTRL                 (AM33XX_CTRL_BASE + 0x1408)
45 #define DDR_CMD2_IOCTRL                 (AM33XX_CTRL_BASE + 0x140C)
46 #define DDR_DATA0_IOCTRL                (AM33XX_CTRL_BASE + 0x1440)
47 #define DDR_DATA1_IOCTRL                (AM33XX_CTRL_BASE + 0x1444)
49 #define DDR_IO_CTRL                     (AM33XX_CTRL_BASE + 0x0E04)
50 #define VTP0_CTRL_REG                   (AM33XX_CTRL_BASE + 0x0E0C)
51 #define DDR_CKE_CTRL                    (AM33XX_CTRL_BASE + 0x131C)
52 #define DDR_PHY_BASE_ADDR               (AM33XX_CTRL_BASE + 0x2000)
54 #define CMD0_CTRL_SLAVE_RATIO_0         (DDR_PHY_BASE_ADDR + 0x01C)
55 #define CMD0_CTRL_SLAVE_FORCE_0         (DDR_PHY_BASE_ADDR + 0x020)
56 #define CMD0_CTRL_SLAVE_DELAY_0         (DDR_PHY_BASE_ADDR + 0x024)
57 #define CMD0_DLL_LOCK_DIFF_0            (DDR_PHY_BASE_ADDR + 0x028)
58 #define CMD0_INVERT_CLKOUT_0            (DDR_PHY_BASE_ADDR + 0x02C)
60 #define CMD1_CTRL_SLAVE_RATIO_0         (DDR_PHY_BASE_ADDR + 0x050)
61 #define CMD1_CTRL_SLAVE_FORCE_0         (DDR_PHY_BASE_ADDR + 0x054)
62 #define CMD1_CTRL_SLAVE_DELAY_0         (DDR_PHY_BASE_ADDR + 0x058)
63 #define CMD1_DLL_LOCK_DIFF_0            (DDR_PHY_BASE_ADDR + 0x05C)
64 #define CMD1_INVERT_CLKOUT_0            (DDR_PHY_BASE_ADDR + 0x060)
66 #define CMD2_CTRL_SLAVE_RATIO_0         (DDR_PHY_BASE_ADDR + 0x084)
67 #define CMD2_CTRL_SLAVE_FORCE_0         (DDR_PHY_BASE_ADDR + 0x088)
68 #define CMD2_CTRL_SLAVE_DELAY_0         (DDR_PHY_BASE_ADDR + 0x08C)
69 #define CMD2_DLL_LOCK_DIFF_0            (DDR_PHY_BASE_ADDR + 0x090)
70 #define CMD2_INVERT_CLKOUT_0            (DDR_PHY_BASE_ADDR + 0x094)
72 #define DATA0_RD_DQS_SLAVE_RATIO_0      (DDR_PHY_BASE_ADDR + 0x0C8)
73 #define DATA0_RD_DQS_SLAVE_RATIO_1      (DDR_PHY_BASE_ADDR + 0x0CC)
75 #define DATA0_WR_DQS_SLAVE_RATIO_0      (DDR_PHY_BASE_ADDR + 0x0DC)
76 #define DATA0_WR_DQS_SLAVE_RATIO_1      (DDR_PHY_BASE_ADDR + 0x0E0)
78 #define DATA0_WRLVL_INIT_RATIO_0        (DDR_PHY_BASE_ADDR + 0x0F0)
79 #define DATA0_WRLVL_INIT_RATIO_1        (DDR_PHY_BASE_ADDR + 0x0F4)
81 #define DATA0_GATELVL_INIT_RATIO_0      (DDR_PHY_BASE_ADDR + 0x0FC)
82 #define DATA0_GATELVL_INIT_RATIO_1      (DDR_PHY_BASE_ADDR + 0x100)
84 #define DATA0_FIFO_WE_SLAVE_RATIO_0     (DDR_PHY_BASE_ADDR + 0x108)
85 #define DATA0_FIFO_WE_SLAVE_RATIO_1     (DDR_PHY_BASE_ADDR + 0x10C)
87 #define DATA0_WR_DATA_SLAVE_RATIO_0     (DDR_PHY_BASE_ADDR + 0x120)
88 #define DATA0_WR_DATA_SLAVE_RATIO_1     (DDR_PHY_BASE_ADDR + 0x124)
90 #define DATA0_DLL_LOCK_DIFF_0           (DDR_PHY_BASE_ADDR + 0x138)
92 #define DATA0_RANK0_DELAYS_0            (DDR_PHY_BASE_ADDR + 0x134)
93 #define DATA1_RANK0_DELAYS_0            (DDR_PHY_BASE_ADDR + 0x1D8)
95 /* Temp placeholder for the values we want in the registers */
96 #define EMIF_READ_LATENCY       0x04
97 #define EMIF_TIM1               0x0666B3D6
98 #define EMIF_TIM2               0x143731DA
99 #define EMIF_TIM3               0x00000347
100 #define EMIF_SDCFG              0x43805332
101 #define EMIF_SDREF              0x0000081a
102 #define EMIF_SDMGT              0x80000000
103 #define EMIF_SDRAM              0x00004650
104 #define EMIF_PHYCFG             0x2
106 #define DDR2_DLL_LOCK_DIFF      0x0
107 #define DDR2_RD_DQS             0x12
108 #define DDR2_PHY_FIFO_WE        0x80
110 #define DDR_PHY_RESET           (0x1 << 10)
111 #define DDR_PHY_READY           (0x1 << 2)
112 #define DDR2_RATIO              0x80
113 #define CMD_FORCE               0x00
114 #define CMD_DELAY               0x00
116 #define DDR2_INVERT_CLKOUT      0x00
117 #define DDR2_WR_DQS             0x00
118 #define DDR2_PHY_WRLVL          0x00
119 #define DDR2_PHY_GATELVL        0x00
120 #define DDR2_PHY_WR_DATA        0x40
121 #define PHY_RANK0_DELAY         0x01
122 #define PHY_DLL_LOCK_DIFF       0x0
123 #define DDR_IOCTRL_VALUE        0x18B
125 #define VTP_CTRL_READY          (0x1 << 5)
126 #define VTP_CTRL_ENABLE         (0x1 << 6)
127 #define VTP_CTRL_LOCK_EN        (0x1 << 4)
128 #define VTP_CTRL_START_EN       (0x1)
130 #endif