1 /*
2 * linux/arch/arm/mach-omap2/prcm.c
3 *
4 * OMAP 24xx Power Reset and Clock Management (PRCM) functions
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 *
10 * Copyright (C) 2007 Texas Instruments, Inc.
11 * Rajendra Nayak <rnayak@ti.com>
12 *
13 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
14 * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/clk.h>
24 #include <linux/io.h>
25 #include <linux/delay.h>
26 #include <linux/export.h>
28 #include <mach/system.h>
29 #include "common.h"
30 #include <plat/prcm.h>
31 #include <plat/irqs.h>
33 #include "clock.h"
34 #include "clock2xxx.h"
35 #include "cm2xxx_3xxx.h"
36 #include "prm2xxx_3xxx.h"
37 #include "prm44xx.h"
38 #include "prm33xx.h"
39 #include "prminst44xx.h"
40 #include "prm-regbits-24xx.h"
41 #include "prm-regbits-44xx.h"
42 #include "control.h"
44 void __iomem *prm_base;
45 void __iomem *cm_base;
46 void __iomem *cm2_base;
48 #define MAX_MODULE_ENABLE_WAIT 100000
50 u32 omap_prcm_get_reset_sources(void)
51 {
52 /* XXX This presumably needs modification for 34XX */
53 if (cpu_is_omap24xx() || cpu_is_omap34xx())
54 return omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
55 if (cpu_is_omap44xx())
56 return omap2_prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
58 return 0;
59 }
60 EXPORT_SYMBOL(omap_prcm_get_reset_sources);
62 /* Resets clock rates and reboots the system. Only called from system.h */
63 static void omap_prcm_arch_reset(char mode, const char *cmd)
64 {
65 s16 prcm_offs = 0;
67 if (cpu_is_omap24xx()) {
68 omap2xxx_clk_prepare_for_reboot();
70 prcm_offs = WKUP_MOD;
71 } else if (cpu_is_am33xx()) {
72 prcm_offs = AM33XX_PRM_DEVICE_MOD;
73 omap2_prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_COLD_SW_MASK,
74 prcm_offs, AM33XX_PRM_RSTCTRL_OFFSET);
75 } else if (cpu_is_omap34xx()) {
76 prcm_offs = OMAP3430_GR_MOD;
77 omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
78 } else if (cpu_is_omap44xx()) {
79 omap4_prminst_global_warm_sw_reset(); /* never returns */
80 } else {
81 WARN_ON(1);
82 }
84 /*
85 * As per Errata i520, in some cases, user will not be able to
86 * access DDR memory after warm-reset.
87 * This situation occurs while the warm-reset happens during a read
88 * access to DDR memory. In that particular condition, DDR memory
89 * does not respond to a corrupted read command due to the warm
90 * reset occurrence but SDRC is waiting for read completion.
91 * SDRC is not sensitive to the warm reset, but the interconnect is
92 * reset on the fly, thus causing a misalignment between SDRC logic,
93 * interconnect logic and DDR memory state.
94 * WORKAROUND:
95 * Steps to perform before a Warm reset is trigged:
96 * 1. enable self-refresh on idle request
97 * 2. put SDRC in idle
98 * 3. wait until SDRC goes to idle
99 * 4. generate SW reset (Global SW reset)
100 *
101 * Steps to be performed after warm reset occurs (in bootloader):
102 * if HW warm reset is the source, apply below steps before any
103 * accesses to SDRAM:
104 * 1. Reset SMS and SDRC and wait till reset is complete
105 * 2. Re-initialize SMS, SDRC and memory
106 *
107 * NOTE: Above work around is required only if arch reset is implemented
108 * using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need
109 * the WA since it resets SDRC as well as part of cold reset.
110 */
112 /* XXX should be moved to some OMAP2/3 specific code */
113 omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
114 OMAP2_RM_RSTCTRL);
115 omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
116 }
118 void (*arch_reset)(char, const char *) = omap_prcm_arch_reset;
120 /**
121 * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
122 * @reg: physical address of module IDLEST register
123 * @mask: value to mask against to determine if the module is active
124 * @idlest: idle state indicator (0 or 1) for the clock
125 * @name: name of the clock (for printk)
126 *
127 * Returns 1 if the module indicated readiness in time, or 0 if it
128 * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
129 *
130 * XXX This function is deprecated. It should be removed once the
131 * hwmod conversion is complete.
132 */
133 int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
134 const char *name)
135 {
136 int i = 0;
137 int ena = 0;
139 if (idlest)
140 ena = 0;
141 else
142 ena = mask;
144 /* Wait for lock */
145 omap_test_timeout(((__raw_readl(reg) & mask) == ena),
146 MAX_MODULE_ENABLE_WAIT, i);
148 if (i < MAX_MODULE_ENABLE_WAIT)
149 pr_debug("cm: Module associated with clock %s ready after %d "
150 "loops\n", name, i);
151 else
152 pr_err("cm: Module associated with clock %s didn't enable in "
153 "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
155 return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
156 };
158 void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
159 {
160 if (omap2_globals->prm)
161 prm_base = omap2_globals->prm;
162 if (omap2_globals->cm)
163 cm_base = omap2_globals->cm;
164 if (omap2_globals->cm2)
165 cm2_base = omap2_globals->cm2;
166 }