1 /*
2 * OMAP2/3 PRM module functions
3 *
4 * Copyright (C) 2010-2011 Texas Instruments, Inc.
5 * Copyright (C) 2010 Nokia Corporation
6 * BenoƮt Cousson
7 * Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
14 #include <linux/kernel.h>
15 #include <linux/errno.h>
16 #include <linux/err.h>
17 #include <linux/io.h>
19 #include "common.h"
20 #include <plat/cpu.h>
21 #include <plat/prcm.h>
23 #include "vp.h"
25 #include "prm2xxx_3xxx.h"
26 #include "cm2xxx_3xxx.h"
27 #include "prm-regbits-24xx.h"
28 #include "prm-regbits-34xx.h"
30 static const struct omap_prcm_irq omap3_prcm_irqs[] = {
31 OMAP_PRCM_IRQ("wkup", 0, 0),
32 OMAP_PRCM_IRQ("io", 9, 1),
33 };
35 static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
36 .ack = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
37 .mask = OMAP3_PRM_IRQENABLE_MPU_OFFSET,
38 .nr_regs = 1,
39 .irqs = omap3_prcm_irqs,
40 .nr_irqs = ARRAY_SIZE(omap3_prcm_irqs),
41 .irq = INT_34XX_PRCM_MPU_IRQ,
42 .read_pending_irqs = &omap3xxx_prm_read_pending_irqs,
43 .ocp_barrier = &omap3xxx_prm_ocp_barrier,
44 .save_and_clear_irqen = &omap3xxx_prm_save_and_clear_irqen,
45 .restore_irqen = &omap3xxx_prm_restore_irqen,
46 };
48 u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
49 {
50 return __raw_readl(prm_base + module + idx);
51 }
53 void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
54 {
55 __raw_writel(val, prm_base + module + idx);
56 }
58 /* Read-modify-write a register in a PRM module. Caller must lock */
59 u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
60 {
61 u32 v;
63 v = omap2_prm_read_mod_reg(module, idx);
64 v &= ~mask;
65 v |= bits;
66 omap2_prm_write_mod_reg(v, module, idx);
68 return v;
69 }
71 /* Read a PRM register, AND it, and shift the result down to bit 0 */
72 u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
73 {
74 u32 v;
76 v = omap2_prm_read_mod_reg(domain, idx);
77 v &= mask;
78 v >>= __ffs(mask);
80 return v;
81 }
83 u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
84 {
85 return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
86 }
88 u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
89 {
90 return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
91 }
94 /**
95 * omap2_prm_is_hardreset_asserted - read the HW reset line state of
96 * submodules contained in the hwmod module
97 * @prm_mod: PRM submodule base (e.g. CORE_MOD)
98 * @shift: register bit shift corresponding to the reset line to check
99 *
100 * Returns 1 if the (sub)module hardreset line is currently asserted,
101 * 0 if the (sub)module hardreset line is not currently asserted, or
102 * -EINVAL if called while running on a non-OMAP2/3 chip.
103 */
104 int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
105 {
106 if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
107 return -EINVAL;
109 return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
110 (1 << shift));
111 }
113 /**
114 * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
115 * @prm_mod: PRM submodule base (e.g. CORE_MOD)
116 * @shift: register bit shift corresponding to the reset line to assert
117 *
118 * Some IPs like dsp or iva contain processors that require an HW
119 * reset line to be asserted / deasserted in order to fully enable the
120 * IP. These modules may have multiple hard-reset lines that reset
121 * different 'submodules' inside the IP block. This function will
122 * place the submodule into reset. Returns 0 upon success or -EINVAL
123 * upon an argument error.
124 */
125 int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
126 {
127 u32 mask;
129 if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
130 return -EINVAL;
132 mask = 1 << shift;
133 omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);
135 return 0;
136 }
138 /**
139 * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait
140 * @prm_mod: PRM submodule base (e.g. CORE_MOD)
141 * @rst_shift: register bit shift corresponding to the reset line to deassert
142 * @st_shift: register bit shift for the status of the deasserted submodule
143 *
144 * Some IPs like dsp or iva contain processors that require an HW
145 * reset line to be asserted / deasserted in order to fully enable the
146 * IP. These modules may have multiple hard-reset lines that reset
147 * different 'submodules' inside the IP block. This function will
148 * take the submodule out of reset and wait until the PRCM indicates
149 * that the reset has completed before returning. Returns 0 upon success or
150 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
151 * of reset, or -EBUSY if the submodule did not exit reset promptly.
152 */
153 int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
154 {
155 u32 rst, st;
156 int c;
158 if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
159 return -EINVAL;
161 rst = 1 << rst_shift;
162 st = 1 << st_shift;
164 /* Check the current status to avoid de-asserting the line twice */
165 if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, rst) == 0)
166 return -EEXIST;
168 /* Clear the reset status by writing 1 to the status bit */
169 omap2_prm_rmw_mod_reg_bits(0xffffffff, st, prm_mod, OMAP2_RM_RSTST);
170 /* de-assert the reset control line */
171 omap2_prm_rmw_mod_reg_bits(rst, 0, prm_mod, OMAP2_RM_RSTCTRL);
172 /* wait the status to be set */
173 omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST,
174 st),
175 MAX_MODULE_HARDRESET_WAIT, c);
177 return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
178 }
180 /* PRM VP */
182 /*
183 * struct omap3_vp - OMAP3 VP register access description.
184 * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
185 */
186 struct omap3_vp {
187 u32 tranxdone_status;
188 };
190 static struct omap3_vp omap3_vp[] = {
191 [OMAP3_VP_VDD_MPU_ID] = {
192 .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
193 },
194 [OMAP3_VP_VDD_CORE_ID] = {
195 .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
196 },
197 };
199 #define MAX_VP_ID ARRAY_SIZE(omap3_vp);
201 u32 omap3_prm_vp_check_txdone(u8 vp_id)
202 {
203 struct omap3_vp *vp = &omap3_vp[vp_id];
204 u32 irqstatus;
206 irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
207 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
208 return irqstatus & vp->tranxdone_status;
209 }
211 void omap3_prm_vp_clear_txdone(u8 vp_id)
212 {
213 struct omap3_vp *vp = &omap3_vp[vp_id];
215 omap2_prm_write_mod_reg(vp->tranxdone_status,
216 OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
217 }
219 u32 omap3_prm_vcvp_read(u8 offset)
220 {
221 return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset);
222 }
224 void omap3_prm_vcvp_write(u32 val, u8 offset)
225 {
226 omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
227 }
229 u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
230 {
231 return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
232 }
234 /**
235 * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
236 * @events: ptr to a u32, preallocated by caller
237 *
238 * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM
239 * MPU IRQs, and store the result into the u32 pointed to by @events.
240 * No return value.
241 */
242 void omap3xxx_prm_read_pending_irqs(unsigned long *events)
243 {
244 u32 mask, st;
246 /* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
247 mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
248 st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
250 events[0] = mask & st;
251 }
253 /**
254 * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
255 *
256 * Force any buffered writes to the PRM IP block to complete. Needed
257 * by the PRM IRQ handler, which reads and writes directly to the IP
258 * block, to avoid race conditions after acknowledging or clearing IRQ
259 * bits. No return value.
260 */
261 void omap3xxx_prm_ocp_barrier(void)
262 {
263 omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
264 }
266 /**
267 * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg
268 * @saved_mask: ptr to a u32 array to save IRQENABLE bits
269 *
270 * Save the PRM_IRQENABLE_MPU register to @saved_mask. @saved_mask
271 * must be allocated by the caller. Intended to be used in the PRM
272 * interrupt handler suspend callback. The OCP barrier is needed to
273 * ensure the write to disable PRM interrupts reaches the PRM before
274 * returning; otherwise, spurious interrupts might occur. No return
275 * value.
276 */
277 void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
278 {
279 saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
280 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
281 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
283 /* OCP barrier */
284 omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
285 }
287 /**
288 * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args
289 * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
290 *
291 * Restore the PRM_IRQENABLE_MPU register from @saved_mask. Intended
292 * to be used in the PRM interrupt handler resume callback to restore
293 * values saved by omap3xxx_prm_save_and_clear_irqen(). No OCP
294 * barrier should be needed here; any pending PRM interrupts will fire
295 * once the writes reach the PRM. No return value.
296 */
297 void omap3xxx_prm_restore_irqen(u32 *saved_mask)
298 {
299 omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
300 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
301 }
303 static int __init omap3xxx_prcm_init(void)
304 {
305 if (cpu_is_omap34xx() && !cpu_is_am33xx())
306 return omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
307 return 0;
308 }
309 subsys_initcall(omap3xxx_prcm_init);