arch/arm/mach-omap2/prm_common.c

   1 /*
   2  * OMAP2+ common Power & Reset Management (PRM) IP block functions
   3  *
   4  * Copyright (C) 2011 Texas Instruments, Inc.
   5  * Tero Kristo <t-kristo@ti.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  *
  12  * For historical purposes, the API used to configure the PRM
  13  * interrupt handler refers to it as the "PRCM interrupt."  The
  14  * underlying registers are located in the PRM on OMAP3/4.
  15  *
  16  * XXX This code should eventually be moved to a PRM driver.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/init.h>
  22 #include <linux/io.h>
  23 #include <linux/irq.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/slab.h>
  26
  27 #include <mach/system.h>
  28 #include <plat/common.h>
  29 #include <plat/prcm.h>
  30 #include <plat/irqs.h>
  31
  32 #include "prm2xxx_3xxx.h"
  33 #include "prm44xx.h"
  34
  35 /*
  36  * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
  37  * XXX this is technically not needed, since
  38  * omap_prcm_register_chain_handler() could allocate this based on the
  39  * actual amount of memory needed for the SoC
  40  */
  41 #define OMAP_PRCM_MAX_NR_PENDING_REG            2
  42
  43 /*
  44  * prcm_irq_chips: an array of all of the "generic IRQ chips" in use
  45  * by the PRCM interrupt handler code.  There will be one 'chip' per
  46  * PRM_{IRQSTATUS,IRQENABLE}_MPU register pair.  (So OMAP3 will have
  47  * one "chip" and OMAP4 will have two.)
  48  */
  49 static struct irq_chip_generic **prcm_irq_chips;
  50
  51 /*
  52  * prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
  53  * is currently running on.  Defined and passed by initialization code
  54  * that calls omap_prcm_register_chain_handler().
  55  */
  56 static struct omap_prcm_irq_setup *prcm_irq_setup;
  57
  58 /* Private functions */
  59
  60 /*
  61  * Move priority events from events to priority_events array
  62  */
  63 static void omap_prcm_events_filter_priority(unsigned long *events,
  64         unsigned long *priority_events)
  65 {
  66         int i;
  67
  68         for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
  69                 priority_events[i] =
  70                         events[i] & prcm_irq_setup->priority_mask[i];
  71                 events[i] ^= priority_events[i];
  72         }
  73 }
  74
  75 /*
  76  * PRCM Interrupt Handler
  77  *
  78  * This is a common handler for the OMAP PRCM interrupts. Pending
  79  * interrupts are detected by a call to prcm_pending_events and
  80  * dispatched accordingly. Clearing of the wakeup events should be
  81  * done by the SoC specific individual handlers.
  82  */
  83 static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
  84 {
  85         unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
  86         unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
  87         struct irq_chip *chip = irq_desc_get_chip(desc);
  88         unsigned int virtirq;
  89         int nr_irqs = prcm_irq_setup->nr_regs * 32;
  90
  91         /*
  92          * If we are suspended, mask all interrupts from PRCM level,
  93          * this does not ack them, and they will be pending until we
  94          * re-enable the interrupts, at which point the
  95          * omap_prcm_irq_handler will be executed again.  The
  96          * _save_and_clear_irqen() function must ensure that the PRM
  97          * write to disable all IRQs has reached the PRM before
  98          * returning, or spurious PRCM interrupts may occur during
  99          * suspend.
 100          */
 101         if (prcm_irq_setup->suspended) {
 102                 prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask);
 103                 prcm_irq_setup->suspend_save_flag = true;
 104         }
 105
 106         /*
 107          * Loop until all pending irqs are handled, since
 108          * generic_handle_irq() can cause new irqs to come
 109          */
 110         while (!prcm_irq_setup->suspended) {
 111                 prcm_irq_setup->read_pending_irqs(pending);
 112
 113                 /* No bit set, then all IRQs are handled */
 114                 if (find_first_bit(pending, nr_irqs) >= nr_irqs)
 115                         break;
 116
 117                 omap_prcm_events_filter_priority(pending, priority_pending);
 118
 119                 /*
 120                  * Loop on all currently pending irqs so that new irqs
 121                  * cannot starve previously pending irqs
 122                  */
 123
 124                 /* Serve priority events first */
 125                 for_each_set_bit(virtirq, priority_pending, nr_irqs)
 126                         generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
 127
 128                 /* Serve normal events next */
 129                 for_each_set_bit(virtirq, pending, nr_irqs)
 130                         generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
 131         }
 132         if (chip->irq_ack)
 133                 chip->irq_ack(&desc->irq_data);
 134         if (chip->irq_eoi)
 135                 chip->irq_eoi(&desc->irq_data);
 136         chip->irq_unmask(&desc->irq_data);
 137
 138         prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
 139 }
 140
 141 /* Public functions */
 142
 143 /**
 144  * omap_prcm_event_to_irq - given a PRCM event name, returns the
 145  * corresponding IRQ on which the handler should be registered
 146  * @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
 147  *
 148  * Returns the Linux internal IRQ ID corresponding to @name upon success,
 149  * or -ENOENT upon failure.
 150  */
 151 int omap_prcm_event_to_irq(const char *name)
 152 {
 153         int i;
 154
 155         if (!prcm_irq_setup || !name)
 156                 return -ENOENT;
 157
 158         for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
 159                 if (!strcmp(prcm_irq_setup->irqs[i].name, name))
 160                         return prcm_irq_setup->base_irq +
 161                                 prcm_irq_setup->irqs[i].offset;
 162
 163         return -ENOENT;
 164 }
 165
 166 /**
 167  * omap_prcm_irq_cleanup - reverses memory allocated and other steps
 168  * done by omap_prcm_register_chain_handler()
 169  *
 170  * No return value.
 171  */
 172 void omap_prcm_irq_cleanup(void)
 173 {
 174         int i;
 175
 176         if (!prcm_irq_setup) {
 177                 pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
 178                 return;
 179         }
 180
 181         if (prcm_irq_chips) {
 182                 for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
 183                         if (prcm_irq_chips[i])
 184                                 irq_remove_generic_chip(prcm_irq_chips[i],
 185                                         0xffffffff, 0, 0);
 186                         prcm_irq_chips[i] = NULL;
 187                 }
 188                 kfree(prcm_irq_chips);
 189                 prcm_irq_chips = NULL;
 190         }
 191
 192         kfree(prcm_irq_setup->saved_mask);
 193         prcm_irq_setup->saved_mask = NULL;
 194
 195         kfree(prcm_irq_setup->priority_mask);
 196         prcm_irq_setup->priority_mask = NULL;
 197
 198         irq_set_chained_handler(prcm_irq_setup->irq, NULL);
 199
 200         if (prcm_irq_setup->base_irq > 0)
 201                 irq_free_descs(prcm_irq_setup->base_irq,
 202                         prcm_irq_setup->nr_regs * 32);
 203         prcm_irq_setup->base_irq = 0;
 204 }
 205
 206 void omap_prcm_irq_prepare(void)
 207 {
 208         prcm_irq_setup->suspended = true;
 209 }
 210
 211 void omap_prcm_irq_complete(void)
 212 {
 213         prcm_irq_setup->suspended = false;
 214
 215         /* If we have not saved the masks, do not attempt to restore */
 216         if (!prcm_irq_setup->suspend_save_flag)
 217                 return;
 218
 219         prcm_irq_setup->suspend_save_flag = false;
 220
 221         /*
 222          * Re-enable all masked PRCM irq sources, this causes the PRCM
 223          * interrupt to fire immediately if the events were masked
 224          * previously in the chain handler
 225          */
 226         prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
 227 }
 228
 229 /**
 230  * omap_prcm_register_chain_handler - initializes the prcm chained interrupt
 231  * handler based on provided parameters
 232  * @irq_setup: hardware data about the underlying PRM/PRCM
 233  *
 234  * Set up the PRCM chained interrupt handler on the PRCM IRQ.  Sets up
 235  * one generic IRQ chip per PRM interrupt status/enable register pair.
 236  * Returns 0 upon success, -EINVAL if called twice or if invalid
 237  * arguments are passed, or -ENOMEM on any other error.
 238  */
 239 int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
 240 {
 241         int nr_regs = irq_setup->nr_regs;
 242         u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
 243         int offset, i;
 244         struct irq_chip_generic *gc;
 245         struct irq_chip_type *ct;
 246
 247         if (!irq_setup)
 248                 return -EINVAL;
 249
 250         if (prcm_irq_setup) {
 251                 pr_err("PRCM: already initialized; won't reinitialize\n");
 252                 return -EINVAL;
 253         }
 254
 255         if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
 256                 pr_err("PRCM: nr_regs too large\n");
 257                 return -EINVAL;
 258         }
 259
 260         prcm_irq_setup = irq_setup;
 261
 262         prcm_irq_chips = kzalloc(sizeof(void *) * nr_regs, GFP_KERNEL);
 263         prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL);
 264         prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs,
 265                 GFP_KERNEL);
 266
 267         if (!prcm_irq_chips || !prcm_irq_setup->saved_mask ||
 268             !prcm_irq_setup->priority_mask) {
 269                 pr_err("PRCM: kzalloc failed\n");
 270                 goto err;
 271         }
 272
 273         memset(mask, 0, sizeof(mask));
 274
 275         for (i = 0; i < irq_setup->nr_irqs; i++) {
 276                 offset = irq_setup->irqs[i].offset;
 277                 mask[offset >> 5] |= 1 << (offset & 0x1f);
 278                 if (irq_setup->irqs[i].priority)
 279                         irq_setup->priority_mask[offset >> 5] |=
 280                                 1 << (offset & 0x1f);
 281         }
 282
 283         irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);
 284
 285         irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
 286                 0);
 287
 288         if (irq_setup->base_irq < 0) {
 289                 pr_err("PRCM: failed to allocate irq descs: %d\n",
 290                         irq_setup->base_irq);
 291                 goto err;
 292         }
 293
 294         for (i = 0; i <= irq_setup->nr_regs; i++) {
 295                 gc = irq_alloc_generic_chip("PRCM", 1,
 296                         irq_setup->base_irq + i * 32, prm_base,
 297                         handle_level_irq);
 298
 299                 if (!gc) {
 300                         pr_err("PRCM: failed to allocate generic chip\n");
 301                         goto err;
 302                 }
 303                 ct = gc->chip_types;
 304                 ct->chip.irq_ack = irq_gc_ack_set_bit;
 305                 ct->chip.irq_mask = irq_gc_mask_clr_bit;
 306                 ct->chip.irq_unmask = irq_gc_mask_set_bit;
 307
 308                 ct->regs.ack = irq_setup->ack + i * 4;
 309                 ct->regs.mask = irq_setup->mask + i * 4;
 310
 311                 irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
 312                 prcm_irq_chips[i] = gc;
 313         }
 314
 315         return 0;
 316
 317 err:
 318         omap_prcm_irq_cleanup();
 319         return -ENOMEM;
 320 }