ARM: OMAP2+: sys_timer: Add suspend/resume callback api's to sys_timer
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / timer.c
1 /*
2  * linux/arch/arm/mach-omap2/timer.c
3  *
4  * OMAP2 GP timer support.
5  *
6  * Copyright (C) 2009 Nokia Corporation
7  *
8  * Update to use new clocksource/clockevent layers
9  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10  * Copyright (C) 2007 MontaVista Software, Inc.
11  *
12  * Original driver:
13  * Copyright (C) 2005 Nokia Corporation
14  * Author: Paul Mundt <paul.mundt@nokia.com>
15  *         Juha Yrjölä <juha.yrjola@nokia.com>
16  * OMAP Dual-mode timer framework support by Timo Teras
17  *
18  * Some parts based off of TI's 24xx code:
19  *
20  * Copyright (C) 2004-2009 Texas Instruments, Inc.
21  *
22  * Roughly modelled after the OMAP1 MPU timer code.
23  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
24  *
25  * This file is subject to the terms and conditions of the GNU General Public
26  * License. See the file "COPYING" in the main directory of this archive
27  * for more details.
28  */
29 #include <linux/init.h>
30 #include <linux/time.h>
31 #include <linux/interrupt.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/irq.h>
36 #include <linux/clocksource.h>
37 #include <linux/clockchips.h>
38 #include <linux/slab.h>
40 #include <asm/mach/time.h>
41 #include <plat/dmtimer.h>
42 #include <asm/localtimer.h>
43 #include <asm/sched_clock.h>
44 #include "common.h"
45 #include <plat/omap_hwmod.h>
46 #include <plat/omap_device.h>
47 #include <plat/omap-pm.h>
49 #include "powerdomain.h"
51 /* Parent clocks, eventually these will come from the clock framework */
53 #define OMAP2_MPU_SOURCE        "sys_ck"
54 #define OMAP3_MPU_SOURCE        OMAP2_MPU_SOURCE
55 #define OMAP4_MPU_SOURCE        "sys_clkin_ck"
56 #define OMAP2_32K_SOURCE        "func_32k_ck"
57 #define OMAP3_32K_SOURCE        "omap_32k_fck"
58 #define OMAP4_32K_SOURCE        "sys_32k_ck"
60 #ifdef CONFIG_OMAP_32K_TIMER
61 #define OMAP2_CLKEV_SOURCE      OMAP2_32K_SOURCE
62 #define OMAP3_CLKEV_SOURCE      OMAP3_32K_SOURCE
63 #define OMAP4_CLKEV_SOURCE      OMAP4_32K_SOURCE
64 #define OMAP3_SECURE_TIMER      12
65 #else
66 #define OMAP2_CLKEV_SOURCE      OMAP2_MPU_SOURCE
67 #define OMAP3_CLKEV_SOURCE      OMAP3_MPU_SOURCE
68 #define OMAP4_CLKEV_SOURCE      OMAP4_MPU_SOURCE
69 #define OMAP3_SECURE_TIMER      1
70 #endif
72 /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
73 #define MAX_GPTIMER_ID          12
75 static u32 sys_timer_reserved;
77 /* Clockevent code */
79 static struct omap_dm_timer clkev;
80 static struct clock_event_device clockevent_gpt;
82 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
83 {
84         struct clock_event_device *evt = &clockevent_gpt;
86         __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
88         evt->event_handler(evt);
89         return IRQ_HANDLED;
90 }
92 static struct irqaction omap2_gp_timer_irq = {
93         .name           = "gp timer",
94         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
95         .handler        = omap2_gp_timer_interrupt,
96 };
98 static int omap2_gp_timer_set_next_event(unsigned long cycles,
99                                          struct clock_event_device *evt)
101         __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
102                                                 0xffffffff - cycles, 1);
104         return 0;
107 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
108                                     struct clock_event_device *evt)
110         u32 period;
112         __omap_dm_timer_stop(&clkev, 1, clkev.rate);
114         switch (mode) {
115         case CLOCK_EVT_MODE_PERIODIC:
116                 period = clkev.rate / HZ;
117                 period -= 1;
118                 /* Looks like we need to first set the load value separately */
119                 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
120                                         0xffffffff - period, 1);
121                 __omap_dm_timer_load_start(&clkev,
122                                         OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
123                                                 0xffffffff - period, 1);
124                 break;
125         case CLOCK_EVT_MODE_ONESHOT:
126                 break;
127         case CLOCK_EVT_MODE_UNUSED:
128         case CLOCK_EVT_MODE_SHUTDOWN:
129         case CLOCK_EVT_MODE_RESUME:
130                 break;
131         }
134 static struct clock_event_device clockevent_gpt = {
135         .name           = "gp timer",
136         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
137         .shift          = 32,
138         .set_next_event = omap2_gp_timer_set_next_event,
139         .set_mode       = omap2_gp_timer_set_mode,
140 };
142 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
143                                                 int gptimer_id,
144                                                 const char *fck_source)
146         char name[10]; /* 10 = sizeof("gptXX_Xck0") */
147         struct omap_hwmod *oh;
148         size_t size;
149         int res = 0;
151         sprintf(name, "timer%d", gptimer_id);
152         omap_hwmod_setup_one(name);
153         oh = omap_hwmod_lookup(name);
154         if (!oh)
155                 return -ENODEV;
157         timer->irq = oh->mpu_irqs[0].irq;
158         timer->id = gptimer_id;
159         timer->phys_base = oh->slaves[0]->addr->pa_start;
160         size = oh->slaves[0]->addr->pa_end - timer->phys_base;
162         /* Static mapping, never released */
163         timer->io_base = ioremap(timer->phys_base, size);
164         if (!timer->io_base)
165                 return -ENXIO;
167         /* After the dmtimer is using hwmod these clocks won't be needed */
168         sprintf(name, "gpt%d_fck", gptimer_id);
169         timer->fclk = clk_get(NULL, name);
170         if (IS_ERR(timer->fclk))
171                 return -ENODEV;
173         sprintf(name, "gpt%d_ick", gptimer_id);
174         timer->iclk = clk_get(NULL, name);
175         if (IS_ERR(timer->iclk)) {
176                 clk_put(timer->fclk);
177                 return -ENODEV;
178         }
180         omap_hwmod_enable(oh);
182         sys_timer_reserved |= (1 << (gptimer_id));
184         if (gptimer_id != 12) {
185                 struct clk *src;
187                 src = clk_get(NULL, fck_source);
188                 if (IS_ERR(src)) {
189                         res = -EINVAL;
190                 } else {
191                         res = __omap_dm_timer_set_source(timer->fclk, src);
192                         if (IS_ERR_VALUE(res))
193                                 pr_warning("%s: timer%i cannot set source\n",
194                                                 __func__, gptimer_id);
195                         clk_put(src);
196                 }
197         }
198         __omap_dm_timer_init_regs(timer);
199         __omap_dm_timer_reset(timer, 1, 1);
200         timer->posted = 1;
202         timer->rate = clk_get_rate(timer->fclk);
204         timer->reserved = 1;
206         return res;
209 static void __init omap2_gp_clockevent_init(int gptimer_id,
210                                                 const char *fck_source)
212         int res;
214         res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
215         BUG_ON(res);
217         omap2_gp_timer_irq.dev_id = (void *)&clkev;
218         setup_irq(clkev.irq, &omap2_gp_timer_irq);
220         __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
222         clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
223                                      clockevent_gpt.shift);
224         clockevent_gpt.max_delta_ns =
225                 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
226         clockevent_gpt.min_delta_ns =
227                 clockevent_delta2ns(3, &clockevent_gpt);
228                 /* Timer internal resynch latency. */
230         clockevent_gpt.cpumask = cpumask_of(0);
231         clockevents_register_device(&clockevent_gpt);
233         pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
234                 gptimer_id, clkev.rate);
237 /* Clocksource code */
239 #ifdef CONFIG_OMAP_32K_TIMER
240 /*
241  * When 32k-timer is enabled, don't use GPTimer for clocksource
242  * instead, just leave default clocksource which uses the 32k
243  * sync counter.  See clocksource setup in plat-omap/counter_32k.c
244  */
246 static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
248         omap_init_clocksource_32k();
251 #else
253 static struct omap_dm_timer clksrc;
255 /*
256  * clocksource
257  */
258 static DEFINE_CLOCK_DATA(cd);
259 static cycle_t clocksource_read_cycles(struct clocksource *cs)
261         return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
264 static struct clocksource clocksource_gpt = {
265         .name           = "gp timer",
266         .rating         = 300,
267         .read           = clocksource_read_cycles,
268         .mask           = CLOCKSOURCE_MASK(32),
269         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
270 };
272 static void notrace dmtimer_update_sched_clock(void)
274         u32 cyc;
276         cyc = __omap_dm_timer_read_counter(&clksrc, 1);
278         update_sched_clock(&cd, cyc, (u32)~0);
281 unsigned long long notrace sched_clock(void)
283         u32 cyc = 0;
285         if (clksrc.reserved)
286                 cyc = __omap_dm_timer_read_counter(&clksrc, 1);
288         return cyc_to_sched_clock(&cd, cyc, (u32)~0);
291 /* Setup free-running counter for clocksource */
292 static void __init omap2_gp_clocksource_init(int gptimer_id,
293                                                 const char *fck_source)
295         int res;
297         res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
298         BUG_ON(res);
300         pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
301                 gptimer_id, clksrc.rate);
303         __omap_dm_timer_load_start(&clksrc,
304                         OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
305         init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate);
307         if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
308                 pr_err("Could not register clocksource %s\n",
309                         clocksource_gpt.name);
311 #endif
313 static void omap_dmtimer_resume(void)
315         char name[10];
316         struct omap_hwmod *oh;
318         sprintf(name, "timer%d", clkev.id);
319         oh = omap_hwmod_lookup(name);
320         if (!oh)
321                 return;
323         omap_hwmod_enable(oh);
324         __omap_dm_timer_load_start(&clkev,
325                         OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
326         __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
329 static void omap_dmtimer_suspend(void)
331         char name[10];
332         struct omap_hwmod *oh;
334         sprintf(name, "timer%d", clkev.id);
335         oh = omap_hwmod_lookup(name);
336         if (!oh)
337                 return;
339         omap_hwmod_idle(oh);
342 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,                  \
343                                 clksrc_nr, clksrc_src)                  \
344 static void __init omap##name##_timer_init(void)                        \
345 {                                                                       \
346         omap2_gp_clockevent_init((clkev_nr), clkev_src);                \
347         omap2_gp_clocksource_init((clksrc_nr), clksrc_src);             \
350 #define OMAP_SYS_TIMER(name)                                            \
351 struct sys_timer omap##name##_timer = {                                 \
352         .init           = omap##name##_timer_init,                      \
353         .suspend        = omap_dmtimer_suspend,                         \
354         .resume         = omap_dmtimer_resume,                          \
355 };
357 #ifdef CONFIG_ARCH_OMAP2
358 OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
359 OMAP_SYS_TIMER(2)
360 #endif
362 #ifdef CONFIG_ARCH_OMAP3
363 OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
364 OMAP_SYS_TIMER(3)
365 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
366                         2, OMAP3_MPU_SOURCE)
367 OMAP_SYS_TIMER(3_secure)
368 OMAP_SYS_TIMER_INIT(3_am33xx, 2, OMAP4_MPU_SOURCE, 1, OMAP4_MPU_SOURCE)
369 OMAP_SYS_TIMER(3_am33xx)
370 #endif
372 #ifdef CONFIG_ARCH_OMAP4
373 static void __init omap4_timer_init(void)
375 #ifdef CONFIG_LOCAL_TIMERS
376         twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
377         BUG_ON(!twd_base);
378 #endif
379         omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
380         omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE);
382 OMAP_SYS_TIMER(4)
383 #endif
385 /**
386  * omap2_dm_timer_set_src - change the timer input clock source
387  * @pdev:       timer platform device pointer
388  * @source:     array index of parent clock source
389  */
390 static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
392         int ret;
393         struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
394         struct clk *fclk, *parent;
395         char *parent_name = NULL;
397         fclk = clk_get(&pdev->dev, "fck");
398         if (IS_ERR_OR_NULL(fclk)) {
399                 dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n",
400                                 __func__, __LINE__);
401                 return -EINVAL;
402         }
404         switch (source) {
405         case OMAP_TIMER_SRC_SYS_CLK:
406                 parent_name = "sys_ck";
407                 break;
409         case OMAP_TIMER_SRC_32_KHZ:
410                 parent_name = "32k_ck";
411                 break;
413         case OMAP_TIMER_SRC_EXT_CLK:
414                 if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) {
415                         parent_name = "alt_ck";
416                         break;
417                 }
418                 dev_err(&pdev->dev, "%s: %d: invalid clk src.\n",
419                         __func__, __LINE__);
420                 clk_put(fclk);
421                 return -EINVAL;
422         }
424         parent = clk_get(&pdev->dev, parent_name);
425         if (IS_ERR_OR_NULL(parent)) {
426                 dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n",
427                         __func__, __LINE__, parent_name);
428                 clk_put(fclk);
429                 return -EINVAL;
430         }
432         ret = clk_set_parent(fclk, parent);
433         if (IS_ERR_VALUE(ret)) {
434                 dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n",
435                         __func__, parent_name);
436                 ret = -EINVAL;
437         }
439         clk_put(parent);
440         clk_put(fclk);
442         return ret;
445 /**
446  * omap_timer_init - build and register timer device with an
447  * associated timer hwmod
448  * @oh: timer hwmod pointer to be used to build timer device
449  * @user:       parameter that can be passed from calling hwmod API
450  *
451  * Called by omap_hwmod_for_each_by_class to register each of the timer
452  * devices present in the system. The number of timer devices is known
453  * by parsing through the hwmod database for a given class name. At the
454  * end of function call memory is allocated for timer device and it is
455  * registered to the framework ready to be proved by the driver.
456  */
457 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
459         int id;
460         int ret = 0;
461         char *name = "omap_timer";
462         struct dmtimer_platform_data *pdata;
463         struct platform_device *pdev;
464         struct omap_timer_capability_dev_attr *timer_dev_attr;
465         struct powerdomain *pwrdm;
467         pr_debug("%s: %s\n", __func__, oh->name);
469         /* on secure device, do not register secure timer */
470         timer_dev_attr = oh->dev_attr;
471         if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
472                 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
473                         return ret;
475         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
476         if (!pdata) {
477                 pr_err("%s: No memory for [%s]\n", __func__, oh->name);
478                 return -ENOMEM;
479         }
481         /*
482          * Extract the IDs from name field in hwmod database
483          * and use the same for constructing ids' for the
484          * timer devices. In a way, we are avoiding usage of
485          * static variable witin the function to do the same.
486          * CAUTION: We have to be careful and make sure the
487          * name in hwmod database does not change in which case
488          * we might either make corresponding change here or
489          * switch back static variable mechanism.
490          */
491         sscanf(oh->name, "timer%2d", &id);
493         pdata->set_timer_src = omap2_dm_timer_set_src;
494         pdata->timer_ip_version = oh->class->rev;
496         /* Mark clocksource and clockevent timers as reserved */
497         if ((sys_timer_reserved & (0x1 << id)))
498                 pdata->reserved = 1;
500         pwrdm = omap_hwmod_get_pwrdm(oh);
501         pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
502 #ifdef CONFIG_PM
503         pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
504 #endif
505         pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
506                                  NULL, 0, 0);
508         if (IS_ERR(pdev)) {
509                 pr_err("%s: Can't build omap_device for %s: %s.\n",
510                         __func__, name, oh->name);
511                 ret = -EINVAL;
512         }
514         kfree(pdata);
516         return ret;
519 /**
520  * omap2_dm_timer_init - top level regular device initialization
521  *
522  * Uses dedicated hwmod api to parse through hwmod database for
523  * given class name and then build and register the timer device.
524  */
525 static int __init omap2_dm_timer_init(void)
527         int ret;
529         ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
530         if (unlikely(ret)) {
531                 pr_err("%s: device registration failed.\n", __func__);
532                 return -EINVAL;
533         }
535         return 0;
537 arch_initcall(omap2_dm_timer_init);