arm:omap:am33xx: Register HSMMC Platform on AM335x EVM
[sitara-epos/sitara-epos-kernel.git] / arch / arm / plat-omap / include / plat / dma-33xx.h
1 /*
2  * AM33XX SDMA channel definitions
3  *
4  * This file is automatically generated from the AM33XX hardware databases.
5  *
6  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation version 2.
11  *
12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13  * kind, whether express or implied; without even the implied warranty
14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  */
18 #ifndef __ARCH_ARM_MACH_OMAP2_AM33XX_DMA_H
19 #define __ARCH_ARM_MACH_OMAP2_AM33XX_DMA_H
22 #define AM33XX_DMA_ICSS0_7                              0
23 #define AM33XX_DMA_ICSS0_6                              1
24 #define AM33XX_DMA_MMCHS1_W                             2
25 #define AM33XX_DMA_MMCHS1_R                             3
26 #define AM33XX_DMA_AESEIP36T0_CTXIN                     4
27 #define AM33XX_DMA_AESEIP36T0_DIN                       5
28 #define AM33XX_DMA_AESEIP36T0_DOUT                      6
29 #define AM33XX_DMA_AESEIP36T0_CTXOUT                    7
30 #define AM33XX_DMA_MCASP0_X                             8
31 #define AM33XX_DMA_MCASP0_R                             9
32 #define AM33XX_DMA_MCASP1_X                             10
33 #define AM33XX_DMA_MCASP1_R                             11
34 #define AM33XX_DMA_MCASP2_X                             12
35 #define AM33XX_DMA_MCASP2_R                             13
36 #define AM33XX_DMA_PWMSS0_EPWM                          14
37 #define AM33XX_DMA_PWMSS1_EPWM                          15
38 #define AM33XX_DMA_SPIOCP0_CH0W                         16
39 #define AM33XX_DMA_SPIOCP0_CH0R                         17
40 #define AM33XX_DMA_SPIOCP0_CH1W                         18
41 #define AM33XX_DMA_SPIOCP0_CH1R                         19
42 #define AM33XX_DMA_SPIOCP3_CH1W                         20
43 #define AM33XX_DMA_SPIOCP3_CH1R                         21
44 #define AM33XX_DMA_GPIO                                 22
45 #define AM33XX_DMA_GPIO1                                23
46 #define AM33XX_DMA_MMCHS0_W                             24
47 #define AM33XX_DMA_MMCHS0_R                             25
48 #define AM33XX_DMA_UART0_0                              26
49 #define AM33XX_DMA_UART0_1                              27
50 #define AM33XX_DMA_UART1_0                              28
51 #define AM33XX_DMA_UART1_1                              29
52 #define AM33XX_DMA_UART2_0                              30
53 #define AM33XX_DMA_UART2_1                              31
54 #define AM33XX_DMA_DESEIP16T0_IN                        32
55 #define AM33XX_DMA_DESEIP16T0                           33
56 #define AM33XX_DMA_DESEIP16T0_OUT                       34
57 #define AM33XX_DMA_SHAEIP57T0_CTXIN                     35
58 #define AM33XX_DMA_SHAEIP57T0_DIN                       36
59 #define AM33XX_DMA_SHAEIP57T0_CTXOUT                    37
60 #define AM33XX_DMA_PWMSS0_ECAP                          38
61 #define AM33XX_DMA_PWMSS1_ECAP                          39
62 #define AM33XX_DMA_DCAN_1                               40
63 #define AM33XX_DMA_DCAN_2                               41
64 #define AM33XX_DMA_SPIOCP1_CH0W                         42
65 #define AM33XX_DMA_SPIOCP1_CH0R                         43
66 #define AM33XX_DMA_SPIOCP1_CH1W                         44
67 #define AM33XX_DMA_SPIOCP1_CH1R                         45
68 #define AM33XX_DMA_PWMSS0_EQEP                          46
69 #define AM33XX_DMA_DCAN_3                               47
70 #define AM33XX_DMA_TIMER_4                              48
71 #define AM33XX_DMA_TIMER_5                              49
72 #define AM33XX_DMA_TIMER_6                              50
73 #define AM33XX_DMA_TIMER_7                              51
74 #define AM33XX_DMA_GPM                                  52
75 #define AM33XX_DMA_ADC0                                 53
76 #define AM33XX_DMA_PWMSS1_EQEP                          56
77 #define AM33XX_DMA_ADC1                                 57
78 #define AM33XX_DMA_MSHSI2COCP0_TX                       58
79 #define AM33XX_DMA_MSHSI2COCP0_RX                       59
80 #define AM33XX_DMA_MSHSI2COCP1_TX                       60
81 #define AM33XX_DMA_MSHSI2COCP1_RX                       61
82 #define AM33XX_DMA_PWMSS2_ECAP                          62
83 #define AM33XX_DMA_PWMSS2_EPW                           63
84 #define AM33XX_DMA_MMCHS2_W                             64      /* xBar */
85 #define AM33XX_DMA_MMCHS2_R                             65      /* xBar */
87 #endif