bfe33ee795e64a74dab14d95e23f0d0655821f76
[sitara-epos/sitara-epos-kernel.git] / arch / arm / plat-omap / include / plat / sram.h
1 /*
2  * arch/arm/plat-omap/include/mach/sram.h
3  *
4  * Interface for functions that need to be run in internal SRAM
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
11 #ifndef __ARCH_ARM_OMAP_SRAM_H
12 #define __ARCH_ARM_OMAP_SRAM_H
14 #ifndef __ASSEMBLY__
15 #include <linux/slab.h>
16 #include <linux/genalloc.h>
17 #include <asm/fncpy.h>
19 extern struct gen_pool *omap_gen_pool;
21 /*
22  * Note that fncpy requires the SRAM address to be aligned to an 8-byte
23  * boundary, so the min_alloc_order for the pool is set appropriately.
24  */
25 #define omap_sram_push(funcp, size) ({                                  \
26         typeof(&(funcp)) _res;                                          \
27         size_t _sz = size;                                              \
28         void *_sram = (void *) gen_pool_alloc(omap_gen_pool, _sz);      \
29         _res = (_sram ? fncpy(_sram, &(funcp), _sz) : NULL);            \
30         if (!_res)                                                      \
31                 pr_err("Not enough space in SRAM\n");                   \
32         _res;                                                           \
33 })
35 extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
37 extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
38                                 u32 base_cs, u32 force_unlock);
39 extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
40                                       u32 mem_type);
41 extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
43 extern u32 omap3_configure_core_dpll(
44                         u32 m2, u32 unlock_dll, u32 f, u32 inc,
45                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
46                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
47                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
48                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
49 extern void omap3_sram_restore_context(void);
51 /* Do not use these */
52 extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
53 extern unsigned long omap1_sram_reprogram_clock_sz;
55 extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
56 extern unsigned long omap24xx_sram_reprogram_clock_sz;
58 extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
59                                                 u32 base_cs, u32 force_unlock);
60 extern unsigned long omap242x_sram_ddr_init_sz;
62 extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
63                                                 int bypass);
64 extern unsigned long omap242x_sram_set_prcm_sz;
66 extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
67                                                 u32 mem_type);
68 extern unsigned long omap242x_sram_reprogram_sdrc_sz;
71 extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
72                                                 u32 base_cs, u32 force_unlock);
73 extern unsigned long omap243x_sram_ddr_init_sz;
75 extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
76                                                 int bypass);
77 extern unsigned long omap243x_sram_set_prcm_sz;
79 extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
80                                                 u32 mem_type);
81 extern unsigned long omap243x_sram_reprogram_sdrc_sz;
83 extern u32 omap3_sram_configure_core_dpll(
84                         u32 m2, u32 unlock_dll, u32 f, u32 inc,
85                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
86                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
87                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
88                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
89 extern unsigned long omap3_sram_configure_core_dpll_sz;
91 #ifdef CONFIG_PM
92 extern void omap_push_sram_idle(void);
93 #else
94 static inline void omap_push_sram_idle(void) {}
95 #endif /* CONFIG_PM */
97 #endif /* __ASSEMBLY__ */
99 /*
100  * OMAP2+: define the SRAM PA addresses.
101  * Used by the SRAM management code and the idle sleep code.
102  */
103 #define OMAP2_SRAM_PA           0x40200000
104 #define OMAP3_SRAM_PA           0x40200000
105 #ifdef CONFIG_OMAP4_ERRATA_I688
106 #define OMAP4_SRAM_PA           0x40304000
107 #define OMAP4_SRAM_VA           0xfe404000
108 #else
109 #define OMAP4_SRAM_PA           0x40300000
110 #endif
111 #endif