343c4f9e2103c57002f8db9394245ede23b4604b
[sitara-epos/sitara-epos-kernel.git] / arch / arm / plat-omap / sram.c
1 /*
2  * linux/arch/arm/plat-omap/sram.c
3  *
4  * OMAP SRAM detection and management
5  *
6  * Copyright (C) 2005 Nokia Corporation
7  * Written by Tony Lindgren <tony@atomide.com>
8  *
9  * Copyright (C) 2009 Texas Instruments
10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License version 2 as
14  * published by the Free Software Foundation.
15  */
16 #undef DEBUG
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/io.h>
23 #include <asm/tlb.h>
24 #include <asm/cacheflush.h>
26 #include <asm/mach/map.h>
28 #include <plat/sram.h>
29 #include <plat/board.h>
30 #include <plat/cpu.h>
32 #include "sram.h"
34 /* XXX These "sideways" includes are a sign that something is wrong */
35 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
36 # include "../mach-omap2/prm2xxx_3xxx.h"
37 # include "../mach-omap2/sdrc.h"
38 #endif
40 #define OMAP1_SRAM_PA           0x20000000
41 #define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
42 #define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
43 #ifdef CONFIG_OMAP4_ERRATA_I688
44 #define OMAP4_SRAM_PUB_PA       OMAP4_SRAM_PA
45 #else
46 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
47 #endif
49 #if defined(CONFIG_ARCH_OMAP2PLUS)
50 #define SRAM_BOOTLOADER_SZ      0x00
51 #else
52 #define SRAM_BOOTLOADER_SZ      0x80
53 #endif
55 #define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
56 #define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
57 #define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
59 #define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
60 #define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
61 #define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
62 #define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
63 #define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
65 #define GP_DEVICE               0x300
67 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
69 static unsigned long omap_sram_start;
70 static void __iomem *omap_sram_base;
71 static unsigned long omap_sram_size;
73 /*
74  * Depending on the target RAMFS firewall setup, the public usable amount of
75  * SRAM varies.  The default accessible size for all device types is 2k. A GP
76  * device allows ARM11 but not other initiators for full size. This
77  * functionality seems ok until some nice security API happens.
78  */
79 static int is_sram_locked(void)
80 {
81         if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
82                 /* RAMFW: R/W access to all initiators for all qualifier sets */
83                 if (cpu_is_omap242x()) {
84                         __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
85                         __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
86                         __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
87                 }
88                 if (cpu_is_omap34xx()) {
89                         __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
90                         __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
91                         __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
92                         __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
93                         __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
94                 }
95                 return 0;
96         } else
97                 return 1; /* assume locked with no PPA or security driver */
98 }
100 struct gen_pool *omap_gen_pool;
101 EXPORT_SYMBOL_GPL(omap_gen_pool);
103 /*
104  * The amount of SRAM depends on the core type.
105  * Note that we cannot try to test for SRAM here because writes
106  * to secure SRAM will hang the system. Also the SRAM is not
107  * yet mapped at this point.
108  */
109 static void __init omap_detect_sram(void)
111         if (cpu_class_is_omap2()) {
112                 if (is_sram_locked()) {
113                         if (cpu_is_omap34xx()) {
114                                 omap_sram_start = OMAP3_SRAM_PUB_PA;
115                                 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
116                                     (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
117                                         omap_sram_size = 0x7000; /* 28K */
118                                 } else {
119                                         omap_sram_size = 0x8000; /* 32K */
120                                 }
121                         } else if (cpu_is_omap44xx()) {
122                                 omap_sram_start = OMAP4_SRAM_PUB_PA;
123                                 omap_sram_size = 0xa000; /* 40K */
124                         } else {
125                                 omap_sram_start = OMAP2_SRAM_PUB_PA;
126                                 omap_sram_size = 0x800; /* 2K */
127                         }
128                 } else {
129                         if (cpu_is_omap34xx()) {
130                                 omap_sram_start = OMAP3_SRAM_PA;
131                                 omap_sram_size = 0x10000; /* 64K */
132                         } else if (cpu_is_omap44xx()) {
133                                 omap_sram_start = OMAP4_SRAM_PA;
134                                 omap_sram_size = 0xe000; /* 56K */
135                         } else {
136                                 omap_sram_start = OMAP2_SRAM_PA;
137                                 if (cpu_is_omap242x())
138                                         omap_sram_size = 0xa0000; /* 640K */
139                                 else if (cpu_is_omap243x())
140                                         omap_sram_size = 0x10000; /* 64K */
141                         }
142                 }
143         } else {
144                 omap_sram_start = OMAP1_SRAM_PA;
146                 if (cpu_is_omap7xx())
147                         omap_sram_size = 0x32000;       /* 200K */
148                 else if (cpu_is_omap15xx())
149                         omap_sram_size = 0x30000;       /* 192K */
150                 else if (cpu_is_omap1610() || cpu_is_omap1611() ||
151                                 cpu_is_omap1621() || cpu_is_omap1710())
152                         omap_sram_size = 0x4000;        /* 16K */
153                 else {
154                         pr_err("Could not detect SRAM size\n");
155                         omap_sram_size = 0x4000;
156                 }
157         }
158         {
159                 /* The first SRAM_BOOTLOADER_SZ of SRAM are reserved */
160                 void *base = (void *)omap_sram_base + SRAM_BOOTLOADER_SZ;
161                 phys_addr_t phys = omap_sram_start + SRAM_BOOTLOADER_SZ;
162                 size_t len = omap_sram_size - SRAM_BOOTLOADER_SZ;
164                 omap_gen_pool = gen_pool_create(ilog2(FNCPY_ALIGN), -1);
165                 if (omap_gen_pool)
166                         WARN_ON(gen_pool_add_virt(omap_gen_pool,
167                                         (unsigned long)base, phys, len, -1));
168                 WARN_ON(!omap_gen_pool);
169         }
172 /*
173  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
174  */
175 static void __init omap_map_sram(void)
177         int cached = 1;
179         if (omap_sram_size == 0)
180                 return;
182 #ifdef CONFIG_OMAP4_ERRATA_I688
183                 omap_sram_start += PAGE_SIZE;
184                 omap_sram_size -= SZ_16K;
185 #endif
186         if (cpu_is_omap34xx()) {
187                 /*
188                  * SRAM must be marked as non-cached on OMAP3 since the
189                  * CORE DPLL M2 divider change code (in SRAM) runs with the
190                  * SDRAM controller disabled, and if it is marked cached,
191                  * the ARM may attempt to write cache lines back to SDRAM
192                  * which will cause the system to hang.
193                  */
194                 cached = 0;
195         }
197         omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
198         omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size,
199                                                 cached);
200         if (!omap_sram_base) {
201                 pr_err("SRAM: Could not map\n");
202                 return;
203         }
205         /*
206          * Looks like we need to preserve some bootloader code at the
207          * beginning of SRAM for jumping to flash for reboot to work...
208          */
209         memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
210                omap_sram_size - SRAM_BOOTLOADER_SZ);
213 #ifdef CONFIG_ARCH_OMAP1
215 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
217 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
219         BUG_ON(!_omap_sram_reprogram_clock);
220         /* On 730, bit 13 must always be 1 */
221         if (cpu_is_omap7xx())
222                 ckctl |= 0x2000;
223         _omap_sram_reprogram_clock(dpllctl, ckctl);
226 static int __init omap1_sram_init(void)
228         _omap_sram_reprogram_clock =
229                         omap_sram_push(omap1_sram_reprogram_clock,
230                                         omap1_sram_reprogram_clock_sz);
232         return 0;
235 #else
236 #define omap1_sram_init()       do {} while (0)
237 #endif
239 #if defined(CONFIG_ARCH_OMAP2)
241 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
242                               u32 base_cs, u32 force_unlock);
244 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
245                    u32 base_cs, u32 force_unlock)
247         BUG_ON(!_omap2_sram_ddr_init);
248         _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
249                              base_cs, force_unlock);
252 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
253                                           u32 mem_type);
255 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
257         BUG_ON(!_omap2_sram_reprogram_sdrc);
258         _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
261 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
263 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
265         BUG_ON(!_omap2_set_prcm);
266         return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
268 #endif
270 #ifdef CONFIG_SOC_OMAP2420
271 static int __init omap242x_sram_init(void)
273         _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
274                                         omap242x_sram_ddr_init_sz);
276         _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
277                                             omap242x_sram_reprogram_sdrc_sz);
279         _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
280                                          omap242x_sram_set_prcm_sz);
282         return 0;
284 #else
285 static inline int omap242x_sram_init(void)
287         return 0;
289 #endif
291 #ifdef CONFIG_SOC_OMAP2430
292 static int __init omap243x_sram_init(void)
294         _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
295                                         omap243x_sram_ddr_init_sz);
297         _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
298                                             omap243x_sram_reprogram_sdrc_sz);
300         _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
301                                          omap243x_sram_set_prcm_sz);
303         return 0;
305 #else
306 static inline int omap243x_sram_init(void)
308         return 0;
310 #endif
312 #ifdef CONFIG_ARCH_OMAP3
314 static u32 (*_omap3_sram_configure_core_dpll)(
315                         u32 m2, u32 unlock_dll, u32 f, u32 inc,
316                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
317                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
318                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
319                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
321 u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
322                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
323                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
324                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
325                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
327         BUG_ON(!_omap3_sram_configure_core_dpll);
328         return _omap3_sram_configure_core_dpll(
329                         m2, unlock_dll, f, inc,
330                         sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
331                         sdrc_actim_ctrl_b_0, sdrc_mr_0,
332                         sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
333                         sdrc_actim_ctrl_b_1, sdrc_mr_1);
336 #ifdef CONFIG_PM
337 void omap3_sram_restore_context(void)
339         _omap3_sram_configure_core_dpll =
340                 omap_sram_push(omap3_sram_configure_core_dpll,
341                                omap3_sram_configure_core_dpll_sz);
342         omap_push_sram_idle();
344 #endif /* CONFIG_PM */
346 #endif /* CONFIG_ARCH_OMAP3 */
348 static inline int omap34xx_sram_init(void)
350 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
351         omap3_sram_restore_context();
352 #endif
353         return 0;
356 int __init omap_sram_init(void)
358         if (cpu_is_am33xx())
359                 return 0;
361         omap_detect_sram();
362         omap_map_sram();
364         if (!(cpu_class_is_omap2()))
365                 omap1_sram_init();
366         else if (cpu_is_omap242x())
367                 omap242x_sram_init();
368         else if (cpu_is_omap2430())
369                 omap243x_sram_init();
370         else if (cpu_is_omap34xx())
371                 omap34xx_sram_init();
373         return 0;