arch/arm/plat-omap/sram.c

   1 /*
   2  * linux/arch/arm/plat-omap/sram.c
   3  *
   4  * OMAP SRAM detection and management
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * Copyright (C) 2009 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16 #undef DEBUG
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/tlb.h>
  24 #include <asm/cacheflush.h>
  25
  26 #include <asm/mach/map.h>
  27
  28 #include <plat/sram.h>
  29 #include <plat/board.h>
  30 #include <plat/cpu.h>
  31
  32 #include "sram.h"
  33
  34 /* XXX These "sideways" includes are a sign that something is wrong */
  35 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  36 # include "../mach-omap2/prm2xxx_3xxx.h"
  37 # include "../mach-omap2/sdrc.h"
  38 #endif
  39
  40 #define OMAP1_SRAM_PA           0x20000000
  41 #define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
  42 #define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
  43 #ifdef CONFIG_OMAP4_ERRATA_I688
  44 #define OMAP4_SRAM_PUB_PA       OMAP4_SRAM_PA
  45 #else
  46 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
  47 #endif
  48
  49 #if defined(CONFIG_ARCH_OMAP2PLUS)
  50 #define SRAM_BOOTLOADER_SZ      0x00
  51 #else
  52 #define SRAM_BOOTLOADER_SZ      0x80
  53 #endif
  54
  55 #define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
  56 #define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
  57 #define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
  58
  59 #define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
  60 #define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
  61 #define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
  62 #define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
  63 #define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
  64
  65 #define GP_DEVICE               0x300
  66
  67 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
  68
  69 static unsigned long omap_sram_start;
  70 static void __iomem *omap_sram_base;
  71 static unsigned long omap_sram_size;
  72 static void __iomem *omap_sram_ceil;
  73
  74 /*
  75  * Depending on the target RAMFS firewall setup, the public usable amount of
  76  * SRAM varies.  The default accessible size for all device types is 2k. A GP
  77  * device allows ARM11 but not other initiators for full size. This
  78  * functionality seems ok until some nice security API happens.
  79  */
  80 static int is_sram_locked(void)
  81 {
  82         if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
  83                 /* RAMFW: R/W access to all initiators for all qualifier sets */
  84                 if (cpu_is_omap242x()) {
  85                         __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
  86                         __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
  87                         __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
  88                 }
  89                 if (cpu_is_omap34xx()) {
  90                         __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
  91                         __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
  92                         __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
  93                         __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
  94                         __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
  95                 }
  96                 return 0;
  97         } else
  98                 return 1; /* assume locked with no PPA or security driver */
  99 }
 100
 101 /*
 102  * The amount of SRAM depends on the core type.
 103  * Note that we cannot try to test for SRAM here because writes
 104  * to secure SRAM will hang the system. Also the SRAM is not
 105  * yet mapped at this point.
 106  */
 107 static void __init omap_detect_sram(void)
 108 {
 109         if (cpu_class_is_omap2()) {
 110                 if (is_sram_locked()) {
 111                         if (cpu_is_omap34xx()) {
 112                                 omap_sram_start = OMAP3_SRAM_PUB_PA;
 113                                 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
 114                                     (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
 115                                         omap_sram_size = 0x7000; /* 28K */
 116                                 } else {
 117                                         omap_sram_size = 0x8000; /* 32K */
 118                                 }
 119                         } else if (cpu_is_omap44xx()) {
 120                                 omap_sram_start = OMAP4_SRAM_PUB_PA;
 121                                 omap_sram_size = 0xa000; /* 40K */
 122                         } else {
 123                                 omap_sram_start = OMAP2_SRAM_PUB_PA;
 124                                 omap_sram_size = 0x800; /* 2K */
 125                         }
 126                 } else {
 127                         if (cpu_is_omap34xx()) {
 128                                 omap_sram_start = OMAP3_SRAM_PA;
 129                                 omap_sram_size = 0x10000; /* 64K */
 130                         } else if (cpu_is_omap44xx()) {
 131                                 omap_sram_start = OMAP4_SRAM_PA;
 132                                 omap_sram_size = 0xe000; /* 56K */
 133                         } else {
 134                                 omap_sram_start = OMAP2_SRAM_PA;
 135                                 if (cpu_is_omap242x())
 136                                         omap_sram_size = 0xa0000; /* 640K */
 137                                 else if (cpu_is_omap243x())
 138                                         omap_sram_size = 0x10000; /* 64K */
 139                         }
 140                 }
 141         } else {
 142                 omap_sram_start = OMAP1_SRAM_PA;
 143
 144                 if (cpu_is_omap7xx())
 145                         omap_sram_size = 0x32000;       /* 200K */
 146                 else if (cpu_is_omap15xx())
 147                         omap_sram_size = 0x30000;       /* 192K */
 148                 else if (cpu_is_omap1610() || cpu_is_omap1611() ||
 149                                 cpu_is_omap1621() || cpu_is_omap1710())
 150                         omap_sram_size = 0x4000;        /* 16K */
 151                 else {
 152                         pr_err("Could not detect SRAM size\n");
 153                         omap_sram_size = 0x4000;
 154                 }
 155         }
 156 }
 157
 158 /*
 159  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
 160  */
 161 static void __init omap_map_sram(void)
 162 {
 163         int cached = 1;
 164
 165         if (omap_sram_size == 0)
 166                 return;
 167
 168 #ifdef CONFIG_OMAP4_ERRATA_I688
 169                 omap_sram_start += PAGE_SIZE;
 170                 omap_sram_size -= SZ_16K;
 171 #endif
 172         if (cpu_is_omap34xx()) {
 173                 /*
 174                  * SRAM must be marked as non-cached on OMAP3 since the
 175                  * CORE DPLL M2 divider change code (in SRAM) runs with the
 176                  * SDRAM controller disabled, and if it is marked cached,
 177                  * the ARM may attempt to write cache lines back to SDRAM
 178                  * which will cause the system to hang.
 179                  */
 180                 cached = 0;
 181         }
 182
 183         omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
 184         omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size,
 185                                                 cached);
 186         if (!omap_sram_base) {
 187                 pr_err("SRAM: Could not map\n");
 188                 return;
 189         }
 190
 191         omap_sram_ceil = omap_sram_base + omap_sram_size;
 192
 193         /*
 194          * Looks like we need to preserve some bootloader code at the
 195          * beginning of SRAM for jumping to flash for reboot to work...
 196          */
 197         memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
 198                omap_sram_size - SRAM_BOOTLOADER_SZ);
 199 }
 200
 201 /*
 202  * Memory allocator for SRAM: calculates the new ceiling address
 203  * for pushing a function using the fncpy API.
 204  *
 205  * Note that fncpy requires the returned address to be aligned
 206  * to an 8-byte boundary.
 207  */
 208 void *omap_sram_push_address(unsigned long size)
 209 {
 210         unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;
 211
 212         available = omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ);
 213
 214         if (size > available) {
 215                 pr_err("Not enough space in SRAM\n");
 216                 return NULL;
 217         }
 218
 219         new_ceil -= size;
 220         new_ceil = ROUND_DOWN(new_ceil, FNCPY_ALIGN);
 221         omap_sram_ceil = IOMEM(new_ceil);
 222
 223         return (void *)omap_sram_ceil;
 224 }
 225
 226 #ifdef CONFIG_ARCH_OMAP1
 227
 228 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
 229
 230 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
 231 {
 232         BUG_ON(!_omap_sram_reprogram_clock);
 233         /* On 730, bit 13 must always be 1 */
 234         if (cpu_is_omap7xx())
 235                 ckctl |= 0x2000;
 236         _omap_sram_reprogram_clock(dpllctl, ckctl);
 237 }
 238
 239 static int __init omap1_sram_init(void)
 240 {
 241         _omap_sram_reprogram_clock =
 242                         omap_sram_push(omap1_sram_reprogram_clock,
 243                                         omap1_sram_reprogram_clock_sz);
 244
 245         return 0;
 246 }
 247
 248 #else
 249 #define omap1_sram_init()       do {} while (0)
 250 #endif
 251
 252 #if defined(CONFIG_ARCH_OMAP2)
 253
 254 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 255                               u32 base_cs, u32 force_unlock);
 256
 257 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 258                    u32 base_cs, u32 force_unlock)
 259 {
 260         BUG_ON(!_omap2_sram_ddr_init);
 261         _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
 262                              base_cs, force_unlock);
 263 }
 264
 265 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
 266                                           u32 mem_type);
 267
 268 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
 269 {
 270         BUG_ON(!_omap2_sram_reprogram_sdrc);
 271         _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
 272 }
 273
 274 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 275
 276 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 277 {
 278         BUG_ON(!_omap2_set_prcm);
 279         return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
 280 }
 281 #endif
 282
 283 #ifdef CONFIG_SOC_OMAP2420
 284 static int __init omap242x_sram_init(void)
 285 {
 286         _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
 287                                         omap242x_sram_ddr_init_sz);
 288
 289         _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
 290                                             omap242x_sram_reprogram_sdrc_sz);
 291
 292         _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
 293                                          omap242x_sram_set_prcm_sz);
 294
 295         return 0;
 296 }
 297 #else
 298 static inline int omap242x_sram_init(void)
 299 {
 300         return 0;
 301 }
 302 #endif
 303
 304 #ifdef CONFIG_SOC_OMAP2430
 305 static int __init omap243x_sram_init(void)
 306 {
 307         _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
 308                                         omap243x_sram_ddr_init_sz);
 309
 310         _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
 311                                             omap243x_sram_reprogram_sdrc_sz);
 312
 313         _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
 314                                          omap243x_sram_set_prcm_sz);
 315
 316         return 0;
 317 }
 318 #else
 319 static inline int omap243x_sram_init(void)
 320 {
 321         return 0;
 322 }
 323 #endif
 324
 325 #ifdef CONFIG_ARCH_OMAP3
 326
 327 static u32 (*_omap3_sram_configure_core_dpll)(
 328                         u32 m2, u32 unlock_dll, u32 f, u32 inc,
 329                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 330                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 331                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 332                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 333
 334 u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
 335                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 336                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 337                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 338                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
 339 {
 340         BUG_ON(!_omap3_sram_configure_core_dpll);
 341         return _omap3_sram_configure_core_dpll(
 342                         m2, unlock_dll, f, inc,
 343                         sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
 344                         sdrc_actim_ctrl_b_0, sdrc_mr_0,
 345                         sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
 346                         sdrc_actim_ctrl_b_1, sdrc_mr_1);
 347 }
 348
 349 #ifdef CONFIG_PM
 350 void omap3_sram_restore_context(void)
 351 {
 352         omap_sram_ceil = omap_sram_base + omap_sram_size;
 353
 354         _omap3_sram_configure_core_dpll =
 355                 omap_sram_push(omap3_sram_configure_core_dpll,
 356                                omap3_sram_configure_core_dpll_sz);
 357         omap_push_sram_idle();
 358 }
 359 #endif /* CONFIG_PM */
 360
 361 #endif /* CONFIG_ARCH_OMAP3 */
 362
 363 static inline int omap34xx_sram_init(void)
 364 {
 365 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 366         omap3_sram_restore_context();
 367 #endif
 368         return 0;
 369 }
 370
 371 int __init omap_sram_init(void)
 372 {
 373         if (cpu_is_am33xx())
 374                 return 0;
 375
 376         omap_detect_sram();
 377         omap_map_sram();
 378
 379         if (!(cpu_class_is_omap2()))
 380                 omap1_sram_init();
 381         else if (cpu_is_omap242x())
 382                 omap242x_sram_init();
 383         else if (cpu_is_omap2430())
 384                 omap243x_sram_init();
 385         else if (cpu_is_omap34xx())
 386                 omap34xx_sram_init();
 387
 388         return 0;
 389 }