1 /*
2 * drivers/crypto/omap4.h
3 *
4 * Copyright © 2011 Texas Instruments Incorporated
5 * Author: Greg Turner
6 *
7 * Adapted from Netra/Centaurus crypto driver
8 * Copyright © 2011 Texas Instruments Incorporated
9 * Author: Herman Schuurman
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25 #ifndef __DRIVERS_CRYPTO_AM33X_H
26 #define __DRIVERS_CRYPTO_AM33X_H
28 /* ==================================================================== */
29 /** Crypto subsystem module layout
30 */
31 /* ==================================================================== */
33 #define AM33X_AES_CLKCTRL (AM33XX_PRCM_BASE + 0x00000094)
34 #define AM33X_SHA_CLKCTRL (AM33XX_PRCM_BASE + 0x000000A0)
36 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
37 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
39 /* ==================================================================== */
40 /** AES module layout
41 */
42 /* ==================================================================== */
44 #define AES_REG_KEY2(x) (0x1C - ((x ^ 0x01) * 0x04))
45 #define AES_REG_KEY1(x) (0x3C - ((x ^ 0x01) * 0x04))
46 #define AES_REG_IV(x) (0x40 + ((x) * 0x04))
48 #define AES_REG_CTRL 0x50
49 #define AES_REG_CTRL_CTX_RDY (1 << 31)
50 #define AES_REG_CTRL_SAVE_CTX_RDY (1 << 30)
51 #define AES_REG_CTRL_SAVE_CTX (1 << 29)
52 #define AES_REG_CTRL_CCM_M_MASK (7 << 22)
53 #define AES_REG_CTRL_CCM_M_SHFT 22
54 #define AES_REG_CTRL_CCM_L_MASK (7 << 19)
55 #define AES_REG_CTRL_CCM_L_SHFT 19
56 #define AES_REG_CTRL_CCM (1 << 18)
57 #define AES_REG_CTRL_GCM (3 << 16)
58 #define AES_REG_CTRL_CBCMAC (1 << 15)
59 #define AES_REG_CTRL_F9 (1 << 14)
60 #define AES_REG_CTRL_F8 (1 << 13)
61 #define AES_REG_CTRL_XTS_MASK (3 << 11)
62 #define AES_REG_CTRL_XTS_01 (1 << 11)
63 #define AES_REG_CTRL_XTS_10 (2 << 11)
64 #define AES_REG_CTRL_XTS_11 (3 << 11)
65 #define AES_REG_CTRL_CFB (1 << 10)
66 #define AES_REG_CTRL_ICM (1 << 9)
67 #define AES_REG_CTRL_CTR_WIDTH_MASK (3 << 7)
68 #define AES_REG_CTRL_CTR_WIDTH_32 (0 << 7)
69 #define AES_REG_CTRL_CTR_WIDTH_64 (1 << 7)
70 #define AES_REG_CTRL_CTR_WIDTH_96 (2 << 7)
71 #define AES_REG_CTRL_CTR_WIDTH_128 (3 << 7)
72 #define AES_REG_CTRL_CTR (1 << 6)
73 #define AES_REG_CTRL_CBC (1 << 5)
74 #define AES_REG_CTRL_KEY_SIZE_MASK (3 << 3)
75 #define AES_REG_CTRL_KEY_SIZE_128 (1 << 3)
76 #define AES_REG_CTRL_KEY_SIZE_192 (2 << 3)
77 #define AES_REG_CTRL_KEY_SIZE_256 (3 << 3)
78 #define AES_REG_CTRL_DIRECTION (1 << 2)
79 #define AES_REG_CTRL_INPUT_RDY (1 << 1)
80 #define AES_REG_CTRL_OUTPUT_RDY (1 << 0)
82 #define AES_REG_LENGTH_N(x) (0x54 + ((x) * 0x04))
83 #define AES_REG_AUTH_LENGTH 0x5C
84 #define AES_REG_DATA 0x60
85 #define AES_REG_DATA_N(x) (0x60 + ((x) * 0x04))
86 #define AES_REG_TAG 0x70
87 #define AES_REG_TAG_N(x) (0x70 + ((x) * 0x04))
89 #define AES_REG_REV 0x80
90 #define AES_REG_REV_SCHEME_MASK (3 << 30)
91 #define AES_REG_REV_FUNC_MASK (0xFFF << 16)
92 #define AES_REG_REV_R_RTL_MASK (0x1F << 11)
93 #define AES_REG_REV_X_MAJOR_MASK (7 << 8)
94 #define AES_REG_REV_CUSTOM_MASK (3 << 6)
95 #define AES_REG_REV_Y_MINOR_MASK (0x3F << 0)
97 #define AES_REG_SYSCFG 0x84
98 #define AES_REG_SYSCFG_K3 (1 << 12)
99 #define AES_REG_SYSCFG_KEY_ENC (1 << 11)
100 #define AES_REG_SYSCFG_KEK_MODE (1 << 10)
101 #define AES_REG_SYSCFG_MAP_CTX_OUT (1 << 9)
102 #define AES_REG_SYSCFG_DREQ_MASK (15 << 5)
103 #define AES_REG_SYSCFG_DREQ_CTX_OUT_EN (1 << 8)
104 #define AES_REG_SYSCFG_DREQ_CTX_IN_EN (1 << 7)
105 #define AES_REG_SYSCFG_DREQ_DATA_OUT_EN (1 << 6)
106 #define AES_REG_SYSCFG_DREQ_DATA_IN_EN (1 << 5)
107 #define AES_REG_SYSCFG_DIRECTBUSEN (1 << 4)
108 #define AES_REG_SYSCFG_SIDLE_MASK (3 << 2)
109 #define AES_REG_SYSCFG_SIDLE_FORCEIDLE (0 << 2)
110 #define AES_REG_SYSCFG_SIDLE_NOIDLE (1 << 2)
111 #define AES_REG_SYSCFG_SIDLE_SMARTIDLE (2 << 2)
112 #define AES_REG_SYSCFG_SOFTRESET (1 << 1)
113 #define AES_REG_SYSCFG_AUTOIDLE (1 << 0)
115 #define AES_REG_SYSSTATUS 0x88
116 #define AES_REG_SYSSTATUS_RESETDONE (1 << 0)
118 #define AES_REG_IRQSTATUS 0x8C
119 #define AES_REG_IRQSTATUS_CTX_OUT (1 << 3)
120 #define AES_REG_IRQSTATUS_DATA_OUT (1 << 2)
121 #define AES_REG_IRQSTATUS_DATA_IN (1 << 1)
122 #define AES_REG_IRQSTATUS_CTX_IN (1 << 0)
124 #define AES_REG_IRQENA 0x90
125 #define AES_REG_IRQENA_CTX_OUT (1 << 3)
126 #define AES_REG_IRQENA_DATA_OUT (1 << 2)
127 #define AES_REG_IRQENA_DATA_IN (1 << 1)
128 #define AES_REG_IRQENA_CTX_IN (1 << 0)
130 /* ==================================================================== */
131 /** SHA / MD5 module layout.
132 */
133 /* ==================================================================== */
135 #define SHA_REG_ODIGEST 0x00
136 #define SHA_REG_ODIGEST_N(x) (0x00 + ((x) * 0x04))
137 #define SHA_REG_IDIGEST 0x20
138 #define SHA_REG_IDIGEST_N(x) (0x20 + ((x) * 0x04))
140 #define SHA_REG_DIGEST_COUNT 0x40
141 #define SHA_REG_MODE 0x44
142 #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7)
143 #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5)
144 #define SHA_REG_MODE_CLOSE_HASH (1 << 4)
145 #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3)
146 #define SHA_REG_MODE_ALGO_MASK (3 << 1)
147 #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1)
148 #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1)
149 #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1)
150 #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1)
152 #define SHA_REG_LENGTH 0x48
154 #define SHA_REG_DATA 0x80
155 #define SHA_REG_DATA_N(x) (0x80 + ((x) * 0x04))
157 #define SHA_REG_REV 0x100
158 #define SHA_REG_REV_SCHEME_MASK (3 << 30)
159 #define SHA_REG_REV_FUNC_MASK (0xFFF << 16)
160 #define SHA_REG_REV_R_RTL_MASK (0x1F << 11)
161 #define SHA_REG_REV_X_MAJOR_MASK (7 << 8)
162 #define SHA_REG_REV_CUSTOM_MASK (3 << 6)
163 #define SHA_REG_REV_Y_MINOR_MASK (0x3F << 0)
165 #define SHA_REG_SYSCFG 0x110
166 #define SHA_REG_SYSCFG_SADVANCED (1 << 7)
167 #define SHA_REG_SYSCFG_SCONT_SWT (1 << 6)
168 #define SHA_REG_SYSCFG_SIDLE_MASK (3 << 4)
169 #define SHA_REG_SYSCFG_SIDLE_FORCEIDLE (0 << 4)
170 #define SHA_REG_SYSCFG_SIDLE_NOIDLE (1 << 4)
171 #define SHA_REG_SYSCFG_SIDLE_SMARTIDLE (2 << 4)
172 #define SHA_REG_SYSCFG_SDMA_EN (1 << 3)
173 #define SHA_REG_SYSCFG_SIT_EN (1 << 2)
174 #define SHA_REG_SYSCFG_SOFTRESET (1 << 1)
175 #define SHA_REG_SYSCFG_AUTOIDLE (1 << 0)
177 #define SHA_REG_SYSSTATUS 0x114
178 #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0)
180 #define SHA_REG_IRQSTATUS 0x118
181 #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3)
182 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
183 #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1)
184 #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0)
186 #define SHA_REG_IRQENA 0x11C
187 #define SHA_REG_IRQENA_CTX_RDY (1 << 3)
188 #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2)
189 #define SHA_REG_IRQENA_INPUT_RDY (1 << 1)
190 #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0)
192 #endif /* __DRIVERS_CRYPTO_AM33X_H */