5343ad3fb36b66c39ca8cb7e20058da84a062db5
1 /*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/workqueue.h>
28 #include <linux/timer.h>
29 #include <linux/clk.h>
30 #include <linux/mmc/host.h>
31 #include <linux/mmc/core.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/io.h>
34 #include <linux/semaphore.h>
35 #include <linux/gpio.h>
36 #include <linux/regulator/consumer.h>
37 #include <linux/pm_runtime.h>
38 #include <plat/dma.h>
39 #include <mach/hardware.h>
40 #include <plat/board.h>
41 #include <plat/mmc.h>
42 #include <plat/cpu.h>
44 /* OMAP HSMMC Host Controller Registers */
45 #define OMAP_HSMMC_SYSCONFIG 0x0010
46 #define OMAP_HSMMC_SYSSTATUS 0x0014
47 #define OMAP_HSMMC_CON 0x002C
48 #define OMAP_HSMMC_BLK 0x0104
49 #define OMAP_HSMMC_ARG 0x0108
50 #define OMAP_HSMMC_CMD 0x010C
51 #define OMAP_HSMMC_RSP10 0x0110
52 #define OMAP_HSMMC_RSP32 0x0114
53 #define OMAP_HSMMC_RSP54 0x0118
54 #define OMAP_HSMMC_RSP76 0x011C
55 #define OMAP_HSMMC_DATA 0x0120
56 #define OMAP_HSMMC_HCTL 0x0128
57 #define OMAP_HSMMC_SYSCTL 0x012C
58 #define OMAP_HSMMC_STAT 0x0130
59 #define OMAP_HSMMC_IE 0x0134
60 #define OMAP_HSMMC_ISE 0x0138
61 #define OMAP_HSMMC_CAPA 0x0140
63 #define VS18 (1 << 26)
64 #define VS30 (1 << 25)
65 #define SDVS18 (0x5 << 9)
66 #define SDVS30 (0x6 << 9)
67 #define SDVS33 (0x7 << 9)
68 #define SDVS_MASK 0x00000E00
69 #define SDVSCLR 0xFFFFF1FF
70 #define SDVSDET 0x00000400
71 #define AUTOIDLE 0x1
72 #define SDBP (1 << 8)
73 #define DTO 0xe
74 #define ICE 0x1
75 #define ICS 0x2
76 #define CEN (1 << 2)
77 #define CLKD_MASK 0x0000FFC0
78 #define CLKD_SHIFT 6
79 #define DTO_MASK 0x000F0000
80 #define DTO_SHIFT 16
81 #define INT_EN_MASK 0x307F0033
82 #define BWR_ENABLE (1 << 4)
83 #define BRR_ENABLE (1 << 5)
84 #define DTO_ENABLE (1 << 20)
85 #define INIT_STREAM (1 << 1)
86 #define DP_SELECT (1 << 21)
87 #define DDIR (1 << 4)
88 #define DMA_EN 0x1
89 #define MSBS (1 << 5)
90 #define BCE (1 << 1)
91 #define FOUR_BIT (1 << 1)
92 #define DW8 (1 << 5)
93 #define CC 0x1
94 #define TC 0x02
95 #define OD 0x1
96 #define ERR (1 << 15)
97 #define CMD_TIMEOUT (1 << 16)
98 #define DATA_TIMEOUT (1 << 20)
99 #define CMD_CRC (1 << 17)
100 #define DATA_CRC (1 << 21)
101 #define CARD_ERR (1 << 28)
102 #define STAT_CLEAR 0xFFFFFFFF
103 #define INIT_STREAM_CMD 0x00000000
104 #define DUAL_VOLT_OCR_BIT 7
105 #define SRC (1 << 25)
106 #define SRD (1 << 26)
107 #define SOFTRESET (1 << 1)
108 #define RESETDONE (1 << 0)
110 /*
111 * FIXME: Most likely all the data using these _DEVID defines should come
112 * from the platform_data, or implemented in controller and slot specific
113 * functions.
114 */
115 #define OMAP_MMC1_DEVID 0
116 #define OMAP_MMC2_DEVID 1
117 #define OMAP_MMC3_DEVID 2
118 #define OMAP_MMC4_DEVID 3
119 #define OMAP_MMC5_DEVID 4
121 #define MMC_AUTOSUSPEND_DELAY 100
122 #define MMC_TIMEOUT_MS 20
123 #define OMAP_MMC_MIN_CLOCK 400000
124 #define OMAP_MMC_MAX_CLOCK 52000000
125 #define DRIVER_NAME "omap_hsmmc"
127 /*
128 * One controller can have multiple slots, like on some omap boards using
129 * omap.c controller driver. Luckily this is not currently done on any known
130 * omap_hsmmc.c device.
131 */
132 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
134 /*
135 * MMC Host controller read/write API's
136 */
137 #define OMAP_HSMMC_READ(base, reg) \
138 __raw_readl((base) + OMAP_HSMMC_##reg)
140 #define OMAP_HSMMC_WRITE(base, reg, val) \
141 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
143 struct omap_hsmmc_next {
144 unsigned int dma_len;
145 s32 cookie;
146 };
148 struct omap_hsmmc_host {
149 struct device *dev;
150 struct mmc_host *mmc;
151 struct mmc_request *mrq;
152 struct mmc_command *cmd;
153 struct mmc_data *data;
154 struct clk *fclk;
155 struct clk *dbclk;
156 /*
157 * vcc == configured supply
158 * vcc_aux == optional
159 * - MMC1, supply for DAT4..DAT7
160 * - MMC2/MMC2, external level shifter voltage supply, for
161 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
162 */
163 struct regulator *vcc;
164 struct regulator *vcc_aux;
165 struct work_struct mmc_carddetect_work;
166 void __iomem *base;
167 resource_size_t mapbase;
168 spinlock_t irq_lock; /* Prevent races with irq handler */
169 unsigned int id;
170 unsigned int dma_len;
171 unsigned int dma_sg_idx;
172 unsigned char bus_mode;
173 unsigned char power_mode;
174 u32 *buffer;
175 u32 bytesleft;
176 int suspended;
177 int irq;
178 int use_dma, dma_ch;
179 int dma_line_tx, dma_line_rx;
180 int slot_id;
181 int got_dbclk;
182 int response_busy;
183 int context_loss;
184 int dpm_state;
185 int vdd;
186 int protect_card;
187 int reqs_blocked;
188 int use_reg;
189 int req_in_progress;
190 struct omap_hsmmc_next next_data;
192 struct omap_mmc_platform_data *pdata;
193 };
195 static int omap_hsmmc_card_detect(struct device *dev, int slot)
196 {
197 struct omap_mmc_platform_data *mmc = dev->platform_data;
199 /* NOTE: assumes card detect signal is active-low */
200 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
201 }
203 static int omap_hsmmc_get_wp(struct device *dev, int slot)
204 {
205 struct omap_mmc_platform_data *mmc = dev->platform_data;
207 /* NOTE: assumes write protect signal is active-high */
208 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
209 }
211 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
212 {
213 struct omap_mmc_platform_data *mmc = dev->platform_data;
215 /* NOTE: assumes card detect signal is active-low */
216 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
217 }
219 #ifdef CONFIG_PM
221 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
222 {
223 struct omap_mmc_platform_data *mmc = dev->platform_data;
225 disable_irq(mmc->slots[0].card_detect_irq);
226 return 0;
227 }
229 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
230 {
231 struct omap_mmc_platform_data *mmc = dev->platform_data;
233 enable_irq(mmc->slots[0].card_detect_irq);
234 return 0;
235 }
237 #else
239 #define omap_hsmmc_suspend_cdirq NULL
240 #define omap_hsmmc_resume_cdirq NULL
242 #endif
244 #ifdef CONFIG_REGULATOR
246 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
247 int vdd)
248 {
249 struct omap_hsmmc_host *host =
250 platform_get_drvdata(to_platform_device(dev));
251 int ret;
253 if (mmc_slot(host).before_set_reg)
254 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
256 if (power_on)
257 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
258 else
259 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
261 if (mmc_slot(host).after_set_reg)
262 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
264 return ret;
265 }
267 static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
268 int vdd)
269 {
270 struct omap_hsmmc_host *host =
271 platform_get_drvdata(to_platform_device(dev));
272 int ret = 0;
274 /*
275 * If we don't see a Vcc regulator, assume it's a fixed
276 * voltage always-on regulator.
277 */
278 if (!host->vcc)
279 return 0;
281 if (mmc_slot(host).before_set_reg)
282 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
284 /*
285 * Assume Vcc regulator is used only to power the card ... OMAP
286 * VDDS is used to power the pins, optionally with a transceiver to
287 * support cards using voltages other than VDDS (1.8V nominal). When a
288 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
289 *
290 * In some cases this regulator won't support enable/disable;
291 * e.g. it's a fixed rail for a WLAN chip.
292 *
293 * In other cases vcc_aux switches interface power. Example, for
294 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
295 * chips/cards need an interface voltage rail too.
296 */
297 if (power_on) {
298 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
299 /* Enable interface voltage rail, if needed */
300 if (ret == 0 && host->vcc_aux) {
301 ret = regulator_enable(host->vcc_aux);
302 if (ret < 0)
303 ret = mmc_regulator_set_ocr(host->mmc,
304 host->vcc, 0);
305 }
306 } else {
307 /* Shut down the rail */
308 if (host->vcc_aux)
309 ret = regulator_disable(host->vcc_aux);
310 if (!ret) {
311 /* Then proceed to shut down the local regulator */
312 ret = mmc_regulator_set_ocr(host->mmc,
313 host->vcc, 0);
314 }
315 }
317 if (mmc_slot(host).after_set_reg)
318 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
320 return ret;
321 }
323 static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
324 int vdd)
325 {
326 return 0;
327 }
329 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
330 int vdd, int cardsleep)
331 {
332 struct omap_hsmmc_host *host =
333 platform_get_drvdata(to_platform_device(dev));
334 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
336 return regulator_set_mode(host->vcc, mode);
337 }
339 static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
340 int vdd, int cardsleep)
341 {
342 struct omap_hsmmc_host *host =
343 platform_get_drvdata(to_platform_device(dev));
344 int err, mode;
346 /*
347 * If we don't see a Vcc regulator, assume it's a fixed
348 * voltage always-on regulator.
349 */
350 if (!host->vcc)
351 return 0;
353 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
355 if (!host->vcc_aux)
356 return regulator_set_mode(host->vcc, mode);
358 if (cardsleep) {
359 /* VCC can be turned off if card is asleep */
360 if (sleep)
361 err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
362 else
363 err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
364 } else
365 err = regulator_set_mode(host->vcc, mode);
366 if (err)
367 return err;
369 if (!mmc_slot(host).vcc_aux_disable_is_sleep)
370 return regulator_set_mode(host->vcc_aux, mode);
372 if (sleep)
373 return regulator_disable(host->vcc_aux);
374 else
375 return regulator_enable(host->vcc_aux);
376 }
378 static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
379 int vdd, int cardsleep)
380 {
381 return 0;
382 }
384 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
385 {
386 struct regulator *reg;
387 int ret = 0;
388 int ocr_value = 0;
390 switch (host->id) {
391 case OMAP_MMC1_DEVID:
392 /* On-chip level shifting via PBIAS0/PBIAS1 */
393 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
394 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
395 break;
396 case OMAP_MMC2_DEVID:
397 case OMAP_MMC3_DEVID:
398 case OMAP_MMC5_DEVID:
399 /* Off-chip level shifting, or none */
400 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
401 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
402 break;
403 case OMAP_MMC4_DEVID:
404 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
405 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
406 default:
407 pr_err("MMC%d configuration not supported!\n", host->id);
408 return -EINVAL;
409 }
411 reg = regulator_get(host->dev, "vmmc");
412 if (IS_ERR(reg)) {
413 dev_dbg(host->dev, "vmmc regulator missing\n");
414 /*
415 * HACK: until fixed.c regulator is usable,
416 * we don't require a main regulator
417 * for MMC2 or MMC3
418 */
419 if (host->id == OMAP_MMC1_DEVID) {
420 ret = PTR_ERR(reg);
421 goto err;
422 }
423 } else {
424 host->vcc = reg;
425 ocr_value = mmc_regulator_get_ocrmask(reg);
426 if (!mmc_slot(host).ocr_mask) {
427 mmc_slot(host).ocr_mask = ocr_value;
428 } else {
429 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
430 pr_err("MMC%d ocrmask %x is not supported\n",
431 host->id, mmc_slot(host).ocr_mask);
432 mmc_slot(host).ocr_mask = 0;
433 return -EINVAL;
434 }
435 }
437 /* Allow an aux regulator */
438 reg = regulator_get(host->dev, "vmmc_aux");
439 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
441 /* For eMMC do not power off when not in sleep state */
442 if (mmc_slot(host).no_regulator_off_init)
443 return 0;
444 /*
445 * UGLY HACK: workaround regulator framework bugs.
446 * When the bootloader leaves a supply active, it's
447 * initialized with zero usecount ... and we can't
448 * disable it without first enabling it. Until the
449 * framework is fixed, we need a workaround like this
450 * (which is safe for MMC, but not in general).
451 */
452 if (regulator_is_enabled(host->vcc) > 0 ||
453 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
454 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
456 mmc_slot(host).set_power(host->dev, host->slot_id,
457 1, vdd);
458 mmc_slot(host).set_power(host->dev, host->slot_id,
459 0, 0);
460 }
461 }
463 return 0;
465 err:
466 mmc_slot(host).set_power = NULL;
467 mmc_slot(host).set_sleep = NULL;
468 return ret;
469 }
471 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
472 {
473 regulator_put(host->vcc);
474 regulator_put(host->vcc_aux);
475 mmc_slot(host).set_power = NULL;
476 mmc_slot(host).set_sleep = NULL;
477 }
479 static inline int omap_hsmmc_have_reg(void)
480 {
481 return 1;
482 }
484 #else
486 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
487 {
488 return -EINVAL;
489 }
491 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
492 {
493 }
495 static inline int omap_hsmmc_have_reg(void)
496 {
497 return 0;
498 }
500 #endif
502 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
503 {
504 int ret;
506 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
507 if (pdata->slots[0].cover)
508 pdata->slots[0].get_cover_state =
509 omap_hsmmc_get_cover_state;
510 else
511 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
512 pdata->slots[0].card_detect_irq =
513 gpio_to_irq(pdata->slots[0].switch_pin);
514 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
515 if (ret)
516 return ret;
517 ret = gpio_direction_input(pdata->slots[0].switch_pin);
518 if (ret)
519 goto err_free_sp;
520 } else
521 pdata->slots[0].switch_pin = -EINVAL;
523 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
524 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
525 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
526 if (ret)
527 goto err_free_cd;
528 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
529 if (ret)
530 goto err_free_wp;
531 } else
532 pdata->slots[0].gpio_wp = -EINVAL;
534 return 0;
536 err_free_wp:
537 gpio_free(pdata->slots[0].gpio_wp);
538 err_free_cd:
539 if (gpio_is_valid(pdata->slots[0].switch_pin))
540 err_free_sp:
541 gpio_free(pdata->slots[0].switch_pin);
542 return ret;
543 }
545 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
546 {
547 if (gpio_is_valid(pdata->slots[0].gpio_wp))
548 gpio_free(pdata->slots[0].gpio_wp);
549 if (gpio_is_valid(pdata->slots[0].switch_pin))
550 gpio_free(pdata->slots[0].switch_pin);
551 }
553 /*
554 * Start clock to the card
555 */
556 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
557 {
558 OMAP_HSMMC_WRITE(host->base, SYSCTL,
559 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
560 }
562 /*
563 * Stop clock to the card
564 */
565 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
566 {
567 OMAP_HSMMC_WRITE(host->base, SYSCTL,
568 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
569 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
570 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
571 }
573 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
574 struct mmc_command *cmd)
575 {
576 unsigned int irq_mask;
578 if (host->use_dma)
579 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
580 else
581 irq_mask = INT_EN_MASK;
583 /* Disable timeout for erases */
584 if (cmd->opcode == MMC_ERASE)
585 irq_mask &= ~DTO_ENABLE;
587 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
588 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
589 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
590 }
592 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
593 {
594 OMAP_HSMMC_WRITE(host->base, ISE, 0);
595 OMAP_HSMMC_WRITE(host->base, IE, 0);
596 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
597 }
599 /* Calculate divisor for the given clock frequency */
600 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
601 {
602 u16 dsor = 0;
604 if (ios->clock) {
605 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
606 if (dsor > 250)
607 dsor = 250;
608 }
610 return dsor;
611 }
613 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
614 {
615 struct mmc_ios *ios = &host->mmc->ios;
616 unsigned long regval;
617 unsigned long timeout;
619 dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
621 omap_hsmmc_stop_clock(host);
623 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
624 regval = regval & ~(CLKD_MASK | DTO_MASK);
625 regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
626 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
627 OMAP_HSMMC_WRITE(host->base, SYSCTL,
628 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
630 /* Wait till the ICS bit is set */
631 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
632 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
633 && time_before(jiffies, timeout))
634 cpu_relax();
636 omap_hsmmc_start_clock(host);
637 }
639 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
640 {
641 struct mmc_ios *ios = &host->mmc->ios;
642 u32 con;
644 con = OMAP_HSMMC_READ(host->base, CON);
645 switch (ios->bus_width) {
646 case MMC_BUS_WIDTH_8:
647 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
648 break;
649 case MMC_BUS_WIDTH_4:
650 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
651 OMAP_HSMMC_WRITE(host->base, HCTL,
652 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
653 break;
654 case MMC_BUS_WIDTH_1:
655 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
656 OMAP_HSMMC_WRITE(host->base, HCTL,
657 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
658 break;
659 }
660 }
662 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
663 {
664 struct mmc_ios *ios = &host->mmc->ios;
665 u32 con;
667 con = OMAP_HSMMC_READ(host->base, CON);
668 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
669 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
670 else
671 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
672 }
674 #ifdef CONFIG_PM
676 /*
677 * Restore the MMC host context, if it was lost as result of a
678 * power state change.
679 */
680 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
681 {
682 struct mmc_ios *ios = &host->mmc->ios;
683 struct omap_mmc_platform_data *pdata = host->pdata;
684 int context_loss = 0;
685 u32 hctl, capa;
686 unsigned long timeout;
688 if (pdata->get_context_loss_count) {
689 context_loss = pdata->get_context_loss_count(host->dev);
690 if (context_loss < 0)
691 return 1;
692 }
694 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
695 context_loss == host->context_loss ? "not " : "");
696 if (host->context_loss == context_loss)
697 return 1;
699 /* Wait for hardware reset */
700 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
701 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
702 && time_before(jiffies, timeout))
703 ;
705 /* Do software reset */
706 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
707 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
708 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
709 && time_before(jiffies, timeout))
710 ;
712 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
713 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
715 if (host->id == OMAP_MMC1_DEVID) {
716 if (host->power_mode != MMC_POWER_OFF &&
717 (1 << ios->vdd) <= MMC_VDD_23_24)
718 hctl = SDVS18;
719 else
720 hctl = SDVS30;
721 capa = VS30 | VS18;
722 } else {
723 hctl = SDVS18;
724 capa = VS18;
725 }
727 OMAP_HSMMC_WRITE(host->base, HCTL,
728 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
730 OMAP_HSMMC_WRITE(host->base, CAPA,
731 OMAP_HSMMC_READ(host->base, CAPA) | capa);
733 OMAP_HSMMC_WRITE(host->base, HCTL,
734 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
736 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
737 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
738 && time_before(jiffies, timeout))
739 ;
741 omap_hsmmc_disable_irq(host);
743 /* Do not initialize card-specific things if the power is off */
744 if (host->power_mode == MMC_POWER_OFF)
745 goto out;
747 omap_hsmmc_set_bus_width(host);
749 omap_hsmmc_set_clock(host);
751 omap_hsmmc_set_bus_mode(host);
753 out:
754 host->context_loss = context_loss;
756 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
757 return 0;
758 }
760 /*
761 * Save the MMC host context (store the number of power state changes so far).
762 */
763 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
764 {
765 struct omap_mmc_platform_data *pdata = host->pdata;
766 int context_loss;
768 if (pdata->get_context_loss_count) {
769 context_loss = pdata->get_context_loss_count(host->dev);
770 if (context_loss < 0)
771 return;
772 host->context_loss = context_loss;
773 }
774 }
776 #else
778 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
779 {
780 return 0;
781 }
783 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
784 {
785 }
787 #endif
789 /*
790 * Send init stream sequence to card
791 * before sending IDLE command
792 */
793 static void send_init_stream(struct omap_hsmmc_host *host)
794 {
795 int reg = 0;
796 unsigned long timeout;
798 if (host->protect_card)
799 return;
801 disable_irq(host->irq);
803 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
804 OMAP_HSMMC_WRITE(host->base, CON,
805 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
806 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
808 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
809 while ((reg != CC) && time_before(jiffies, timeout))
810 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
812 OMAP_HSMMC_WRITE(host->base, CON,
813 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
815 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
816 OMAP_HSMMC_READ(host->base, STAT);
818 enable_irq(host->irq);
819 }
821 static inline
822 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
823 {
824 int r = 1;
826 if (mmc_slot(host).get_cover_state)
827 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
828 return r;
829 }
831 static ssize_t
832 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
833 char *buf)
834 {
835 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
836 struct omap_hsmmc_host *host = mmc_priv(mmc);
838 return sprintf(buf, "%s\n",
839 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
840 }
842 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
844 static ssize_t
845 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
846 char *buf)
847 {
848 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
849 struct omap_hsmmc_host *host = mmc_priv(mmc);
851 return sprintf(buf, "%s\n", mmc_slot(host).name);
852 }
854 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
856 /*
857 * Configure the response type and send the cmd.
858 */
859 static void
860 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
861 struct mmc_data *data)
862 {
863 int cmdreg = 0, resptype = 0, cmdtype = 0;
865 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
866 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
867 host->cmd = cmd;
869 omap_hsmmc_enable_irq(host, cmd);
871 host->response_busy = 0;
872 if (cmd->flags & MMC_RSP_PRESENT) {
873 if (cmd->flags & MMC_RSP_136)
874 resptype = 1;
875 else if (cmd->flags & MMC_RSP_BUSY) {
876 resptype = 3;
877 host->response_busy = 1;
878 } else
879 resptype = 2;
880 }
882 /*
883 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
884 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
885 * a val of 0x3, rest 0x0.
886 */
887 if (cmd == host->mrq->stop)
888 cmdtype = 0x3;
890 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
892 if (data) {
893 cmdreg |= DP_SELECT | MSBS | BCE;
894 if (data->flags & MMC_DATA_READ)
895 cmdreg |= DDIR;
896 else
897 cmdreg &= ~(DDIR);
898 }
900 if (host->use_dma)
901 cmdreg |= DMA_EN;
903 host->req_in_progress = 1;
905 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
906 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
907 }
909 static int
910 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
911 {
912 if (data->flags & MMC_DATA_WRITE)
913 return DMA_TO_DEVICE;
914 else
915 return DMA_FROM_DEVICE;
916 }
918 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
919 {
920 int dma_ch;
922 spin_lock(&host->irq_lock);
923 host->req_in_progress = 0;
924 dma_ch = host->dma_ch;
925 spin_unlock(&host->irq_lock);
927 omap_hsmmc_disable_irq(host);
928 /* Do not complete the request if DMA is still in progress */
929 if (mrq->data && host->use_dma && dma_ch != -1)
930 return;
931 host->mrq = NULL;
932 mmc_request_done(host->mmc, mrq);
933 }
935 /*
936 * Notify the transfer complete to MMC core
937 */
938 static void
939 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
940 {
941 if (!data) {
942 struct mmc_request *mrq = host->mrq;
944 /* TC before CC from CMD6 - don't know why, but it happens */
945 if (host->cmd && host->cmd->opcode == 6 &&
946 host->response_busy) {
947 host->response_busy = 0;
948 return;
949 }
951 omap_hsmmc_request_done(host, mrq);
952 return;
953 }
955 host->data = NULL;
957 if (!data->error)
958 data->bytes_xfered += data->blocks * (data->blksz);
959 else
960 data->bytes_xfered = 0;
962 if (!data->stop) {
963 omap_hsmmc_request_done(host, data->mrq);
964 return;
965 }
966 omap_hsmmc_start_command(host, data->stop, NULL);
967 }
969 /*
970 * Notify the core about command completion
971 */
972 static void
973 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
974 {
975 host->cmd = NULL;
977 if (cmd->flags & MMC_RSP_PRESENT) {
978 if (cmd->flags & MMC_RSP_136) {
979 /* response type 2 */
980 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
981 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
982 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
983 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
984 } else {
985 /* response types 1, 1b, 3, 4, 5, 6 */
986 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
987 }
988 }
989 if ((host->data == NULL && !host->response_busy) || cmd->error)
990 omap_hsmmc_request_done(host, cmd->mrq);
991 }
993 /*
994 * DMA clean up for command errors
995 */
996 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
997 {
998 int dma_ch;
1000 host->data->error = errno;
1002 spin_lock(&host->irq_lock);
1003 dma_ch = host->dma_ch;
1004 host->dma_ch = -1;
1005 spin_unlock(&host->irq_lock);
1007 if (host->use_dma && dma_ch != -1) {
1008 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
1009 host->data->sg_len,
1010 omap_hsmmc_get_dma_dir(host, host->data));
1011 omap_free_dma(dma_ch);
1012 host->data->host_cookie = 0;
1013 }
1014 host->data = NULL;
1015 }
1017 /*
1018 * Readable error output
1019 */
1020 #ifdef CONFIG_MMC_DEBUG
1021 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1022 {
1023 /* --- means reserved bit without definition at documentation */
1024 static const char *omap_hsmmc_status_bits[] = {
1025 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1026 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1027 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1028 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1029 };
1030 char res[256];
1031 char *buf = res;
1032 int len, i;
1034 len = sprintf(buf, "MMC IRQ 0x%x :", status);
1035 buf += len;
1037 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1038 if (status & (1 << i)) {
1039 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1040 buf += len;
1041 }
1043 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
1044 }
1045 #else
1046 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1047 u32 status)
1048 {
1049 }
1050 #endif /* CONFIG_MMC_DEBUG */
1052 /*
1053 * MMC controller internal state machines reset
1054 *
1055 * Used to reset command or data internal state machines, using respectively
1056 * SRC or SRD bit of SYSCTL register
1057 * Can be called from interrupt context
1058 */
1059 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1060 unsigned long bit)
1061 {
1062 unsigned long i = 0;
1063 unsigned long limit = (loops_per_jiffy *
1064 msecs_to_jiffies(MMC_TIMEOUT_MS));
1066 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1067 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1069 /*
1070 * OMAP4 ES2 and greater has an updated reset logic.
1071 * Monitor a 0->1 transition first
1072 */
1073 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1074 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1075 && (i++ < limit))
1076 cpu_relax();
1077 }
1078 i = 0;
1080 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1081 (i++ < limit))
1082 cpu_relax();
1084 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1085 dev_err(mmc_dev(host->mmc),
1086 "Timeout waiting on controller reset in %s\n",
1087 __func__);
1088 }
1090 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1091 {
1092 struct mmc_data *data;
1093 int end_cmd = 0, end_trans = 0;
1095 if (!host->req_in_progress) {
1096 do {
1097 OMAP_HSMMC_WRITE(host->base, STAT, status);
1098 /* Flush posted write */
1099 status = OMAP_HSMMC_READ(host->base, STAT);
1100 } while (status & INT_EN_MASK);
1101 return;
1102 }
1104 data = host->data;
1105 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1107 if (status & ERR) {
1108 omap_hsmmc_dbg_report_irq(host, status);
1109 if ((status & CMD_TIMEOUT) ||
1110 (status & CMD_CRC)) {
1111 if (host->cmd) {
1112 if (status & CMD_TIMEOUT) {
1113 omap_hsmmc_reset_controller_fsm(host,
1114 SRC);
1115 host->cmd->error = -ETIMEDOUT;
1116 } else {
1117 host->cmd->error = -EILSEQ;
1118 }
1119 end_cmd = 1;
1120 }
1121 if (host->data || host->response_busy) {
1122 if (host->data)
1123 omap_hsmmc_dma_cleanup(host,
1124 -ETIMEDOUT);
1125 host->response_busy = 0;
1126 omap_hsmmc_reset_controller_fsm(host, SRD);
1127 }
1128 }
1129 if ((status & DATA_TIMEOUT) ||
1130 (status & DATA_CRC)) {
1131 if (host->data || host->response_busy) {
1132 int err = (status & DATA_TIMEOUT) ?
1133 -ETIMEDOUT : -EILSEQ;
1135 if (host->data)
1136 omap_hsmmc_dma_cleanup(host, err);
1137 else
1138 host->mrq->cmd->error = err;
1139 host->response_busy = 0;
1140 omap_hsmmc_reset_controller_fsm(host, SRD);
1141 end_trans = 1;
1142 }
1143 }
1144 if (status & CARD_ERR) {
1145 dev_dbg(mmc_dev(host->mmc),
1146 "Ignoring card err CMD%d\n", host->cmd->opcode);
1147 if (host->cmd)
1148 end_cmd = 1;
1149 if (host->data)
1150 end_trans = 1;
1151 }
1152 }
1154 OMAP_HSMMC_WRITE(host->base, STAT, status);
1156 if (end_cmd || ((status & CC) && host->cmd))
1157 omap_hsmmc_cmd_done(host, host->cmd);
1158 if ((end_trans || (status & TC)) && host->mrq)
1159 omap_hsmmc_xfer_done(host, data);
1160 }
1162 /*
1163 * MMC controller IRQ handler
1164 */
1165 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1166 {
1167 struct omap_hsmmc_host *host = dev_id;
1168 int status;
1170 status = OMAP_HSMMC_READ(host->base, STAT);
1171 do {
1172 omap_hsmmc_do_irq(host, status);
1173 /* Flush posted write */
1174 status = OMAP_HSMMC_READ(host->base, STAT);
1175 } while (status & INT_EN_MASK);
1177 return IRQ_HANDLED;
1178 }
1180 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1181 {
1182 unsigned long i;
1184 OMAP_HSMMC_WRITE(host->base, HCTL,
1185 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1186 for (i = 0; i < loops_per_jiffy; i++) {
1187 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1188 break;
1189 cpu_relax();
1190 }
1191 }
1193 /*
1194 * Switch MMC interface voltage ... only relevant for MMC1.
1195 *
1196 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1197 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1198 * Some chips, like eMMC ones, use internal transceivers.
1199 */
1200 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1201 {
1202 u32 reg_val = 0;
1203 int ret;
1205 /* Disable the clocks */
1206 pm_runtime_put_sync(host->dev);
1207 if (host->got_dbclk)
1208 clk_disable(host->dbclk);
1210 /* Turn the power off */
1211 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1213 /* Turn the power ON with given VDD 1.8 or 3.0v */
1214 if (!ret)
1215 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1216 vdd);
1217 pm_runtime_get_sync(host->dev);
1218 if (host->got_dbclk)
1219 clk_enable(host->dbclk);
1221 if (ret != 0)
1222 goto err;
1224 OMAP_HSMMC_WRITE(host->base, HCTL,
1225 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1226 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1228 /*
1229 * If a MMC dual voltage card is detected, the set_ios fn calls
1230 * this fn with VDD bit set for 1.8V. Upon card removal from the
1231 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1232 *
1233 * Cope with a bit of slop in the range ... per data sheets:
1234 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1235 * but recommended values are 1.71V to 1.89V
1236 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1237 * but recommended values are 2.7V to 3.3V
1238 *
1239 * Board setup code shouldn't permit anything very out-of-range.
1240 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1241 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1242 */
1243 if ((1 << vdd) <= MMC_VDD_23_24)
1244 reg_val |= SDVS18;
1245 else
1246 reg_val |= SDVS30;
1248 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1249 set_sd_bus_power(host);
1251 return 0;
1252 err:
1253 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1254 return ret;
1255 }
1257 /* Protect the card while the cover is open */
1258 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1259 {
1260 if (!mmc_slot(host).get_cover_state)
1261 return;
1263 host->reqs_blocked = 0;
1264 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1265 if (host->protect_card) {
1266 pr_info("%s: cover is closed, "
1267 "card is now accessible\n",
1268 mmc_hostname(host->mmc));
1269 host->protect_card = 0;
1270 }
1271 } else {
1272 if (!host->protect_card) {
1273 pr_info("%s: cover is open, "
1274 "card is now inaccessible\n",
1275 mmc_hostname(host->mmc));
1276 host->protect_card = 1;
1277 }
1278 }
1279 }
1281 /*
1282 * Work Item to notify the core about card insertion/removal
1283 */
1284 static void omap_hsmmc_detect(struct work_struct *work)
1285 {
1286 struct omap_hsmmc_host *host =
1287 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
1288 struct omap_mmc_slot_data *slot = &mmc_slot(host);
1289 int carddetect;
1291 if (host->suspended)
1292 return;
1294 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1296 if (slot->card_detect)
1297 carddetect = slot->card_detect(host->dev, host->slot_id);
1298 else {
1299 omap_hsmmc_protect_card(host);
1300 carddetect = -ENOSYS;
1301 }
1303 if (carddetect)
1304 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1305 else
1306 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1307 }
1309 /*
1310 * ISR for handling card insertion and removal
1311 */
1312 static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
1313 {
1314 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
1316 if (host->suspended)
1317 return IRQ_HANDLED;
1318 schedule_work(&host->mmc_carddetect_work);
1320 return IRQ_HANDLED;
1321 }
1323 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1324 struct mmc_data *data)
1325 {
1326 int sync_dev;
1328 if (data->flags & MMC_DATA_WRITE)
1329 sync_dev = host->dma_line_tx;
1330 else
1331 sync_dev = host->dma_line_rx;
1332 return sync_dev;
1333 }
1335 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1336 struct mmc_data *data,
1337 struct scatterlist *sgl)
1338 {
1339 int blksz, nblk, dma_ch;
1341 dma_ch = host->dma_ch;
1342 if (data->flags & MMC_DATA_WRITE) {
1343 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1344 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1345 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1346 sg_dma_address(sgl), 0, 0);
1347 } else {
1348 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1349 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1350 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1351 sg_dma_address(sgl), 0, 0);
1352 }
1354 blksz = host->data->blksz;
1355 nblk = sg_dma_len(sgl) / blksz;
1357 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1358 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1359 omap_hsmmc_get_dma_sync_dev(host, data),
1360 !(data->flags & MMC_DATA_WRITE));
1362 omap_start_dma(dma_ch);
1363 }
1365 /*
1366 * DMA call back function
1367 */
1368 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1369 {
1370 struct omap_hsmmc_host *host = cb_data;
1371 struct mmc_data *data;
1372 int dma_ch, req_in_progress;
1374 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1375 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1376 ch_status);
1377 return;
1378 }
1380 spin_lock(&host->irq_lock);
1381 if (host->dma_ch < 0) {
1382 spin_unlock(&host->irq_lock);
1383 return;
1384 }
1386 data = host->mrq->data;
1387 host->dma_sg_idx++;
1388 if (host->dma_sg_idx < host->dma_len) {
1389 /* Fire up the next transfer. */
1390 omap_hsmmc_config_dma_params(host, data,
1391 data->sg + host->dma_sg_idx);
1392 spin_unlock(&host->irq_lock);
1393 return;
1394 }
1396 if (!data->host_cookie)
1397 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1398 omap_hsmmc_get_dma_dir(host, data));
1400 req_in_progress = host->req_in_progress;
1401 dma_ch = host->dma_ch;
1402 host->dma_ch = -1;
1403 spin_unlock(&host->irq_lock);
1405 omap_free_dma(dma_ch);
1407 /* If DMA has finished after TC, complete the request */
1408 if (!req_in_progress) {
1409 struct mmc_request *mrq = host->mrq;
1411 host->mrq = NULL;
1412 mmc_request_done(host->mmc, mrq);
1413 }
1414 }
1416 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1417 struct mmc_data *data,
1418 struct omap_hsmmc_next *next)
1419 {
1420 int dma_len;
1422 if (!next && data->host_cookie &&
1423 data->host_cookie != host->next_data.cookie) {
1424 pr_warning("[%s] invalid cookie: data->host_cookie %d"
1425 " host->next_data.cookie %d\n",
1426 __func__, data->host_cookie, host->next_data.cookie);
1427 data->host_cookie = 0;
1428 }
1430 /* Check if next job is already prepared */
1431 if (next ||
1432 (!next && data->host_cookie != host->next_data.cookie)) {
1433 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1434 data->sg_len,
1435 omap_hsmmc_get_dma_dir(host, data));
1437 } else {
1438 dma_len = host->next_data.dma_len;
1439 host->next_data.dma_len = 0;
1440 }
1443 if (dma_len == 0)
1444 return -EINVAL;
1446 if (next) {
1447 next->dma_len = dma_len;
1448 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1449 } else
1450 host->dma_len = dma_len;
1452 return 0;
1453 }
1455 /*
1456 * Routine to configure and start DMA for the MMC card
1457 */
1458 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1459 struct mmc_request *req)
1460 {
1461 int dma_ch = 0, ret = 0, i;
1462 struct mmc_data *data = req->data;
1464 /* Sanity check: all the SG entries must be aligned by block size. */
1465 for (i = 0; i < data->sg_len; i++) {
1466 struct scatterlist *sgl;
1468 sgl = data->sg + i;
1469 if (sgl->length % data->blksz)
1470 return -EINVAL;
1471 }
1472 if ((data->blksz % 4) != 0)
1473 /* REVISIT: The MMC buffer increments only when MSB is written.
1474 * Return error for blksz which is non multiple of four.
1475 */
1476 return -EINVAL;
1478 BUG_ON(host->dma_ch != -1);
1480 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1481 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1482 if (ret != 0) {
1483 dev_err(mmc_dev(host->mmc),
1484 "%s: omap_request_dma() failed with %d\n",
1485 mmc_hostname(host->mmc), ret);
1486 return ret;
1487 }
1488 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1489 if (ret)
1490 return ret;
1492 host->dma_ch = dma_ch;
1493 host->dma_sg_idx = 0;
1495 omap_hsmmc_config_dma_params(host, data, data->sg);
1497 return 0;
1498 }
1500 static void set_data_timeout(struct omap_hsmmc_host *host,
1501 unsigned int timeout_ns,
1502 unsigned int timeout_clks)
1503 {
1504 unsigned int timeout, cycle_ns;
1505 uint32_t reg, clkd, dto = 0;
1507 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1508 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1509 if (clkd == 0)
1510 clkd = 1;
1512 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1513 timeout = timeout_ns / cycle_ns;
1514 timeout += timeout_clks;
1515 if (timeout) {
1516 while ((timeout & 0x80000000) == 0) {
1517 dto += 1;
1518 timeout <<= 1;
1519 }
1520 dto = 31 - dto;
1521 timeout <<= 1;
1522 if (timeout && dto)
1523 dto += 1;
1524 if (dto >= 13)
1525 dto -= 13;
1526 else
1527 dto = 0;
1528 if (dto > 14)
1529 dto = 14;
1530 }
1532 reg &= ~DTO_MASK;
1533 reg |= dto << DTO_SHIFT;
1534 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1535 }
1537 /*
1538 * Configure block length for MMC/SD cards and initiate the transfer.
1539 */
1540 static int
1541 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1542 {
1543 int ret;
1544 host->data = req->data;
1546 if (req->data == NULL) {
1547 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1548 /*
1549 * Set an arbitrary 100ms data timeout for commands with
1550 * busy signal.
1551 */
1552 if (req->cmd->flags & MMC_RSP_BUSY)
1553 set_data_timeout(host, 100000000U, 0);
1554 return 0;
1555 }
1557 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1558 | (req->data->blocks << 16));
1559 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1561 if (host->use_dma) {
1562 ret = omap_hsmmc_start_dma_transfer(host, req);
1563 if (ret != 0) {
1564 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1565 return ret;
1566 }
1567 }
1568 return 0;
1569 }
1571 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1572 int err)
1573 {
1574 struct omap_hsmmc_host *host = mmc_priv(mmc);
1575 struct mmc_data *data = mrq->data;
1577 if (host->use_dma) {
1578 if (data->host_cookie)
1579 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1580 data->sg_len,
1581 omap_hsmmc_get_dma_dir(host, data));
1582 data->host_cookie = 0;
1583 }
1584 }
1586 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1587 bool is_first_req)
1588 {
1589 struct omap_hsmmc_host *host = mmc_priv(mmc);
1591 if (mrq->data->host_cookie) {
1592 mrq->data->host_cookie = 0;
1593 return ;
1594 }
1596 if (host->use_dma)
1597 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1598 &host->next_data))
1599 mrq->data->host_cookie = 0;
1600 }
1602 /*
1603 * Request function. for read/write operation
1604 */
1605 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1606 {
1607 struct omap_hsmmc_host *host = mmc_priv(mmc);
1608 int err;
1610 BUG_ON(host->req_in_progress);
1611 BUG_ON(host->dma_ch != -1);
1612 if (host->protect_card) {
1613 if (host->reqs_blocked < 3) {
1614 /*
1615 * Ensure the controller is left in a consistent
1616 * state by resetting the command and data state
1617 * machines.
1618 */
1619 omap_hsmmc_reset_controller_fsm(host, SRD);
1620 omap_hsmmc_reset_controller_fsm(host, SRC);
1621 host->reqs_blocked += 1;
1622 }
1623 req->cmd->error = -EBADF;
1624 if (req->data)
1625 req->data->error = -EBADF;
1626 req->cmd->retries = 0;
1627 mmc_request_done(mmc, req);
1628 return;
1629 } else if (host->reqs_blocked)
1630 host->reqs_blocked = 0;
1631 WARN_ON(host->mrq != NULL);
1632 host->mrq = req;
1633 err = omap_hsmmc_prepare_data(host, req);
1634 if (err) {
1635 req->cmd->error = err;
1636 if (req->data)
1637 req->data->error = err;
1638 host->mrq = NULL;
1639 mmc_request_done(mmc, req);
1640 return;
1641 }
1643 omap_hsmmc_start_command(host, req->cmd, req->data);
1644 }
1646 /* Routine to configure clock values. Exposed API to core */
1647 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1648 {
1649 struct omap_hsmmc_host *host = mmc_priv(mmc);
1650 int do_send_init_stream = 0;
1652 pm_runtime_get_sync(host->dev);
1654 if (ios->power_mode != host->power_mode) {
1655 switch (ios->power_mode) {
1656 case MMC_POWER_OFF:
1657 mmc_slot(host).set_power(host->dev, host->slot_id,
1658 0, 0);
1659 host->vdd = 0;
1660 break;
1661 case MMC_POWER_UP:
1662 mmc_slot(host).set_power(host->dev, host->slot_id,
1663 1, ios->vdd);
1664 host->vdd = ios->vdd;
1665 break;
1666 case MMC_POWER_ON:
1667 do_send_init_stream = 1;
1668 break;
1669 }
1670 host->power_mode = ios->power_mode;
1671 }
1673 /* FIXME: set registers based only on changes to ios */
1675 omap_hsmmc_set_bus_width(host);
1677 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1678 /* Only MMC1 can interface at 3V without some flavor
1679 * of external transceiver; but they all handle 1.8V.
1680 */
1681 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1682 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1683 /*
1684 * The mmc_select_voltage fn of the core does
1685 * not seem to set the power_mode to
1686 * MMC_POWER_UP upon recalculating the voltage.
1687 * vdd 1.8v.
1688 */
1689 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1690 dev_dbg(mmc_dev(host->mmc),
1691 "Switch operation failed\n");
1692 }
1693 }
1695 omap_hsmmc_set_clock(host);
1697 if (do_send_init_stream)
1698 send_init_stream(host);
1700 omap_hsmmc_set_bus_mode(host);
1702 pm_runtime_put_autosuspend(host->dev);
1703 }
1705 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1706 {
1707 struct omap_hsmmc_host *host = mmc_priv(mmc);
1709 if (!mmc_slot(host).card_detect)
1710 return -ENOSYS;
1711 return mmc_slot(host).card_detect(host->dev, host->slot_id);
1712 }
1714 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1715 {
1716 struct omap_hsmmc_host *host = mmc_priv(mmc);
1718 if (!mmc_slot(host).get_ro)
1719 return -ENOSYS;
1720 return mmc_slot(host).get_ro(host->dev, 0);
1721 }
1723 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1724 {
1725 struct omap_hsmmc_host *host = mmc_priv(mmc);
1727 if (mmc_slot(host).init_card)
1728 mmc_slot(host).init_card(card);
1729 }
1731 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1732 {
1733 u32 hctl, capa, value;
1735 /* Only MMC1 supports 3.0V */
1736 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1737 hctl = SDVS30;
1738 capa = VS30 | VS18;
1739 } else {
1740 hctl = SDVS18;
1741 capa = VS18;
1742 }
1744 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1745 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1747 value = OMAP_HSMMC_READ(host->base, CAPA);
1748 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1750 /* Set the controller to AUTO IDLE mode */
1751 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1752 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1754 /* Set SD bus power bit */
1755 set_sd_bus_power(host);
1756 }
1758 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1759 {
1760 struct omap_hsmmc_host *host = mmc_priv(mmc);
1762 pm_runtime_get_sync(host->dev);
1764 return 0;
1765 }
1767 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1768 {
1769 struct omap_hsmmc_host *host = mmc_priv(mmc);
1771 pm_runtime_mark_last_busy(host->dev);
1772 pm_runtime_put_autosuspend(host->dev);
1774 return 0;
1775 }
1777 static const struct mmc_host_ops omap_hsmmc_ops = {
1778 .enable = omap_hsmmc_enable_fclk,
1779 .disable = omap_hsmmc_disable_fclk,
1780 .post_req = omap_hsmmc_post_req,
1781 .pre_req = omap_hsmmc_pre_req,
1782 .request = omap_hsmmc_request,
1783 .set_ios = omap_hsmmc_set_ios,
1784 .get_cd = omap_hsmmc_get_cd,
1785 .get_ro = omap_hsmmc_get_ro,
1786 .init_card = omap_hsmmc_init_card,
1787 /* NYET -- enable_sdio_irq */
1788 };
1790 #ifdef CONFIG_DEBUG_FS
1792 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1793 {
1794 struct mmc_host *mmc = s->private;
1795 struct omap_hsmmc_host *host = mmc_priv(mmc);
1796 int context_loss = 0;
1798 if (host->pdata->get_context_loss_count)
1799 context_loss = host->pdata->get_context_loss_count(host->dev);
1801 seq_printf(s, "mmc%d:\n"
1802 " enabled:\t%d\n"
1803 " dpm_state:\t%d\n"
1804 " nesting_cnt:\t%d\n"
1805 " ctx_loss:\t%d:%d\n"
1806 "\nregs:\n",
1807 mmc->index, mmc->enabled ? 1 : 0,
1808 host->dpm_state, mmc->nesting_cnt,
1809 host->context_loss, context_loss);
1811 if (host->suspended) {
1812 seq_printf(s, "host suspended, can't read registers\n");
1813 return 0;
1814 }
1816 pm_runtime_get_sync(host->dev);
1818 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1819 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1820 seq_printf(s, "CON:\t\t0x%08x\n",
1821 OMAP_HSMMC_READ(host->base, CON));
1822 seq_printf(s, "HCTL:\t\t0x%08x\n",
1823 OMAP_HSMMC_READ(host->base, HCTL));
1824 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1825 OMAP_HSMMC_READ(host->base, SYSCTL));
1826 seq_printf(s, "IE:\t\t0x%08x\n",
1827 OMAP_HSMMC_READ(host->base, IE));
1828 seq_printf(s, "ISE:\t\t0x%08x\n",
1829 OMAP_HSMMC_READ(host->base, ISE));
1830 seq_printf(s, "CAPA:\t\t0x%08x\n",
1831 OMAP_HSMMC_READ(host->base, CAPA));
1833 pm_runtime_mark_last_busy(host->dev);
1834 pm_runtime_put_autosuspend(host->dev);
1836 return 0;
1837 }
1839 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1840 {
1841 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1842 }
1844 static const struct file_operations mmc_regs_fops = {
1845 .open = omap_hsmmc_regs_open,
1846 .read = seq_read,
1847 .llseek = seq_lseek,
1848 .release = single_release,
1849 };
1851 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1852 {
1853 if (mmc->debugfs_root)
1854 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1855 mmc, &mmc_regs_fops);
1856 }
1858 #else
1860 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1861 {
1862 }
1864 #endif
1866 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1867 {
1868 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1869 struct mmc_host *mmc;
1870 struct omap_hsmmc_host *host = NULL;
1871 struct resource *res;
1872 int ret, irq;
1874 if (pdata == NULL) {
1875 dev_err(&pdev->dev, "Platform Data is missing\n");
1876 return -ENXIO;
1877 }
1879 if (pdata->nr_slots == 0) {
1880 dev_err(&pdev->dev, "No Slots\n");
1881 return -ENXIO;
1882 }
1884 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1885 irq = platform_get_irq(pdev, 0);
1886 if (res == NULL || irq < 0)
1887 return -ENXIO;
1889 res->start += pdata->reg_offset;
1890 res->end += pdata->reg_offset;
1891 res = request_mem_region(res->start, resource_size(res), pdev->name);
1892 if (res == NULL)
1893 return -EBUSY;
1895 ret = omap_hsmmc_gpio_init(pdata);
1896 if (ret)
1897 goto err;
1899 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1900 if (!mmc) {
1901 ret = -ENOMEM;
1902 goto err_alloc;
1903 }
1905 host = mmc_priv(mmc);
1906 host->mmc = mmc;
1907 host->pdata = pdata;
1908 host->dev = &pdev->dev;
1909 host->use_dma = 1;
1910 host->dev->dma_mask = &pdata->dma_mask;
1911 host->dma_ch = -1;
1912 host->irq = irq;
1913 host->id = pdev->id;
1914 host->slot_id = 0;
1915 host->mapbase = res->start;
1916 host->base = ioremap(host->mapbase, SZ_4K);
1917 host->power_mode = MMC_POWER_OFF;
1918 host->next_data.cookie = 1;
1920 platform_set_drvdata(pdev, host);
1921 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
1923 mmc->ops = &omap_hsmmc_ops;
1925 /*
1926 * If regulator_disable can only put vcc_aux to sleep then there is
1927 * no off state.
1928 */
1929 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1930 mmc_slot(host).no_off = 1;
1932 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1933 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1935 spin_lock_init(&host->irq_lock);
1937 host->fclk = clk_get(&pdev->dev, "fck");
1938 if (IS_ERR(host->fclk)) {
1939 ret = PTR_ERR(host->fclk);
1940 host->fclk = NULL;
1941 goto err1;
1942 }
1944 omap_hsmmc_context_save(host);
1946 mmc->caps |= MMC_CAP_DISABLE;
1947 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1948 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1949 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1950 }
1952 pm_runtime_enable(host->dev);
1953 pm_runtime_get_sync(host->dev);
1954 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1955 pm_runtime_use_autosuspend(host->dev);
1957 if (cpu_is_omap2430()) {
1958 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1959 /*
1960 * MMC can still work without debounce clock.
1961 */
1962 if (IS_ERR(host->dbclk))
1963 dev_warn(mmc_dev(host->mmc),
1964 "Failed to get debounce clock\n");
1965 else
1966 host->got_dbclk = 1;
1968 if (host->got_dbclk)
1969 if (clk_enable(host->dbclk) != 0)
1970 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1971 " clk failed\n");
1972 }
1974 /* Since we do only SG emulation, we can have as many segs
1975 * as we want. */
1976 mmc->max_segs = 1024;
1978 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1979 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1980 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1981 mmc->max_seg_size = mmc->max_req_size;
1983 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1984 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1986 mmc->caps |= mmc_slot(host).caps;
1987 if (mmc->caps & MMC_CAP_8_BIT_DATA)
1988 mmc->caps |= MMC_CAP_4_BIT_DATA;
1990 if (mmc_slot(host).nonremovable)
1991 mmc->caps |= MMC_CAP_NONREMOVABLE;
1993 mmc->pm_caps = mmc_slot(host).pm_caps;
1995 omap_hsmmc_conf_bus_power(host);
1997 /* Select DMA lines */
1998 switch (host->id) {
1999 case OMAP_MMC1_DEVID:
2000 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2001 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2002 break;
2003 case OMAP_MMC2_DEVID:
2004 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2005 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2006 break;
2007 case OMAP_MMC3_DEVID:
2008 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2009 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2010 break;
2011 case OMAP_MMC4_DEVID:
2012 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2013 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2014 break;
2015 case OMAP_MMC5_DEVID:
2016 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2017 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2018 break;
2019 default:
2020 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2021 goto err_irq;
2022 }
2024 /* Request IRQ for MMC operations */
2025 ret = request_irq(host->irq, omap_hsmmc_irq, 0,
2026 mmc_hostname(mmc), host);
2027 if (ret) {
2028 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2029 goto err_irq;
2030 }
2032 if (pdata->init != NULL) {
2033 if (pdata->init(&pdev->dev) != 0) {
2034 dev_dbg(mmc_dev(host->mmc),
2035 "Unable to configure MMC IRQs\n");
2036 goto err_irq_cd_init;
2037 }
2038 }
2040 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2041 ret = omap_hsmmc_reg_get(host);
2042 if (ret)
2043 goto err_reg;
2044 host->use_reg = 1;
2045 }
2047 mmc->ocr_avail = mmc_slot(host).ocr_mask;
2049 /* Request IRQ for card detect */
2050 if ((mmc_slot(host).card_detect_irq)) {
2051 ret = request_irq(mmc_slot(host).card_detect_irq,
2052 omap_hsmmc_cd_handler,
2053 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
2054 mmc_hostname(mmc), host);
2055 if (ret) {
2056 dev_dbg(mmc_dev(host->mmc),
2057 "Unable to grab MMC CD IRQ\n");
2058 goto err_irq_cd;
2059 }
2060 pdata->suspend = omap_hsmmc_suspend_cdirq;
2061 pdata->resume = omap_hsmmc_resume_cdirq;
2062 }
2064 omap_hsmmc_disable_irq(host);
2066 omap_hsmmc_protect_card(host);
2068 mmc_add_host(mmc);
2070 if (mmc_slot(host).name != NULL) {
2071 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2072 if (ret < 0)
2073 goto err_slot_name;
2074 }
2075 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2076 ret = device_create_file(&mmc->class_dev,
2077 &dev_attr_cover_switch);
2078 if (ret < 0)
2079 goto err_slot_name;
2080 }
2082 omap_hsmmc_debugfs(mmc);
2083 pm_runtime_mark_last_busy(host->dev);
2084 pm_runtime_put_autosuspend(host->dev);
2086 return 0;
2088 err_slot_name:
2089 mmc_remove_host(mmc);
2090 free_irq(mmc_slot(host).card_detect_irq, host);
2091 err_irq_cd:
2092 if (host->use_reg)
2093 omap_hsmmc_reg_put(host);
2094 err_reg:
2095 if (host->pdata->cleanup)
2096 host->pdata->cleanup(&pdev->dev);
2097 err_irq_cd_init:
2098 free_irq(host->irq, host);
2099 err_irq:
2100 pm_runtime_mark_last_busy(host->dev);
2101 pm_runtime_put_autosuspend(host->dev);
2102 clk_put(host->fclk);
2103 if (host->got_dbclk) {
2104 clk_disable(host->dbclk);
2105 clk_put(host->dbclk);
2106 }
2107 err1:
2108 iounmap(host->base);
2109 platform_set_drvdata(pdev, NULL);
2110 mmc_free_host(mmc);
2111 err_alloc:
2112 omap_hsmmc_gpio_free(pdata);
2113 err:
2114 release_mem_region(res->start, resource_size(res));
2115 return ret;
2116 }
2118 static int omap_hsmmc_remove(struct platform_device *pdev)
2119 {
2120 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2121 struct resource *res;
2123 if (host) {
2124 pm_runtime_get_sync(host->dev);
2125 mmc_remove_host(host->mmc);
2126 if (host->use_reg)
2127 omap_hsmmc_reg_put(host);
2128 if (host->pdata->cleanup)
2129 host->pdata->cleanup(&pdev->dev);
2130 free_irq(host->irq, host);
2131 if (mmc_slot(host).card_detect_irq)
2132 free_irq(mmc_slot(host).card_detect_irq, host);
2133 flush_work_sync(&host->mmc_carddetect_work);
2135 pm_runtime_put_sync(host->dev);
2136 pm_runtime_disable(host->dev);
2137 clk_put(host->fclk);
2138 if (host->got_dbclk) {
2139 clk_disable(host->dbclk);
2140 clk_put(host->dbclk);
2141 }
2143 mmc_free_host(host->mmc);
2144 iounmap(host->base);
2145 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2146 }
2148 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2149 if (res)
2150 release_mem_region(res->start, resource_size(res));
2151 platform_set_drvdata(pdev, NULL);
2153 return 0;
2154 }
2156 #ifdef CONFIG_PM
2157 static int omap_hsmmc_suspend(struct device *dev)
2158 {
2159 int ret = 0;
2160 struct platform_device *pdev = to_platform_device(dev);
2161 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2163 if (host && host->suspended)
2164 return 0;
2166 if (host) {
2167 pm_runtime_get_sync(host->dev);
2168 host->suspended = 1;
2169 if (host->pdata->suspend) {
2170 ret = host->pdata->suspend(&pdev->dev,
2171 host->slot_id);
2172 if (ret) {
2173 dev_dbg(mmc_dev(host->mmc),
2174 "Unable to handle MMC board"
2175 " level suspend\n");
2176 host->suspended = 0;
2177 return ret;
2178 }
2179 }
2180 cancel_work_sync(&host->mmc_carddetect_work);
2181 ret = mmc_suspend_host(host->mmc);
2183 if (ret) {
2184 host->suspended = 0;
2185 if (host->pdata->resume) {
2186 ret = host->pdata->resume(&pdev->dev,
2187 host->slot_id);
2188 if (ret)
2189 dev_dbg(mmc_dev(host->mmc),
2190 "Unmask interrupt failed\n");
2191 }
2192 goto err;
2193 }
2195 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2196 omap_hsmmc_disable_irq(host);
2197 OMAP_HSMMC_WRITE(host->base, HCTL,
2198 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2199 }
2200 if (host->got_dbclk)
2201 clk_disable(host->dbclk);
2203 }
2204 err:
2205 pm_runtime_put_sync(host->dev);
2206 return ret;
2207 }
2209 /* Routine to resume the MMC device */
2210 static int omap_hsmmc_resume(struct device *dev)
2211 {
2212 int ret = 0;
2213 struct platform_device *pdev = to_platform_device(dev);
2214 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2216 if (host && !host->suspended)
2217 return 0;
2219 if (host) {
2220 pm_runtime_get_sync(host->dev);
2222 if (host->got_dbclk)
2223 clk_enable(host->dbclk);
2225 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2226 omap_hsmmc_conf_bus_power(host);
2228 if (host->pdata->resume) {
2229 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2230 if (ret)
2231 dev_dbg(mmc_dev(host->mmc),
2232 "Unmask interrupt failed\n");
2233 }
2235 omap_hsmmc_protect_card(host);
2237 /* Notify the core to resume the host */
2238 ret = mmc_resume_host(host->mmc);
2239 if (ret == 0)
2240 host->suspended = 0;
2242 pm_runtime_mark_last_busy(host->dev);
2243 pm_runtime_put_autosuspend(host->dev);
2244 }
2246 return ret;
2248 }
2250 #else
2251 #define omap_hsmmc_suspend NULL
2252 #define omap_hsmmc_resume NULL
2253 #endif
2255 static int omap_hsmmc_runtime_suspend(struct device *dev)
2256 {
2257 struct omap_hsmmc_host *host;
2259 host = platform_get_drvdata(to_platform_device(dev));
2260 omap_hsmmc_context_save(host);
2261 dev_dbg(mmc_dev(host->mmc), "disabled\n");
2263 return 0;
2264 }
2266 static int omap_hsmmc_runtime_resume(struct device *dev)
2267 {
2268 struct omap_hsmmc_host *host;
2270 host = platform_get_drvdata(to_platform_device(dev));
2271 omap_hsmmc_context_restore(host);
2272 dev_dbg(mmc_dev(host->mmc), "enabled\n");
2274 return 0;
2275 }
2277 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2278 .suspend = omap_hsmmc_suspend,
2279 .resume = omap_hsmmc_resume,
2280 .runtime_suspend = omap_hsmmc_runtime_suspend,
2281 .runtime_resume = omap_hsmmc_runtime_resume,
2282 };
2284 static struct platform_driver omap_hsmmc_driver = {
2285 .remove = omap_hsmmc_remove,
2286 .driver = {
2287 .name = DRIVER_NAME,
2288 .owner = THIS_MODULE,
2289 .pm = &omap_hsmmc_dev_pm_ops,
2290 },
2291 };
2293 static int __init omap_hsmmc_init(void)
2294 {
2295 /* Register the MMC driver */
2296 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2297 }
2299 static void __exit omap_hsmmc_cleanup(void)
2300 {
2301 /* Unregister MMC driver */
2302 platform_driver_unregister(&omap_hsmmc_driver);
2303 }
2305 module_init(omap_hsmmc_init);
2306 module_exit(omap_hsmmc_cleanup);
2308 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2309 MODULE_LICENSE("GPL");
2310 MODULE_ALIAS("platform:" DRIVER_NAME);
2311 MODULE_AUTHOR("Texas Instruments Inc");