1 /*
2 * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
3 * Copyright © 2004 Micron Technology Inc.
4 * Copyright © 2004 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
11 #include <linux/platform_device.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/delay.h>
14 #include <linux/module.h>
15 #include <linux/interrupt.h>
16 #include <linux/jiffies.h>
17 #include <linux/sched.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/nand.h>
20 #include <linux/mtd/partitions.h>
21 #include <linux/io.h>
22 #include <linux/slab.h>
24 #include <plat/dma.h>
25 #include <plat/gpmc.h>
26 #include <plat/nand.h>
27 #include <plat/elm.h>
29 #define DRIVER_NAME "omap2-nand"
30 #define OMAP_NAND_TIMEOUT_MS 5000
32 #define NAND_Ecc_P1e (1 << 0)
33 #define NAND_Ecc_P2e (1 << 1)
34 #define NAND_Ecc_P4e (1 << 2)
35 #define NAND_Ecc_P8e (1 << 3)
36 #define NAND_Ecc_P16e (1 << 4)
37 #define NAND_Ecc_P32e (1 << 5)
38 #define NAND_Ecc_P64e (1 << 6)
39 #define NAND_Ecc_P128e (1 << 7)
40 #define NAND_Ecc_P256e (1 << 8)
41 #define NAND_Ecc_P512e (1 << 9)
42 #define NAND_Ecc_P1024e (1 << 10)
43 #define NAND_Ecc_P2048e (1 << 11)
45 #define NAND_Ecc_P1o (1 << 16)
46 #define NAND_Ecc_P2o (1 << 17)
47 #define NAND_Ecc_P4o (1 << 18)
48 #define NAND_Ecc_P8o (1 << 19)
49 #define NAND_Ecc_P16o (1 << 20)
50 #define NAND_Ecc_P32o (1 << 21)
51 #define NAND_Ecc_P64o (1 << 22)
52 #define NAND_Ecc_P128o (1 << 23)
53 #define NAND_Ecc_P256o (1 << 24)
54 #define NAND_Ecc_P512o (1 << 25)
55 #define NAND_Ecc_P1024o (1 << 26)
56 #define NAND_Ecc_P2048o (1 << 27)
58 #define TF(value) (value ? 1 : 0)
60 #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
61 #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
62 #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
63 #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
64 #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
65 #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
66 #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
67 #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
69 #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
70 #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
71 #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
72 #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
73 #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
74 #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
75 #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
76 #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
78 #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
79 #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
80 #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
81 #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
82 #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
83 #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
84 #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
85 #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
87 #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
88 #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
89 #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
90 #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
91 #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
92 #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
93 #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
94 #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
96 #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
97 #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
99 #define MAX_HWECC_BYTES_OOB_64 24
100 #define JFFS2_CLEAN_MARKER_OFFSET 0x2
102 #define BCH_ECC_POS 0x2
103 #define BCH_JFFS2_CLEAN_MARKER_OFFSET 0x3a
104 #define OMAP_BCH8_ECC_SECT_BYTES 14
106 /* oob info generated runtime depending on ecc algorithm and layout selected */
107 static struct nand_ecclayout omap_oobinfo;
108 /* Define some generic bad / good block scan pattern which are used
109 * while scanning a device for factory marked good / bad blocks
110 */
111 static uint8_t scan_ff_pattern[] = { 0xff };
112 static struct nand_bbt_descr bb_descrip_flashbased = {
113 .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
114 .offs = 0,
115 .len = 1,
116 .pattern = scan_ff_pattern,
117 };
120 struct omap_nand_info {
121 struct nand_hw_control controller;
122 struct omap_nand_platform_data *pdata;
123 struct mtd_info mtd;
124 struct nand_chip nand;
125 struct platform_device *pdev;
127 int gpmc_cs;
128 unsigned long phys_base;
129 struct completion comp;
130 int dma_ch;
131 int gpmc_irq;
132 enum {
133 OMAP_NAND_IO_READ = 0, /* read */
134 OMAP_NAND_IO_WRITE, /* write */
135 } iomode;
136 u_char *buf;
137 int buf_len;
138 int ecc_opt;
139 };
141 /**
142 * omap_hwcontrol - hardware specific access to control-lines
143 * @mtd: MTD device structure
144 * @cmd: command to device
145 * @ctrl:
146 * NAND_NCE: bit 0 -> don't care
147 * NAND_CLE: bit 1 -> Command Latch
148 * NAND_ALE: bit 2 -> Address Latch
149 *
150 * NOTE: boards may use different bits for these!!
151 */
152 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
153 {
154 struct omap_nand_info *info = container_of(mtd,
155 struct omap_nand_info, mtd);
157 if (cmd != NAND_CMD_NONE) {
158 if (ctrl & NAND_CLE)
159 gpmc_nand_write(info->gpmc_cs, GPMC_NAND_COMMAND, cmd);
161 else if (ctrl & NAND_ALE)
162 gpmc_nand_write(info->gpmc_cs, GPMC_NAND_ADDRESS, cmd);
164 else /* NAND_NCE */
165 gpmc_nand_write(info->gpmc_cs, GPMC_NAND_DATA, cmd);
166 }
167 }
169 /**
170 * omap_read_buf8 - read data from NAND controller into buffer
171 * @mtd: MTD device structure
172 * @buf: buffer to store date
173 * @len: number of bytes to read
174 */
175 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
176 {
177 struct nand_chip *nand = mtd->priv;
179 ioread8_rep(nand->IO_ADDR_R, buf, len);
180 }
182 /**
183 * omap_write_buf8 - write buffer to NAND controller
184 * @mtd: MTD device structure
185 * @buf: data buffer
186 * @len: number of bytes to write
187 */
188 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
189 {
190 struct omap_nand_info *info = container_of(mtd,
191 struct omap_nand_info, mtd);
192 u_char *p = (u_char *)buf;
193 u32 status = 0;
195 while (len--) {
196 iowrite8(*p++, info->nand.IO_ADDR_W);
197 /* wait until buffer is available for write */
198 do {
199 status = gpmc_read_status(GPMC_STATUS_BUFFER);
200 } while (!status);
201 }
202 }
204 /**
205 * omap_read_buf16 - read data from NAND controller into buffer
206 * @mtd: MTD device structure
207 * @buf: buffer to store date
208 * @len: number of bytes to read
209 */
210 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
211 {
212 struct nand_chip *nand = mtd->priv;
214 ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
215 }
217 /**
218 * omap_write_buf16 - write buffer to NAND controller
219 * @mtd: MTD device structure
220 * @buf: data buffer
221 * @len: number of bytes to write
222 */
223 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
224 {
225 struct omap_nand_info *info = container_of(mtd,
226 struct omap_nand_info, mtd);
227 u16 *p = (u16 *) buf;
228 u32 status = 0;
229 /* FIXME try bursts of writesw() or DMA ... */
230 len >>= 1;
232 while (len--) {
233 iowrite16(*p++, info->nand.IO_ADDR_W);
234 /* wait until buffer is available for write */
235 do {
236 status = gpmc_read_status(GPMC_STATUS_BUFFER);
237 } while (!status);
238 }
239 }
241 /**
242 * omap_read_buf_pref - read data from NAND controller into buffer
243 * @mtd: MTD device structure
244 * @buf: buffer to store date
245 * @len: number of bytes to read
246 */
247 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
248 {
249 struct omap_nand_info *info = container_of(mtd,
250 struct omap_nand_info, mtd);
251 uint32_t r_count = 0;
252 int ret = 0;
253 u32 *p = (u32 *)buf;
255 /* take care of subpage reads */
256 if (len % 4) {
257 if (info->nand.options & NAND_BUSWIDTH_16)
258 omap_read_buf16(mtd, buf, len % 4);
259 else
260 omap_read_buf8(mtd, buf, len % 4);
261 p = (u32 *) (buf + len % 4);
262 len -= len % 4;
263 }
265 /* configure and start prefetch transfer */
266 ret = gpmc_prefetch_enable(info->gpmc_cs,
267 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0);
268 if (ret) {
269 /* PFPW engine is busy, use cpu copy method */
270 if (info->nand.options & NAND_BUSWIDTH_16)
271 omap_read_buf16(mtd, (u_char *)p, len);
272 else
273 omap_read_buf8(mtd, (u_char *)p, len);
274 } else {
275 do {
276 r_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
277 r_count = r_count >> 2;
278 ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
279 p += r_count;
280 len -= r_count << 2;
281 } while (len);
282 /* disable and stop the PFPW engine */
283 gpmc_prefetch_reset(info->gpmc_cs);
284 }
285 }
287 /**
288 * omap_write_buf_pref - write buffer to NAND controller
289 * @mtd: MTD device structure
290 * @buf: data buffer
291 * @len: number of bytes to write
292 */
293 static void omap_write_buf_pref(struct mtd_info *mtd,
294 const u_char *buf, int len)
295 {
296 struct omap_nand_info *info = container_of(mtd,
297 struct omap_nand_info, mtd);
298 uint32_t w_count = 0;
299 int i = 0, ret = 0;
300 u16 *p = (u16 *)buf;
301 unsigned long tim, limit;
303 /* take care of subpage writes */
304 if (len % 2 != 0) {
305 writeb(*buf, info->nand.IO_ADDR_W);
306 p = (u16 *)(buf + 1);
307 len--;
308 }
310 /* configure and start prefetch transfer */
311 ret = gpmc_prefetch_enable(info->gpmc_cs,
312 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1);
313 if (ret) {
314 /* PFPW engine is busy, use cpu copy method */
315 if (info->nand.options & NAND_BUSWIDTH_16)
316 omap_write_buf16(mtd, (u_char *)p, len);
317 else
318 omap_write_buf8(mtd, (u_char *)p, len);
319 } else {
320 while (len) {
321 w_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
322 w_count = w_count >> 1;
323 for (i = 0; (i < w_count) && len; i++, len -= 2)
324 iowrite16(*p++, info->nand.IO_ADDR_W);
325 }
326 /* wait for data to flushed-out before reset the prefetch */
327 tim = 0;
328 limit = (loops_per_jiffy *
329 msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
330 while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
331 cpu_relax();
333 /* disable and stop the PFPW engine */
334 gpmc_prefetch_reset(info->gpmc_cs);
335 }
336 }
338 /*
339 * omap_nand_dma_cb: callback on the completion of dma transfer
340 * @lch: logical channel
341 * @ch_satuts: channel status
342 * @data: pointer to completion data structure
343 */
344 static void omap_nand_dma_cb(int lch, u16 ch_status, void *data)
345 {
346 complete((struct completion *) data);
347 }
349 /*
350 * omap_nand_dma_transfer: configer and start dma transfer
351 * @mtd: MTD device structure
352 * @addr: virtual address in RAM of source/destination
353 * @len: number of data bytes to be transferred
354 * @is_write: flag for read/write operation
355 */
356 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
357 unsigned int len, int is_write)
358 {
359 struct omap_nand_info *info = container_of(mtd,
360 struct omap_nand_info, mtd);
361 enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
362 DMA_FROM_DEVICE;
363 dma_addr_t dma_addr;
364 int ret;
365 unsigned long tim, limit;
367 /* The fifo depth is 64 bytes max.
368 * But configure the FIFO-threahold to 32 to get a sync at each frame
369 * and frame length is 32 bytes.
370 */
371 int buf_len = len >> 6;
373 if (addr >= high_memory) {
374 struct page *p1;
376 if (((size_t)addr & PAGE_MASK) !=
377 ((size_t)(addr + len - 1) & PAGE_MASK))
378 goto out_copy;
379 p1 = vmalloc_to_page(addr);
380 if (!p1)
381 goto out_copy;
382 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
383 }
385 dma_addr = dma_map_single(&info->pdev->dev, addr, len, dir);
386 if (dma_mapping_error(&info->pdev->dev, dma_addr)) {
387 dev_err(&info->pdev->dev,
388 "Couldn't DMA map a %d byte buffer\n", len);
389 goto out_copy;
390 }
392 if (is_write) {
393 omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
394 info->phys_base, 0, 0);
395 omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
396 dma_addr, 0, 0);
397 omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
398 0x10, buf_len, OMAP_DMA_SYNC_FRAME,
399 OMAP24XX_DMA_GPMC, OMAP_DMA_DST_SYNC);
400 } else {
401 omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
402 info->phys_base, 0, 0);
403 omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
404 dma_addr, 0, 0);
405 omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
406 0x10, buf_len, OMAP_DMA_SYNC_FRAME,
407 OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC);
408 }
409 /* configure and start prefetch transfer */
410 ret = gpmc_prefetch_enable(info->gpmc_cs,
411 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write);
412 if (ret)
413 /* PFPW engine is busy, use cpu copy method */
414 goto out_copy;
416 init_completion(&info->comp);
418 omap_start_dma(info->dma_ch);
420 /* setup and start DMA using dma_addr */
421 wait_for_completion(&info->comp);
422 tim = 0;
423 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
424 while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
425 cpu_relax();
427 /* disable and stop the PFPW engine */
428 gpmc_prefetch_reset(info->gpmc_cs);
430 dma_unmap_single(&info->pdev->dev, dma_addr, len, dir);
431 return 0;
433 out_copy:
434 if (info->nand.options & NAND_BUSWIDTH_16)
435 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
436 : omap_write_buf16(mtd, (u_char *) addr, len);
437 else
438 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
439 : omap_write_buf8(mtd, (u_char *) addr, len);
440 return 0;
441 }
443 /**
444 * omap_read_buf_dma_pref - read data from NAND controller into buffer
445 * @mtd: MTD device structure
446 * @buf: buffer to store date
447 * @len: number of bytes to read
448 */
449 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
450 {
451 if (len <= mtd->oobsize)
452 omap_read_buf_pref(mtd, buf, len);
453 else
454 /* start transfer in DMA mode */
455 omap_nand_dma_transfer(mtd, buf, len, 0x0);
456 }
458 /**
459 * omap_write_buf_dma_pref - write buffer to NAND controller
460 * @mtd: MTD device structure
461 * @buf: data buffer
462 * @len: number of bytes to write
463 */
464 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
465 const u_char *buf, int len)
466 {
467 if (len <= mtd->oobsize)
468 omap_write_buf_pref(mtd, buf, len);
469 else
470 /* start transfer in DMA mode */
471 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
472 }
474 /*
475 * omap_nand_irq - GMPC irq handler
476 * @this_irq: gpmc irq number
477 * @dev: omap_nand_info structure pointer is passed here
478 */
479 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
480 {
481 struct omap_nand_info *info = (struct omap_nand_info *) dev;
482 u32 bytes;
483 u32 irq_stat;
485 irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS);
486 bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
487 bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
488 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
489 if (irq_stat & 0x2)
490 goto done;
492 if (info->buf_len && (info->buf_len < bytes))
493 bytes = info->buf_len;
494 else if (!info->buf_len)
495 bytes = 0;
496 iowrite32_rep(info->nand.IO_ADDR_W,
497 (u32 *)info->buf, bytes >> 2);
498 info->buf = info->buf + bytes;
499 info->buf_len -= bytes;
501 } else {
502 ioread32_rep(info->nand.IO_ADDR_R,
503 (u32 *)info->buf, bytes >> 2);
504 info->buf = info->buf + bytes;
506 if (irq_stat & 0x2)
507 goto done;
508 }
509 gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
511 return IRQ_HANDLED;
513 done:
514 complete(&info->comp);
515 /* disable irq */
516 gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0);
518 /* clear status */
519 gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
521 return IRQ_HANDLED;
522 }
524 /*
525 * omap_read_buf_irq_pref - read data from NAND controller into buffer
526 * @mtd: MTD device structure
527 * @buf: buffer to store date
528 * @len: number of bytes to read
529 */
530 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
531 {
532 struct omap_nand_info *info = container_of(mtd,
533 struct omap_nand_info, mtd);
534 int ret = 0;
536 if (len <= mtd->oobsize) {
537 omap_read_buf_pref(mtd, buf, len);
538 return;
539 }
541 info->iomode = OMAP_NAND_IO_READ;
542 info->buf = buf;
543 init_completion(&info->comp);
545 /* configure and start prefetch transfer */
546 ret = gpmc_prefetch_enable(info->gpmc_cs,
547 PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0);
548 if (ret)
549 /* PFPW engine is busy, use cpu copy method */
550 goto out_copy;
552 info->buf_len = len;
553 /* enable irq */
554 gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
555 (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
557 /* waiting for read to complete */
558 wait_for_completion(&info->comp);
560 /* disable and stop the PFPW engine */
561 gpmc_prefetch_reset(info->gpmc_cs);
562 return;
564 out_copy:
565 if (info->nand.options & NAND_BUSWIDTH_16)
566 omap_read_buf16(mtd, buf, len);
567 else
568 omap_read_buf8(mtd, buf, len);
569 }
571 /*
572 * omap_write_buf_irq_pref - write buffer to NAND controller
573 * @mtd: MTD device structure
574 * @buf: data buffer
575 * @len: number of bytes to write
576 */
577 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
578 const u_char *buf, int len)
579 {
580 struct omap_nand_info *info = container_of(mtd,
581 struct omap_nand_info, mtd);
582 int ret = 0;
583 unsigned long tim, limit;
585 if (len <= mtd->oobsize) {
586 omap_write_buf_pref(mtd, buf, len);
587 return;
588 }
590 info->iomode = OMAP_NAND_IO_WRITE;
591 info->buf = (u_char *) buf;
592 init_completion(&info->comp);
594 /* configure and start prefetch transfer : size=24 */
595 ret = gpmc_prefetch_enable(info->gpmc_cs,
596 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1);
597 if (ret)
598 /* PFPW engine is busy, use cpu copy method */
599 goto out_copy;
601 info->buf_len = len;
602 /* enable irq */
603 gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
604 (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
606 /* waiting for write to complete */
607 wait_for_completion(&info->comp);
608 /* wait for data to flushed-out before reset the prefetch */
609 tim = 0;
610 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
611 while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
612 cpu_relax();
614 /* disable and stop the PFPW engine */
615 gpmc_prefetch_reset(info->gpmc_cs);
616 return;
618 out_copy:
619 if (info->nand.options & NAND_BUSWIDTH_16)
620 omap_write_buf16(mtd, buf, len);
621 else
622 omap_write_buf8(mtd, buf, len);
623 }
625 /**
626 * omap_verify_buf - Verify chip data against buffer
627 * @mtd: MTD device structure
628 * @buf: buffer containing the data to compare
629 * @len: number of bytes to compare
630 */
631 static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
632 {
633 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
634 mtd);
635 u16 *p = (u16 *) buf;
637 len >>= 1;
638 while (len--) {
639 if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R)))
640 return -EFAULT;
641 }
643 return 0;
644 }
646 /**
647 * gen_true_ecc - This function will generate true ECC value
648 * @ecc_buf: buffer to store ecc code
649 *
650 * This generated true ECC value can be used when correcting
651 * data read from NAND flash memory core
652 */
653 static void gen_true_ecc(u8 *ecc_buf)
654 {
655 u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
656 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
658 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
659 P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
660 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
661 P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
662 ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
663 P1e(tmp) | P2048o(tmp) | P2048e(tmp));
664 }
666 /**
667 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
668 * @ecc_data1: ecc code from nand spare area
669 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
670 * @page_data: page data
671 *
672 * This function compares two ECC's and indicates if there is an error.
673 * If the error can be corrected it will be corrected to the buffer.
674 * If there is no error, %0 is returned. If there is an error but it
675 * was corrected, %1 is returned. Otherwise, %-1 is returned.
676 */
677 static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
678 u8 *ecc_data2, /* read from register */
679 u8 *page_data)
680 {
681 uint i;
682 u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
683 u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
684 u8 ecc_bit[24];
685 u8 ecc_sum = 0;
686 u8 find_bit = 0;
687 uint find_byte = 0;
688 int isEccFF;
690 isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
692 gen_true_ecc(ecc_data1);
693 gen_true_ecc(ecc_data2);
695 for (i = 0; i <= 2; i++) {
696 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
697 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
698 }
700 for (i = 0; i < 8; i++) {
701 tmp0_bit[i] = *ecc_data1 % 2;
702 *ecc_data1 = *ecc_data1 / 2;
703 }
705 for (i = 0; i < 8; i++) {
706 tmp1_bit[i] = *(ecc_data1 + 1) % 2;
707 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
708 }
710 for (i = 0; i < 8; i++) {
711 tmp2_bit[i] = *(ecc_data1 + 2) % 2;
712 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
713 }
715 for (i = 0; i < 8; i++) {
716 comp0_bit[i] = *ecc_data2 % 2;
717 *ecc_data2 = *ecc_data2 / 2;
718 }
720 for (i = 0; i < 8; i++) {
721 comp1_bit[i] = *(ecc_data2 + 1) % 2;
722 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
723 }
725 for (i = 0; i < 8; i++) {
726 comp2_bit[i] = *(ecc_data2 + 2) % 2;
727 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
728 }
730 for (i = 0; i < 6; i++)
731 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
733 for (i = 0; i < 8; i++)
734 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
736 for (i = 0; i < 8; i++)
737 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
739 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
740 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
742 for (i = 0; i < 24; i++)
743 ecc_sum += ecc_bit[i];
745 switch (ecc_sum) {
746 case 0:
747 /* Not reached because this function is not called if
748 * ECC values are equal
749 */
750 return 0;
752 case 1:
753 /* Uncorrectable error */
754 pr_debug("ECC UNCORRECTED_ERROR 1\n");
755 return -1;
757 case 11:
758 /* UN-Correctable error */
759 pr_debug("ECC UNCORRECTED_ERROR B\n");
760 return -1;
762 case 12:
763 /* Correctable error */
764 find_byte = (ecc_bit[23] << 8) +
765 (ecc_bit[21] << 7) +
766 (ecc_bit[19] << 6) +
767 (ecc_bit[17] << 5) +
768 (ecc_bit[15] << 4) +
769 (ecc_bit[13] << 3) +
770 (ecc_bit[11] << 2) +
771 (ecc_bit[9] << 1) +
772 ecc_bit[7];
774 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
776 pr_debug("Correcting single bit ECC error at offset: "
777 "%d, bit: %d\n", find_byte, find_bit);
779 page_data[find_byte] ^= (1 << find_bit);
781 return 1;
782 default:
783 if (isEccFF) {
784 if (ecc_data2[0] == 0 &&
785 ecc_data2[1] == 0 &&
786 ecc_data2[2] == 0)
787 return 0;
788 }
789 pr_debug("UNCORRECTED_ERROR default\n");
790 return -1;
791 }
792 }
794 /**
795 * omap_read_page_bch - BCH ecc based page read function
796 * @mtd: mtd info structure
797 * @chip: nand chip info structure
798 * @buf: buffer to store read data
799 * @page: page number to read
800 *
801 * For BCH ECC scheme, GPMC used for syndrome calculation and ELM module
802 * used for error correction.
803 */
804 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
805 uint8_t *buf, int page)
806 {
807 int i, eccsize = chip->ecc.size;
808 int eccbytes = chip->ecc.bytes;
809 int eccsteps = chip->ecc.steps;
810 uint8_t *p = buf;
811 uint8_t *ecc_calc = chip->buffers->ecccalc;
812 uint8_t *ecc_code = chip->buffers->ecccode;
813 uint32_t *eccpos = chip->ecc.layout->eccpos;
814 uint8_t *oob = &chip->oob_poi[eccpos[0]];
815 uint32_t data_pos;
816 uint32_t oob_pos;
818 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
819 mtd);
820 data_pos = 0;
821 /* oob area start */
822 oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0];
824 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
825 oob += eccbytes) {
826 chip->ecc.hwctl(mtd, NAND_ECC_READ);
827 /* read data */
828 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page);
829 chip->read_buf(mtd, p, eccsize);
831 /* read respective ecc from oob area */
832 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page);
834 if (info->ecc_opt == OMAP_ECC_BCH8_CODE_HW)
835 chip->read_buf(mtd, oob, 13);
836 else
837 chip->read_buf(mtd, oob, eccbytes);
838 /* read syndrome */
839 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
841 data_pos += eccsize;
842 oob_pos += eccbytes;
843 }
845 for (i = 0; i < chip->ecc.total; i++)
846 ecc_code[i] = chip->oob_poi[eccpos[i]];
848 eccsteps = chip->ecc.steps;
849 p = buf;
851 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
852 int stat;
854 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
856 if (stat < 0)
857 mtd->ecc_stats.failed++;
858 else
859 mtd->ecc_stats.corrected += stat;
860 }
861 return 0;
862 }
864 /**
865 * omap_correct_data - Compares the ECC read with HW generated ECC
866 * @mtd: MTD device structure
867 * @dat: page data
868 * @read_ecc: ecc read from nand flash
869 * @calc_ecc: ecc read from HW ECC registers
870 *
871 * Compares the ecc read from nand spare area with ECC registers values
872 * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
873 * detection and correction. If there are no errors, %0 is returned. If
874 * there were errors and all of the errors were corrected, the number of
875 * corrected errors is returned. If uncorrectable errors exist, %-1 is
876 * returned.
877 */
878 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
879 u_char *read_ecc, u_char *calc_ecc)
880 {
881 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
882 mtd);
883 int blockCnt = 0, i = 0, ret = 0;
884 int stat = 0;
885 int j, eccsize, eccflag, count;
886 unsigned int err_loc[8];
888 /* Ex NAND_ECC_HW12_2048 */
889 if ((info->nand.ecc.mode == NAND_ECC_HW) &&
890 (info->nand.ecc.size == 2048))
891 blockCnt = 4;
892 else
893 blockCnt = 1;
895 switch (info->ecc_opt) {
896 case OMAP_ECC_HAMMING_CODE_HW:
897 case OMAP_ECC_HAMMING_CODE_HW_ROMCODE:
898 for (i = 0; i < blockCnt; i++) {
899 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
900 ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
901 if (ret < 0)
902 return ret;
904 /* keep track of number of corrected errors */
905 stat += ret;
906 }
907 read_ecc += 3;
908 calc_ecc += 3;
909 dat += 512;
910 }
911 break;
912 case OMAP_ECC_BCH8_CODE_HW:
913 eccsize = BCH8_ECC_OOB_BYTES;
915 for (i = 0; i < blockCnt; i++) {
916 eccflag = 0;
917 /* check if area is flashed */
918 for (j = 0; (j < eccsize) && (eccflag == 0); j++)
919 if (read_ecc[j] != 0xFF)
920 eccflag = 1;
922 if (eccflag == 1) {
923 eccflag = 0;
924 /* check if any ecc error */
925 for (j = 0; (j < eccsize) && (eccflag == 0);
926 j++)
927 if (calc_ecc[j] != 0)
928 eccflag = 1;
929 }
931 count = 0;
932 if (eccflag == 1)
933 count = omap_elm_decode_bch_error(0, calc_ecc,
934 err_loc);
936 for (j = 0; j < count; j++) {
937 u32 bit_pos, byte_pos;
939 bit_pos = err_loc[j] % 8;
940 byte_pos = (BCH8_ECC_MAX - err_loc[j] - 1) / 8;
941 if (err_loc[j] < BCH8_ECC_MAX)
942 dat[byte_pos] ^=
943 1 << bit_pos;
944 /* else, not interested to correct ecc */
945 }
947 stat += count;
948 calc_ecc = calc_ecc + OMAP_BCH8_ECC_SECT_BYTES;
949 read_ecc = read_ecc + OMAP_BCH8_ECC_SECT_BYTES;
950 dat += BCH8_ECC_BYTES;
951 }
952 break;
953 }
954 return stat;
955 }
957 /**
958 * omap_calcuate_ecc - Generate non-inverted ECC bytes.
959 * @mtd: MTD device structure
960 * @dat: The pointer to data on which ecc is computed
961 * @ecc_code: The ecc_code buffer
962 *
963 * Using noninverted ECC can be considered ugly since writing a blank
964 * page ie. padding will clear the ECC bytes. This is no problem as long
965 * nobody is trying to write data on the seemingly unused page. Reading
966 * an erased page will produce an ECC mismatch between generated and read
967 * ECC bytes that has to be dealt with separately.
968 */
969 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
970 u_char *ecc_code)
971 {
972 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
973 mtd);
974 return gpmc_calculate_ecc(info->ecc_opt, info->gpmc_cs, dat, ecc_code);
975 }
977 /**
978 * omap_enable_hwecc - This function enables the hardware ecc functionality
979 * @mtd: MTD device structure
980 * @mode: Read/Write mode
981 */
982 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
983 {
984 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
985 mtd);
986 struct nand_chip *chip = mtd->priv;
987 unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
989 gpmc_enable_hwecc(info->ecc_opt, info->gpmc_cs, mode,
990 dev_width, info->nand.ecc.size);
991 }
993 /**
994 * omap_wait - wait until the command is done
995 * @mtd: MTD device structure
996 * @chip: NAND Chip structure
997 *
998 * Wait function is called during Program and erase operations and
999 * the way it is called from MTD layer, we should wait till the NAND
1000 * chip is ready after the programming/erase operation has completed.
1001 *
1002 * Erase can take up to 400ms and program up to 20ms according to
1003 * general NAND and SmartMedia specs
1004 */
1005 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
1006 {
1007 struct nand_chip *this = mtd->priv;
1008 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1009 mtd);
1010 unsigned long timeo = jiffies;
1011 int status = NAND_STATUS_FAIL, state = this->state;
1013 if (state == FL_ERASING)
1014 timeo += (HZ * 400) / 1000;
1015 else
1016 timeo += (HZ * 20) / 1000;
1018 gpmc_nand_write(info->gpmc_cs,
1019 GPMC_NAND_COMMAND, (NAND_CMD_STATUS & 0xFF));
1020 while (time_before(jiffies, timeo)) {
1021 status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA);
1022 if (status & NAND_STATUS_READY)
1023 break;
1024 cond_resched();
1025 }
1026 return status;
1027 }
1029 /**
1030 * omap_dev_ready - calls the platform specific dev_ready function
1031 * @mtd: MTD device structure
1032 */
1033 static int omap_dev_ready(struct mtd_info *mtd)
1034 {
1035 unsigned int val = 0;
1036 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1037 mtd);
1039 val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
1040 if ((val & 0x100) == 0x100) {
1041 /* Clear IRQ Interrupt */
1042 val |= 0x100;
1043 val &= ~(0x0);
1044 gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, val);
1045 } else {
1046 unsigned int cnt = 0;
1047 while (cnt++ < 0x1FF) {
1048 if ((val & 0x100) == 0x100)
1049 return 0;
1050 val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
1051 }
1052 }
1054 return 1;
1055 }
1057 static int __devinit omap_nand_probe(struct platform_device *pdev)
1058 {
1059 struct omap_nand_info *info;
1060 struct omap_nand_platform_data *pdata;
1061 int err;
1062 int i, offset;
1064 pdata = pdev->dev.platform_data;
1065 if (pdata == NULL) {
1066 dev_err(&pdev->dev, "platform data missing\n");
1067 return -ENODEV;
1068 }
1070 info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
1071 if (!info)
1072 return -ENOMEM;
1074 platform_set_drvdata(pdev, info);
1076 spin_lock_init(&info->controller.lock);
1077 init_waitqueue_head(&info->controller.wq);
1079 info->pdev = pdev;
1081 info->gpmc_cs = pdata->cs;
1082 info->phys_base = pdata->phys_base;
1084 info->mtd.priv = &info->nand;
1085 info->mtd.name = dev_name(&pdev->dev);
1086 info->mtd.owner = THIS_MODULE;
1087 info->ecc_opt = pdata->ecc_opt;
1089 info->nand.options = pdata->devsize;
1090 info->nand.options |= NAND_SKIP_BBTSCAN;
1092 /*
1093 * If ELM feature is used in OMAP NAND driver, then configure it
1094 */
1095 if (pdata->elm_used) {
1096 if (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)
1097 omap_configure_elm(&info->mtd, OMAP_BCH8_ECC);
1098 }
1100 /* NAND write protect off */
1101 gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0);
1103 if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
1104 pdev->dev.driver->name)) {
1105 err = -EBUSY;
1106 goto out_free_info;
1107 }
1109 info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
1110 if (!info->nand.IO_ADDR_R) {
1111 err = -ENOMEM;
1112 goto out_release_mem_region;
1113 }
1115 info->nand.controller = &info->controller;
1117 info->nand.IO_ADDR_W = info->nand.IO_ADDR_R;
1118 info->nand.cmd_ctrl = omap_hwcontrol;
1120 /*
1121 * If RDY/BSY line is connected to OMAP then use the omap ready
1122 * funcrtion and the generic nand_wait function which reads the status
1123 * register after monitoring the RDY/BSY line.Otherwise use a standard
1124 * chip delay which is slightly more than tR (AC Timing) of the NAND
1125 * device and read status register until you get a failure or success
1126 */
1127 if (pdata->dev_ready) {
1128 info->nand.dev_ready = omap_dev_ready;
1129 info->nand.chip_delay = 0;
1130 } else {
1131 info->nand.waitfunc = omap_wait;
1132 info->nand.chip_delay = 50;
1133 }
1135 switch (pdata->xfer_type) {
1136 case NAND_OMAP_PREFETCH_POLLED:
1137 info->nand.read_buf = omap_read_buf_pref;
1138 info->nand.write_buf = omap_write_buf_pref;
1139 break;
1141 case NAND_OMAP_POLLED:
1142 if (info->nand.options & NAND_BUSWIDTH_16) {
1143 info->nand.read_buf = omap_read_buf16;
1144 info->nand.write_buf = omap_write_buf16;
1145 } else {
1146 info->nand.read_buf = omap_read_buf8;
1147 info->nand.write_buf = omap_write_buf8;
1148 }
1149 break;
1151 case NAND_OMAP_PREFETCH_DMA:
1152 err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND",
1153 omap_nand_dma_cb, &info->comp, &info->dma_ch);
1154 if (err < 0) {
1155 info->dma_ch = -1;
1156 dev_err(&pdev->dev, "DMA request failed!\n");
1157 goto out_release_mem_region;
1158 } else {
1159 omap_set_dma_dest_burst_mode(info->dma_ch,
1160 OMAP_DMA_DATA_BURST_16);
1161 omap_set_dma_src_burst_mode(info->dma_ch,
1162 OMAP_DMA_DATA_BURST_16);
1164 info->nand.read_buf = omap_read_buf_dma_pref;
1165 info->nand.write_buf = omap_write_buf_dma_pref;
1166 }
1167 break;
1169 case NAND_OMAP_PREFETCH_IRQ:
1170 err = request_irq(pdata->gpmc_irq,
1171 omap_nand_irq, IRQF_SHARED, "gpmc-nand", info);
1172 if (err) {
1173 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1174 pdata->gpmc_irq, err);
1175 goto out_release_mem_region;
1176 } else {
1177 info->gpmc_irq = pdata->gpmc_irq;
1178 info->nand.read_buf = omap_read_buf_irq_pref;
1179 info->nand.write_buf = omap_write_buf_irq_pref;
1180 }
1181 break;
1183 default:
1184 dev_err(&pdev->dev,
1185 "xfer_type(%d) not supported!\n", pdata->xfer_type);
1186 err = -EINVAL;
1187 goto out_release_mem_region;
1188 }
1190 info->nand.verify_buf = omap_verify_buf;
1192 /* selsect the ecc type */
1193 if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
1194 info->nand.ecc.mode = NAND_ECC_SOFT;
1195 else {
1196 if (pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) {
1197 info->nand.ecc.bytes = 4*7;
1198 info->nand.ecc.size = 4*512;
1199 } else if (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW) {
1200 info->nand.ecc.bytes = OMAP_BCH8_ECC_SECT_BYTES;
1201 info->nand.ecc.size = 512;
1202 info->nand.ecc.read_page = omap_read_page_bch;
1203 } else {
1204 info->nand.ecc.bytes = 3;
1205 info->nand.ecc.size = 512;
1206 }
1208 info->nand.ecc.calculate = omap_calculate_ecc;
1209 info->nand.ecc.hwctl = omap_enable_hwecc;
1210 info->nand.ecc.correct = omap_correct_data;
1211 info->nand.ecc.mode = NAND_ECC_HW;
1212 }
1214 /* DIP switches on some boards change between 8 and 16 bit
1215 * bus widths for flash. Try the other width if the first try fails.
1216 */
1217 if (nand_scan_ident(&info->mtd, 1, NULL)) {
1218 info->nand.options ^= NAND_BUSWIDTH_16;
1219 if (nand_scan_ident(&info->mtd, 1, NULL)) {
1220 err = -ENXIO;
1221 goto out_release_mem_region;
1222 }
1223 }
1225 /* select ecc lyout */
1226 if (info->nand.ecc.mode != NAND_ECC_SOFT) {
1228 if (!(info->nand.options & NAND_BUSWIDTH_16))
1229 info->nand.badblock_pattern = &bb_descrip_flashbased;
1231 offset = JFFS2_CLEAN_MARKER_OFFSET;
1233 if (info->mtd.oobsize == 64)
1234 omap_oobinfo.eccbytes = info->nand.ecc.bytes *
1235 2048/info->nand.ecc.size;
1236 else
1237 omap_oobinfo.eccbytes = info->nand.ecc.bytes;
1239 if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
1240 omap_oobinfo.oobfree->offset =
1241 offset + omap_oobinfo.eccbytes;
1242 omap_oobinfo.oobfree->length = info->mtd.oobsize -
1243 (offset + omap_oobinfo.eccbytes);
1244 } else if (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW) {
1245 offset = BCH_ECC_POS; /* Synchronize with U-boot */
1246 omap_oobinfo.oobfree->offset =
1247 BCH_JFFS2_CLEAN_MARKER_OFFSET;
1248 omap_oobinfo.oobfree->length = info->mtd.oobsize -
1249 offset - omap_oobinfo.eccbytes;
1250 } else {
1251 omap_oobinfo.oobfree->offset = offset;
1252 omap_oobinfo.oobfree->length = info->mtd.oobsize -
1253 offset - omap_oobinfo.eccbytes;
1254 /*
1255 offset is calculated considering the following :
1256 1) 12 bytes ECC for 512 byte access and 24 bytes ECC for
1257 256 byte access in OOB_64 can be supported
1258 2)Ecc bytes lie to the end of OOB area.
1259 3)Ecc layout must match with u-boot's ECC layout.
1260 */
1261 offset = info->mtd.oobsize - MAX_HWECC_BYTES_OOB_64;
1262 }
1264 for (i = 0; i < omap_oobinfo.eccbytes; i++)
1265 omap_oobinfo.eccpos[i] = i+offset;
1267 info->nand.ecc.layout = &omap_oobinfo;
1268 }
1270 /* second phase scan */
1271 if (nand_scan_tail(&info->mtd)) {
1272 err = -ENXIO;
1273 goto out_release_mem_region;
1274 }
1276 mtd_device_parse_register(&info->mtd, NULL, 0,
1277 pdata->parts, pdata->nr_parts);
1279 platform_set_drvdata(pdev, &info->mtd);
1281 return 0;
1283 out_release_mem_region:
1284 release_mem_region(info->phys_base, NAND_IO_SIZE);
1285 out_free_info:
1286 kfree(info);
1288 return err;
1289 }
1291 static int omap_nand_remove(struct platform_device *pdev)
1292 {
1293 struct mtd_info *mtd = platform_get_drvdata(pdev);
1294 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1295 mtd);
1297 platform_set_drvdata(pdev, NULL);
1298 if (info->dma_ch != -1)
1299 omap_free_dma(info->dma_ch);
1301 if (info->gpmc_irq)
1302 free_irq(info->gpmc_irq, info);
1304 /* Release NAND device, its internal structures and partitions */
1305 nand_release(&info->mtd);
1306 iounmap(info->nand.IO_ADDR_R);
1307 release_mem_region(info->phys_base, NAND_IO_SIZE);
1308 kfree(&info->mtd);
1309 return 0;
1310 }
1312 static struct platform_driver omap_nand_driver = {
1313 .probe = omap_nand_probe,
1314 .remove = omap_nand_remove,
1315 .driver = {
1316 .name = DRIVER_NAME,
1317 .owner = THIS_MODULE,
1318 },
1319 };
1321 static int __init omap_nand_init(void)
1322 {
1323 pr_info("%s driver initializing\n", DRIVER_NAME);
1325 return platform_driver_register(&omap_nand_driver);
1326 }
1328 static void __exit omap_nand_exit(void)
1329 {
1330 platform_driver_unregister(&omap_nand_driver);
1331 }
1333 module_init(omap_nand_init);
1334 module_exit(omap_nand_exit);
1336 MODULE_ALIAS("platform:" DRIVER_NAME);
1337 MODULE_LICENSE("GPL");
1338 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");