1 /*
2 * eHRPWM driver for simple PWM output generation
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed .as is. WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/clk.h>
18 #include <linux/err.h>
19 #include <linux/io.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23 #include <linux/pwm/pwm.h>
24 #include <linux/pwm/ehrpwm.h>
25 #include <linux/pm_runtime.h>
27 #include <plat/clock.h>
28 #include <plat/config_pwm.h>
30 #ifdef DEBUG
31 #define debug(format, args...) printk(format, ##args)
32 #else
33 #define debug(format, args...) { }
34 #endif
36 /******************** Time base sub module*****************************/
37 #define TBCTL 0x0
38 #define TBSTS 0x2
39 #define TBPHS 0x6
40 #define TBCTR 0x8
41 #define TBPRD 0xA
43 #define TBCTL_CLKDIV_MASK (BIT(12) | BIT(11) | BIT(10))
44 #define TBCTL_HSPCLKDIV_MASK (BIT(9) | BIT(8) | BIT(7))
45 #define TBCTL_SYNCOSEL_MASK (BIT(5) | BIT(4))
46 #define TBCTL_CTRMODE_MASK (BIT(1) | BIT(0))
48 #define TBCTL_CLKDIV_POS 0xA
49 #define TBCTL_HSPCLKDIV_POS 0x7
50 #define TBCTL_PHSEN_POS 0x2
51 #define TBCTL_SYNCOSEL_POS 0x4
52 #define TBCTL_PHSDIR_POS 0xD
53 #define TBCTL_FRC_SYC_POS 0x6
54 #define TBCTL_LOAD_MD_POS 0x3
56 #define TBCTL_FREERUN_FREE 0x2
57 #define TBCTL_CTRMOD_CTRUP 0x0
59 /******************* Counter-Compare Sub Module ***********************/
60 #define CMPCTL 0xE
61 #define CMPA 0x12
62 #define CMPB 0x14
64 #define CMPCTL_LDBMODE_MASK (BIT(3) | BIT(2))
65 #define CMPCTL_LDAMODE_MASK (BIT(1) | BIT(0))
67 #define CMPCTL_SHDAMODE_POS 0x4
68 #define CMPCTL_SHDBMODE_POS 0x6
69 #define CMPCTL_LDBMODE_POS 0x2
71 /*********************** Action Control Sub module ********************/
72 #define AQCTLA 0x16
73 #define AQCTLB 0x18
74 #define AQSFRC 0x1A
75 #define AQCSFRC 0x1c
77 #define ACTCTL_CBD_MASK (BIT(11) | BIT(10))
78 #define ACTCTL_CBU_MASK (BIT(9) | BIT(8))
79 #define ACTCTL_CAD_MASK (BIT(7) | BIT(6))
80 #define ACTCTL_CAU_MASK (BIT(5) | BIT(4))
81 #define ACTCTL_CPRD_MASK (BIT(3) | BIT(2))
82 #define ACTCTL_CZRO_MASK (BIT(1) | BIT(0))
84 #define ACTCTL_CTREQPRD_POS 0x2
85 #define ACTCTL_CTREQCMPAUP_POS 0x4
86 #define ACTCTL_CTREQCMPADN_POS 0x6
87 #define ACTCTL_CTREQCMPBUP_POS 0x8
88 #define ACTCTL_CTREQCMPBDN_POS 0xA
90 #define ACTCTL_CTREQCMP_LOW 0x1
91 #define ACTCTL_CTREQCMP_HIGH 0x2
92 #define ACTCTL_CTREQZRO_LOW 0x1
93 #define ACTCTL_CTREQZRO_HIGH 0x2
95 #define AQSFRC_ACTA_MASK (BIT(1) | BIT(0))
96 #define AQSFRC_ACTB_MASK (BIT(4) | BIT(3))
97 #define AQCSFRC_CFRC_LOAD_MASK (BIT(7) | BIT(6))
98 #define AQCSFRC_OUTB_MASK (BIT(3) | BIT(2))
99 #define AQCSFRC_OUTA_MASK (BIT(1) | BIT(0))
101 #define AQSFRC_ACTB_POS 0x3
102 #define AQSFRC_OTFRCA_POS 0x2
103 #define AQSFRC_OTFRCB_POS 0x5
104 #define AQSFRC_LDMD_POS 0x6
106 #define AQCSFRC_OUTB_POS 0x2
108 /******************** Dead Band Generator Sub module *******************/
109 #define DBCTL 0x1E
110 #define DBRED 0x20
111 #define DBFED 0x22
113 #define DBCTL_INMODE_MASK (BIT(5) | BIT(4))
114 #define DBCTL_PLSEL_MASK (BIT(3) | BIT(2))
115 #define DBCTL_OUTMODE_MASK (BIT(1) | BIT(0))
117 #define DBCTL_INMODE_POS 0x4
118 #define DBCTL_POLSEL_POS 0x2
120 /********************** PWM Chopper Sub module ************************/
121 #define PCCTL 0x3C
123 #define PCCTL_CHPDUTY_MASK (BIT(10) | BIT(9) | BIT(8))
124 #define PCCTL_CHPFREQ_MASK (BIT(7) | BIT(6) | BIT(5))
125 #define PCCTL_OSHTWTH_MASK (BIT(4) | BIT(3) | BIT(2) | BIT(1))
127 #define PCCTL_CHPDUTY_POS 0x8
128 #define PCCTL_CHPFRQ_POS 0x5
129 #define PCCTL_OSTWID_POS 0x1
131 /*************************Trip-zone submodule **************************/
132 #define TZSEL 0x24
133 #define TZCTL 0x28
134 #define TZEINT 0x2A
135 #define TZFLG 0x2C
136 #define TZCLR 0x2E
137 #define TZFRC 0x30
139 #define TZCTL_ACTA_MASK (BIT(1) | BIT(0))
140 #define TZCTL_ACTB_MASK (BIT(3) | BIT(2))
142 #define TZCTL_ACTB_POS 0x2
144 #define TZEINT_OSHTEVT_POS 0x2
145 #define TZEINT_CBCEVT_POS 0x1
147 /*************************Event-Trigger submodule registers**************/
148 #define ETSEL 0x32
149 #define ETPS 0x34
150 #define ETFLG 0x36
151 #define ETCLR 0x38
152 #define ETFRC 0x3A
154 #define ETSEL_INTSEL_MASK (BIT(2) | BIT(1) | BIT(0))
155 #define ETPS_INTCNT_MASK (BIT(3) | BIT(2))
156 #define ETPS_INTPRD_MASK (BIT(1) | BIT(0))
158 #define ETSEL_EN_INT_EN_POS 0x3
160 /**********************High Resolution Registers ********************/
161 #define TBPHSHR 0x4
162 #define CMPAHR 0x10
163 #define HRCNFG 0x1040
165 #define AM335X_HRCNFG 0x40
167 #define HRCNFG_EDGEMD_MASK (BIT(1) | BIT(0))
168 #define HRCNFG_LDMD_POS 0x3
169 #define HRCNFG_CTLMD_POS 0x2
171 struct ehrpwm_suspend_params {
172 struct pwm_device *pch;
173 unsigned long req_delay_cycles;
174 unsigned long act_delay;
175 } ehrpwm_suspend_params;
177 static inline unsigned short ehrpwm_read(struct ehrpwm_pwm *ehrpwm,
178 unsigned int offset)
179 {
180 return readw(ehrpwm->mmio_base + offset);
181 }
183 static inline void ehrpwm_write(struct ehrpwm_pwm *ehrpwm, unsigned int offset,
184 unsigned short val)
185 {
186 writew(val, ehrpwm->mmio_base + offset);
187 }
189 static void ehrpwm_reg_config(struct ehrpwm_pwm *ehrpwm, unsigned int offset,
190 unsigned short val, unsigned short mask)
191 {
192 unsigned short read_val;
194 read_val = ehrpwm_read(ehrpwm, offset);
195 read_val = read_val & ~mask;
196 read_val = read_val | val;
197 ehrpwm_write(ehrpwm, offset, read_val);
198 }
200 static inline struct ehrpwm_pwm *to_ehrpwm_pwm(const struct pwm_device *p)
201 {
202 return pwm_get_drvdata(p);
203 }
205 /* Time Base Module Configurations */
206 int ehrpwm_tb_set_prescalar_val(struct pwm_device *p, unsigned char clkdiv,
207 unsigned char hspclkdiv)
208 {
209 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
211 if (clkdiv > 0x7 || hspclkdiv > 0x7)
212 return -EINVAL;
214 ehrpwm_reg_config(ehrpwm, TBCTL, clkdiv << TBCTL_CLKDIV_POS,
215 TBCTL_CLKDIV_MASK);
216 ehrpwm_reg_config(ehrpwm, TBCTL, hspclkdiv << TBCTL_HSPCLKDIV_POS,
217 TBCTL_HSPCLKDIV_MASK);
219 return 0;
220 }
221 EXPORT_SYMBOL(ehrpwm_tb_set_prescalar_val);
223 int ehrpwm_tb_config_sync(struct pwm_device *p, unsigned char phsen,
224 unsigned char syncosel)
225 {
226 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
228 if (phsen > 1 || syncosel > 0x3)
229 return -EINVAL;
231 ehrpwm_reg_config(ehrpwm, TBCTL, phsen << TBCTL_PHSEN_POS, BIT(2));
232 ehrpwm_reg_config(ehrpwm, TBCTL, syncosel << TBCTL_SYNCOSEL_POS,
233 TBCTL_SYNCOSEL_MASK);
235 return 0;
236 }
237 EXPORT_SYMBOL(ehrpwm_tb_config_sync);
239 int ehrpwm_tb_set_counter_mode(struct pwm_device *p, unsigned char ctrmode,
240 unsigned char phsdir)
241 {
242 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
244 if (ctrmode > 0x3 || phsdir > 1)
245 return -EINVAL;
247 ehrpwm_reg_config(ehrpwm, TBCTL, phsdir << TBCTL_PHSDIR_POS, BIT(13));
248 ehrpwm_reg_config(ehrpwm, TBCTL, ctrmode, TBCTL_CTRMODE_MASK);
250 return 0;
251 }
252 EXPORT_SYMBOL(ehrpwm_tb_set_counter_mode);
254 int ehrpwm_tb_force_sync(struct pwm_device *p)
255 {
256 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
258 ehrpwm_reg_config(ehrpwm, TBCTL, ENABLE << TBCTL_FRC_SYC_POS, BIT(6));
260 return 0;
261 }
262 EXPORT_SYMBOL(ehrpwm_tb_force_sync);
264 int ehrpwm_tb_set_periodload(struct pwm_device *p, unsigned char loadmode)
265 {
266 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
268 if (loadmode > 0x1)
269 return -EINVAL;
271 ehrpwm_reg_config(ehrpwm, TBCTL, loadmode << TBCTL_LOAD_MD_POS, BIT(3));
273 return 0;
274 }
275 EXPORT_SYMBOL(ehrpwm_tb_set_periodload);
277 int ehrpwm_tb_read_status(struct pwm_device *p, unsigned short *val)
278 {
279 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
281 *val = ehrpwm_read(ehrpwm, TBSTS);
283 return 0;
284 }
285 EXPORT_SYMBOL(ehrpwm_tb_read_status);
287 int ehrpwm_tb_read_counter(struct pwm_device *p, unsigned short *val)
288 {
289 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
291 *val = ehrpwm_read(ehrpwm, TBCTR);
293 return 0;
294 }
295 EXPORT_SYMBOL(ehrpwm_tb_read_counter);
297 int ehrpwm_tb_set_period(struct pwm_device *p, unsigned short val)
298 {
299 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
301 ehrpwm_write(ehrpwm, TBPRD, val);
303 return 0;
304 }
305 EXPORT_SYMBOL(ehrpwm_tb_set_period);
307 int ehrpwm_tb_set_phase(struct pwm_device *p, unsigned short val)
308 {
309 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
311 ehrpwm_write(ehrpwm, TBPHS, val);
313 return 0;
314 }
315 EXPORT_SYMBOL(ehrpwm_tb_set_phase);
317 int ehrpwm_cmp_set_cmp_ctl(struct pwm_device *p, unsigned char shdwamode,
318 unsigned char shdwbmode, unsigned char loadamode,
319 unsigned char loadbmode)
320 {
321 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
323 if (shdwamode > 0x1 || shdwbmode > 0x1 || loadamode > 0x3 ||
324 loadbmode > 0x3)
325 return -EINVAL;
327 ehrpwm_reg_config(ehrpwm, CMPCTL, shdwamode << CMPCTL_SHDAMODE_POS,
328 BIT(4));
329 ehrpwm_reg_config(ehrpwm, CMPCTL, shdwbmode << CMPCTL_SHDBMODE_POS,
330 BIT(6));
331 ehrpwm_reg_config(ehrpwm, CMPCTL, loadamode, CMPCTL_LDAMODE_MASK);
332 ehrpwm_reg_config(ehrpwm, CMPCTL, loadbmode << CMPCTL_LDBMODE_POS,
333 CMPCTL_LDBMODE_MASK);
335 return 0;
336 }
337 EXPORT_SYMBOL(ehrpwm_cmp_set_cmp_ctl);
339 int ehrpwm_cmp_set_cmp_val(struct pwm_device *p, unsigned char reg,
340 unsigned short val)
341 {
342 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
343 unsigned char offset;
345 if (reg > 0x1)
346 return -EINVAL;
348 if (reg == 0)
349 offset = CMPA;
350 else
351 offset = CMPB;
353 ehrpwm_write(ehrpwm, offset, val);
355 return 0;
356 }
357 EXPORT_SYMBOL(ehrpwm_cmp_set_cmp_val);
359 int ehrpwm_aq_set_act_ctrl(struct pwm_device *p, struct aq_config_params *cfg)
360 {
361 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
362 unsigned char reg;
364 if (!cfg)
365 return -EINVAL;
367 if (cfg->ch > 1 || cfg->ctreqzro > 3 || cfg->ctreqprd > 3 ||
368 cfg->ctreqcmpaup > 3 || cfg->ctreqcmpadown > 3 ||
369 cfg->ctreqcmpbup > 3 || cfg->ctreqcmpbdown > 3)
370 return -EINVAL;
372 if (cfg->ch == 0)
373 reg = AQCTLA;
374 else
375 reg = AQCTLB;
377 ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqzro, ACTCTL_CZRO_MASK);
378 ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqprd << ACTCTL_CTREQPRD_POS,
379 ACTCTL_CPRD_MASK);
380 ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpaup <<
381 ACTCTL_CTREQCMPAUP_POS, ACTCTL_CAU_MASK);
382 ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpadown <<
383 ACTCTL_CTREQCMPADN_POS, ACTCTL_CAD_MASK);
384 ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpbup <<
385 ACTCTL_CTREQCMPBUP_POS, ACTCTL_CBU_MASK);
386 ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpbdown <<
387 ACTCTL_CTREQCMPBDN_POS, ACTCTL_CBD_MASK);
389 return 0;
390 }
391 EXPORT_SYMBOL(ehrpwm_aq_set_act_ctrl);
393 int ehrpwm_aq_set_one_shot_act(struct pwm_device *p, unsigned char ch,
394 unsigned char act)
395 {
396 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
398 if (ch > 1 || act > 3)
399 return -EINVAL;
401 if (ch == 0)
402 ehrpwm_reg_config(ehrpwm, AQSFRC, act, AQSFRC_ACTA_MASK);
403 else
404 ehrpwm_reg_config(ehrpwm, AQSFRC, act << AQSFRC_ACTB_POS,
405 AQSFRC_ACTB_MASK);
407 return 0;
408 }
409 EXPORT_SYMBOL(ehrpwm_aq_set_one_shot_act);
411 int ehrpwm_aq_ot_frc(struct pwm_device *p, unsigned char ch)
412 {
413 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
415 if (ch > 1)
416 return -EINVAL;
418 if (ch == 0)
419 ehrpwm_reg_config(ehrpwm, AQSFRC, ENABLE << AQSFRC_OTFRCA_POS,
420 BIT(2));
421 else
422 ehrpwm_reg_config(ehrpwm, AQSFRC, ENABLE << AQSFRC_OTFRCB_POS,
423 BIT(5));
425 return 0;
426 }
427 EXPORT_SYMBOL(ehrpwm_aq_ot_frc);
429 int ehrpwm_aq_set_csfrc_load_mode(struct pwm_device *p, unsigned char loadmode)
430 {
431 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
433 if (loadmode > 0x3)
434 return -EINVAL;
436 ehrpwm_reg_config(ehrpwm, AQSFRC, loadmode << AQSFRC_LDMD_POS,
437 AQCSFRC_CFRC_LOAD_MASK);
439 return 0;
440 }
441 EXPORT_SYMBOL(ehrpwm_aq_set_csfrc_load_mode);
443 int ehrpwm_aq_continuous_frc(struct pwm_device *p, unsigned char ch,
444 unsigned char act)
445 {
446 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
448 if (ch > 1)
449 return -EINVAL;
451 if (ch == 0)
452 ehrpwm_reg_config(ehrpwm, AQCSFRC, act, AQCSFRC_OUTA_MASK);
453 else
454 ehrpwm_reg_config(ehrpwm, AQCSFRC, act << AQCSFRC_OUTB_POS,
455 AQCSFRC_OUTB_MASK);
457 return 0;
458 }
459 EXPORT_SYMBOL(ehrpwm_aq_continuous_frc);
461 int ehrpwm_db_get_max_delay(struct pwm_device *p, enum config_mask cfgmask,
462 unsigned long *delay_val)
463 {
464 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
465 unsigned long delay_ns;
466 unsigned long max_ticks;
468 if (cfgmask == CONFIG_NS) {
469 max_ticks = 0x3ff * ehrpwm->prescale_val;
470 delay_ns = pwm_ticks_to_ns(p, max_ticks);
471 *delay_val = delay_ns;
472 } else if (cfgmask == CONFIG_TICKS) {
473 *delay_val = 0x3ff * ehrpwm->prescale_val;
474 } else {
475 return -EINVAL;
476 }
478 return 0;
479 }
480 EXPORT_SYMBOL(ehrpwm_db_get_max_delay);
482 int ehrpwm_db_get_delay(struct pwm_device *p, unsigned char edge,
483 enum config_mask cfgmask, unsigned long *delay_val)
484 {
485 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
486 unsigned long delay_ns;
487 unsigned long delay_ticks;
488 unsigned char offset;
490 if (!ehrpwm)
491 return -EINVAL;
493 if (edge == RISING_EDGE_DELAY)
494 offset = DBRED;
495 else if (edge == FALLING_EDGE_DELAY)
496 offset = DBFED;
497 else
498 return -EINVAL;
500 delay_ticks = ehrpwm_read(ehrpwm, offset);
501 /* Only least 10 bits are required */
502 delay_ticks = delay_ticks & 0x3ff;
503 if (cfgmask == CONFIG_TICKS) {
504 *delay_val = delay_ticks * ehrpwm->prescale_val;
505 } else if (cfgmask == CONFIG_NS) {
506 delay_ticks = delay_ticks * ehrpwm->prescale_val;
507 delay_ns = pwm_ticks_to_ns(p, delay_ticks);
508 debug("\n delay ns value is %lu", delay_ns);
509 *delay_val = delay_ns;
510 } else {
511 return -EINVAL;
512 }
514 return 0;
515 }
516 EXPORT_SYMBOL(ehrpwm_db_get_delay);
518 int ehrpwm_db_set_delay(struct pwm_device *p, unsigned char edge,
519 enum config_mask cfgmask, unsigned long delay)
520 {
521 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
522 unsigned long delay_ticks;
523 unsigned char offset = 0;
525 if (!ehrpwm)
526 return -EINVAL;
528 if (edge == RISING_EDGE_DELAY)
529 offset = DBRED;
530 else if (edge == FALLING_EDGE_DELAY)
531 offset = DBFED;
532 else
533 return -EINVAL;
535 if (cfgmask == CONFIG_TICKS) {
536 delay = delay / ehrpwm->prescale_val;
537 if (delay > 0x3ff)
538 return -EINVAL;
539 ehrpwm_write(ehrpwm, offset, delay);
540 } else if (cfgmask == CONFIG_NS) {
541 delay_ticks = pwm_ns_to_ticks(p, delay);
542 delay_ticks = delay_ticks / ehrpwm->prescale_val;
543 if (delay_ticks > 0x3ff) {
544 ehrpwm_db_get_max_delay(p, CONFIG_NS, &delay_ticks);
545 dev_dbg(p->dev, "%s: Expected delay cannot be"
546 " attained setting the maximum possible delay of"
547 " %lu ns", __func__, delay_ticks);
548 delay_ticks = 0x3ff;
549 }
550 debug("\n delay ticks is %lu", delay_ticks);
551 ehrpwm_write(ehrpwm, offset, delay_ticks);
552 } else {
553 return -EINVAL;
554 }
556 return 0;
557 }
558 EXPORT_SYMBOL(ehrpwm_db_set_delay);
560 /* Dead Band Configuration functions */
561 int ehrpwm_db_set_mode(struct pwm_device *p, unsigned char inmode,
562 unsigned char polsel, unsigned char outmode)
563 {
564 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
566 if (inmode > 0x3 || polsel > 0x3 || outmode > 0x3)
567 return -EINVAL;
569 ehrpwm_reg_config(ehrpwm, DBCTL, inmode << DBCTL_INMODE_POS,
570 DBCTL_INMODE_MASK);
571 ehrpwm_reg_config(ehrpwm, DBCTL, polsel << DBCTL_POLSEL_POS,
572 DBCTL_PLSEL_MASK);
573 ehrpwm_reg_config(ehrpwm, DBCTL, outmode, DBCTL_OUTMODE_MASK);
575 return 0;
576 }
577 EXPORT_SYMBOL(ehrpwm_db_set_mode);
579 /* PWM chopper Configuration functions */
580 int ehrpwm_pc_configure(struct pwm_device *p, unsigned char chpduty,
581 unsigned char chpfreq, unsigned char oshtwidth)
582 {
583 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
585 if (chpduty > 0x7 || chpfreq > 0x7 || oshtwidth > 0xf)
586 return -EINVAL;
588 ehrpwm_reg_config(ehrpwm, PCCTL, chpduty << PCCTL_CHPDUTY_POS,
589 PCCTL_CHPDUTY_MASK);
590 ehrpwm_reg_config(ehrpwm, PCCTL, chpfreq << PCCTL_CHPFRQ_POS,
591 PCCTL_CHPFREQ_MASK);
592 ehrpwm_reg_config(ehrpwm, PCCTL, oshtwidth << PCCTL_OSTWID_POS,
593 PCCTL_OSHTWTH_MASK);
595 return 0;
596 }
597 EXPORT_SYMBOL(ehrpwm_pc_configure);
599 int ehrpwm_pc_en_dis(struct pwm_device *p, unsigned char chpen)
600 {
601 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
603 if (chpen > 1)
604 return -EINVAL;
606 ehrpwm_reg_config(ehrpwm, PCCTL, chpen, BIT(0));
608 return 0;
609 }
610 EXPORT_SYMBOL(ehrpwm_pc_en_dis);
612 /* Trip Zone configuration functions */
613 int ehrpwm_tz_sel_event(struct pwm_device *p, unsigned char input,
614 enum tz_event evt)
615 {
616 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
618 unsigned short val = 0;
619 unsigned short mask;
620 unsigned short pos;
622 if (evt > 4 || input > 7)
623 return -EINVAL;
625 switch (evt) {
626 case TZ_ONE_SHOT_EVENT:
627 pos = input + 8;
628 mask = BIT((pos)) | BIT(input);
629 ehrpwm_reg_config(ehrpwm, TZSEL, 1 << pos, mask);
630 break;
632 case TZ_CYCLE_BY_CYCLE:
633 pos = input;
634 mask = BIT(pos) | BIT((pos + 8));
635 ehrpwm_reg_config(ehrpwm, TZSEL, 1 << pos, mask);
636 break;
638 case TZ_OSHT_CBC:
639 case TZ_DIS_EVT:
640 if (evt == TZ_OSHT_CBC)
641 val = 1;
642 else
643 val = 0;
645 pos = input + 8;
646 mask = BIT((pos));
647 ehrpwm_reg_config(ehrpwm, TZSEL, val << pos, mask);
648 pos = input;
649 mask = BIT((pos));
650 ehrpwm_reg_config(ehrpwm, TZSEL, val << pos, mask);
651 break;
653 default:
654 dev_dbg(p->dev, "%s: Invalid command", __func__);
655 return -EINVAL;
656 }
657 debug("\n TZ_sel val is %0x", ehrpwm_read(ehrpwm, TZSEL));
659 return 0;
660 }
661 EXPORT_SYMBOL(ehrpwm_tz_sel_event);
663 int ehrpwm_tz_set_action(struct pwm_device *p, unsigned char ch,
664 unsigned char act)
665 {
666 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
668 if (act > 0x3 || ch > 1)
669 return -EINVAL;
671 if (ch == 0)
672 ehrpwm_reg_config(ehrpwm, TZCTL, act, TZCTL_ACTA_MASK);
673 else
674 ehrpwm_reg_config(ehrpwm, TZCTL, act << TZCTL_ACTB_POS,
675 TZCTL_ACTB_MASK);
677 debug("\n TZCTL reg val is %0x", ehrpwm_read(ehrpwm, TZCTL));
679 return 0;
680 }
681 EXPORT_SYMBOL(ehrpwm_tz_set_action);
683 int ehrpwm_tz_set_int_en_dis(struct pwm_device *p, enum tz_event event,
684 unsigned char int_en_dis)
685 {
686 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
688 if (event == TZ_ONE_SHOT_EVENT)
689 ehrpwm_reg_config(ehrpwm, TZEINT, int_en_dis <<
690 TZEINT_OSHTEVT_POS, BIT(2));
691 else if (event == TZ_CYCLE_BY_CYCLE)
692 ehrpwm_reg_config(ehrpwm, TZEINT, int_en_dis <<
693 TZEINT_CBCEVT_POS, BIT(1));
694 else
695 return -EINVAL;
697 debug("\n TZEINT reg val is %0x", ehrpwm_read(ehrpwm, TZEINT));
699 return 0;
700 }
701 EXPORT_SYMBOL(ehrpwm_tz_set_int_en_dis);
703 int ehrpwm_tz_force_evt(struct pwm_device *p, enum tz_event event)
704 {
705 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
707 if (event == TZ_ONE_SHOT_EVENT)
708 ehrpwm_write(ehrpwm, TZFRC, 0x4);
709 else if (event == TZ_CYCLE_BY_CYCLE)
710 ehrpwm_write(ehrpwm, TZFRC, 0x2);
711 else
712 return -EINVAL;
714 return 0;
715 }
716 EXPORT_SYMBOL(ehrpwm_tz_force_evt);
718 inline int ehrpwm_tz_read_status(struct pwm_device *p, unsigned short *status)
719 {
720 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
722 *status = ehrpwm_read(ehrpwm, TZFLG);
724 return 0;
725 }
726 EXPORT_SYMBOL(ehrpwm_tz_read_status);
728 inline int ehrpwm_tz_clr_evt_status(struct pwm_device *p)
729 {
730 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
731 unsigned short ret;
733 ret = ehrpwm_read(ehrpwm, TZFLG);
734 ehrpwm_write(ehrpwm, TZCLR, ret & ~0x1);
736 return 0;
737 }
738 EXPORT_SYMBOL(ehrpwm_tz_clr_evt_status);
740 inline int ehrpwm_tz_clr_int_status(struct pwm_device *p)
741 {
742 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
744 ehrpwm_write(ehrpwm, TZCLR, 0x1);
746 return 0;
747 }
748 EXPORT_SYMBOL(ehrpwm_tz_clr_int_status);
750 /* Event Trigger Configuration functions */
751 int ehrpwm_et_set_sel_evt(struct pwm_device *p, unsigned char evt,
752 unsigned char prd)
753 {
754 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
756 if (evt > 0x7 || prd > 0x3)
757 return -EINVAL;
759 ehrpwm_reg_config(ehrpwm, ETSEL, evt, ETSEL_INTSEL_MASK);
760 ehrpwm_reg_config(ehrpwm, ETPS, prd, ETPS_INTPRD_MASK);
762 return 0;
763 }
764 EXPORT_SYMBOL(ehrpwm_et_set_sel_evt);
766 inline int ehrpwm_et_int_en_dis(struct pwm_device *p, unsigned char en_dis)
767 {
768 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
770 ehrpwm_reg_config(ehrpwm, ETSEL, en_dis << ETSEL_EN_INT_EN_POS, BIT(3));
772 return 0;
773 }
774 EXPORT_SYMBOL(ehrpwm_et_int_en_dis);
776 inline int ehrpwm_et_read_evt_cnt(struct pwm_device *p,
777 unsigned long *evtcnt)
778 {
779 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
781 *evtcnt = ehrpwm_read(ehrpwm, ETPS) & ETPS_INTCNT_MASK;
782 *evtcnt >>= 0x2;
784 return 0;
785 }
786 EXPORT_SYMBOL(ehrpwm_et_read_evt_cnt);
788 inline int ehrpwm_et_read_int_status(struct pwm_device *p,
789 unsigned long *status)
790 {
791 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
793 *status = ehrpwm_read(ehrpwm, ETFLG) & BIT(0);
795 return 0;
796 }
797 EXPORT_SYMBOL(ehrpwm_et_read_int_status);
799 inline int ehrpwm_et_frc_int(struct pwm_device *p)
800 {
801 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
803 ehrpwm_write(ehrpwm, ETFRC, ENABLE);
805 return 0;
806 }
807 EXPORT_SYMBOL(ehrpwm_et_frc_int);
809 inline int ehrpwm_et_clr_int(struct pwm_device *p)
810 {
811 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
813 ehrpwm_write(ehrpwm, ETCLR, ENABLE);
815 return 0;
816 }
817 EXPORT_SYMBOL(ehrpwm_et_clr_int);
819 /* High Resolution Module configuration */
820 inline int ehrpwm_hr_set_phase(struct pwm_device *p, unsigned char val)
821 {
822 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
824 ehrpwm_write(ehrpwm, TBPHSHR, val << 8);
826 return 0;
827 }
828 EXPORT_SYMBOL(ehrpwm_hr_set_phase);
830 inline int ehrpwm_hr_set_cmpval(struct pwm_device *p, unsigned char val)
831 {
832 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
834 ehrpwm_write(ehrpwm, CMPAHR, val << 8);
836 return 0;
837 }
838 EXPORT_SYMBOL(ehrpwm_hr_set_cmpval);
840 int ehrpwm_hr_config(struct pwm_device *p, unsigned char loadmode,
841 unsigned char ctlmode, unsigned char edgemode)
842 {
843 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
845 if (loadmode > 1 || ctlmode > 1 || edgemode > 3)
846 return -EINVAL;
848 if (ehrpwm->version == PWM_VERSION_1) {
849 ehrpwm_reg_config(ehrpwm, AM335X_HRCNFG,
850 loadmode << HRCNFG_LDMD_POS, BIT(3));
851 ehrpwm_reg_config(ehrpwm, AM335X_HRCNFG,
852 ctlmode << HRCNFG_CTLMD_POS, BIT(2));
853 ehrpwm_reg_config(ehrpwm, AM335X_HRCNFG,
854 edgemode, HRCNFG_EDGEMD_MASK);
855 } else {
856 ehrpwm_reg_config(ehrpwm, HRCNFG,
857 loadmode << HRCNFG_LDMD_POS, BIT(3));
858 ehrpwm_reg_config(ehrpwm, HRCNFG,
859 ctlmode << HRCNFG_CTLMD_POS, BIT(2));
860 ehrpwm_reg_config(ehrpwm, HRCNFG,
861 edgemode, HRCNFG_EDGEMD_MASK);
862 }
864 return 0;
865 }
866 EXPORT_SYMBOL(ehrpwm_hr_config);
868 inline int ehrpwm_reg_read(struct pwm_device *p, unsigned int reg,
869 unsigned short *val)
870 {
871 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
873 if (!(ehrpwm->version == PWM_VERSION_1)) {
874 if (reg > HRCNFG)
875 return -EINVAL;
876 }
878 *val = ehrpwm_read(ehrpwm, reg);
880 return 0;
881 }
882 EXPORT_SYMBOL(ehrpwm_reg_read);
884 inline int ehrpwm_reg_write(struct pwm_device *p, unsigned int reg,
885 unsigned short val)
886 {
887 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
889 if (!(ehrpwm->version == PWM_VERSION_1)) {
890 if (reg > HRCNFG)
891 return -EINVAL;
892 }
894 ehrpwm_write(ehrpwm, reg, val);
896 return 0;
897 }
898 EXPORT_SYMBOL(ehrpwm_reg_write);
900 static int ehrpwm_pwm_set_pol(struct pwm_device *p)
901 {
902 unsigned int act_ctrl_reg;
903 unsigned int cmp_reg;
904 unsigned int ctreqcmp_mask;
905 unsigned int ctreqcmp;
906 unsigned short val;
907 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
908 int chan;
910 chan = p - &ehrpwm->pwm[0];
911 if (!chan) {
912 act_ctrl_reg = AQCTLA;
913 cmp_reg = CMPA;
914 ctreqcmp_mask = ACTCTL_CAU_MASK;
915 ctreqcmp = 4;
916 } else {
917 act_ctrl_reg = AQCTLB;
918 cmp_reg = CMPB;
919 ctreqcmp_mask = ACTCTL_CBU_MASK;
920 ctreqcmp = 8;
921 }
924 pm_runtime_get_sync(ehrpwm->dev);
925 val = ((p->active_high ? ACTCTL_CTREQCMP_HIGH : ACTCTL_CTREQCMP_LOW)
926 << ctreqcmp) | (p->active_high ? ACTCTL_CTREQZRO_LOW :
927 ACTCTL_CTREQZRO_HIGH);
928 ehrpwm_write(ehrpwm, act_ctrl_reg, val);
929 pm_runtime_put_sync(ehrpwm->dev);
930 return 0;
931 }
933 static int ehrpwm_pwm_start(struct pwm_device *p)
934 {
935 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
936 unsigned short val;
937 unsigned short read_val1;
938 unsigned short read_val2;
939 int chan;
942 /* Trying to start a running PWM, not allowed */
943 if (pwm_is_running(p))
944 return -EPERM;
946 /* For PWM clock should be enabled on start */
947 pm_runtime_get_sync(ehrpwm->dev);
949 ehrpwm_pwm_set_pol(p);
950 chan = p - &ehrpwm->pwm[0];
951 val = ehrpwm_read(ehrpwm, TBCTL);
952 val = (val & ~TBCTL_CTRMODE_MASK) | (TBCTL_CTRMOD_CTRUP |
953 TBCTL_FREERUN_FREE << 14);
954 ehrpwm_write(ehrpwm, TBCTL, val);
955 ehrpwm_tz_set_action(p, chan, 0x3);
956 read_val1 = ehrpwm_read(ehrpwm, TZFLG);
957 read_val2 = ehrpwm_read(ehrpwm, TZCTL);
958 /*
959 * State of the other channel is determined by reading the
960 * TZCTL register. If the other channel is also in running state,
961 * one shot event status is cleared, otherwise one shot action for
962 * this channel is set to "DO NOTHING.
963 */
964 read_val2 = read_val2 & (chan ? 0x3 : (0x3 << 2));
965 read_val2 = chan ? read_val2 : (read_val2 >> 2);
966 if (!(read_val1 & 0x4) || (read_val2 == 0x3))
967 ehrpwm_tz_clr_evt_status(p);
969 set_bit(FLAG_RUNNING, &p->flags);
970 return 0;
971 }
973 /*
974 * Stop function is implemented using the Trip Zone module. Action for the
975 * corresponding channel is set to low and the one shot software force
976 * event is triggered.
977 */
978 static int ehrpwm_pwm_stop(struct pwm_device *p)
979 {
980 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
981 unsigned short read_val;
982 int chan;
984 /* Trying to stop a non-running PWM, not allowed */
985 if (!pwm_is_running(p))
986 return -EPERM;
988 chan = p - &ehrpwm->pwm[0];
989 /* Set the Trip Zone Action to low */
990 ehrpwm_tz_set_action(p, chan, 0x2);
991 read_val = ehrpwm_read(ehrpwm, TZFLG);
992 /*
993 * If the channel is already in stop state, Trip Zone software force is
994 * not required
995 */
996 if (!(read_val & 0x4)) {
997 ehrpwm_tz_clr_evt_status(p);
998 ehrpwm_tz_force_evt(p, TZ_ONE_SHOT_EVENT);
999 }
1001 /* For PWM clock should be disabled on stop */
1002 pm_runtime_put_sync(ehrpwm->dev);
1003 clear_bit(FLAG_RUNNING, &p->flags);
1004 return 0;
1005 }
1007 /*
1008 * Prescalar is used when the period value exceeds the maximum value
1009 * of the 16 bit period register. We always look for the minimum prescalar
1010 * value as it would result in wide range of duty control
1011 */
1012 static char get_divider_val(unsigned int desired_ps_val, unsigned int
1013 *ps_div_val, unsigned int *tb_div_val)
1014 {
1015 char i = 0;
1016 char j = 0;
1018 for (i = 0; i <= 7; i++) {
1019 for (j = 0; j <= 7; j++) {
1020 if (((1 << i) * (j ? (j * 2) : 1)) >= desired_ps_val) {
1021 *ps_div_val = (1 << i) * (j ? (j * 2) : 1);
1022 *tb_div_val = (i << 10) | (j << 7) ;
1023 return 0;
1024 }
1025 }
1026 }
1028 return -1;
1029 }
1031 static int ehrpwm_pwm_set_prd(struct pwm_device *p)
1032 {
1033 unsigned int ps_div_val = 1;
1034 unsigned int tb_div_val = 0;
1035 char ret;
1036 unsigned short val;
1037 unsigned short period_ticks;
1038 struct pwm_device *temp;
1039 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
1040 int chan = 0;
1041 /*
1042 * Since the device has a singe period register, copy the period
1043 * value to the other channel also.
1044 */
1045 chan = p - &ehrpwm->pwm[0];
1046 temp = &ehrpwm->pwm[!chan];
1047 temp->period_ticks = p->period_ticks;
1048 temp->period_ns = p->period_ns;
1049 debug("\n period_ticks is %lu", p->period_ticks);
1051 if (p->period_ticks > 65535) {
1052 ret = get_divider_val(p->period_ticks / 65535 + 1, &ps_div_val,
1053 &tb_div_val);
1054 if (ret) {
1055 dev_err(p->dev, "failed to get the divider value");
1056 return -EINVAL;
1057 }
1058 }
1060 pm_runtime_get_sync(ehrpwm->dev);
1061 val = ehrpwm_read(ehrpwm, TBCTL);
1062 val = (val & ~TBCTL_CLKDIV_MASK & ~TBCTL_HSPCLKDIV_MASK) | tb_div_val;
1063 ehrpwm_write(ehrpwm, TBCTL, val);
1064 period_ticks = p->period_ticks / ps_div_val;
1066 if (period_ticks <= 1) {
1067 dev_err(p->dev, "Required period/frequency cannot be obtained");
1068 pm_runtime_put_sync(ehrpwm->dev);
1069 return -EINVAL;
1070 }
1071 /*
1072 * Program the period register with 1 less than the actual value since
1073 * the module generates waveform with period always 1 greater
1074 * the programmed value.
1075 */
1076 ehrpwm_write(ehrpwm, TBPRD, (unsigned short)(period_ticks - 1));
1077 pm_runtime_put_sync(ehrpwm->dev);
1078 debug("\n period_ticks is %d", period_ticks);
1079 ehrpwm->prescale_val = ps_div_val;
1080 debug("\n Prescaler value is %d", ehrpwm->prescale_val);
1082 return 0;
1083 }
1085 static int ehrpwm_hr_duty_config(struct pwm_device *p)
1086 {
1087 unsigned char no_of_mepsteps;
1088 unsigned short cmphr_val;
1089 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
1091 if (!p->tick_hz) {
1092 dev_dbg(p->dev, "%s: p->tick_hz is zero\n", __func__);
1093 return -EINVAL;
1094 }
1096 /*
1097 * Calculate the no of MEP steps. Assume system clock
1098 * is in the order of MHZ.
1099 */
1100 no_of_mepsteps = USEC_PER_SEC / ((p->tick_hz / USEC_PER_SEC) * 63);
1102 pm_runtime_get_sync(ehrpwm->dev);
1103 /* Calculate the CMPHR Value */
1104 cmphr_val = p->tick_hz / USEC_PER_SEC;
1105 cmphr_val = (p->duty_ns * cmphr_val) % MSEC_PER_SEC;
1106 cmphr_val = (cmphr_val * no_of_mepsteps) / 1000;
1107 cmphr_val = (cmphr_val << 8) + 0x180;
1108 ehrpwm_write(ehrpwm, CMPAHR, cmphr_val);
1110 if (ehrpwm->version == PWM_VERSION_1)
1111 ehrpwm_write(ehrpwm, AM335X_HRCNFG, 0x2);
1112 else
1113 ehrpwm_write(ehrpwm, HRCNFG, 0x2);
1115 pm_runtime_put_sync(ehrpwm->dev);
1116 return 0;
1117 }
1119 static int ehrpwm_pwm_set_dty(struct pwm_device *p)
1120 {
1121 unsigned short duty_ticks = 0;
1122 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
1123 int ret = 0;
1124 int chan;
1126 chan = p - &ehrpwm->pwm[0];
1128 if (!ehrpwm->prescale_val) {
1129 dev_dbg(p->dev, "%s: prescale_val is zero\n", __func__);
1130 return -EINVAL;
1131 }
1133 duty_ticks = p->duty_ticks / ehrpwm->prescale_val;
1134 debug("\n Prescaler value is %d", ehrpwm->prescale_val);
1135 debug("\n duty ticks is %d", duty_ticks);
1136 pm_runtime_get_sync(ehrpwm->dev);
1137 /* High resolution module */
1138 if (chan && ehrpwm->prescale_val <= 1) {
1139 ret = ehrpwm_hr_duty_config(p);
1140 if (ehrpwm->version == PWM_VERSION_1)
1141 ehrpwm_write(ehrpwm, AM335X_HRCNFG, 0x2);
1142 else
1143 ehrpwm_write(ehrpwm, HRCNFG, 0x2);
1144 }
1146 ehrpwm_write(ehrpwm, (chan ? CMPB : CMPA), duty_ticks);
1147 pm_runtime_put_sync(ehrpwm->dev);
1148 return ret;
1149 }
1151 int ehrpwm_et_cb_register(struct pwm_device *p, void *data,
1152 p_fcallback cb)
1153 {
1154 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
1155 unsigned long flags;
1157 spin_lock_irqsave(&ehrpwm->lock, flags);
1158 ehrpwm->st_etint.data = data;
1159 ehrpwm->st_etint.pcallback = cb;
1160 spin_unlock_irqrestore(&ehrpwm->lock, flags);
1162 return 0;
1163 }
1164 EXPORT_SYMBOL(ehrpwm_et_cb_register);
1166 int ehrpwm_tz_cb_register(struct pwm_device *p, void *data,
1167 p_fcallback cb)
1168 {
1169 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
1170 unsigned long flags;
1172 spin_lock_irqsave(&ehrpwm->lock, flags);
1173 ehrpwm->st_tzint.data = data;
1174 ehrpwm->st_tzint.pcallback = cb;
1175 spin_unlock_irqrestore(&ehrpwm->lock, flags);
1177 return 0;
1178 }
1179 EXPORT_SYMBOL(ehrpwm_tz_cb_register);
1181 static int ehrpwm_pwm_suspend_cb(struct ehrpwm_pwm *ehrpwm, void *data)
1182 {
1183 struct ehrpwm_suspend_params *pwm_suspend_params =
1184 (struct ehrpwm_suspend_params *)data;
1186 if (pwm_suspend_params->act_delay++ >= pwm_suspend_params->
1187 req_delay_cycles) {
1188 pwm_start(pwm_suspend_params->pch);
1189 ehrpwm_et_cb_register(pwm_suspend_params->pch, NULL, NULL);
1190 ehrpwm_et_int_en_dis(pwm_suspend_params->pch, DISABLE);
1191 }
1193 return 0;
1194 }
1196 int ehrpwm_pwm_suspend(struct pwm_device *p, enum config_mask config_mask,
1197 unsigned long val)
1198 {
1199 unsigned long long req_cycles = 0;
1201 if (!p->period_ns)
1202 return -EINVAL;
1204 ehrpwm_pwm_stop(p);
1205 /* Calculate the delay in terms of cycles */
1206 if (config_mask == CONFIG_NS)
1207 req_cycles = val / p->period_ns;
1208 else if (config_mask == CONFIG_TICKS)
1209 req_cycles = val;
1210 else
1211 return -EINVAL;
1213 /* Configute the event interrupt */
1214 ehrpwm_et_set_sel_evt(p, 0x2, 0x1);
1215 ehrpwm_suspend_params.pch = p;
1216 ehrpwm_suspend_params.req_delay_cycles = req_cycles;
1217 ehrpwm_suspend_params.act_delay = 0;
1218 ehrpwm_et_cb_register(p, &ehrpwm_suspend_params,
1219 ehrpwm_pwm_suspend_cb);
1220 ehrpwm_et_int_en_dis(p, ENABLE);
1222 return 0;
1223 }
1224 EXPORT_SYMBOL(ehrpwm_pwm_suspend);
1226 static irqreturn_t ehrpwm_trip_zone_irq_handler(int irq, void *data)
1227 {
1228 struct ehrpwm_pwm *ehrpwm = (struct ehrpwm_pwm *)data;
1229 unsigned long flags;
1230 int ret = 0;
1232 spin_lock_irqsave(&ehrpwm->lock, flags);
1233 ret = ehrpwm_read(ehrpwm, TZFLG);
1234 if (!(ret & 0x1))
1235 return IRQ_NONE;
1237 if (ehrpwm->st_tzint.pcallback)
1238 ret = ehrpwm->st_tzint.pcallback(ehrpwm, ehrpwm->st_tzint.data);
1240 ret = ehrpwm_read(ehrpwm, TZFLG);
1241 ehrpwm_write(ehrpwm, TZCLR, ret & ~0x1);
1242 ehrpwm_write(ehrpwm, TZCLR, 0x1);
1243 spin_unlock_irqrestore(&ehrpwm->lock, flags);
1245 return IRQ_HANDLED;
1246 }
1248 static irqreturn_t ehrpwm_event_irq_handler(int irq, void *data)
1249 {
1250 struct ehrpwm_pwm *ehrpwm = (struct ehrpwm_pwm *)data;
1251 unsigned long flags;
1253 spin_lock_irqsave(&ehrpwm->lock, flags);
1255 if (ehrpwm->st_etint.pcallback)
1256 ehrpwm->st_etint.pcallback(ehrpwm, ehrpwm->st_etint.data);
1258 ehrpwm_write(ehrpwm, ETCLR, 0x1);
1260 spin_unlock_irqrestore(&ehrpwm->lock, flags);
1262 return IRQ_HANDLED;
1263 }
1265 static int ehrpwm_pwm_config(struct pwm_device *p,
1266 struct pwm_config *c)
1267 {
1268 int ret = 0;
1270 switch (c->config_mask) {
1271 case BIT(PWM_CONFIG_PERIOD_TICKS):
1272 if (p->max_period_ticks &&
1273 (p->max_period_ticks >= c->period_ticks))
1274 p->period_ticks = p->max_period_ticks;
1275 else
1276 p->period_ticks = c->period_ticks;
1278 ret = ehrpwm_pwm_set_prd(p);
1279 break;
1281 case BIT(PWM_CONFIG_DUTY_TICKS):
1282 p->duty_ticks = c->duty_ticks;
1283 ret = ehrpwm_pwm_set_dty(p);
1284 break;
1286 case BIT(PWM_CONFIG_POLARITY):
1287 p->active_high = c->polarity;
1288 ret = ehrpwm_pwm_set_pol(p);
1289 break;
1291 case BIT(PWM_CONFIG_START):
1292 ret = ehrpwm_pwm_start(p);
1293 break;
1295 case BIT(PWM_CONFIG_STOP):
1296 ret = ehrpwm_pwm_stop(p);
1297 break;
1299 default:
1300 dev_dbg(p->dev, "%s: Invalid configuration\n", __func__);
1301 ret = -EINVAL;
1302 }
1304 return ret;
1305 }
1307 static int ehrpwm_pwm_request(struct pwm_device *p)
1308 {
1309 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
1310 int chan;
1312 chan = p - &ehrpwm->pwm[0];
1314 p->tick_hz = clk_get_rate(ehrpwm->clk);
1315 debug("\n The clk freq is %lu", p->tick_hz);
1316 ehrpwm_pwm_stop(p);
1318 return 0;
1319 }
1321 static int ehrpwm_freq_transition_cb(struct pwm_device *p)
1322 {
1323 struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
1324 unsigned long duty_ns;
1326 p->tick_hz = clk_get_rate(ehrpwm->clk);
1327 duty_ns = p->duty_ns;
1328 if (pwm_is_running(p)) {
1329 pwm_stop(p);
1330 pwm_set_duty_ns(p, 0);
1331 pwm_set_period_ns(p, p->period_ns);
1332 pwm_set_duty_ns(p, duty_ns);
1333 pwm_start(p);
1334 } else {
1335 pwm_set_duty_ns(p, 0);
1336 pwm_set_period_ns(p, p->period_ns);
1337 pwm_set_duty_ns(p, duty_ns);
1338 }
1339 return 0;
1340 }
1342 static int ehrpwm_probe(struct platform_device *pdev)
1343 {
1344 struct ehrpwm_pwm *ehrpwm = NULL;
1345 struct resource *r;
1346 int ret = 0;
1347 int chan = 0;
1348 struct pwmss_platform_data *pdata = (&pdev->dev)->platform_data;
1349 int ch_mask = 0;
1350 int val;
1351 char con_id[PWM_CON_ID_STRING_LENGTH] = "epwmss";
1353 ehrpwm = kzalloc(sizeof(*ehrpwm), GFP_KERNEL);
1354 if (!ehrpwm) {
1355 dev_err(&pdev->dev, "failed to allocate memory\n");
1356 ret = -ENOMEM;
1357 goto err_mem_failure;
1358 }
1360 ehrpwm->version = pdata->version;
1362 if (ehrpwm->version == PWM_VERSION_1) {
1363 sprintf(con_id, "%s%d_%s", con_id, pdev->id, "fck");
1364 ehrpwm->clk = clk_get(&pdev->dev, con_id);
1365 } else
1366 ehrpwm->clk = clk_get(&pdev->dev, "ehrpwm");
1368 pm_runtime_enable(&pdev->dev);
1369 ehrpwm->dev = &pdev->dev;
1370 if (IS_ERR(ehrpwm->clk)) {
1371 ret = PTR_ERR(ehrpwm->clk);
1372 goto err_clock_failure;
1373 }
1375 if (ehrpwm->version == PWM_VERSION_1) {
1376 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1378 if (!r) {
1379 dev_err(&pdev->dev, "no memory resource defined\n");
1380 ret = -ENOMEM;
1381 goto err_resource_mem_failure;
1382 }
1384 ehrpwm->config_mem_base = ioremap(r->start, resource_size(r));
1386 if (!ehrpwm->config_mem_base) {
1388 dev_err(&pdev->dev, "failed to ioremap() registers\n");
1389 ret = -ENODEV;
1390 goto err_free_mem_config;
1391 }
1393 pm_runtime_get_sync(ehrpwm->dev);
1394 val = readw(ehrpwm->config_mem_base + PWMSS_CLKCONFIG);
1395 val |= BIT(EPWM_CLK_EN);
1396 writew(val, ehrpwm->config_mem_base + PWMSS_CLKCONFIG);
1397 pm_runtime_put_sync(ehrpwm->dev);
1398 } else
1399 ch_mask = pdata->channel_mask;
1401 spin_lock_init(&ehrpwm->lock);
1402 ehrpwm->ops.config = ehrpwm_pwm_config;
1403 ehrpwm->ops.request = ehrpwm_pwm_request;
1404 ehrpwm->ops.freq_transition_notifier_cb = ehrpwm_freq_transition_cb;
1405 ehrpwm->prescale_val = 1;
1407 if (ehrpwm->version == PWM_VERSION_1)
1408 r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1409 else
1410 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1412 if (!r) {
1413 dev_err(&pdev->dev, "no memory resource defined\n");
1414 ret = -ENODEV;
1415 goto err_resource_mem2_failiure;
1416 }
1418 r = request_mem_region(r->start, resource_size(r), pdev->name);
1419 if (!r) {
1420 dev_err(&pdev->dev, "failed to request memory resource\n");
1421 ret = -EBUSY;
1422 goto err_request_mem2_failure;
1423 }
1425 ehrpwm->mmio_base = ioremap(r->start, resource_size(r));
1426 if (!ehrpwm->mmio_base) {
1427 dev_err(&pdev->dev, "failed to ioremap() registers\n");
1428 ret = -ENODEV;
1429 goto err_free_mem2;
1430 }
1432 ehrpwm->irq[0] = platform_get_irq(pdev, 0);
1433 if (ehrpwm->irq[0] == -ENXIO) {
1434 dev_err(&pdev->dev, "No IRQ resource\n");
1435 ret = -ENXIO;
1436 goto err_free_io;
1437 }
1439 ret = request_irq(ehrpwm->irq[0], ehrpwm_trip_zone_irq_handler,
1440 0, "ehrpwmTZ", ehrpwm);
1441 if (ret)
1442 goto err_free_io;
1444 ehrpwm->irq[1] = platform_get_irq(pdev, 1);
1445 if (ehrpwm->irq[1] == -ENXIO) {
1446 dev_err(&pdev->dev, "No IRQ resource\n");
1447 ret = -ENXIO;
1448 goto err_request_irq;
1449 }
1451 ret = request_irq(ehrpwm->irq[1], ehrpwm_event_irq_handler,
1452 0, "ehrpwm_evt", ehrpwm);
1453 if (ret)
1454 goto err_request_irq;
1456 for (chan = 0; chan < NCHAN; chan++) {
1457 ehrpwm->pwm[chan].ops = &ehrpwm->ops;
1458 pwm_set_drvdata(&ehrpwm->pwm[chan], ehrpwm);
1459 ehrpwm->pwm[chan].tick_hz = clk_get_rate(ehrpwm->clk);
1461 if (pdata->chan_attrib[chan].max_freq) {
1462 int period_ns = NSEC_PER_SEC
1463 / pdata->chan_attrib[chan].max_freq;
1465 ehrpwm->pwm[chan].max_period_ticks =
1466 pwm_ns_to_ticks(&ehrpwm->pwm[chan], period_ns);
1467 }
1469 if (!(ehrpwm->version == PWM_VERSION_1)) {
1470 if (!(ch_mask & (0x1 << chan)))
1471 continue;
1472 }
1474 ret = pwm_register(&ehrpwm->pwm[chan], &pdev->dev, chan);
1475 if (ret)
1476 goto err_pwm_register;
1477 }
1479 platform_set_drvdata(pdev, ehrpwm);
1480 return 0;
1482 err_pwm_register:
1483 for (chan = 0; chan < NCHAN; chan++) {
1484 if (pwm_is_registered(&ehrpwm->pwm[chan]))
1485 pwm_unregister(&ehrpwm->pwm[chan]);
1486 }
1488 err_request_irq:
1489 if (ehrpwm->irq[0] != -ENXIO)
1490 free_irq(ehrpwm->irq[0], ehrpwm);
1491 err_free_io:
1492 iounmap(ehrpwm->mmio_base);
1493 err_free_mem2:
1494 release_mem_region(r->start, resource_size(r));
1495 err_request_mem2_failure:
1496 err_resource_mem2_failiure:
1497 if (ehrpwm->version == PWM_VERSION_1) {
1498 iounmap(ehrpwm->config_mem_base);
1499 ehrpwm->config_mem_base = NULL;
1500 }
1501 err_free_mem_config:
1502 err_resource_mem_failure:
1503 clk_put(ehrpwm->clk);
1504 pm_runtime_disable(ehrpwm->dev);
1505 err_clock_failure:
1506 kfree(ehrpwm);
1507 err_mem_failure:
1508 return ret;
1509 }
1511 #ifdef CONFIG_PM
1513 void ehrpwm_context_save(struct ehrpwm_pwm *ehrpwm,
1514 struct ehrpwm_context *ehrpwm_ctx)
1515 {
1516 pm_runtime_get_sync(ehrpwm->dev);
1517 ehrpwm_ctx->tbctl = ehrpwm_read(ehrpwm, TBCTL);
1518 ehrpwm_ctx->tbprd = ehrpwm_read(ehrpwm, TBPRD);
1519 if (ehrpwm->version == PWM_VERSION_1)
1520 ehrpwm_ctx->hrcfg = ehrpwm_read(ehrpwm, AM335X_HRCNFG);
1521 else
1522 ehrpwm_ctx->hrcfg = ehrpwm_read(ehrpwm, HRCNFG);
1523 ehrpwm_ctx->aqctla = ehrpwm_read(ehrpwm, AQCTLA);
1524 ehrpwm_ctx->aqctlb = ehrpwm_read(ehrpwm, AQCTLB);
1525 ehrpwm_ctx->cmpa = ehrpwm_read(ehrpwm, CMPA);
1526 ehrpwm_ctx->cmpb = ehrpwm_read(ehrpwm, CMPB);
1527 ehrpwm_ctx->tzctl = ehrpwm_read(ehrpwm, TZCTL);
1528 ehrpwm_ctx->tzflg = ehrpwm_read(ehrpwm, TZFLG);
1529 ehrpwm_ctx->tzclr = ehrpwm_read(ehrpwm, TZCLR);
1530 ehrpwm_ctx->tzfrc = ehrpwm_read(ehrpwm, TZFRC);
1531 pm_runtime_put_sync(ehrpwm->dev);
1532 }
1534 void ehrpwm_context_restore(struct ehrpwm_pwm *ehrpwm,
1535 struct ehrpwm_context *ehrpwm_ctx)
1536 {
1537 ehrpwm_write(ehrpwm, TBCTL, ehrpwm_ctx->tbctl);
1538 ehrpwm_write(ehrpwm, TBPRD, ehrpwm_ctx->tbprd);
1539 if (ehrpwm->version == PWM_VERSION_1)
1540 ehrpwm_write(ehrpwm, AM335X_HRCNFG, ehrpwm_ctx->hrcfg);
1541 else
1542 ehrpwm_write(ehrpwm, HRCNFG, ehrpwm_ctx->hrcfg);
1543 ehrpwm_write(ehrpwm, AQCTLA, ehrpwm_ctx->aqctla);
1544 ehrpwm_write(ehrpwm, AQCTLB, ehrpwm_ctx->aqctlb);
1545 ehrpwm_write(ehrpwm, CMPA, ehrpwm_ctx->cmpa);
1546 ehrpwm_write(ehrpwm, CMPB, ehrpwm_ctx->cmpb);
1547 ehrpwm_write(ehrpwm, TZCTL, ehrpwm_ctx->tzctl);
1548 ehrpwm_write(ehrpwm, TZFLG, ehrpwm_ctx->tzflg);
1549 ehrpwm_write(ehrpwm, TZCLR, ehrpwm_ctx->tzclr);
1550 ehrpwm_write(ehrpwm, TZFRC, ehrpwm_ctx->tzfrc);
1551 }
1553 static int ehrpwm_suspend(struct platform_device *pdev, pm_message_t state)
1554 {
1555 struct ehrpwm_pwm *ehrpwm = platform_get_drvdata(pdev);
1557 ehrpwm_context_save(ehrpwm, &ehrpwm->ctx);
1558 pm_runtime_put_sync(ehrpwm->dev);
1560 return 0;
1561 }
1563 static int ehrpwm_resume(struct platform_device *pdev)
1564 {
1565 struct ehrpwm_pwm *ehrpwm = platform_get_drvdata(pdev);
1567 pm_runtime_get_sync(ehrpwm->dev);
1568 ehrpwm_context_restore(ehrpwm, &ehrpwm->ctx);
1570 return 0;
1571 }
1573 #else
1574 #define ehrpwm_suspend NULL
1575 #define ehrpwm_resume NULL
1576 #endif /* CONFIG_PM */
1578 static int __devexit ehrpwm_remove(struct platform_device *pdev)
1579 {
1580 struct ehrpwm_pwm *ehrpwm = platform_get_drvdata(pdev);
1581 struct resource *r;
1582 unsigned char i;
1583 int val;
1584 struct pwmss_platform_data *pdata;
1586 if (ehrpwm->version == PWM_VERSION_1) {
1587 pdata = (&pdev->dev)->platform_data;
1588 val = readw(ehrpwm->config_mem_base + PWMSS_CLKCONFIG);
1589 val &= ~BIT(EPWM_CLK_EN);
1590 writew(val, ehrpwm->config_mem_base + PWMSS_CLKCONFIG);
1591 iounmap(ehrpwm->config_mem_base);
1592 ehrpwm->config_mem_base = NULL;
1593 }
1595 for (i = 0; i < NCHAN; i++) {
1596 if (pwm_is_registered(&ehrpwm->pwm[i]))
1597 pwm_unregister(&ehrpwm->pwm[i]);
1598 }
1600 for (i = 0; i < 2; i++)
1601 if (ehrpwm->irq[i] != -ENXIO)
1602 free_irq(ehrpwm->irq[i], ehrpwm);
1603 iounmap(ehrpwm->mmio_base);
1605 if (ehrpwm->version == PWM_VERSION_1)
1606 r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1607 else
1608 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1610 release_mem_region(r->start, resource_size(r));
1611 platform_set_drvdata(pdev, NULL);
1612 clk_put(ehrpwm->clk);
1613 pm_runtime_disable(ehrpwm->dev);
1614 kfree(ehrpwm);
1616 return 0;
1617 }
1619 static struct platform_driver ehrpwm_driver = {
1620 .driver = {
1621 .name = "ehrpwm",
1622 .owner = THIS_MODULE,
1623 },
1624 .probe = ehrpwm_probe,
1625 .remove = __devexit_p(ehrpwm_remove),
1626 .suspend = ehrpwm_suspend,
1627 .resume = ehrpwm_resume,
1628 };
1630 static int __init ehrpwm_init(void)
1631 {
1632 return platform_driver_register(&ehrpwm_driver);
1633 }
1634 module_init(ehrpwm_init);
1636 static void __exit ehrpwm_exit(void)
1637 {
1638 platform_driver_unregister(&ehrpwm_driver);
1639 }
1640 module_exit(ehrpwm_exit);
1642 MODULE_AUTHOR("Texas Instruments");
1643 MODULE_DESCRIPTION("Driver for Davinci eHRPWM peripheral");
1644 MODULE_LICENSE("GPL");
1645 MODULE_ALIAS("platform:ehrpwm");