PWM: ecap: Clean the access method for PWMSS config space.
[sitara-epos/sitara-epos-kernel.git] / drivers / pwm / ehrpwm.c
1 /*
2  * eHRPWM driver for simple PWM output generation
3  *
4  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation version 2.
9  *
10  * This program is distributed .as is. WITHOUT ANY WARRANTY of any
11  * kind, whether express or implied; without even the implied warranty
12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/clk.h>
18 #include <linux/err.h>
19 #include <linux/io.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23 #include <linux/pwm/pwm.h>
24 #include <linux/pwm/ehrpwm.h>
26 #include <plat/clock.h>
27 #include <plat/config_pwm.h>
29 #ifdef DEBUG
30 #define debug(format, args...) printk(format, ##args)
31 #else
32 #define debug(format, args...) { }
33 #endif
35 /******************** Time base sub module*****************************/
36 #define TBCTL                           0x0
37 #define TBSTS                           0x2
38 #define TBPHS                           0x6
39 #define TBCTR                           0x8
40 #define TBPRD                           0xA
42 #define TBCTL_CLKDIV_MASK               (BIT(12) | BIT(11) | BIT(10))
43 #define TBCTL_HSPCLKDIV_MASK            (BIT(9) | BIT(8) | BIT(7))
44 #define TBCTL_SYNCOSEL_MASK             (BIT(5) | BIT(4))
45 #define TBCTL_CTRMODE_MASK              (BIT(1) | BIT(0))
47 #define TBCTL_CLKDIV_POS                0xA
48 #define TBCTL_HSPCLKDIV_POS             0x7
49 #define TBCTL_PHSEN_POS                 0x2
50 #define TBCTL_SYNCOSEL_POS              0x4
51 #define TBCTL_PHSDIR_POS                0xD
52 #define TBCTL_FRC_SYC_POS               0x6
53 #define TBCTL_LOAD_MD_POS               0x3
55 #define TBCTL_FREERUN_FREE              0x2
56 #define TBCTL_CTRMOD_CTRUP              0x0
58 /******************* Counter-Compare Sub Module ***********************/
59 #define CMPCTL                          0xE
60 #define CMPA                            0x12
61 #define CMPB                            0x14
63 #define CMPCTL_LDBMODE_MASK             (BIT(3) | BIT(2))
64 #define CMPCTL_LDAMODE_MASK             (BIT(1) | BIT(0))
66 #define CMPCTL_SHDAMODE_POS             0x4
67 #define CMPCTL_SHDBMODE_POS             0x6
68 #define CMPCTL_LDBMODE_POS              0x2
70 /*********************** Action Control Sub module ********************/
71 #define AQCTLA                          0x16
72 #define AQCTLB                          0x18
73 #define AQSFRC                          0x1A
74 #define AQCSFRC                         0x1c
76 #define ACTCTL_CBD_MASK                 (BIT(11) | BIT(10))
77 #define ACTCTL_CBU_MASK                 (BIT(9) | BIT(8))
78 #define ACTCTL_CAD_MASK                 (BIT(7) | BIT(6))
79 #define ACTCTL_CAU_MASK                 (BIT(5) | BIT(4))
80 #define ACTCTL_CPRD_MASK                (BIT(3) | BIT(2))
81 #define ACTCTL_CZRO_MASK                (BIT(1) | BIT(0))
83 #define ACTCTL_CTREQPRD_POS             0x2
84 #define ACTCTL_CTREQCMPAUP_POS          0x4
85 #define ACTCTL_CTREQCMPADN_POS          0x6
86 #define ACTCTL_CTREQCMPBUP_POS          0x8
87 #define ACTCTL_CTREQCMPBDN_POS          0xA
89 #define ACTCTL_CTREQCMP_LOW             0x1
90 #define ACTCTL_CTREQCMP_HIGH            0x2
91 #define ACTCTL_CTREQZRO_LOW             0x1
92 #define ACTCTL_CTREQZRO_HIGH            0x2
94 #define AQSFRC_ACTA_MASK                (BIT(1) | BIT(0))
95 #define AQSFRC_ACTB_MASK                (BIT(4) | BIT(3))
96 #define AQCSFRC_CFRC_LOAD_MASK          (BIT(7) | BIT(6))
97 #define AQCSFRC_OUTB_MASK               (BIT(3) | BIT(2))
98 #define AQCSFRC_OUTA_MASK               (BIT(1) | BIT(0))
100 #define AQSFRC_ACTB_POS                 0x3
101 #define AQSFRC_OTFRCA_POS               0x2
102 #define AQSFRC_OTFRCB_POS               0x5
103 #define AQSFRC_LDMD_POS                 0x6
105 #define AQCSFRC_OUTB_POS                0x2
107 /******************** Dead Band Generator Sub module *******************/
108 #define DBCTL                           0x1E
109 #define DBRED                           0x20
110 #define DBFED                           0x22
112 #define DBCTL_INMODE_MASK               (BIT(5) | BIT(4))
113 #define DBCTL_PLSEL_MASK                (BIT(3) | BIT(2))
114 #define DBCTL_OUTMODE_MASK              (BIT(1) | BIT(0))
116 #define DBCTL_INMODE_POS                0x4
117 #define DBCTL_POLSEL_POS                0x2
119 /********************** PWM Chopper Sub module ************************/
120 #define PCCTL                           0x3C
122 #define PCCTL_CHPDUTY_MASK              (BIT(10) | BIT(9) | BIT(8))
123 #define PCCTL_CHPFREQ_MASK              (BIT(7) | BIT(6) | BIT(5))
124 #define PCCTL_OSHTWTH_MASK              (BIT(4) | BIT(3) | BIT(2) | BIT(1))
126 #define PCCTL_CHPDUTY_POS               0x8
127 #define PCCTL_CHPFRQ_POS                0x5
128 #define PCCTL_OSTWID_POS                0x1
130 /*************************Trip-zone submodule **************************/
131 #define TZSEL                           0x24
132 #define TZCTL                           0x28
133 #define TZEINT                          0x2A
134 #define TZFLG                           0x2C
135 #define TZCLR                           0x2E
136 #define TZFRC                           0x30
138 #define TZCTL_ACTA_MASK                 (BIT(1) | BIT(0))
139 #define TZCTL_ACTB_MASK                 (BIT(3) | BIT(2))
141 #define TZCTL_ACTB_POS                  0x2
143 #define TZEINT_OSHTEVT_POS              0x2
144 #define TZEINT_CBCEVT_POS               0x1
146 /*************************Event-Trigger submodule registers**************/
147 #define ETSEL                           0x32
148 #define ETPS                            0x34
149 #define ETFLG                           0x36
150 #define ETCLR                           0x38
151 #define ETFRC                           0x3A
153 #define ETSEL_INTSEL_MASK               (BIT(2) | BIT(1) | BIT(0))
154 #define ETPS_INTCNT_MASK                (BIT(3) | BIT(2))
155 #define ETPS_INTPRD_MASK                (BIT(1) | BIT(0))
157 #define ETSEL_EN_INT_EN_POS             0x3
159 /**********************High Resolution Registers ********************/
160 #define TBPHSHR                         0x4
161 #define CMPAHR                          0x10
162 #define HRCNFG                          0x1040
164 #define AM335X_HRCNFG                   0x40
166 #define HRCNFG_EDGEMD_MASK              (BIT(1) | BIT(0))
167 #define HRCNFG_LDMD_POS                 0x3
168 #define HRCNFG_CTLMD_POS                0x2
170 struct ehrpwm_suspend_params {
171         struct pwm_device *pch;
172         unsigned long req_delay_cycles;
173         unsigned long act_delay;
174 } ehrpwm_suspend_params;
176 static inline unsigned short ehrpwm_read(struct ehrpwm_pwm *ehrpwm,
177         unsigned int offset)
179         return readw(ehrpwm->mmio_base + offset);
182 static inline void ehrpwm_write(struct ehrpwm_pwm *ehrpwm, unsigned int offset,
183         unsigned short val)
185         writew(val, ehrpwm->mmio_base + offset);
188 static void ehrpwm_reg_config(struct ehrpwm_pwm *ehrpwm, unsigned int offset,
189                unsigned short val, unsigned short mask)
191         unsigned short read_val;
193         read_val = ehrpwm_read(ehrpwm, offset);
194         read_val = read_val & ~mask;
195         read_val = read_val | val;
196         ehrpwm_write(ehrpwm, offset, read_val);
199 static inline struct ehrpwm_pwm *to_ehrpwm_pwm(const struct pwm_device *p)
201         return pwm_get_drvdata(p);
204 /* Time Base Module Configurations */
205 int ehrpwm_tb_set_prescalar_val(struct pwm_device *p, unsigned char clkdiv,
206         unsigned char hspclkdiv)
208         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
210         if (clkdiv > 0x7 || hspclkdiv > 0x7)
211                 return -EINVAL;
213         ehrpwm_reg_config(ehrpwm, TBCTL, clkdiv << TBCTL_CLKDIV_POS,
214                        TBCTL_CLKDIV_MASK);
215         ehrpwm_reg_config(ehrpwm, TBCTL, hspclkdiv << TBCTL_HSPCLKDIV_POS,
216                        TBCTL_HSPCLKDIV_MASK);
218         return 0;
220 EXPORT_SYMBOL(ehrpwm_tb_set_prescalar_val);
222 int ehrpwm_tb_config_sync(struct pwm_device *p, unsigned char phsen,
223         unsigned char syncosel)
225         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
227         if (phsen > 1 || syncosel > 0x3)
228                 return -EINVAL;
230         ehrpwm_reg_config(ehrpwm, TBCTL, phsen << TBCTL_PHSEN_POS, BIT(2));
231         ehrpwm_reg_config(ehrpwm, TBCTL, syncosel << TBCTL_SYNCOSEL_POS,
232                        TBCTL_SYNCOSEL_MASK);
234         return 0;
236 EXPORT_SYMBOL(ehrpwm_tb_config_sync);
238 int ehrpwm_tb_set_counter_mode(struct pwm_device *p, unsigned char ctrmode,
239                unsigned char phsdir)
241         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
243         if (ctrmode > 0x3 || phsdir > 1)
244                 return -EINVAL;
246         ehrpwm_reg_config(ehrpwm, TBCTL, phsdir << TBCTL_PHSDIR_POS, BIT(13));
247         ehrpwm_reg_config(ehrpwm, TBCTL, ctrmode, TBCTL_CTRMODE_MASK);
249         return 0;
251 EXPORT_SYMBOL(ehrpwm_tb_set_counter_mode);
253 int ehrpwm_tb_force_sync(struct pwm_device *p)
255         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
257         ehrpwm_reg_config(ehrpwm, TBCTL, ENABLE << TBCTL_FRC_SYC_POS, BIT(6));
259         return 0;
261 EXPORT_SYMBOL(ehrpwm_tb_force_sync);
263 int ehrpwm_tb_set_periodload(struct pwm_device *p, unsigned char loadmode)
265         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
267         if (loadmode > 0x1)
268                 return -EINVAL;
270         ehrpwm_reg_config(ehrpwm, TBCTL, loadmode << TBCTL_LOAD_MD_POS, BIT(3));
272         return 0;
274 EXPORT_SYMBOL(ehrpwm_tb_set_periodload);
276 int ehrpwm_tb_read_status(struct pwm_device *p, unsigned short *val)
278         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
280         *val = ehrpwm_read(ehrpwm, TBSTS);
282         return 0;
284 EXPORT_SYMBOL(ehrpwm_tb_read_status);
286 int ehrpwm_tb_read_counter(struct pwm_device *p, unsigned short *val)
288         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
290         *val = ehrpwm_read(ehrpwm, TBCTR);
292         return 0;
294 EXPORT_SYMBOL(ehrpwm_tb_read_counter);
296 int ehrpwm_tb_set_period(struct pwm_device *p,  unsigned short val)
298         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
300         ehrpwm_write(ehrpwm, TBPRD, val);
302         return 0;
304 EXPORT_SYMBOL(ehrpwm_tb_set_period);
306 int ehrpwm_tb_set_phase(struct pwm_device *p, unsigned short val)
308         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
310         ehrpwm_write(ehrpwm, TBPHS, val);
312         return 0;
314 EXPORT_SYMBOL(ehrpwm_tb_set_phase);
316 int ehrpwm_cmp_set_cmp_ctl(struct pwm_device *p, unsigned char shdwamode,
317         unsigned char shdwbmode, unsigned char loadamode,
318         unsigned char loadbmode)
320         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
322         if (shdwamode > 0x1 || shdwbmode > 0x1 || loadamode > 0x3 ||
323                 loadbmode > 0x3)
324                 return -EINVAL;
326         ehrpwm_reg_config(ehrpwm, CMPCTL, shdwamode << CMPCTL_SHDAMODE_POS,
327                        BIT(4));
328         ehrpwm_reg_config(ehrpwm, CMPCTL, shdwbmode << CMPCTL_SHDBMODE_POS,
329                        BIT(6));
330         ehrpwm_reg_config(ehrpwm, CMPCTL, loadamode, CMPCTL_LDAMODE_MASK);
331         ehrpwm_reg_config(ehrpwm, CMPCTL, loadbmode << CMPCTL_LDBMODE_POS,
332                        CMPCTL_LDBMODE_MASK);
334         return 0;
336 EXPORT_SYMBOL(ehrpwm_cmp_set_cmp_ctl);
338 int ehrpwm_cmp_set_cmp_val(struct pwm_device *p, unsigned char reg,
339         unsigned short val)
341         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
342         unsigned char offset;
344         if (reg > 0x1)
345                 return -EINVAL;
347         if (reg == 0)
348                 offset = CMPA;
349         else
350                 offset = CMPB;
352         ehrpwm_write(ehrpwm, offset, val);
354         return 0;
356 EXPORT_SYMBOL(ehrpwm_cmp_set_cmp_val);
358 int ehrpwm_aq_set_act_ctrl(struct pwm_device *p, struct aq_config_params *cfg)
360         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
361         unsigned char reg;
363         if (!cfg)
364                 return -EINVAL;
366         if (cfg->ch > 1 || cfg->ctreqzro > 3 || cfg->ctreqprd > 3 ||
367                 cfg->ctreqcmpaup > 3 || cfg->ctreqcmpadown > 3 ||
368                 cfg->ctreqcmpbup > 3 || cfg->ctreqcmpbdown > 3)
369                 return -EINVAL;
371         if (cfg->ch == 0)
372                 reg = AQCTLA;
373         else
374                 reg = AQCTLB;
376         ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqzro, ACTCTL_CZRO_MASK);
377         ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqprd << ACTCTL_CTREQPRD_POS,
378                        ACTCTL_CPRD_MASK);
379         ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpaup <<
380                        ACTCTL_CTREQCMPAUP_POS, ACTCTL_CAU_MASK);
381         ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpadown <<
382                        ACTCTL_CTREQCMPADN_POS, ACTCTL_CAD_MASK);
383         ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpbup <<
384                        ACTCTL_CTREQCMPBUP_POS, ACTCTL_CBU_MASK);
385         ehrpwm_reg_config(ehrpwm, reg, cfg->ctreqcmpbdown <<
386                        ACTCTL_CTREQCMPBDN_POS, ACTCTL_CBD_MASK);
388         return 0;
390 EXPORT_SYMBOL(ehrpwm_aq_set_act_ctrl);
392 int ehrpwm_aq_set_one_shot_act(struct pwm_device  *p, unsigned char ch,
393         unsigned char act)
395         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
397         if (ch > 1 || act > 3)
398                 return -EINVAL;
400         if (ch == 0)
401                 ehrpwm_reg_config(ehrpwm, AQSFRC, act, AQSFRC_ACTA_MASK);
402         else
403                 ehrpwm_reg_config(ehrpwm, AQSFRC, act << AQSFRC_ACTB_POS,
404                                AQSFRC_ACTB_MASK);
406         return 0;
408 EXPORT_SYMBOL(ehrpwm_aq_set_one_shot_act);
410 int ehrpwm_aq_ot_frc(struct pwm_device *p, unsigned char ch)
412         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
414         if (ch > 1)
415                 return -EINVAL;
417         if (ch == 0)
418                 ehrpwm_reg_config(ehrpwm, AQSFRC, ENABLE << AQSFRC_OTFRCA_POS,
419                                BIT(2));
420         else
421                 ehrpwm_reg_config(ehrpwm, AQSFRC, ENABLE << AQSFRC_OTFRCB_POS,
422                                BIT(5));
424         return 0;
426 EXPORT_SYMBOL(ehrpwm_aq_ot_frc);
428 int ehrpwm_aq_set_csfrc_load_mode(struct pwm_device *p, unsigned char loadmode)
430         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
432         if (loadmode > 0x3)
433                 return -EINVAL;
435         ehrpwm_reg_config(ehrpwm, AQSFRC, loadmode << AQSFRC_LDMD_POS,
436                        AQCSFRC_CFRC_LOAD_MASK);
438         return 0;
440 EXPORT_SYMBOL(ehrpwm_aq_set_csfrc_load_mode);
442 int ehrpwm_aq_continuous_frc(struct pwm_device *p, unsigned char ch,
443         unsigned char act)
445         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
447         if (ch > 1)
448                 return -EINVAL;
450         if (ch == 0)
451                 ehrpwm_reg_config(ehrpwm, AQCSFRC, act, AQCSFRC_OUTA_MASK);
452         else
453                 ehrpwm_reg_config(ehrpwm, AQCSFRC, act << AQCSFRC_OUTB_POS,
454                                AQCSFRC_OUTB_MASK);
456         return 0;
458 EXPORT_SYMBOL(ehrpwm_aq_continuous_frc);
460 int ehrpwm_db_get_max_delay(struct pwm_device *p, enum config_mask cfgmask,
461         unsigned long *delay_val)
463         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
464         unsigned long delay_ns;
465         unsigned long max_ticks;
467         if (cfgmask == CONFIG_NS) {
468                 max_ticks = 0x3ff * ehrpwm->prescale_val;
469                 delay_ns = pwm_ticks_to_ns(p, max_ticks);
470                 *delay_val = delay_ns;
471         } else if (cfgmask == CONFIG_TICKS) {
472                 *delay_val = 0x3ff * ehrpwm->prescale_val;
473         } else {
474                 return -EINVAL;
475         }
477         return 0;
479 EXPORT_SYMBOL(ehrpwm_db_get_max_delay);
481 int ehrpwm_db_get_delay(struct pwm_device *p, unsigned char edge,
482         enum config_mask cfgmask, unsigned long *delay_val)
484         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
485         unsigned long delay_ns;
486         unsigned long delay_ticks;
487         unsigned char offset;
489         if (!ehrpwm)
490                 return -EINVAL;
492         if (edge == RISING_EDGE_DELAY)
493                 offset = DBRED;
494         else if (edge == FALLING_EDGE_DELAY)
495                 offset = DBFED;
496         else
497                 return -EINVAL;
499         delay_ticks = ehrpwm_read(ehrpwm, offset);
500         /* Only least 10 bits are required */
501         delay_ticks = delay_ticks & 0x3ff;
502         if (cfgmask == CONFIG_TICKS) {
503                 *delay_val = delay_ticks * ehrpwm->prescale_val;
504         } else if (cfgmask == CONFIG_NS) {
505                 delay_ticks = delay_ticks * ehrpwm->prescale_val;
506                 delay_ns = pwm_ticks_to_ns(p, delay_ticks);
507                 debug("\n delay ns value is %lu", delay_ns);
508                 *delay_val = delay_ns;
509         } else {
510                 return -EINVAL;
511         }
513         return 0;
515 EXPORT_SYMBOL(ehrpwm_db_get_delay);
517 int ehrpwm_db_set_delay(struct pwm_device *p, unsigned char edge,
518                 enum config_mask cfgmask, unsigned long delay)
520         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
521         unsigned long delay_ticks;
522         unsigned char offset = 0;
524         if (!ehrpwm)
525                 return -EINVAL;
527         if (edge == RISING_EDGE_DELAY)
528                 offset = DBRED;
529         else if (edge == FALLING_EDGE_DELAY)
530                 offset = DBFED;
531         else
532                 return -EINVAL;
534         if (cfgmask == CONFIG_TICKS) {
535                 delay = delay / ehrpwm->prescale_val;
536                 if (delay > 0x3ff)
537                         return -EINVAL;
538                 ehrpwm_write(ehrpwm, offset, delay);
539         } else if (cfgmask == CONFIG_NS) {
540                 delay_ticks = pwm_ns_to_ticks(p, delay);
541                 delay_ticks = delay_ticks / ehrpwm->prescale_val;
542                 if (delay_ticks > 0x3ff) {
543                         ehrpwm_db_get_max_delay(p, CONFIG_NS, &delay_ticks);
544                         dev_dbg(p->dev, "%s: Expected delay cannot be"
545                         " attained setting the maximum possible delay of"
546                         " %lu ns", __func__, delay_ticks);
547                         delay_ticks = 0x3ff;
548                 }
549                 debug("\n delay ticks is %lu", delay_ticks);
550                 ehrpwm_write(ehrpwm, offset, delay_ticks);
551         } else {
552                 return -EINVAL;
553         }
555         return 0;
557 EXPORT_SYMBOL(ehrpwm_db_set_delay);
559 /* Dead Band Configuration functions */
560 int ehrpwm_db_set_mode(struct pwm_device *p, unsigned char inmode,
561                 unsigned char polsel, unsigned char outmode)
563         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
565         if (inmode > 0x3 || polsel > 0x3 || outmode > 0x3)
566                 return -EINVAL;
568         ehrpwm_reg_config(ehrpwm, DBCTL, inmode << DBCTL_INMODE_POS,
569                        DBCTL_INMODE_MASK);
570         ehrpwm_reg_config(ehrpwm, DBCTL, polsel << DBCTL_POLSEL_POS,
571                        DBCTL_PLSEL_MASK);
572         ehrpwm_reg_config(ehrpwm, DBCTL, outmode, DBCTL_OUTMODE_MASK);
574         return 0;
576 EXPORT_SYMBOL(ehrpwm_db_set_mode);
578 /* PWM chopper Configuration functions */
579 int ehrpwm_pc_configure(struct pwm_device *p, unsigned char chpduty,
580                 unsigned char chpfreq, unsigned char oshtwidth)
582         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
584         if (chpduty > 0x7 || chpfreq > 0x7 || oshtwidth > 0xf)
585                 return -EINVAL;
587         ehrpwm_reg_config(ehrpwm, PCCTL, chpduty << PCCTL_CHPDUTY_POS,
588                        PCCTL_CHPDUTY_MASK);
589         ehrpwm_reg_config(ehrpwm, PCCTL, chpfreq << PCCTL_CHPFRQ_POS,
590                        PCCTL_CHPFREQ_MASK);
591         ehrpwm_reg_config(ehrpwm, PCCTL, oshtwidth << PCCTL_OSTWID_POS,
592                        PCCTL_OSHTWTH_MASK);
594         return 0;
596 EXPORT_SYMBOL(ehrpwm_pc_configure);
598 int ehrpwm_pc_en_dis(struct pwm_device *p, unsigned char chpen)
600         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
602         if (chpen > 1)
603                 return -EINVAL;
605         ehrpwm_reg_config(ehrpwm, PCCTL, chpen, BIT(0));
607         return 0;
609 EXPORT_SYMBOL(ehrpwm_pc_en_dis);
611 /* Trip Zone configuration functions */
612 int ehrpwm_tz_sel_event(struct pwm_device *p, unsigned char input,
613                enum tz_event evt)
615         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
617         unsigned short val = 0;
618         unsigned short mask;
619         unsigned short pos;
621         if (evt > 4 || input > 7)
622                 return -EINVAL;
624         switch (evt) {
625         case TZ_ONE_SHOT_EVENT:
626                 pos = input + 8;
627                 mask = BIT((pos)) | BIT(input);
628                 ehrpwm_reg_config(ehrpwm, TZSEL, 1 << pos, mask);
629                 break;
631         case TZ_CYCLE_BY_CYCLE:
632                 pos = input;
633                 mask = BIT(pos) | BIT((pos + 8));
634                 ehrpwm_reg_config(ehrpwm, TZSEL, 1 << pos, mask);
635                 break;
637         case TZ_OSHT_CBC:
638         case TZ_DIS_EVT:
639                 if (evt == TZ_OSHT_CBC)
640                         val = 1;
641                 else
642                         val = 0;
644                 pos = input + 8;
645                 mask = BIT((pos));
646                 ehrpwm_reg_config(ehrpwm, TZSEL, val << pos, mask);
647                 pos = input;
648                 mask = BIT((pos));
649                 ehrpwm_reg_config(ehrpwm, TZSEL, val << pos, mask);
650                 break;
652         default:
653                 dev_dbg(p->dev, "%s: Invalid command", __func__);
654                 return -EINVAL;
655         }
656         debug("\n TZ_sel val is %0x", ehrpwm_read(ehrpwm, TZSEL));
658         return 0;
660 EXPORT_SYMBOL(ehrpwm_tz_sel_event);
662 int ehrpwm_tz_set_action(struct pwm_device *p, unsigned char ch,
663         unsigned char act)
665         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
667         if (act > 0x3 || ch > 1)
668                 return -EINVAL;
670         if (ch == 0)
671                 ehrpwm_reg_config(ehrpwm, TZCTL, act, TZCTL_ACTA_MASK);
672         else
673                 ehrpwm_reg_config(ehrpwm, TZCTL, act << TZCTL_ACTB_POS,
674                                TZCTL_ACTB_MASK);
676         debug("\n TZCTL reg val is %0x", ehrpwm_read(ehrpwm, TZCTL));
678         return 0;
680 EXPORT_SYMBOL(ehrpwm_tz_set_action);
682 int ehrpwm_tz_set_int_en_dis(struct pwm_device *p, enum tz_event event,
683                 unsigned char int_en_dis)
685         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
687         if (event == TZ_ONE_SHOT_EVENT)
688                 ehrpwm_reg_config(ehrpwm, TZEINT, int_en_dis <<
689                                TZEINT_OSHTEVT_POS, BIT(2));
690         else if (event == TZ_CYCLE_BY_CYCLE)
691                 ehrpwm_reg_config(ehrpwm, TZEINT, int_en_dis <<
692                                TZEINT_CBCEVT_POS, BIT(1));
693         else
694                 return -EINVAL;
696         debug("\n TZEINT reg val is %0x", ehrpwm_read(ehrpwm, TZEINT));
698         return 0;
700 EXPORT_SYMBOL(ehrpwm_tz_set_int_en_dis);
702 int ehrpwm_tz_force_evt(struct pwm_device *p, enum tz_event event)
704         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
706         if (event == TZ_ONE_SHOT_EVENT)
707                 ehrpwm_write(ehrpwm, TZFRC, 0x4);
708         else if (event == TZ_CYCLE_BY_CYCLE)
709                 ehrpwm_write(ehrpwm, TZFRC, 0x2);
710         else
711                 return -EINVAL;
713         return 0;
715 EXPORT_SYMBOL(ehrpwm_tz_force_evt);
717 inline int ehrpwm_tz_read_status(struct pwm_device *p, unsigned short *status)
719         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
721         *status = ehrpwm_read(ehrpwm, TZFLG);
723         return 0;
725 EXPORT_SYMBOL(ehrpwm_tz_read_status);
727 inline int ehrpwm_tz_clr_evt_status(struct pwm_device *p)
729         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
730         unsigned short ret;
732         ret = ehrpwm_read(ehrpwm, TZFLG);
733         ehrpwm_write(ehrpwm, TZCLR, ret & ~0x1);
735         return 0;
737 EXPORT_SYMBOL(ehrpwm_tz_clr_evt_status);
739 inline int ehrpwm_tz_clr_int_status(struct pwm_device *p)
741         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
743         ehrpwm_write(ehrpwm, TZCLR, 0x1);
745         return 0;
747 EXPORT_SYMBOL(ehrpwm_tz_clr_int_status);
749 /* Event Trigger Configuration functions */
750 int ehrpwm_et_set_sel_evt(struct pwm_device *p, unsigned char evt,
751                 unsigned char prd)
753         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
755         if (evt > 0x7 || prd > 0x3)
756                 return -EINVAL;
758         ehrpwm_reg_config(ehrpwm, ETSEL, evt, ETSEL_INTSEL_MASK);
759         ehrpwm_reg_config(ehrpwm, ETPS, prd, ETPS_INTPRD_MASK);
761         return 0;
763 EXPORT_SYMBOL(ehrpwm_et_set_sel_evt);
765 inline int ehrpwm_et_int_en_dis(struct pwm_device *p, unsigned char en_dis)
767         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
769         ehrpwm_reg_config(ehrpwm, ETSEL, en_dis << ETSEL_EN_INT_EN_POS, BIT(3));
771         return 0;
773 EXPORT_SYMBOL(ehrpwm_et_int_en_dis);
775 inline int ehrpwm_et_read_evt_cnt(struct pwm_device *p,
776         unsigned long *evtcnt)
778         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
780         *evtcnt = ehrpwm_read(ehrpwm, ETPS) & ETPS_INTCNT_MASK;
781         *evtcnt >>= 0x2;
783         return 0;
785 EXPORT_SYMBOL(ehrpwm_et_read_evt_cnt);
787 inline int ehrpwm_et_read_int_status(struct pwm_device *p,
788         unsigned long *status)
790         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
792         *status = ehrpwm_read(ehrpwm, ETFLG) & BIT(0);
794         return 0;
796 EXPORT_SYMBOL(ehrpwm_et_read_int_status);
798 inline int ehrpwm_et_frc_int(struct pwm_device *p)
800         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
802         ehrpwm_write(ehrpwm, ETFRC, ENABLE);
804         return 0;
806 EXPORT_SYMBOL(ehrpwm_et_frc_int);
808 inline int ehrpwm_et_clr_int(struct pwm_device *p)
810         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
812         ehrpwm_write(ehrpwm, ETCLR, ENABLE);
814         return 0;
816 EXPORT_SYMBOL(ehrpwm_et_clr_int);
818 /* High Resolution Module configuration */
819 inline int ehrpwm_hr_set_phase(struct pwm_device *p, unsigned char val)
821         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
823         ehrpwm_write(ehrpwm, TBPHSHR, val << 8);
825         return 0;
827 EXPORT_SYMBOL(ehrpwm_hr_set_phase);
829 inline int ehrpwm_hr_set_cmpval(struct pwm_device *p, unsigned char val)
831         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
833         ehrpwm_write(ehrpwm, CMPAHR, val << 8);
835         return 0;
837 EXPORT_SYMBOL(ehrpwm_hr_set_cmpval);
839 int ehrpwm_hr_config(struct pwm_device *p, unsigned char loadmode,
840                 unsigned char ctlmode, unsigned char edgemode)
842         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
844         if (loadmode > 1 || ctlmode > 1 || edgemode > 3)
845                 return -EINVAL;
847         if (ehrpwm->version == PWM_VERSION_1) {
848                 ehrpwm_reg_config(ehrpwm, AM335X_HRCNFG,
849                                 loadmode << HRCNFG_LDMD_POS, BIT(3));
850                 ehrpwm_reg_config(ehrpwm, AM335X_HRCNFG,
851                                 ctlmode << HRCNFG_CTLMD_POS, BIT(2));
852                 ehrpwm_reg_config(ehrpwm, AM335X_HRCNFG,
853                                 edgemode, HRCNFG_EDGEMD_MASK);
854         } else {
855                 ehrpwm_reg_config(ehrpwm, HRCNFG,
856                                 loadmode << HRCNFG_LDMD_POS, BIT(3));
857                 ehrpwm_reg_config(ehrpwm, HRCNFG,
858                                 ctlmode << HRCNFG_CTLMD_POS, BIT(2));
859                 ehrpwm_reg_config(ehrpwm, HRCNFG,
860                                 edgemode, HRCNFG_EDGEMD_MASK);
861         }
863         return 0;
865 EXPORT_SYMBOL(ehrpwm_hr_config);
867 inline int ehrpwm_reg_read(struct pwm_device *p, unsigned int reg,
868                unsigned short *val)
870         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
872         if (!(ehrpwm->version == PWM_VERSION_1)) {
873                 if (reg > HRCNFG)
874                         return -EINVAL;
875         }
877         *val = ehrpwm_read(ehrpwm, reg);
879         return 0;
881 EXPORT_SYMBOL(ehrpwm_reg_read);
883 inline int ehrpwm_reg_write(struct pwm_device *p, unsigned int reg,
884                unsigned short val)
886         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
888         if (!(ehrpwm->version == PWM_VERSION_1)) {
889                 if (reg > HRCNFG)
890                         return -EINVAL;
891         }
893         ehrpwm_write(ehrpwm, reg, val);
895         return 0;
897 EXPORT_SYMBOL(ehrpwm_reg_write);
899 static int ehrpwm_pwm_start(struct pwm_device *p)
901         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
902         unsigned short val;
903         unsigned short read_val1;
904         unsigned short read_val2;
905         int chan;
907         chan = p - &ehrpwm->pwm[0];
908         val = ehrpwm_read(ehrpwm, TBCTL);
909         val = (val & ~TBCTL_CTRMODE_MASK) | (TBCTL_CTRMOD_CTRUP |
910                  TBCTL_FREERUN_FREE << 14);
911         ehrpwm_write(ehrpwm, TBCTL, val);
912         ehrpwm_tz_set_action(p, chan, 0x3);
913         read_val1 = ehrpwm_read(ehrpwm, TZFLG);
914         read_val2 = ehrpwm_read(ehrpwm, TZCTL);
915         /*
916          * State of the other channel is determined by reading the
917          * TZCTL register. If the other channel is also in running state,
918          * one shot event status is cleared, otherwise one shot action for
919          * this channel is set to "DO NOTHING.
920          */
921         read_val2 = read_val2 & (chan ? 0x3 : (0x3 << 2));
922         read_val2 = chan ? read_val2 : (read_val2 >> 2);
923         if (!(read_val1 & 0x4) || (read_val2 == 0x3))
924                 ehrpwm_tz_clr_evt_status(p);
925         set_bit(FLAG_RUNNING, &p->flags);
927         return 0;
930 /*
931  * Stop function is implemented using the Trip Zone module. Action for the
932  * corresponding channel is set to low and the one shot software force
933  * event is triggered.
934  */
935 static int ehrpwm_pwm_stop(struct pwm_device *p)
937         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
938         unsigned short read_val;
939         int chan;
941         chan = p - &ehrpwm->pwm[0];
942         /* Set the Trip Zone Action to low */
943         ehrpwm_tz_set_action(p, chan, 0x2);
944         read_val = ehrpwm_read(ehrpwm, TZFLG);
945         /*
946          * If the channel is already in stop state, Trip Zone software force is
947          * not required
948          */
949         if (!(read_val & 0x4)) {
950                 ehrpwm_tz_clr_evt_status(p);
951                 ehrpwm_tz_force_evt(p, TZ_ONE_SHOT_EVENT);
952         }
953         clear_bit(FLAG_RUNNING, &p->flags);
955         return 0;
958 static int ehrpwm_pwm_set_pol(struct pwm_device *p)
960         unsigned int act_ctrl_reg;
961         unsigned int cmp_reg;
962         unsigned int ctreqcmp_mask;
963         unsigned int ctreqcmp;
964         unsigned short val;
965         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
966         int chan;
968         chan = p - &ehrpwm->pwm[0];
969         if (!chan) {
970                 act_ctrl_reg = AQCTLA;
971                 cmp_reg = CMPA;
972                 ctreqcmp_mask = ACTCTL_CAU_MASK;
973                 ctreqcmp = 4;
974         } else {
975                 act_ctrl_reg = AQCTLB;
976                 cmp_reg = CMPB;
977                 ctreqcmp_mask = ACTCTL_CBU_MASK;
978                 ctreqcmp = 8;
979         }
982         val = ((p->active_high ? ACTCTL_CTREQCMP_HIGH : ACTCTL_CTREQCMP_LOW)
983                  << ctreqcmp) | (p->active_high ? ACTCTL_CTREQZRO_LOW :
984                         ACTCTL_CTREQZRO_HIGH);
985         ehrpwm_write(ehrpwm, act_ctrl_reg, val);
987         return 0;
990 /*
991  * Prescalar is used when the period value exceeds the maximum value
992  * of the 16 bit period register. We always look for the minimum prescalar
993  * value as it would result in wide range of duty control
994  */
995 static char get_divider_val(unsigned int desired_ps_val, unsigned int
996 *ps_div_val, unsigned int *tb_div_val)
998         char i = 0;
999         char j = 0;
1001         for (i = 0; i <= 7; i++) {
1002                 for (j = 0; j <= 7; j++) {
1003                         if (((1 << i) * (j ? (j * 2) : 1)) >= desired_ps_val) {
1004                                 *ps_div_val = (1 << i) * (j ? (j * 2) : 1);
1005                                 *tb_div_val = (i << 10) | (j << 7) ;
1006                                 return 0;
1007                         }
1008                 }
1009         }
1011         return -1;
1014 static int ehrpwm_pwm_set_prd(struct pwm_device *p)
1016         unsigned int ps_div_val = 1;
1017         unsigned int tb_div_val = 0;
1018         char ret;
1019         unsigned short val;
1020         unsigned short period_ticks;
1021         struct pwm_device *temp;
1022         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
1023         int chan = 0;
1024         /*
1025          * Since the device has a singe period register, copy the period
1026          * value to the other channel also.
1027          */
1028         chan = p - &ehrpwm->pwm[0];
1029         temp = &ehrpwm->pwm[!chan];
1030         temp->period_ticks = p->period_ticks;
1031         temp->period_ns = p->period_ns;
1032         debug("\n period_ticks is %lu", p->period_ticks);
1034         if (p->period_ticks > 65535) {
1035                 ret = get_divider_val(p->period_ticks / 65535 + 1, &ps_div_val,
1036                                 &tb_div_val);
1037                 if (ret) {
1038                         dev_err(p->dev, "failed to get the divider value");
1039                         return -EINVAL;
1040                 }
1041         }
1043         val = ehrpwm_read(ehrpwm, TBCTL);
1044         val = (val & ~TBCTL_CLKDIV_MASK & ~TBCTL_HSPCLKDIV_MASK) | tb_div_val;
1045         ehrpwm_write(ehrpwm, TBCTL, val);
1046         period_ticks = p->period_ticks / ps_div_val;
1048         if (period_ticks <= 1) {
1049                 dev_err(p->dev, "Required period/frequency cannot be obtained");
1050                 return -EINVAL;
1051         }
1052         /*
1053          * Program the period register with 1 less than the actual value since
1054          * the module generates waveform with period always 1 greater
1055          * the programmed value.
1056          */
1057         ehrpwm_write(ehrpwm, TBPRD, (unsigned short)(period_ticks - 1));
1058         debug("\n period_ticks is %d", period_ticks);
1059         ehrpwm->prescale_val = ps_div_val;
1060         debug("\n Prescaler value is %d", ehrpwm->prescale_val);
1062         return 0;
1065 static int ehrpwm_hr_duty_config(struct pwm_device *p)
1067         unsigned char no_of_mepsteps;
1068         unsigned short cmphr_val;
1069         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
1071         if (!p->tick_hz) {
1072                 dev_dbg(p->dev, "%s: p->tick_hz is zero\n", __func__);
1073                 return -EINVAL;
1074         }
1076         /*
1077          * Calculate the no of MEP steps. Assume system clock
1078          * is in the order of MHZ.
1079          */
1080         no_of_mepsteps = USEC_PER_SEC / ((p->tick_hz / USEC_PER_SEC) * 63);
1082         /* Calculate the CMPHR Value */
1083         cmphr_val = p->tick_hz / USEC_PER_SEC;
1084         cmphr_val = (p->duty_ns * cmphr_val) % MSEC_PER_SEC;
1085         cmphr_val = (cmphr_val * no_of_mepsteps) / 1000;
1086         cmphr_val = (cmphr_val << 8) + 0x180;
1087         ehrpwm_write(ehrpwm, CMPAHR, cmphr_val);
1089         if (ehrpwm->version == PWM_VERSION_1)
1090                 ehrpwm_write(ehrpwm, AM335X_HRCNFG, 0x2);
1091         else
1092                 ehrpwm_write(ehrpwm, HRCNFG, 0x2);
1094         return 0;
1097 static int ehrpwm_pwm_set_dty(struct pwm_device *p)
1099         unsigned short duty_ticks = 0;
1100         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
1101         int ret = 0;
1102         int chan;
1104         chan = p - &ehrpwm->pwm[0];
1106         if (!ehrpwm->prescale_val) {
1107                 dev_dbg(p->dev, "%s: prescale_val is zero\n", __func__);
1108                 return -EINVAL;
1109         }
1111         duty_ticks = p->duty_ticks / ehrpwm->prescale_val;
1112         debug("\n Prescaler value is %d", ehrpwm->prescale_val);
1113         debug("\n duty ticks is %d", duty_ticks);
1114         /* High resolution module */
1115         if (chan && ehrpwm->prescale_val <= 1) {
1116                 ret = ehrpwm_hr_duty_config(p);
1117                 if (ehrpwm->version == PWM_VERSION_1)
1118                         ehrpwm_write(ehrpwm, AM335X_HRCNFG, 0x2);
1119                 else
1120                         ehrpwm_write(ehrpwm, HRCNFG, 0x2);
1121         }
1123         ehrpwm_pwm_set_pol(p);
1124         ehrpwm_write(ehrpwm, (chan ? CMPB : CMPA), duty_ticks);
1126         return ret;
1129 int ehrpwm_et_cb_register(struct pwm_device *p, void *data,
1130         p_fcallback cb)
1132         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
1133         unsigned long flags;
1135         spin_lock_irqsave(&ehrpwm->lock, flags);
1136         ehrpwm->st_etint.data = data;
1137         ehrpwm->st_etint.pcallback = cb;
1138         spin_unlock_irqrestore(&ehrpwm->lock, flags);
1140         return 0;
1142 EXPORT_SYMBOL(ehrpwm_et_cb_register);
1144 int ehrpwm_tz_cb_register(struct pwm_device *p, void *data,
1145         p_fcallback cb)
1147         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
1148         unsigned long flags;
1150         spin_lock_irqsave(&ehrpwm->lock, flags);
1151         ehrpwm->st_tzint.data = data;
1152         ehrpwm->st_tzint.pcallback = cb;
1153         spin_unlock_irqrestore(&ehrpwm->lock, flags);
1155         return 0;
1157 EXPORT_SYMBOL(ehrpwm_tz_cb_register);
1159 static int ehrpwm_pwm_suspend_cb(struct ehrpwm_pwm *ehrpwm, void *data)
1161         struct ehrpwm_suspend_params *pwm_suspend_params =
1162                                 (struct ehrpwm_suspend_params *)data;
1164         if (pwm_suspend_params->act_delay++ >= pwm_suspend_params->
1165                         req_delay_cycles) {
1166                 pwm_start(pwm_suspend_params->pch);
1167                 ehrpwm_et_cb_register(pwm_suspend_params->pch, NULL, NULL);
1168                 ehrpwm_et_int_en_dis(pwm_suspend_params->pch, DISABLE);
1169         }
1171         return 0;
1174 int ehrpwm_pwm_suspend(struct pwm_device *p, enum config_mask config_mask,
1175                unsigned long val)
1177         unsigned long long req_cycles = 0;
1179         if (!p->period_ns)
1180                 return -EINVAL;
1182         ehrpwm_pwm_stop(p);
1183         /* Calculate the delay in terms of cycles */
1184         if (config_mask == CONFIG_NS)
1185                 req_cycles =  val / p->period_ns;
1186         else if (config_mask == CONFIG_TICKS)
1187                 req_cycles = val;
1188         else
1189                 return -EINVAL;
1191         /* Configute the event interrupt */
1192         ehrpwm_et_set_sel_evt(p, 0x2, 0x1);
1193         ehrpwm_suspend_params.pch = p;
1194         ehrpwm_suspend_params.req_delay_cycles = req_cycles;
1195         ehrpwm_suspend_params.act_delay = 0;
1196         ehrpwm_et_cb_register(p, &ehrpwm_suspend_params,
1197                 ehrpwm_pwm_suspend_cb);
1198         ehrpwm_et_int_en_dis(p, ENABLE);
1200         return 0;
1202 EXPORT_SYMBOL(ehrpwm_pwm_suspend);
1204 static irqreturn_t ehrpwm_trip_zone_irq_handler(int irq, void *data)
1206         struct ehrpwm_pwm *ehrpwm = (struct ehrpwm_pwm *)data;
1207         unsigned long flags;
1208         int ret = 0;
1210         spin_lock_irqsave(&ehrpwm->lock, flags);
1211          ret = ehrpwm_read(ehrpwm, TZFLG);
1212         if (!(ret & 0x1))
1213                 return IRQ_NONE;
1215         if (ehrpwm->st_tzint.pcallback)
1216                 ret = ehrpwm->st_tzint.pcallback(ehrpwm, ehrpwm->st_tzint.data);
1218         ret = ehrpwm_read(ehrpwm, TZFLG);
1219         ehrpwm_write(ehrpwm, TZCLR, ret & ~0x1);
1220         ehrpwm_write(ehrpwm, TZCLR, 0x1);
1221         spin_unlock_irqrestore(&ehrpwm->lock, flags);
1223         return IRQ_HANDLED;
1226 static irqreturn_t ehrpwm_event_irq_handler(int irq, void *data)
1228         struct ehrpwm_pwm *ehrpwm = (struct ehrpwm_pwm *)data;
1229         unsigned long flags;
1231         spin_lock_irqsave(&ehrpwm->lock, flags);
1233         if (ehrpwm->st_etint.pcallback)
1234                 ehrpwm->st_etint.pcallback(ehrpwm, ehrpwm->st_etint.data);
1236         ehrpwm_write(ehrpwm, ETCLR, 0x1);
1238         spin_unlock_irqrestore(&ehrpwm->lock, flags);
1240         return IRQ_HANDLED;
1243 static int ehrpwm_pwm_config(struct pwm_device *p,
1244         struct pwm_config *c)
1246         int ret = 0;
1248         switch (c->config_mask) {
1249         case BIT(PWM_CONFIG_PERIOD_TICKS):
1250                 if (p->max_period_ticks &&
1251                                 (p->max_period_ticks >= c->period_ticks))
1252                         p->period_ticks = p->max_period_ticks;
1253                 else
1254                         p->period_ticks = c->period_ticks;
1256                 ret = ehrpwm_pwm_set_prd(p);
1257                 break;
1259         case BIT(PWM_CONFIG_DUTY_TICKS):
1260                 p->duty_ticks = c->duty_ticks;
1261                 ret = ehrpwm_pwm_set_dty(p);
1262                 break;
1264         case BIT(PWM_CONFIG_POLARITY):
1265                 p->active_high = c->polarity;
1266                 ret = ehrpwm_pwm_set_pol(p);
1267                 break;
1269         case BIT(PWM_CONFIG_START):
1270                  ret = ehrpwm_pwm_start(p);
1271                  break;
1273         case BIT(PWM_CONFIG_STOP):
1274                 ret = ehrpwm_pwm_stop(p);
1275                 break;
1277         default:
1278                 dev_dbg(p->dev, "%s: Invalid configuration\n", __func__);
1279                 ret = -EINVAL;
1280         }
1282         return ret;
1285 static int ehrpwm_pwm_request(struct pwm_device *p)
1287         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
1288         int chan;
1290         chan = p - &ehrpwm->pwm[0];
1292         p->tick_hz = clk_get_rate(ehrpwm->clk);
1293         debug("\n The clk freq is %lu", p->tick_hz);
1294         clk_enable(ehrpwm->clk);
1295         ehrpwm_pwm_stop(p);
1297         return 0;
1300 static int ehrpwm_freq_transition_cb(struct pwm_device *p)
1302         struct ehrpwm_pwm *ehrpwm = to_ehrpwm_pwm(p);
1303         unsigned long duty_ns;
1305         p->tick_hz = clk_get_rate(ehrpwm->clk);
1306         duty_ns = p->duty_ns;
1307         if (pwm_is_running(p)) {
1308                 pwm_stop(p);
1309                 pwm_set_duty_ns(p, 0);
1310                 pwm_set_period_ns(p, p->period_ns);
1311                 pwm_set_duty_ns(p, duty_ns);
1312                 pwm_start(p);
1313         } else {
1314                 pwm_set_duty_ns(p, 0);
1315                 pwm_set_period_ns(p, p->period_ns);
1316                 pwm_set_duty_ns(p, duty_ns);
1317         }
1318                 return 0;
1321 static int ehrpwm_probe(struct platform_device *pdev)
1323         struct ehrpwm_pwm *ehrpwm = NULL;
1324         struct resource *r;
1325         int ret = 0;
1326         int chan = 0;
1327         struct pwmss_platform_data *pdata = (&pdev->dev)->platform_data;
1328         int ch_mask = 0;
1329         int val;
1330         char con_id[PWM_CON_ID_STRING_LENGTH] = "epwmss";
1332         ehrpwm = kzalloc(sizeof(*ehrpwm), GFP_KERNEL);
1333         if (!ehrpwm) {
1334                 dev_err(&pdev->dev, "failed to allocate memory\n");
1335                 ret = -ENOMEM;
1336                 goto err_mem_failure;
1337         }
1339         ehrpwm->version = pdata->version;
1341         if (ehrpwm->version == PWM_VERSION_1) {
1342                 sprintf(con_id, "%s%d_%s", con_id, pdev->id, "fck");
1343                 ehrpwm->clk = clk_get(&pdev->dev, con_id);
1344         } else
1345                 ehrpwm->clk = clk_get(&pdev->dev, "ehrpwm");
1347         if (IS_ERR(ehrpwm->clk)) {
1348                 ret = PTR_ERR(ehrpwm->clk);
1349                 goto err_clock_failure;
1350         }
1352         if (ehrpwm->version == PWM_VERSION_1) {
1353                 down(&pdata->config_semaphore);
1354                 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1356                 if (!r) {
1357                         dev_err(&pdev->dev, "no memory resource defined\n");
1358                         ret = -ENOMEM;
1359                         up(&pdata->config_semaphore);
1360                         goto err_resource_mem_failure;
1361                 }
1363                 r = request_mem_region(r->start, resource_size(r), pdev->name);
1365                 if (!r) {
1367                         if (pdata->config_mem_base) {
1368                                 goto set_bit;
1369                         } else {
1370                                 dev_err(&pdev->dev,
1371                                         "failed to request memory resource\n");
1372                                 ret = -EBUSY;
1373                                 up(&pdata->config_semaphore);
1374                                 goto err_request_mem_failure;
1375                         }
1376                 }
1378                 pdata->config_mem_base = ioremap(r->start, resource_size(r));
1380                 if (!pdata->config_mem_base) {
1382                         dev_err(&pdev->dev, "failed to ioremap() registers\n");
1383                         ret = -ENODEV;
1384                         up(&pdata->config_semaphore);
1385                         goto err_free_mem_config;
1386                 }
1388 set_bit:
1389                 pdata->pwmss_module_usage_count++;
1390                 clk_enable(ehrpwm->clk);
1391                 val = __raw_readw(pdata->config_mem_base + PWMSS_CLKCONFIG);
1392                 val |= BIT(EPWM_CLK_EN);
1393                 __raw_writew(val, pdata->config_mem_base + PWMSS_CLKCONFIG);
1394                 clk_disable(ehrpwm->clk);
1395                 up(&pdata->config_semaphore);
1397         } else
1398                 ch_mask = pdata->channel_mask;
1400         spin_lock_init(&ehrpwm->lock);
1401         ehrpwm->ops.config = ehrpwm_pwm_config;
1402         ehrpwm->ops.request = ehrpwm_pwm_request;
1403         ehrpwm->ops.freq_transition_notifier_cb = ehrpwm_freq_transition_cb;
1404         ehrpwm->prescale_val = 1;
1406         if (ehrpwm->version == PWM_VERSION_1)
1407                 r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1408         else
1409                 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1411         if (!r) {
1412                 dev_err(&pdev->dev, "no memory resource defined\n");
1413                 ret = -ENODEV;
1414                 goto err_resource_mem2_failiure;
1415         }
1417         r = request_mem_region(r->start, resource_size(r), pdev->name);
1418         if (!r) {
1419                 dev_err(&pdev->dev, "failed to request memory resource\n");
1420                 ret = -EBUSY;
1421                 goto err_request_mem2_failure;
1422         }
1424         ehrpwm->mmio_base = ioremap(r->start, resource_size(r));
1425         if (!ehrpwm->mmio_base) {
1426                 dev_err(&pdev->dev, "failed to ioremap() registers\n");
1427                 ret = -ENODEV;
1428                 goto err_free_mem2;
1429         }
1431         ehrpwm->irq[0] = platform_get_irq(pdev, 0);
1432         if (ehrpwm->irq[0] == -ENXIO) {
1433                 dev_err(&pdev->dev, "No IRQ resource\n");
1434                 ret = -ENXIO;
1435                 goto err_free_io;
1436         }
1438         ret = request_irq(ehrpwm->irq[0], ehrpwm_trip_zone_irq_handler,
1439                                 0, "ehrpwmTZ", ehrpwm);
1440         if (ret)
1441                 goto err_free_io;
1443         ehrpwm->irq[1] = platform_get_irq(pdev, 1);
1444         if (ehrpwm->irq[1] == -ENXIO) {
1445                 dev_err(&pdev->dev, "No IRQ resource\n");
1446                 ret = -ENXIO;
1447                 goto err_request_irq;
1448         }
1450         ret = request_irq(ehrpwm->irq[1], ehrpwm_event_irq_handler,
1451                                 0, "ehrpwm_evt", ehrpwm);
1452         if (ret)
1453                 goto err_request_irq;
1455         for (chan = 0; chan < NCHAN; chan++) {
1456                 ehrpwm->pwm[chan].ops = &ehrpwm->ops;
1457                 pwm_set_drvdata(&ehrpwm->pwm[chan], ehrpwm);
1458                 ehrpwm->pwm[chan].tick_hz = clk_get_rate(ehrpwm->clk);
1460                 if (pdata->chan_attrib[chan].max_freq) {
1461                         int period_ns = NSEC_PER_SEC
1462                                 / pdata->chan_attrib[chan].max_freq;
1464                         ehrpwm->pwm[chan].max_period_ticks =
1465                                 pwm_ns_to_ticks(&ehrpwm->pwm[chan], period_ns);
1466                 }
1468                 if (!(ehrpwm->version == PWM_VERSION_1)) {
1469                         if (!(ch_mask & (0x1 << chan)))
1470                                 continue;
1471                 }
1473                 ret =  pwm_register(&ehrpwm->pwm[chan], &pdev->dev, chan);
1474                 if (ret)
1475                         goto err_pwm_register;
1476         }
1478                 platform_set_drvdata(pdev, ehrpwm);
1479         return 0;
1481 err_pwm_register:
1482         for (chan = 0; chan < NCHAN; chan++) {
1483                 if (pwm_is_registered(&ehrpwm->pwm[chan]))
1484                         pwm_unregister(&ehrpwm->pwm[chan]);
1485         }
1487 err_request_irq:
1488         if (ehrpwm->irq[0] != -ENXIO)
1489                 free_irq(ehrpwm->irq[0], ehrpwm);
1490 err_free_io:
1491         iounmap(ehrpwm->mmio_base);
1492 err_free_mem2:
1493         release_mem_region(r->start, resource_size(r));
1494 err_request_mem2_failure:
1495 err_resource_mem2_failiure:
1496         if (ehrpwm->version == PWM_VERSION_1) {
1497                 down(&pdata->config_semaphore);
1498                 pdata->pwmss_module_usage_count--;
1500                 if (!pdata->pwmss_module_usage_count) {
1501                         iounmap(pdata->config_mem_base);
1502                         pdata->config_mem_base = NULL;
1503                 }
1504                 up(&pdata->config_semaphore);
1505         }
1506 err_free_mem_config:
1507         if (ehrpwm->version == PWM_VERSION_1) {
1508                 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1509                 release_mem_region(r->start, resource_size(r));
1510         }
1511 err_request_mem_failure:
1512 err_resource_mem_failure:
1513         clk_put(ehrpwm->clk);
1514 err_clock_failure:
1515         kfree(ehrpwm);
1516 err_mem_failure:
1517         return ret;
1520 #ifdef CONFIG_PM
1521 static int ehrpwm_suspend(struct platform_device *pdev, pm_message_t state)
1523         struct ehrpwm_pwm *ehrpwm = platform_get_drvdata(pdev);
1525         if (ehrpwm->clk->usecount > 0)
1526                 clk_disable(ehrpwm->clk);
1528         return 0;
1531 static int ehrpwm_resume(struct platform_device *pdev)
1533         struct ehrpwm_pwm *ehrpwm = platform_get_drvdata(pdev);
1535         clk_enable(ehrpwm->clk);
1537         return 0;
1540 #else
1541 #define ehrpwm_suspend NULL
1542 #define ehrpwm_resume NULL
1543 #endif /* CONFIG_PM */
1545 static int __devexit ehrpwm_remove(struct platform_device *pdev)
1547         struct ehrpwm_pwm *ehrpwm = platform_get_drvdata(pdev);
1548         struct resource *r;
1549         unsigned char i;
1550         int val;
1551         struct pwmss_platform_data *pdata;
1553         if (ehrpwm->version == PWM_VERSION_1) {
1554                 pdata = (&pdev->dev)->platform_data;
1555                 down(&pdata->config_semaphore);
1556                 pdata->pwmss_module_usage_count--;
1557                 val = __raw_readw(pdata->config_mem_base + PWMSS_CLKCONFIG);
1558                 val &= ~BIT(EPWM_CLK_EN);
1559                 __raw_writew(val, pdata->config_mem_base + PWMSS_CLKCONFIG);
1561                 if (!pdata->pwmss_module_usage_count) {
1562                         iounmap(pdata->config_mem_base);
1563                         pdata->config_mem_base = NULL;
1564                         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1565                         release_mem_region(r->start, resource_size(r));
1566                 }
1567                 up(&pdata->config_semaphore);
1568         }
1570         for (i = 0; i < NCHAN; i++) {
1571                 if (pwm_is_registered(&ehrpwm->pwm[i]))
1572                         pwm_unregister(&ehrpwm->pwm[i]);
1573         }
1575         for (i = 0; i < 2; i++)
1576                 if (ehrpwm->irq[i] != -ENXIO)
1577                         free_irq(ehrpwm->irq[i], ehrpwm);
1578         iounmap(ehrpwm->mmio_base);
1580         if (ehrpwm->version == PWM_VERSION_1)
1581                 r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1582         else
1583                 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1585         release_mem_region(r->start, resource_size(r));
1586         platform_set_drvdata(pdev, NULL);
1587         clk_put(ehrpwm->clk);
1588         kfree(ehrpwm);
1590         return 0;
1593 static struct platform_driver ehrpwm_driver = {
1594         .driver = {
1595                 .name   = "ehrpwm",
1596                 .owner  = THIS_MODULE,
1597         },
1598         .probe          = ehrpwm_probe,
1599         .remove         = __devexit_p(ehrpwm_remove),
1600         .suspend        = ehrpwm_suspend,
1601         .resume         = ehrpwm_resume,
1602 };
1604 static int __init ehrpwm_init(void)
1606         return platform_driver_register(&ehrpwm_driver);
1608 module_init(ehrpwm_init);
1610 static void __exit ehrpwm_exit(void)
1612         platform_driver_unregister(&ehrpwm_driver);
1614 module_exit(ehrpwm_exit);
1616 MODULE_AUTHOR("Texas Instruments");
1617 MODULE_DESCRIPTION("Driver for Davinci eHRPWM peripheral");
1618 MODULE_LICENSE("GPL");
1619 MODULE_ALIAS("platform:ehrpwm");