1 /*
2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Authors:
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * Note: This driver is made separate from 8250 driver as we cannot
17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
21 */
23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24 #define SUPPORT_SYSRQ
25 #endif
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/serial_reg.h>
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/io.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/clk.h>
38 #include <linux/serial_core.h>
39 #include <linux/irq.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/of.h>
43 #include <plat/dma.h>
44 #include <plat/dmtimer.h>
45 #include <plat/omap-serial.h>
47 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
49 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
51 /* Forward declaration of functions */
52 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
53 static void serial_omap_rxdma_poll(unsigned long uart_no);
54 static int serial_omap_start_rxdma(struct uart_omap_port *up);
55 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
57 static struct workqueue_struct *serial_omap_uart_wq;
59 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
60 {
61 offset <<= up->port.regshift;
62 return readw(up->port.membase + offset);
63 }
65 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
66 {
67 offset <<= up->port.regshift;
68 writew(value, up->port.membase + offset);
69 }
71 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
72 {
73 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
74 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
75 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
76 serial_out(up, UART_FCR, 0);
77 }
79 /*
80 * serial_omap_get_divisor - calculate divisor value
81 * @port: uart port info
82 * @baud: baudrate for which divisor needs to be calculated.
83 *
84 * We have written our own function to get the divisor so as to support
85 * 13x mode. 3Mbps Baudrate as an different divisor.
86 * Reference OMAP TRM Chapter 17:
87 * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
88 * referring to oversampling - divisor value
89 * baudrate 460,800 to 3,686,400 all have divisor 13
90 * except 3,000,000 which has divisor value 16
91 */
92 static unsigned int
93 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
94 {
95 unsigned int divisor;
97 if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
98 divisor = 13;
99 else
100 divisor = 16;
101 return port->uartclk/(baud * divisor);
102 }
104 static void serial_omap_stop_rxdma(struct uart_omap_port *up)
105 {
106 if (up->uart_dma.rx_dma_used) {
107 del_timer(&up->uart_dma.rx_timer);
108 omap_stop_dma(up->uart_dma.rx_dma_channel);
109 omap_free_dma(up->uart_dma.rx_dma_channel);
110 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
111 up->uart_dma.rx_dma_used = false;
112 pm_runtime_mark_last_busy(&up->pdev->dev);
113 pm_runtime_put_autosuspend(&up->pdev->dev);
114 }
115 }
117 static void serial_omap_enable_ms(struct uart_port *port)
118 {
119 struct uart_omap_port *up = (struct uart_omap_port *)port;
121 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
123 pm_runtime_get_sync(&up->pdev->dev);
124 up->ier |= UART_IER_MSI;
125 serial_out(up, UART_IER, up->ier);
126 pm_runtime_put(&up->pdev->dev);
127 }
129 static void serial_omap_stop_tx(struct uart_port *port)
130 {
131 struct uart_omap_port *up = (struct uart_omap_port *)port;
133 if (up->use_dma &&
134 up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) {
135 /*
136 * Check if dma is still active. If yes do nothing,
137 * return. Else stop dma
138 */
139 if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel))
140 return;
141 omap_stop_dma(up->uart_dma.tx_dma_channel);
142 omap_free_dma(up->uart_dma.tx_dma_channel);
143 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
144 pm_runtime_mark_last_busy(&up->pdev->dev);
145 pm_runtime_put_autosuspend(&up->pdev->dev);
146 }
148 pm_runtime_get_sync(&up->pdev->dev);
149 if (up->ier & UART_IER_THRI) {
150 up->ier &= ~UART_IER_THRI;
151 serial_out(up, UART_IER, up->ier);
152 }
154 pm_runtime_mark_last_busy(&up->pdev->dev);
155 pm_runtime_put_autosuspend(&up->pdev->dev);
156 }
158 static void serial_omap_stop_rx(struct uart_port *port)
159 {
160 struct uart_omap_port *up = (struct uart_omap_port *)port;
162 pm_runtime_get_sync(&up->pdev->dev);
163 if (up->use_dma)
164 serial_omap_stop_rxdma(up);
165 up->ier &= ~UART_IER_RLSI;
166 up->port.read_status_mask &= ~UART_LSR_DR;
167 serial_out(up, UART_IER, up->ier);
168 pm_runtime_mark_last_busy(&up->pdev->dev);
169 pm_runtime_put_autosuspend(&up->pdev->dev);
170 }
172 static inline void receive_chars(struct uart_omap_port *up,
173 unsigned int *status)
174 {
175 struct tty_struct *tty = up->port.state->port.tty;
176 unsigned int flag, lsr = *status;
177 unsigned char ch = 0;
178 int max_count = 256;
180 do {
181 if (likely(lsr & UART_LSR_DR))
182 ch = serial_in(up, UART_RX);
183 flag = TTY_NORMAL;
184 up->port.icount.rx++;
186 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
187 /*
188 * For statistics only
189 */
190 if (lsr & UART_LSR_BI) {
191 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
192 up->port.icount.brk++;
193 /*
194 * We do the SysRQ and SAK checking
195 * here because otherwise the break
196 * may get masked by ignore_status_mask
197 * or read_status_mask.
198 */
199 if (uart_handle_break(&up->port))
200 goto ignore_char;
201 } else if (lsr & UART_LSR_PE) {
202 up->port.icount.parity++;
203 } else if (lsr & UART_LSR_FE) {
204 up->port.icount.frame++;
205 }
207 if (lsr & UART_LSR_OE)
208 up->port.icount.overrun++;
210 /*
211 * Mask off conditions which should be ignored.
212 */
213 lsr &= up->port.read_status_mask;
215 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
216 if (up->port.line == up->port.cons->index) {
217 /* Recover the break flag from console xmit */
218 lsr |= up->lsr_break_flag;
219 }
220 #endif
221 if (lsr & UART_LSR_BI)
222 flag = TTY_BREAK;
223 else if (lsr & UART_LSR_PE)
224 flag = TTY_PARITY;
225 else if (lsr & UART_LSR_FE)
226 flag = TTY_FRAME;
227 }
229 if (uart_handle_sysrq_char(&up->port, ch))
230 goto ignore_char;
231 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
232 ignore_char:
233 lsr = serial_in(up, UART_LSR);
234 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
235 spin_unlock(&up->port.lock);
236 tty_flip_buffer_push(tty);
237 spin_lock(&up->port.lock);
238 }
240 static void transmit_chars(struct uart_omap_port *up)
241 {
242 struct circ_buf *xmit = &up->port.state->xmit;
243 int count;
245 if (up->port.x_char) {
246 serial_out(up, UART_TX, up->port.x_char);
247 up->port.icount.tx++;
248 up->port.x_char = 0;
249 return;
250 }
251 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
252 serial_omap_stop_tx(&up->port);
253 return;
254 }
255 count = up->port.fifosize / 4;
256 do {
257 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
258 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
259 up->port.icount.tx++;
260 if (uart_circ_empty(xmit))
261 break;
262 } while (--count > 0);
264 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
265 uart_write_wakeup(&up->port);
267 if (uart_circ_empty(xmit))
268 serial_omap_stop_tx(&up->port);
269 }
271 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
272 {
273 if (!(up->ier & UART_IER_THRI)) {
274 up->ier |= UART_IER_THRI;
275 serial_out(up, UART_IER, up->ier);
276 }
277 }
279 static void serial_omap_start_tx(struct uart_port *port)
280 {
281 struct uart_omap_port *up = (struct uart_omap_port *)port;
282 struct circ_buf *xmit;
283 unsigned int start;
284 int ret = 0;
286 if (!up->use_dma) {
287 pm_runtime_get_sync(&up->pdev->dev);
288 serial_omap_enable_ier_thri(up);
289 pm_runtime_mark_last_busy(&up->pdev->dev);
290 pm_runtime_put_autosuspend(&up->pdev->dev);
291 return;
292 }
294 if (up->uart_dma.tx_dma_used)
295 return;
297 xmit = &up->port.state->xmit;
299 if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
300 pm_runtime_get_sync(&up->pdev->dev);
301 ret = omap_request_dma(up->uart_dma.uart_dma_tx,
302 "UART Tx DMA",
303 (void *)uart_tx_dma_callback, up,
304 &(up->uart_dma.tx_dma_channel));
306 if (ret < 0) {
307 serial_omap_enable_ier_thri(up);
308 return;
309 }
310 }
311 spin_lock(&(up->uart_dma.tx_lock));
312 up->uart_dma.tx_dma_used = true;
313 spin_unlock(&(up->uart_dma.tx_lock));
315 start = up->uart_dma.tx_buf_dma_phys +
316 (xmit->tail & (UART_XMIT_SIZE - 1));
318 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
319 /*
320 * It is a circular buffer. See if the buffer has wounded back.
321 * If yes it will have to be transferred in two separate dma
322 * transfers
323 */
324 if (start + up->uart_dma.tx_buf_size >=
325 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
326 up->uart_dma.tx_buf_size =
327 (up->uart_dma.tx_buf_dma_phys +
328 UART_XMIT_SIZE) - start;
330 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
331 OMAP_DMA_AMODE_CONSTANT,
332 up->uart_dma.uart_base, 0, 0);
333 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
334 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
335 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
336 OMAP_DMA_DATA_TYPE_S8,
337 up->uart_dma.tx_buf_size, 1,
338 OMAP_DMA_SYNC_ELEMENT,
339 up->uart_dma.uart_dma_tx, 0);
340 /* FIXME: Cache maintenance needed here? */
341 omap_start_dma(up->uart_dma.tx_dma_channel);
342 }
344 static unsigned int check_modem_status(struct uart_omap_port *up)
345 {
346 unsigned int status;
348 status = serial_in(up, UART_MSR);
349 status |= up->msr_saved_flags;
350 up->msr_saved_flags = 0;
351 if ((status & UART_MSR_ANY_DELTA) == 0)
352 return status;
354 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
355 up->port.state != NULL) {
356 if (status & UART_MSR_TERI)
357 up->port.icount.rng++;
358 if (status & UART_MSR_DDSR)
359 up->port.icount.dsr++;
360 if (status & UART_MSR_DDCD)
361 uart_handle_dcd_change
362 (&up->port, status & UART_MSR_DCD);
363 if (status & UART_MSR_DCTS)
364 uart_handle_cts_change
365 (&up->port, status & UART_MSR_CTS);
366 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
367 }
369 return status;
370 }
372 /**
373 * serial_omap_irq() - This handles the interrupt from one port
374 * @irq: uart port irq number
375 * @dev_id: uart port info
376 */
377 static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
378 {
379 struct uart_omap_port *up = dev_id;
380 unsigned int iir, lsr;
381 unsigned long flags;
383 pm_runtime_get_sync(&up->pdev->dev);
384 iir = serial_in(up, UART_IIR);
385 if (iir & UART_IIR_NO_INT) {
386 pm_runtime_mark_last_busy(&up->pdev->dev);
387 pm_runtime_put_autosuspend(&up->pdev->dev);
388 return IRQ_NONE;
389 }
391 spin_lock_irqsave(&up->port.lock, flags);
392 lsr = serial_in(up, UART_LSR);
393 if (iir & UART_IIR_RLSI) {
394 if (!up->use_dma) {
395 if (lsr & UART_LSR_DR)
396 receive_chars(up, &lsr);
397 } else {
398 up->ier &= ~(UART_IER_RDI | UART_IER_RLSI);
399 serial_out(up, UART_IER, up->ier);
400 if ((serial_omap_start_rxdma(up) != 0) &&
401 (lsr & UART_LSR_DR))
402 receive_chars(up, &lsr);
403 }
404 }
406 check_modem_status(up);
407 if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI))
408 transmit_chars(up);
410 spin_unlock_irqrestore(&up->port.lock, flags);
411 pm_runtime_mark_last_busy(&up->pdev->dev);
412 pm_runtime_put_autosuspend(&up->pdev->dev);
414 up->port_activity = jiffies;
415 return IRQ_HANDLED;
416 }
418 static unsigned int serial_omap_tx_empty(struct uart_port *port)
419 {
420 struct uart_omap_port *up = (struct uart_omap_port *)port;
421 unsigned long flags = 0;
422 unsigned int ret = 0;
424 pm_runtime_get_sync(&up->pdev->dev);
425 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
426 spin_lock_irqsave(&up->port.lock, flags);
427 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
428 spin_unlock_irqrestore(&up->port.lock, flags);
429 pm_runtime_put(&up->pdev->dev);
430 return ret;
431 }
433 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
434 {
435 struct uart_omap_port *up = (struct uart_omap_port *)port;
436 unsigned char status;
437 unsigned int ret = 0;
439 pm_runtime_get_sync(&up->pdev->dev);
440 status = check_modem_status(up);
441 pm_runtime_put(&up->pdev->dev);
443 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
445 if (status & UART_MSR_DCD)
446 ret |= TIOCM_CAR;
447 if (status & UART_MSR_RI)
448 ret |= TIOCM_RNG;
449 if (status & UART_MSR_DSR)
450 ret |= TIOCM_DSR;
451 if (status & UART_MSR_CTS)
452 ret |= TIOCM_CTS;
453 return ret;
454 }
456 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
457 {
458 struct uart_omap_port *up = (struct uart_omap_port *)port;
459 unsigned char mcr = 0;
461 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
462 if (mctrl & TIOCM_RTS)
463 mcr |= UART_MCR_RTS;
464 if (mctrl & TIOCM_DTR)
465 mcr |= UART_MCR_DTR;
466 if (mctrl & TIOCM_OUT1)
467 mcr |= UART_MCR_OUT1;
468 if (mctrl & TIOCM_OUT2)
469 mcr |= UART_MCR_OUT2;
470 if (mctrl & TIOCM_LOOP)
471 mcr |= UART_MCR_LOOP;
473 pm_runtime_get_sync(&up->pdev->dev);
474 up->mcr = serial_in(up, UART_MCR);
475 up->mcr |= mcr;
476 serial_out(up, UART_MCR, up->mcr);
477 pm_runtime_put(&up->pdev->dev);
478 }
480 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
481 {
482 struct uart_omap_port *up = (struct uart_omap_port *)port;
483 unsigned long flags = 0;
485 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
486 pm_runtime_get_sync(&up->pdev->dev);
487 spin_lock_irqsave(&up->port.lock, flags);
488 if (break_state == -1)
489 up->lcr |= UART_LCR_SBC;
490 else
491 up->lcr &= ~UART_LCR_SBC;
492 serial_out(up, UART_LCR, up->lcr);
493 spin_unlock_irqrestore(&up->port.lock, flags);
494 pm_runtime_put(&up->pdev->dev);
495 }
497 static int serial_omap_startup(struct uart_port *port)
498 {
499 struct uart_omap_port *up = (struct uart_omap_port *)port;
500 unsigned long flags = 0;
501 int retval;
503 /*
504 * Allocate the IRQ
505 */
506 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
507 up->name, up);
508 if (retval)
509 return retval;
511 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
513 pm_runtime_get_sync(&up->pdev->dev);
514 /*
515 * Clear the FIFO buffers and disable them.
516 * (they will be reenabled in set_termios())
517 */
518 serial_omap_clear_fifos(up);
519 /* For Hardware flow control */
520 serial_out(up, UART_MCR, UART_MCR_RTS);
522 /*
523 * Clear the interrupt registers.
524 */
525 (void) serial_in(up, UART_LSR);
526 if (serial_in(up, UART_LSR) & UART_LSR_DR)
527 (void) serial_in(up, UART_RX);
528 (void) serial_in(up, UART_IIR);
529 (void) serial_in(up, UART_MSR);
531 /*
532 * Now, initialize the UART
533 */
534 serial_out(up, UART_LCR, UART_LCR_WLEN8);
535 spin_lock_irqsave(&up->port.lock, flags);
536 /*
537 * Most PC uarts need OUT2 raised to enable interrupts.
538 */
539 up->port.mctrl |= TIOCM_OUT2;
540 serial_omap_set_mctrl(&up->port, up->port.mctrl);
541 spin_unlock_irqrestore(&up->port.lock, flags);
543 up->msr_saved_flags = 0;
544 if (up->use_dma) {
545 free_page((unsigned long)up->port.state->xmit.buf);
546 up->port.state->xmit.buf = dma_alloc_coherent(NULL,
547 UART_XMIT_SIZE,
548 (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
549 0);
550 init_timer(&(up->uart_dma.rx_timer));
551 up->uart_dma.rx_timer.function = serial_omap_rxdma_poll;
552 up->uart_dma.rx_timer.data = up->port.line;
553 /* Currently the buffer size is 4KB. Can increase it */
554 up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
555 up->uart_dma.rx_buf_size,
556 (dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0);
557 }
558 /*
559 * Finally, enable interrupts. Note: Modem status interrupts
560 * are set via set_termios(), which will be occurring imminently
561 * anyway, so we don't enable them here.
562 */
563 up->ier = UART_IER_RLSI | UART_IER_RDI;
564 serial_out(up, UART_IER, up->ier);
566 /* Enable module level wake up */
567 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
569 pm_runtime_mark_last_busy(&up->pdev->dev);
570 pm_runtime_put_autosuspend(&up->pdev->dev);
571 up->port_activity = jiffies;
572 return 0;
573 }
575 static void serial_omap_shutdown(struct uart_port *port)
576 {
577 struct uart_omap_port *up = (struct uart_omap_port *)port;
578 unsigned long flags = 0;
580 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
582 pm_runtime_get_sync(&up->pdev->dev);
583 /*
584 * Disable interrupts from this port
585 */
586 up->ier = 0;
587 serial_out(up, UART_IER, 0);
589 spin_lock_irqsave(&up->port.lock, flags);
590 up->port.mctrl &= ~TIOCM_OUT2;
591 serial_omap_set_mctrl(&up->port, up->port.mctrl);
592 spin_unlock_irqrestore(&up->port.lock, flags);
594 /*
595 * Disable break condition and FIFOs
596 */
597 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
598 serial_omap_clear_fifos(up);
600 /*
601 * Read data port to reset things, and then free the irq
602 */
603 if (serial_in(up, UART_LSR) & UART_LSR_DR)
604 (void) serial_in(up, UART_RX);
605 if (up->use_dma) {
606 dma_free_coherent(up->port.dev,
607 UART_XMIT_SIZE, up->port.state->xmit.buf,
608 up->uart_dma.tx_buf_dma_phys);
609 up->port.state->xmit.buf = NULL;
610 serial_omap_stop_rx(port);
611 dma_free_coherent(up->port.dev,
612 up->uart_dma.rx_buf_size, up->uart_dma.rx_buf,
613 up->uart_dma.rx_buf_dma_phys);
614 up->uart_dma.rx_buf = NULL;
615 }
617 pm_runtime_put(&up->pdev->dev);
618 free_irq(up->port.irq, up);
619 }
621 static inline void
622 serial_omap_configure_xonxoff
623 (struct uart_omap_port *up, struct ktermios *termios)
624 {
625 up->lcr = serial_in(up, UART_LCR);
626 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
627 up->efr = serial_in(up, UART_EFR);
628 serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
630 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
631 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
633 /* clear SW control mode bits */
634 up->efr &= OMAP_UART_SW_CLR;
636 /*
637 * IXON Flag:
638 * Enable XON/XOFF flow control on output.
639 * Transmit XON1, XOFF1
640 */
641 if (termios->c_iflag & IXON)
642 up->efr |= OMAP_UART_SW_TX;
644 /*
645 * IXOFF Flag:
646 * Enable XON/XOFF flow control on input.
647 * Receiver compares XON1, XOFF1.
648 */
649 if (termios->c_iflag & IXOFF)
650 up->efr |= OMAP_UART_SW_RX;
652 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
653 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
655 up->mcr = serial_in(up, UART_MCR);
657 /*
658 * IXANY Flag:
659 * Enable any character to restart output.
660 * Operation resumes after receiving any
661 * character after recognition of the XOFF character
662 */
663 if (termios->c_iflag & IXANY)
664 up->mcr |= UART_MCR_XONANY;
666 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
667 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
668 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
669 /* Enable special char function UARTi.EFR_REG[5] and
670 * load the new software flow control mode IXON or IXOFF
671 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
672 */
673 serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
674 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
676 serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
677 serial_out(up, UART_LCR, up->lcr);
678 }
680 static void serial_omap_uart_qos_work(struct work_struct *work)
681 {
682 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
683 qos_work);
685 pm_qos_update_request(&up->pm_qos_request, up->latency);
686 }
688 static void
689 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
690 struct ktermios *old)
691 {
692 struct uart_omap_port *up = (struct uart_omap_port *)port;
693 unsigned char cval = 0;
694 unsigned char efr = 0;
695 unsigned long flags = 0;
696 unsigned int baud, quot;
698 switch (termios->c_cflag & CSIZE) {
699 case CS5:
700 cval = UART_LCR_WLEN5;
701 break;
702 case CS6:
703 cval = UART_LCR_WLEN6;
704 break;
705 case CS7:
706 cval = UART_LCR_WLEN7;
707 break;
708 default:
709 case CS8:
710 cval = UART_LCR_WLEN8;
711 break;
712 }
714 if (termios->c_cflag & CSTOPB)
715 cval |= UART_LCR_STOP;
716 if (termios->c_cflag & PARENB)
717 cval |= UART_LCR_PARITY;
718 if (!(termios->c_cflag & PARODD))
719 cval |= UART_LCR_EPAR;
721 /*
722 * Ask the core to calculate the divisor for us.
723 */
725 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
726 quot = serial_omap_get_divisor(port, baud);
728 /* calculate wakeup latency constraint */
729 up->calc_latency = (1000000 * up->port.fifosize) /
730 (1000 * baud / 8);
731 up->latency = up->calc_latency;
732 schedule_work(&up->qos_work);
734 up->dll = quot & 0xff;
735 up->dlh = quot >> 8;
736 up->mdr1 = UART_OMAP_MDR1_DISABLE;
738 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
739 UART_FCR_ENABLE_FIFO;
740 if (up->use_dma)
741 up->fcr |= UART_FCR_DMA_SELECT;
743 /*
744 * Ok, we're now changing the port state. Do it with
745 * interrupts disabled.
746 */
747 pm_runtime_get_sync(&up->pdev->dev);
748 spin_lock_irqsave(&up->port.lock, flags);
750 /*
751 * Update the per-port timeout.
752 */
753 uart_update_timeout(port, termios->c_cflag, baud);
755 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
756 if (termios->c_iflag & INPCK)
757 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
758 if (termios->c_iflag & (BRKINT | PARMRK))
759 up->port.read_status_mask |= UART_LSR_BI;
761 /*
762 * Characters to ignore
763 */
764 up->port.ignore_status_mask = 0;
765 if (termios->c_iflag & IGNPAR)
766 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
767 if (termios->c_iflag & IGNBRK) {
768 up->port.ignore_status_mask |= UART_LSR_BI;
769 /*
770 * If we're ignoring parity and break indicators,
771 * ignore overruns too (for real raw support).
772 */
773 if (termios->c_iflag & IGNPAR)
774 up->port.ignore_status_mask |= UART_LSR_OE;
775 }
777 /*
778 * ignore all characters if CREAD is not set
779 */
780 if ((termios->c_cflag & CREAD) == 0)
781 up->port.ignore_status_mask |= UART_LSR_DR;
783 /*
784 * Modem status interrupts
785 */
786 up->ier &= ~UART_IER_MSI;
787 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
788 up->ier |= UART_IER_MSI;
789 serial_out(up, UART_IER, up->ier);
790 serial_out(up, UART_LCR, cval); /* reset DLAB */
791 up->lcr = cval;
792 up->scr = OMAP_UART_SCR_TX_EMPTY;
794 /* FIFOs and DMA Settings */
796 /* FCR can be changed only when the
797 * baud clock is not running
798 * DLL_REG and DLH_REG set to 0.
799 */
800 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
801 serial_out(up, UART_DLL, 0);
802 serial_out(up, UART_DLM, 0);
803 serial_out(up, UART_LCR, 0);
805 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
807 up->efr = serial_in(up, UART_EFR);
808 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
810 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
811 up->mcr = serial_in(up, UART_MCR);
812 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
813 /* FIFO ENABLE, DMA MODE */
814 serial_out(up, UART_FCR, up->fcr);
815 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
817 if (up->use_dma) {
818 serial_out(up, UART_TI752_TLR, 0);
819 up->scr |= (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8);
820 }
822 serial_out(up, UART_OMAP_SCR, up->scr);
824 serial_out(up, UART_EFR, up->efr);
825 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
826 serial_out(up, UART_MCR, up->mcr);
828 /* Protocol, Baud Rate, and Interrupt Settings */
830 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
831 serial_omap_mdr1_errataset(up, up->mdr1);
832 else
833 serial_out(up, UART_OMAP_MDR1, up->mdr1);
835 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
837 up->efr = serial_in(up, UART_EFR);
838 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
840 serial_out(up, UART_LCR, 0);
841 serial_out(up, UART_IER, 0);
842 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
844 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
845 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
847 serial_out(up, UART_LCR, 0);
848 serial_out(up, UART_IER, up->ier);
849 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
851 serial_out(up, UART_EFR, up->efr);
852 serial_out(up, UART_LCR, cval);
854 if (baud > 230400 && baud != 3000000)
855 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
856 else
857 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
859 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
860 serial_omap_mdr1_errataset(up, up->mdr1);
861 else
862 serial_out(up, UART_OMAP_MDR1, up->mdr1);
864 /* Hardware Flow Control Configuration */
866 if (termios->c_cflag & CRTSCTS) {
867 efr |= (UART_EFR_CTS | UART_EFR_RTS);
868 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
870 up->mcr = serial_in(up, UART_MCR);
871 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
873 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
874 up->efr = serial_in(up, UART_EFR);
875 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
877 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
878 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
879 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
880 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
881 serial_out(up, UART_LCR, cval);
882 }
884 serial_omap_set_mctrl(&up->port, up->port.mctrl);
885 /* Software Flow Control Configuration */
886 serial_omap_configure_xonxoff(up, termios);
888 spin_unlock_irqrestore(&up->port.lock, flags);
889 pm_runtime_put(&up->pdev->dev);
890 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
891 }
893 static void
894 serial_omap_pm(struct uart_port *port, unsigned int state,
895 unsigned int oldstate)
896 {
897 struct uart_omap_port *up = (struct uart_omap_port *)port;
898 unsigned char efr;
900 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
902 pm_runtime_get_sync(&up->pdev->dev);
903 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
904 efr = serial_in(up, UART_EFR);
905 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
906 serial_out(up, UART_LCR, 0);
908 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
909 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
910 serial_out(up, UART_EFR, efr);
911 serial_out(up, UART_LCR, 0);
913 if (!device_may_wakeup(&up->pdev->dev)) {
914 if (!state)
915 pm_runtime_forbid(&up->pdev->dev);
916 else
917 pm_runtime_allow(&up->pdev->dev);
918 }
920 pm_runtime_put(&up->pdev->dev);
921 }
923 static void serial_omap_release_port(struct uart_port *port)
924 {
925 dev_dbg(port->dev, "serial_omap_release_port+\n");
926 }
928 static int serial_omap_request_port(struct uart_port *port)
929 {
930 dev_dbg(port->dev, "serial_omap_request_port+\n");
931 return 0;
932 }
934 static void serial_omap_config_port(struct uart_port *port, int flags)
935 {
936 struct uart_omap_port *up = (struct uart_omap_port *)port;
938 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
939 up->port.line);
940 up->port.type = PORT_OMAP;
941 }
943 static int
944 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
945 {
946 /* we don't want the core code to modify any port params */
947 dev_dbg(port->dev, "serial_omap_verify_port+\n");
948 return -EINVAL;
949 }
951 static const char *
952 serial_omap_type(struct uart_port *port)
953 {
954 struct uart_omap_port *up = (struct uart_omap_port *)port;
956 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
957 return up->name;
958 }
960 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
962 static inline void wait_for_xmitr(struct uart_omap_port *up)
963 {
964 unsigned int status, tmout = 10000;
966 /* Wait up to 10ms for the character(s) to be sent. */
967 do {
968 status = serial_in(up, UART_LSR);
970 if (status & UART_LSR_BI)
971 up->lsr_break_flag = UART_LSR_BI;
973 if (--tmout == 0)
974 break;
975 udelay(1);
976 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
978 /* Wait up to 1s for flow control if necessary */
979 if (up->port.flags & UPF_CONS_FLOW) {
980 tmout = 1000000;
981 for (tmout = 1000000; tmout; tmout--) {
982 unsigned int msr = serial_in(up, UART_MSR);
984 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
985 if (msr & UART_MSR_CTS)
986 break;
988 udelay(1);
989 }
990 }
991 }
993 #ifdef CONFIG_CONSOLE_POLL
995 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
996 {
997 struct uart_omap_port *up = (struct uart_omap_port *)port;
999 pm_runtime_get_sync(&up->pdev->dev);
1000 wait_for_xmitr(up);
1001 serial_out(up, UART_TX, ch);
1002 pm_runtime_put(&up->pdev->dev);
1003 }
1005 static int serial_omap_poll_get_char(struct uart_port *port)
1006 {
1007 struct uart_omap_port *up = (struct uart_omap_port *)port;
1008 unsigned int status;
1010 pm_runtime_get_sync(&up->pdev->dev);
1011 status = serial_in(up, UART_LSR);
1012 if (!(status & UART_LSR_DR))
1013 return NO_POLL_CHAR;
1015 status = serial_in(up, UART_RX);
1016 pm_runtime_put(&up->pdev->dev);
1017 return status;
1018 }
1020 #endif /* CONFIG_CONSOLE_POLL */
1022 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1024 static struct uart_omap_port *serial_omap_console_ports[4];
1026 static struct uart_driver serial_omap_reg;
1028 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1029 {
1030 struct uart_omap_port *up = (struct uart_omap_port *)port;
1032 wait_for_xmitr(up);
1033 serial_out(up, UART_TX, ch);
1034 }
1036 static void
1037 serial_omap_console_write(struct console *co, const char *s,
1038 unsigned int count)
1039 {
1040 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1041 unsigned long flags;
1042 unsigned int ier;
1043 int locked = 1;
1045 pm_runtime_get_sync(&up->pdev->dev);
1047 local_irq_save(flags);
1048 if (up->port.sysrq)
1049 locked = 0;
1050 else if (oops_in_progress)
1051 locked = spin_trylock(&up->port.lock);
1052 else
1053 spin_lock(&up->port.lock);
1055 /*
1056 * First save the IER then disable the interrupts
1057 */
1058 ier = serial_in(up, UART_IER);
1059 serial_out(up, UART_IER, 0);
1061 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1063 /*
1064 * Finally, wait for transmitter to become empty
1065 * and restore the IER
1066 */
1067 wait_for_xmitr(up);
1068 serial_out(up, UART_IER, ier);
1069 /*
1070 * The receive handling will happen properly because the
1071 * receive ready bit will still be set; it is not cleared
1072 * on read. However, modem control will not, we must
1073 * call it if we have saved something in the saved flags
1074 * while processing with interrupts off.
1075 */
1076 if (up->msr_saved_flags)
1077 check_modem_status(up);
1079 pm_runtime_mark_last_busy(&up->pdev->dev);
1080 pm_runtime_put_autosuspend(&up->pdev->dev);
1081 if (locked)
1082 spin_unlock(&up->port.lock);
1083 local_irq_restore(flags);
1084 }
1086 static int __init
1087 serial_omap_console_setup(struct console *co, char *options)
1088 {
1089 struct uart_omap_port *up;
1090 int baud = 115200;
1091 int bits = 8;
1092 int parity = 'n';
1093 int flow = 'n';
1095 if (serial_omap_console_ports[co->index] == NULL)
1096 return -ENODEV;
1097 up = serial_omap_console_ports[co->index];
1099 if (options)
1100 uart_parse_options(options, &baud, &parity, &bits, &flow);
1102 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1103 }
1105 static struct console serial_omap_console = {
1106 .name = OMAP_SERIAL_NAME,
1107 .write = serial_omap_console_write,
1108 .device = uart_console_device,
1109 .setup = serial_omap_console_setup,
1110 .flags = CON_PRINTBUFFER,
1111 .index = -1,
1112 .data = &serial_omap_reg,
1113 };
1115 static void serial_omap_add_console_port(struct uart_omap_port *up)
1116 {
1117 serial_omap_console_ports[up->port.line] = up;
1118 }
1120 #define OMAP_CONSOLE (&serial_omap_console)
1122 #else
1124 #define OMAP_CONSOLE NULL
1126 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1127 {}
1129 #endif
1131 static struct uart_ops serial_omap_pops = {
1132 .tx_empty = serial_omap_tx_empty,
1133 .set_mctrl = serial_omap_set_mctrl,
1134 .get_mctrl = serial_omap_get_mctrl,
1135 .stop_tx = serial_omap_stop_tx,
1136 .start_tx = serial_omap_start_tx,
1137 .stop_rx = serial_omap_stop_rx,
1138 .enable_ms = serial_omap_enable_ms,
1139 .break_ctl = serial_omap_break_ctl,
1140 .startup = serial_omap_startup,
1141 .shutdown = serial_omap_shutdown,
1142 .set_termios = serial_omap_set_termios,
1143 .pm = serial_omap_pm,
1144 .type = serial_omap_type,
1145 .release_port = serial_omap_release_port,
1146 .request_port = serial_omap_request_port,
1147 .config_port = serial_omap_config_port,
1148 .verify_port = serial_omap_verify_port,
1149 #ifdef CONFIG_CONSOLE_POLL
1150 .poll_put_char = serial_omap_poll_put_char,
1151 .poll_get_char = serial_omap_poll_get_char,
1152 #endif
1153 };
1155 static struct uart_driver serial_omap_reg = {
1156 .owner = THIS_MODULE,
1157 .driver_name = "OMAP-SERIAL",
1158 .dev_name = OMAP_SERIAL_NAME,
1159 .nr = OMAP_MAX_HSUART_PORTS,
1160 .cons = OMAP_CONSOLE,
1161 };
1163 #ifdef CONFIG_SUSPEND
1164 static int serial_omap_suspend(struct device *dev)
1165 {
1166 struct uart_omap_port *up = dev_get_drvdata(dev);
1168 if (up) {
1169 /*
1170 In case suspending during Bluetooth traffic, after resume
1171 the bluetooth is stuck.
1172 It was identified that suspend is happening before the
1173 UART buffer was fully drained which caused this hang after
1174 resume. The following delay is a temporary workaround until
1175 the issue is resolved properly.
1176 */
1177 msleep(10);
1179 uart_suspend_port(&serial_omap_reg, &up->port);
1180 flush_work_sync(&up->qos_work);
1181 }
1183 return 0;
1184 }
1186 static int serial_omap_resume(struct device *dev)
1187 {
1188 struct uart_omap_port *up = dev_get_drvdata(dev);
1190 if (up)
1191 uart_resume_port(&serial_omap_reg, &up->port);
1192 return 0;
1193 }
1194 #endif
1196 static void serial_omap_rxdma_poll(unsigned long uart_no)
1197 {
1198 struct uart_omap_port *up = ui[uart_no];
1199 unsigned int curr_dma_pos, curr_transmitted_size;
1200 int ret = 0;
1202 curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel);
1203 if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
1204 (curr_dma_pos == 0)) {
1205 if (jiffies_to_msecs(jiffies - up->port_activity) <
1206 up->uart_dma.rx_timeout) {
1207 mod_timer(&up->uart_dma.rx_timer, jiffies +
1208 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1209 } else {
1210 serial_omap_stop_rxdma(up);
1211 up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1212 serial_out(up, UART_IER, up->ier);
1213 }
1214 return;
1215 }
1217 curr_transmitted_size = curr_dma_pos -
1218 up->uart_dma.prev_rx_dma_pos;
1219 up->port.icount.rx += curr_transmitted_size;
1220 tty_insert_flip_string(up->port.state->port.tty,
1221 up->uart_dma.rx_buf +
1222 (up->uart_dma.prev_rx_dma_pos -
1223 up->uart_dma.rx_buf_dma_phys),
1224 curr_transmitted_size);
1225 tty_flip_buffer_push(up->port.state->port.tty);
1226 up->uart_dma.prev_rx_dma_pos = curr_dma_pos;
1227 if (up->uart_dma.rx_buf_size +
1228 up->uart_dma.rx_buf_dma_phys == curr_dma_pos) {
1229 ret = serial_omap_start_rxdma(up);
1230 if (ret < 0) {
1231 serial_omap_stop_rxdma(up);
1232 up->ier |= (UART_IER_RDI | UART_IER_RLSI);
1233 serial_out(up, UART_IER, up->ier);
1234 }
1235 } else {
1236 mod_timer(&up->uart_dma.rx_timer, jiffies +
1237 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1238 }
1239 up->port_activity = jiffies;
1240 }
1242 static void uart_rx_dma_callback(int lch, u16 ch_status, void *data)
1243 {
1244 return;
1245 }
1247 static int serial_omap_start_rxdma(struct uart_omap_port *up)
1248 {
1249 int ret = 0;
1251 if (up->uart_dma.rx_dma_channel == -1) {
1252 pm_runtime_get_sync(&up->pdev->dev);
1253 ret = omap_request_dma(up->uart_dma.uart_dma_rx,
1254 "UART Rx DMA",
1255 (void *)uart_rx_dma_callback, up,
1256 &(up->uart_dma.rx_dma_channel));
1257 if (ret < 0)
1258 return ret;
1260 omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0,
1261 OMAP_DMA_AMODE_CONSTANT,
1262 up->uart_dma.uart_base, 0, 0);
1263 omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0,
1264 OMAP_DMA_AMODE_POST_INC,
1265 up->uart_dma.rx_buf_dma_phys, 0, 0);
1266 omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel,
1267 OMAP_DMA_DATA_TYPE_S8,
1268 up->uart_dma.rx_buf_size, 1,
1269 OMAP_DMA_SYNC_ELEMENT,
1270 up->uart_dma.uart_dma_rx, 0);
1271 }
1272 up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys;
1273 /* FIXME: Cache maintenance needed here? */
1274 omap_start_dma(up->uart_dma.rx_dma_channel);
1275 mod_timer(&up->uart_dma.rx_timer, jiffies +
1276 usecs_to_jiffies(up->uart_dma.rx_poll_rate));
1277 up->uart_dma.rx_dma_used = true;
1278 return ret;
1279 }
1281 static void serial_omap_continue_tx(struct uart_omap_port *up)
1282 {
1283 struct circ_buf *xmit = &up->port.state->xmit;
1284 unsigned int start = up->uart_dma.tx_buf_dma_phys
1285 + (xmit->tail & (UART_XMIT_SIZE - 1));
1287 if (uart_circ_empty(xmit))
1288 return;
1290 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
1291 /*
1292 * It is a circular buffer. See if the buffer has wounded back.
1293 * If yes it will have to be transferred in two separate dma
1294 * transfers
1295 */
1296 if (start + up->uart_dma.tx_buf_size >=
1297 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
1298 up->uart_dma.tx_buf_size =
1299 (up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start;
1300 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
1301 OMAP_DMA_AMODE_CONSTANT,
1302 up->uart_dma.uart_base, 0, 0);
1303 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
1304 OMAP_DMA_AMODE_POST_INC, start, 0, 0);
1305 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
1306 OMAP_DMA_DATA_TYPE_S8,
1307 up->uart_dma.tx_buf_size, 1,
1308 OMAP_DMA_SYNC_ELEMENT,
1309 up->uart_dma.uart_dma_tx, 0);
1310 /* FIXME: Cache maintenance needed here? */
1311 omap_start_dma(up->uart_dma.tx_dma_channel);
1312 }
1314 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
1315 {
1316 struct uart_omap_port *up = (struct uart_omap_port *)data;
1317 struct circ_buf *xmit = &up->port.state->xmit;
1319 xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \
1320 (UART_XMIT_SIZE - 1);
1321 up->port.icount.tx += up->uart_dma.tx_buf_size;
1323 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1324 uart_write_wakeup(&up->port);
1326 if (uart_circ_empty(xmit)) {
1327 spin_lock(&(up->uart_dma.tx_lock));
1328 serial_omap_stop_tx(&up->port);
1329 up->uart_dma.tx_dma_used = false;
1330 spin_unlock(&(up->uart_dma.tx_lock));
1331 } else {
1332 omap_stop_dma(up->uart_dma.tx_dma_channel);
1333 serial_omap_continue_tx(up);
1334 }
1335 up->port_activity = jiffies;
1336 return;
1337 }
1339 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1340 {
1341 struct omap_uart_port_info *omap_up_info;
1343 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1344 if (!omap_up_info)
1345 return NULL; /* out of memory */
1347 of_property_read_u32(dev->of_node, "clock-frequency",
1348 &omap_up_info->uartclk);
1349 return omap_up_info;
1350 }
1352 static int serial_omap_probe(struct platform_device *pdev)
1353 {
1354 struct uart_omap_port *up;
1355 struct resource *mem, *irq, *dma_tx, *dma_rx;
1356 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1357 int ret = -ENOSPC;
1359 if (pdev->dev.of_node)
1360 omap_up_info = of_get_uart_port_info(&pdev->dev);
1362 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1363 if (!mem) {
1364 dev_err(&pdev->dev, "no mem resource?\n");
1365 return -ENODEV;
1366 }
1368 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1369 if (!irq) {
1370 dev_err(&pdev->dev, "no irq resource?\n");
1371 return -ENODEV;
1372 }
1374 if (!request_mem_region(mem->start, resource_size(mem),
1375 pdev->dev.driver->name)) {
1376 dev_err(&pdev->dev, "memory region already claimed\n");
1377 return -EBUSY;
1378 }
1380 dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1381 if (!dma_rx) {
1382 ret = -EINVAL;
1383 goto err;
1384 }
1386 dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1387 if (!dma_tx) {
1388 ret = -EINVAL;
1389 goto err;
1390 }
1392 up = kzalloc(sizeof(*up), GFP_KERNEL);
1393 if (up == NULL) {
1394 ret = -ENOMEM;
1395 goto do_release_region;
1396 }
1397 up->pdev = pdev;
1398 up->port.dev = &pdev->dev;
1399 up->port.type = PORT_OMAP;
1400 up->port.iotype = UPIO_MEM;
1401 up->port.irq = irq->start;
1403 up->port.regshift = 2;
1404 up->port.fifosize = 64;
1405 up->port.ops = &serial_omap_pops;
1407 if (pdev->dev.of_node)
1408 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1409 else
1410 up->port.line = pdev->id;
1412 if (up->port.line < 0) {
1413 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1414 up->port.line);
1415 ret = -ENODEV;
1416 goto err;
1417 }
1419 sprintf(up->name, "OMAP UART%d", up->port.line);
1420 up->port.mapbase = mem->start;
1421 up->port.membase = ioremap(mem->start, resource_size(mem));
1422 if (!up->port.membase) {
1423 dev_err(&pdev->dev, "can't ioremap UART\n");
1424 ret = -ENOMEM;
1425 goto err;
1426 }
1428 up->port.flags = omap_up_info->flags;
1429 up->port.uartclk = omap_up_info->uartclk;
1430 if (!up->port.uartclk) {
1431 up->port.uartclk = DEFAULT_CLK_SPEED;
1432 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1433 "%d\n", DEFAULT_CLK_SPEED);
1434 }
1435 up->uart_dma.uart_base = mem->start;
1436 up->errata = omap_up_info->errata;
1438 if (omap_up_info->dma_enabled) {
1439 up->uart_dma.uart_dma_tx = dma_tx->start;
1440 up->uart_dma.uart_dma_rx = dma_rx->start;
1441 up->use_dma = 1;
1442 up->uart_dma.rx_buf_size = omap_up_info->dma_rx_buf_size;
1443 up->uart_dma.rx_timeout = omap_up_info->dma_rx_timeout;
1444 up->uart_dma.rx_poll_rate = omap_up_info->dma_rx_poll_rate;
1445 spin_lock_init(&(up->uart_dma.tx_lock));
1446 spin_lock_init(&(up->uart_dma.rx_lock));
1447 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
1448 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
1449 }
1451 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1452 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1453 pm_qos_add_request(&up->pm_qos_request,
1454 PM_QOS_CPU_DMA_LATENCY, up->latency);
1455 serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1456 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1458 pm_runtime_use_autosuspend(&pdev->dev);
1459 pm_runtime_set_autosuspend_delay(&pdev->dev,
1460 omap_up_info->autosuspend_timeout);
1462 pm_runtime_irq_safe(&pdev->dev);
1463 pm_runtime_enable(&pdev->dev);
1464 pm_runtime_get_sync(&pdev->dev);
1466 ui[up->port.line] = up;
1467 serial_omap_add_console_port(up);
1469 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1470 if (ret != 0)
1471 goto do_release_region;
1473 pm_runtime_put(&pdev->dev);
1474 platform_set_drvdata(pdev, up);
1475 return 0;
1476 err:
1477 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1478 pdev->id, __func__, ret);
1479 do_release_region:
1480 release_mem_region(mem->start, resource_size(mem));
1481 return ret;
1482 }
1484 static int serial_omap_remove(struct platform_device *dev)
1485 {
1486 struct uart_omap_port *up = platform_get_drvdata(dev);
1488 if (up) {
1489 pm_runtime_disable(&up->pdev->dev);
1490 uart_remove_one_port(&serial_omap_reg, &up->port);
1491 pm_qos_remove_request(&up->pm_qos_request);
1493 kfree(up);
1494 }
1496 platform_set_drvdata(dev, NULL);
1497 return 0;
1498 }
1500 /*
1501 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1502 * The access to uart register after MDR1 Access
1503 * causes UART to corrupt data.
1504 *
1505 * Need a delay =
1506 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1507 * give 10 times as much
1508 */
1509 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1510 {
1511 u8 timeout = 255;
1513 serial_out(up, UART_OMAP_MDR1, mdr1);
1514 udelay(2);
1515 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1516 UART_FCR_CLEAR_RCVR);
1517 /*
1518 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1519 * TX_FIFO_E bit is 1.
1520 */
1521 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1522 (UART_LSR_THRE | UART_LSR_DR))) {
1523 timeout--;
1524 if (!timeout) {
1525 /* Should *never* happen. we warn and carry on */
1526 dev_crit(&up->pdev->dev, "Errata i202: timedout %x\n",
1527 serial_in(up, UART_LSR));
1528 break;
1529 }
1530 udelay(1);
1531 }
1532 }
1534 static void serial_omap_restore_context(struct uart_omap_port *up)
1535 {
1536 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1537 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1538 else
1539 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1541 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1542 serial_out(up, UART_EFR, UART_EFR_ECB);
1543 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1544 serial_out(up, UART_IER, 0x0);
1545 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1546 serial_out(up, UART_DLL, up->dll);
1547 serial_out(up, UART_DLM, up->dlh);
1548 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1549 serial_out(up, UART_IER, up->ier);
1550 serial_out(up, UART_FCR, up->fcr);
1551 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1552 serial_out(up, UART_MCR, up->mcr);
1553 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1554 serial_out(up, UART_OMAP_SCR, up->scr);
1555 serial_out(up, UART_EFR, up->efr);
1556 serial_out(up, UART_LCR, up->lcr);
1557 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1558 serial_omap_mdr1_errataset(up, up->mdr1);
1559 else
1560 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1561 }
1563 #ifdef CONFIG_PM_RUNTIME
1564 static int serial_omap_runtime_suspend(struct device *dev)
1565 {
1566 struct uart_omap_port *up = dev_get_drvdata(dev);
1567 struct omap_uart_port_info *pdata = dev->platform_data;
1569 if (!up)
1570 return -EINVAL;
1572 if (!pdata || !pdata->enable_wakeup)
1573 return 0;
1575 if (pdata->get_context_loss_count)
1576 up->context_loss_cnt = pdata->get_context_loss_count(dev);
1578 if (device_may_wakeup(dev)) {
1579 if (!up->wakeups_enabled) {
1580 pdata->enable_wakeup(up->pdev, true);
1581 up->wakeups_enabled = true;
1582 }
1583 } else {
1584 if (up->wakeups_enabled) {
1585 pdata->enable_wakeup(up->pdev, false);
1586 up->wakeups_enabled = false;
1587 }
1588 }
1590 /* Errata i291 */
1591 if (up->use_dma && pdata->set_forceidle &&
1592 (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
1593 pdata->set_forceidle(up->pdev);
1595 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1596 schedule_work(&up->qos_work);
1598 return 0;
1599 }
1601 static int serial_omap_runtime_resume(struct device *dev)
1602 {
1603 struct uart_omap_port *up = dev_get_drvdata(dev);
1604 struct omap_uart_port_info *pdata = dev->platform_data;
1606 if (up) {
1607 if (pdata->get_context_loss_count) {
1608 u32 loss_cnt = pdata->get_context_loss_count(dev);
1610 if (up->context_loss_cnt != loss_cnt)
1611 serial_omap_restore_context(up);
1612 }
1614 /* Errata i291 */
1615 if (up->use_dma && pdata->set_noidle &&
1616 (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
1617 pdata->set_noidle(up->pdev);
1619 up->latency = up->calc_latency;
1620 schedule_work(&up->qos_work);
1621 }
1623 return 0;
1624 }
1625 #endif
1627 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1628 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1629 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1630 serial_omap_runtime_resume, NULL)
1631 };
1633 #if defined(CONFIG_OF)
1634 static const struct of_device_id omap_serial_of_match[] = {
1635 { .compatible = "ti,omap2-uart" },
1636 { .compatible = "ti,omap3-uart" },
1637 { .compatible = "ti,omap4-uart" },
1638 {},
1639 };
1640 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1641 #endif
1643 static struct platform_driver serial_omap_driver = {
1644 .probe = serial_omap_probe,
1645 .remove = serial_omap_remove,
1646 .driver = {
1647 .name = DRIVER_NAME,
1648 .pm = &serial_omap_dev_pm_ops,
1649 .of_match_table = of_match_ptr(omap_serial_of_match),
1650 },
1651 };
1653 static int __init serial_omap_init(void)
1654 {
1655 int ret;
1657 ret = uart_register_driver(&serial_omap_reg);
1658 if (ret != 0)
1659 return ret;
1660 ret = platform_driver_register(&serial_omap_driver);
1661 if (ret != 0)
1662 uart_unregister_driver(&serial_omap_reg);
1663 return ret;
1664 }
1666 static void __exit serial_omap_exit(void)
1667 {
1668 platform_driver_unregister(&serial_omap_driver);
1669 uart_unregister_driver(&serial_omap_reg);
1670 }
1672 module_init(serial_omap_init);
1673 module_exit(serial_omap_exit);
1675 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1676 MODULE_LICENSE("GPL");
1677 MODULE_AUTHOR("Texas Instruments Inc");