usb: musb: same MUSB_OFFSET/musb_ep_select for all controller
[sitara-epos/sitara-epos-kernel.git] / drivers / usb / musb / blackfin.c
1 /*
2  * MUSB OTG controller driver for Blackfin Processors
3  *
4  * Copyright 2006-2008 Analog Devices Inc.
5  *
6  * Enter bugs at http://blackfin.uclinux.org/
7  *
8  * Licensed under the GPL-2 or later.
9  */
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/sched.h>
14 #include <linux/init.h>
15 #include <linux/list.h>
16 #include <linux/gpio.h>
17 #include <linux/io.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/prefetch.h>
22 #include <asm/cacheflush.h>
24 #include "musb_core.h"
25 #include "musbhsdma.h"
26 #include "blackfin.h"
28 struct bfin_glue {
29         struct device           *dev;
30         struct platform_device  *musb;
31 };
32 #define glue_to_musb(g)         platform_get_drvdata(g->musb)
34 /*
35  * Load an endpoint's FIFO
36  */
37 static void bfin_musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
38                                 const u8 *src)
39 {
40         struct musb *musb = hw_ep->musb;
41         void __iomem *fifo = hw_ep->fifo;
42         void __iomem *epio = hw_ep->regs;
43         u8 epnum = hw_ep->epnum;
45         prefetch((u8 *)src);
47         musb_writew(epio, MUSB_TXCOUNT, len);
49         dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
50                         hw_ep->epnum, fifo, len, src, epio);
52         dump_fifo_data(src, len);
54         if (!ANOMALY_05000380 && epnum != 0) {
55                 u16 dma_reg;
57                 flush_dcache_range((unsigned long)src,
58                         (unsigned long)(src + len));
60                 /* Setup DMA address register */
61                 dma_reg = (u32)src;
62                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
63                 SSYNC();
65                 dma_reg = (u32)src >> 16;
66                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
67                 SSYNC();
69                 /* Setup DMA count register */
70                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
71                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
72                 SSYNC();
74                 /* Enable the DMA */
75                 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
76                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
77                 SSYNC();
79                 /* Wait for compelete */
80                 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
81                         cpu_relax();
83                 /* acknowledge dma interrupt */
84                 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
85                 SSYNC();
87                 /* Reset DMA */
88                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
89                 SSYNC();
90         } else {
91                 SSYNC();
93                 if (unlikely((unsigned long)src & 0x01))
94                         outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
95                 else
96                         outsw((unsigned long)fifo, src, (len + 1) >> 1);
97         }
98 }
99 /*
100  * Unload an endpoint's FIFO
101  */
102 static void bfin_musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
104         struct musb *musb = hw_ep->musb;
105         void __iomem *fifo = hw_ep->fifo;
106         u8 epnum = hw_ep->epnum;
108         if (ANOMALY_05000467 && epnum != 0) {
109                 u16 dma_reg;
111                 invalidate_dcache_range((unsigned long)dst,
112                         (unsigned long)(dst + len));
114                 /* Setup DMA address register */
115                 dma_reg = (u32)dst;
116                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
117                 SSYNC();
119                 dma_reg = (u32)dst >> 16;
120                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
121                 SSYNC();
123                 /* Setup DMA count register */
124                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
125                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
126                 SSYNC();
128                 /* Enable the DMA */
129                 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
130                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
131                 SSYNC();
133                 /* Wait for compelete */
134                 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
135                         cpu_relax();
137                 /* acknowledge dma interrupt */
138                 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
139                 SSYNC();
141                 /* Reset DMA */
142                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
143                 SSYNC();
144         } else {
145                 SSYNC();
146                 /* Read the last byte of packet with odd size from address fifo + 4
147                  * to trigger 1 byte access to EP0 FIFO.
148                  */
149                 if (len == 1)
150                         *dst = (u8)inw((unsigned long)fifo + 4);
151                 else {
152                         if (unlikely((unsigned long)dst & 0x01))
153                                 insw_8((unsigned long)fifo, dst, len >> 1);
154                         else
155                                 insw((unsigned long)fifo, dst, len >> 1);
157                         if (len & 0x01)
158                                 *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
159                 }
160         }
161         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
162                         'R', hw_ep->epnum, fifo, len, dst);
164         dump_fifo_data(dst, len);
167 static irqreturn_t blackfin_interrupt(int irq, void *__hci)
169         unsigned long   flags;
170         irqreturn_t     retval = IRQ_NONE;
171         struct musb     *musb = __hci;
173         spin_lock_irqsave(&musb->lock, flags);
175         musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
176         musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
177         musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
179         if (musb->int_usb || musb->int_tx || musb->int_rx) {
180                 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
181                 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
182                 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
183                 retval = musb_interrupt(musb);
184         }
186         /* Start sampling ID pin, when plug is removed from MUSB */
187         if ((is_otg_enabled(musb) && (musb->xceiv->state == OTG_STATE_B_IDLE
188                 || musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) ||
189                 (musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
190                 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
191                 musb->a_wait_bcon = TIMER_DELAY;
192         }
194         spin_unlock_irqrestore(&musb->lock, flags);
196         return retval;
199 static void musb_conn_timer_handler(unsigned long _musb)
201         struct musb *musb = (void *)_musb;
202         unsigned long flags;
203         u16 val;
204         static u8 toggle;
206         spin_lock_irqsave(&musb->lock, flags);
207         switch (musb->xceiv->state) {
208         case OTG_STATE_A_IDLE:
209         case OTG_STATE_A_WAIT_BCON:
210                 /* Start a new session */
211                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
212                 val &= ~MUSB_DEVCTL_SESSION;
213                 musb_writew(musb->mregs, MUSB_DEVCTL, val);
214                 val |= MUSB_DEVCTL_SESSION;
215                 musb_writew(musb->mregs, MUSB_DEVCTL, val);
216                 /* Check if musb is host or peripheral. */
217                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
219                 if (!(val & MUSB_DEVCTL_BDEVICE)) {
220                         gpio_set_value(musb->config->gpio_vrsel, 1);
221                         musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
222                 } else {
223                         gpio_set_value(musb->config->gpio_vrsel, 0);
224                         /* Ignore VBUSERROR and SUSPEND IRQ */
225                         val = musb_readb(musb->mregs, MUSB_INTRUSBE);
226                         val &= ~MUSB_INTR_VBUSERROR;
227                         musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
229                         val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
230                         musb_writeb(musb->mregs, MUSB_INTRUSB, val);
231                         if (is_otg_enabled(musb))
232                                 musb->xceiv->state = OTG_STATE_B_IDLE;
233                         else
234                                 musb_writeb(musb->mregs, MUSB_POWER, MUSB_POWER_HSENAB);
235                 }
236                 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
237                 break;
238         case OTG_STATE_B_IDLE:
240                 if (!is_peripheral_enabled(musb))
241                         break;
242                 /* Start a new session.  It seems that MUSB needs taking
243                  * some time to recognize the type of the plug inserted?
244                  */
245                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
246                 val |= MUSB_DEVCTL_SESSION;
247                 musb_writew(musb->mregs, MUSB_DEVCTL, val);
248                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
250                 if (!(val & MUSB_DEVCTL_BDEVICE)) {
251                         gpio_set_value(musb->config->gpio_vrsel, 1);
252                         musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
253                 } else {
254                         gpio_set_value(musb->config->gpio_vrsel, 0);
256                         /* Ignore VBUSERROR and SUSPEND IRQ */
257                         val = musb_readb(musb->mregs, MUSB_INTRUSBE);
258                         val &= ~MUSB_INTR_VBUSERROR;
259                         musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
261                         val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
262                         musb_writeb(musb->mregs, MUSB_INTRUSB, val);
264                         /* Toggle the Soft Conn bit, so that we can response to
265                          * the inserting of either A-plug or B-plug.
266                          */
267                         if (toggle) {
268                                 val = musb_readb(musb->mregs, MUSB_POWER);
269                                 val &= ~MUSB_POWER_SOFTCONN;
270                                 musb_writeb(musb->mregs, MUSB_POWER, val);
271                                 toggle = 0;
272                         } else {
273                                 val = musb_readb(musb->mregs, MUSB_POWER);
274                                 val |= MUSB_POWER_SOFTCONN;
275                                 musb_writeb(musb->mregs, MUSB_POWER, val);
276                                 toggle = 1;
277                         }
278                         /* The delay time is set to 1/4 second by default,
279                          * shortening it, if accelerating A-plug detection
280                          * is needed in OTG mode.
281                          */
282                         mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4);
283                 }
284                 break;
285         default:
286                 dev_dbg(musb->controller, "%s state not handled\n",
287                         otg_state_string(musb->xceiv->state));
288                 break;
289         }
290         spin_unlock_irqrestore(&musb->lock, flags);
292         dev_dbg(musb->controller, "state is %s\n",
293                 otg_state_string(musb->xceiv->state));
296 static void bfin_musb_enable(struct musb *musb)
298         if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
299                 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
300                 musb->a_wait_bcon = TIMER_DELAY;
301         }
304 static void bfin_musb_disable(struct musb *musb)
308 static void bfin_musb_set_vbus(struct musb *musb, int is_on)
310         int value = musb->config->gpio_vrsel_active;
311         if (!is_on)
312                 value = !value;
313         gpio_set_value(musb->config->gpio_vrsel, value);
315         dev_dbg(musb->controller, "VBUS %s, devctl %02x "
316                 /* otg %3x conf %08x prcm %08x */ "\n",
317                 otg_state_string(musb->xceiv->state),
318                 musb_readb(musb->mregs, MUSB_DEVCTL));
321 static int bfin_musb_set_power(struct otg_transceiver *x, unsigned mA)
323         return 0;
326 static void bfin_musb_try_idle(struct musb *musb, unsigned long timeout)
328         if (!is_otg_enabled(musb) && is_host_enabled(musb))
329                 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
332 static int bfin_musb_vbus_status(struct musb *musb)
334         return 0;
337 static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
339         return -EIO;
342 static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
343                                 u16 packet_sz, u8 *mode,
344                                 dma_addr_t *dma_addr, u32 *len)
346         struct musb_dma_channel *musb_channel = channel->private_data;
348         /*
349          * Anomaly 05000450 might cause data corruption when using DMA
350          * MODE 1 transmits with short packet.  So to work around this,
351          * we truncate all MODE 1 transfers down to a multiple of the
352          * max packet size, and then do the last short packet transfer
353          * (if there is any) using MODE 0.
354          */
355         if (ANOMALY_05000450) {
356                 if (musb_channel->transmit && *mode == 1)
357                         *len = *len - (*len % packet_sz);
358         }
360         return 0;
363 static void bfin_musb_reg_init(struct musb *musb)
365         if (ANOMALY_05000346) {
366                 bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
367                 SSYNC();
368         }
370         if (ANOMALY_05000347) {
371                 bfin_write_USB_APHY_CNTRL(0x0);
372                 SSYNC();
373         }
375         /* Configure PLL oscillator register */
376         bfin_write_USB_PLLOSC_CTRL(0x3080 |
377                         ((480/musb->config->clkin) << 1));
378         SSYNC();
380         bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
381         SSYNC();
383         bfin_write_USB_EP_NI0_RXMAXP(64);
384         SSYNC();
386         bfin_write_USB_EP_NI0_TXMAXP(64);
387         SSYNC();
389         /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
390         bfin_write_USB_GLOBINTR(0x7);
391         SSYNC();
393         bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
394                                 EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
395                                 EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
396                                 EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
397                                 EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
398         SSYNC();
401 static int bfin_musb_init(struct musb *musb)
404         /*
405          * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
406          * and OTG HOST modes, while rev 1.1 and greater require PE7 to
407          * be low for DEVICE mode and high for HOST mode. We set it high
408          * here because we are in host mode
409          */
411         if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
412                 printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
413                         musb->config->gpio_vrsel);
414                 return -ENODEV;
415         }
416         gpio_direction_output(musb->config->gpio_vrsel, 0);
418         usb_nop_xceiv_register();
419         musb->xceiv = otg_get_transceiver();
420         if (!musb->xceiv) {
421                 gpio_free(musb->config->gpio_vrsel);
422                 return -ENODEV;
423         }
425         bfin_musb_reg_init(musb);
427         if (is_host_enabled(musb)) {
428                 setup_timer(&musb_conn_timer,
429                         musb_conn_timer_handler, (unsigned long) musb);
430         }
431         if (is_peripheral_enabled(musb))
432                 musb->xceiv->set_power = bfin_musb_set_power;
434         musb->isr = blackfin_interrupt;
435         musb->double_buffer_not_ok = true;
437         return 0;
440 static int bfin_musb_exit(struct musb *musb)
442         gpio_free(musb->config->gpio_vrsel);
444         otg_put_transceiver(musb->xceiv);
445         usb_nop_xceiv_unregister();
446         return 0;
449 static const struct musb_platform_ops bfin_ops = {
450         .fifo_mode      = 2,
451         .flags          = MUSB_GLUE_EP_ADDR_FLAT_MAPPING,
452         .init           = bfin_musb_init,
453         .exit           = bfin_musb_exit,
455         .enable         = bfin_musb_enable,
456         .disable        = bfin_musb_disable,
458         .read_fifo      = bfin_musb_read_fifo,
459         .write_fifo     = bfin_musb_write_fifo,
461         .set_mode       = bfin_musb_set_mode,
462         .try_idle       = bfin_musb_try_idle,
464         .vbus_status    = bfin_musb_vbus_status,
465         .set_vbus       = bfin_musb_set_vbus,
467         .adjust_channel_params = bfin_musb_adjust_channel_params,
468 };
470 static u64 bfin_dmamask = DMA_BIT_MASK(32);
472 static int __init bfin_probe(struct platform_device *pdev)
474         struct musb_hdrc_platform_data  *pdata = pdev->dev.platform_data;
475         struct platform_device          *musb;
476         struct bfin_glue                *glue;
478         int                             ret = -ENOMEM;
480         glue = kzalloc(sizeof(*glue), GFP_KERNEL);
481         if (!glue) {
482                 dev_err(&pdev->dev, "failed to allocate glue context\n");
483                 goto err0;
484         }
486         musb = platform_device_alloc("musb-hdrc", -1);
487         if (!musb) {
488                 dev_err(&pdev->dev, "failed to allocate musb device\n");
489                 goto err1;
490         }
492         musb->dev.parent                = &pdev->dev;
493         musb->dev.dma_mask              = &bfin_dmamask;
494         musb->dev.coherent_dma_mask     = bfin_dmamask;
496         glue->dev                       = &pdev->dev;
497         glue->musb                      = musb;
499         pdata->platform_ops             = &bfin_ops;
501         platform_set_drvdata(pdev, glue);
503         ret = platform_device_add_resources(musb, pdev->resource,
504                         pdev->num_resources);
505         if (ret) {
506                 dev_err(&pdev->dev, "failed to add resources\n");
507                 goto err2;
508         }
510         ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
511         if (ret) {
512                 dev_err(&pdev->dev, "failed to add platform_data\n");
513                 goto err2;
514         }
516         ret = platform_device_add(musb);
517         if (ret) {
518                 dev_err(&pdev->dev, "failed to register musb device\n");
519                 goto err2;
520         }
522         return 0;
524 err2:
525         platform_device_put(musb);
527 err1:
528         kfree(glue);
530 err0:
531         return ret;
534 static int __exit bfin_remove(struct platform_device *pdev)
536         struct bfin_glue                *glue = platform_get_drvdata(pdev);
538         platform_device_del(glue->musb);
539         platform_device_put(glue->musb);
540         kfree(glue);
542         return 0;
545 #ifdef CONFIG_PM
546 static int bfin_suspend(struct device *dev)
548         struct bfin_glue        *glue = dev_get_drvdata(dev);
549         struct musb             *musb = glue_to_musb(glue);
551         if (is_host_active(musb))
552                 /*
553                  * During hibernate gpio_vrsel will change from high to low
554                  * low which will generate wakeup event resume the system
555                  * immediately.  Set it to 0 before hibernate to avoid this
556                  * wakeup event.
557                  */
558                 gpio_set_value(musb->config->gpio_vrsel, 0);
560         return 0;
563 static int bfin_resume(struct device *dev)
565         struct bfin_glue        *glue = dev_get_drvdata(dev);
566         struct musb             *musb = glue_to_musb(glue);
568         bfin_musb_reg_init(musb);
570         return 0;
573 static struct dev_pm_ops bfin_pm_ops = {
574         .suspend        = bfin_suspend,
575         .resume         = bfin_resume,
576 };
578 #define DEV_PM_OPS      &bfin_pm_ops
579 #else
580 #define DEV_PM_OPS      NULL
581 #endif
583 static struct platform_driver bfin_driver = {
584         .remove         = __exit_p(bfin_remove),
585         .driver         = {
586                 .name   = "musb-blackfin",
587                 .pm     = DEV_PM_OPS,
588         },
589 };
591 MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
592 MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
593 MODULE_LICENSE("GPL v2");
595 static int __init bfin_init(void)
597         return platform_driver_probe(&bfin_driver, bfin_probe);
599 subsys_initcall(bfin_init);
601 static void __exit bfin_exit(void)
603         platform_driver_unregister(&bfin_driver);
605 module_exit(bfin_exit);