drivers/usb/musb/cppi41.c

   1 /*
   2  * CPPI 4.1 support
   3  *
   4  * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
   5  *
   6  * Based on the PAL CPPI 4.1 implementation
   7  * Copyright (C) 1998-2006 Texas Instruments Incorporated
   8  *
   9  * This file contains the main implementation for CPPI 4.1 common peripherals,
  10  * including the DMA Controllers and the Queue Managers.
  11  *
  12  * This program is free software; you can distribute it and/or modify it
  13  * under the terms of the GNU General Public License (Version 2) as
  14  * published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope it will be useful, but WITHOUT
  17  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  19  * for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License along
  22  * with this program; if not, write to the Free Software Foundation, Inc.,
  23  * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  24  *
  25  */
  26
  27 #include <linux/io.h>
  28 #include <linux/init.h>
  29 #include <linux/slab.h>
  30 #include <linux/module.h>
  31 #include <linux/dma-mapping.h>
  32
  33 #include "cppi41.h"
  34
  35 #undef  CPPI41_DEBUG
  36
  37 #ifdef  CPPI41_DEBUG
  38 #define DBG(format, args...) printk(format, ##args)
  39 #else
  40 #define DBG(format, args...)
  41 #endif
  42
  43 static struct {
  44         void *virt_addr;
  45         dma_addr_t phys_addr;
  46         u32     size;
  47 } linking_ram[CPPI41_NUM_QUEUE_MGR];
  48
  49 static u32 *allocated_queues[CPPI41_NUM_QUEUE_MGR];
  50
  51 /* First 32 packet descriptors are reserved for unallocated memory regions. */
  52 static u32 next_desc_index[CPPI41_NUM_QUEUE_MGR] = { 1 << 5 };
  53 static u8  next_mem_rgn[CPPI41_NUM_QUEUE_MGR];
  54
  55 static struct {
  56         size_t rgn_size;
  57         void *virt_addr;
  58         dma_addr_t phys_addr;
  59         struct cppi41_queue_obj queue_obj;
  60         u8 mem_rgn;
  61         u16 q_mgr;
  62         u16 q_num;
  63         u32 num_desc;
  64 } dma_teardown[CPPI41_NUM_DMA_BLOCK];
  65
  66 struct cppi41_dma_sched_tbl_t {
  67         u8      pos;
  68         u8      dma_ch;
  69         u8      is_tx;
  70         u8      enb;
  71 };
  72
  73 struct cppi41_dma_sched_tbl_t dma_sched_tbl[MAX_SCHED_TBL_ENTRY] = {
  74         /*pos  dma_ch#  is_tx  enb/dis*/
  75         { 0,    0,      0,      1},
  76         { 1,    0,      1,      1},
  77         { 2,    1,      0,      1},
  78         { 3,    1,      1,      1},
  79         { 4,    2,      0,      1},
  80         { 5,    2,      1,      1},
  81         { 6,    3,      0,      1},
  82         { 7,    3,      1,      1}
  83 };
  84
  85 struct cppi41_queue_mgr cppi41_queue_mgr[CPPI41_NUM_QUEUE_MGR];
  86 EXPORT_SYMBOL(cppi41_queue_mgr);
  87
  88 struct cppi41_dma_block cppi41_dma_block[CPPI41_NUM_DMA_BLOCK];
  89 EXPORT_SYMBOL(cppi41_dma_block);
  90 /******************** CPPI 4.1 Functions (External Interface) *****************/
  91
  92 int cppi41_queue_mgr_init(u8 q_mgr, dma_addr_t rgn0_base, u16 rgn0_size)
  93 {
  94         void __iomem *q_mgr_regs;
  95         void *ptr;
  96
  97         if (q_mgr >= cppi41_num_queue_mgr)
  98                 return -EINVAL;
  99
 100         q_mgr_regs = cppi41_queue_mgr[q_mgr].q_mgr_rgn_base;
 101         ptr = dma_alloc_coherent(NULL, rgn0_size * 4,
 102                                  &linking_ram[q_mgr].phys_addr,
 103                                  GFP_KERNEL | GFP_DMA);
 104         if (ptr == NULL) {
 105                 printk(KERN_ERR "ERROR: %s: Unable to allocate "
 106                        "linking RAM.\n", __func__);
 107                 return -ENOMEM;
 108         }
 109         linking_ram[q_mgr].virt_addr = ptr;
 110         linking_ram[q_mgr].size = rgn0_size * 4;
 111
 112         __raw_writel(linking_ram[q_mgr].phys_addr,
 113                         q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG);
 114         DBG("Linking RAM region 0 base @ %p, value: %x\n",
 115             q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG,
 116             __raw_readl(q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG));
 117
 118         __raw_writel(rgn0_size, q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG);
 119         DBG("Linking RAM region 0 size @ %p, value: %x\n",
 120             q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG,
 121             __raw_readl(q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG));
 122
 123         ptr = kzalloc(BITS_TO_LONGS(cppi41_queue_mgr[q_mgr].num_queue),
 124                       GFP_KERNEL);
 125         if (ptr == NULL) {
 126                 printk(KERN_ERR "ERROR: %s: Unable to allocate queue bitmap.\n",
 127                        __func__);
 128                 dma_free_coherent(NULL, rgn0_size * 4,
 129                                   linking_ram[q_mgr].virt_addr,
 130                                   linking_ram[q_mgr].phys_addr);
 131                 return -ENOMEM;
 132         }
 133         allocated_queues[q_mgr] = ptr;
 134
 135         return 0;
 136 }
 137 EXPORT_SYMBOL(cppi41_queue_mgr_init);
 138
 139 int cppi41_queue_mgr_uninit(u8 q_mgr)
 140 {
 141         void __iomem *q_mgr_regs;
 142
 143         if (q_mgr >= cppi41_num_queue_mgr)
 144                 return -EINVAL;
 145
 146         q_mgr_regs = cppi41_queue_mgr[q_mgr].q_mgr_rgn_base;
 147
 148         /* free the Queue Mgr linking ram space */
 149         __raw_writel(0, q_mgr_regs + QMGR_LINKING_RAM_RGN0_BASE_REG);
 150         __raw_writel(0, q_mgr_regs + QMGR_LINKING_RAM_RGN0_SIZE_REG);
 151         dma_free_coherent(NULL, linking_ram[q_mgr].size,
 152                         linking_ram[q_mgr].virt_addr,
 153                         linking_ram[q_mgr].phys_addr);
 154
 155         /* free the allocated queues */
 156         kfree(allocated_queues[q_mgr]);
 157         return 0;
 158 }
 159 EXPORT_SYMBOL(cppi41_queue_mgr_uninit);
 160
 161 int cppi41_dma_sched_tbl_init(u8 dma_num, u8 q_mgr,
 162                         u32 *sched_tbl, u8 tbl_size)
 163 {
 164         struct cppi41_dma_block *dma_block;
 165         int num_reg, k, i, val = 0;
 166
 167         dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dma_num];
 168
 169         num_reg = (tbl_size + 3) / 4;
 170         for (k = i = 0; i < num_reg; i++) {
 171 #if 0
 172                 for (val = j = 0; j < 4; j++, k++) {
 173                         val >>= 8;
 174                         if (k < tbl_size)
 175                                 val |= sched_tbl[k] << 24;
 176                 }
 177 #endif
 178                 val = sched_tbl[i];
 179                 __raw_writel(val, dma_block->sched_table_base +
 180                         DMA_SCHED_TABLE_WORD_REG(i));
 181                 DBG("DMA scheduler table @ %p, value written: %x\n",
 182                 dma_block->sched_table_base + DMA_SCHED_TABLE_WORD_REG(i),
 183                         val);
 184         }
 185         return 0;
 186 }
 187 EXPORT_SYMBOL(cppi41_dma_sched_tbl_init);
 188
 189 int cppi41_schedtbl_add_dma_ch(u8 dmanum, u8 qmgr, u8 dma_ch, u8 is_tx)
 190 {
 191         struct cppi41_dma_block *dma_block;
 192         int num_ch, i, tbl_index = 0, j = 0, found = 0;
 193         u32 val;
 194
 195         dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dmanum];
 196
 197         val = 0;
 198         for (num_ch = 0, i = 0; i < MAX_SCHED_TBL_ENTRY; i++) {
 199                 if (!found && dma_sched_tbl[i].dma_ch == dma_ch &&
 200                         dma_sched_tbl[i].is_tx == is_tx &&
 201                         dma_sched_tbl[i].enb == 0) {
 202                         dma_sched_tbl[i].enb = 1;
 203                         found = 1;
 204                 }
 205
 206                 if (dma_sched_tbl[i].enb) {
 207                         val |= ((dma_sched_tbl[i].dma_ch |
 208                                 (dma_sched_tbl[i].is_tx ? 0 : (1<<7))) << j*8);
 209                         num_ch++;
 210                         j++;
 211                 }
 212                 if (num_ch % 4 == 0) {
 213                         __raw_writel(val, dma_block->sched_table_base +
 214                                 DMA_SCHED_TABLE_WORD_REG(tbl_index));
 215                         tbl_index++;
 216                         val = j = 0;
 217                 }
 218         }
 219
 220         if (num_ch % 4) {
 221                 __raw_writel(val, dma_block->sched_table_base +
 222                         DMA_SCHED_TABLE_WORD_REG(tbl_index));
 223         }
 224         return num_ch;
 225 }
 226 EXPORT_SYMBOL(cppi41_schedtbl_add_dma_ch);
 227
 228 int cppi41_schedtbl_remove_dma_ch(u8 dmanum, u8 qmgr, u8 dma_ch, u8 is_tx)
 229 {
 230         struct cppi41_dma_block *dma_block;
 231         int num_ch, i, tbl_index = 0, j = 0, found = 0;
 232         u32 val;
 233
 234         dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dmanum];
 235
 236         val = 0;
 237         for (num_ch = 0, i = 0; i < MAX_SCHED_TBL_ENTRY; i++) {
 238                 if (!found && dma_sched_tbl[i].dma_ch == dma_ch &&
 239                         dma_sched_tbl[i].is_tx == is_tx &&
 240                         dma_sched_tbl[i].enb == 1) {
 241                         dma_sched_tbl[i].enb = 0;
 242                 }
 243
 244                 if (dma_sched_tbl[i].enb) {
 245                         val |= ((dma_sched_tbl[i].dma_ch |
 246                                 (dma_sched_tbl[i].is_tx ? 0 : (1<<7))) << j*8);
 247                         num_ch++;
 248                         j++;
 249                 }
 250                 if (num_ch % 4 == 0) {
 251                         __raw_writel(val, dma_block->sched_table_base +
 252                                 DMA_SCHED_TABLE_WORD_REG(tbl_index));
 253                         tbl_index++;
 254                         val = j = 0;
 255                 }
 256         }
 257
 258         if (num_ch % 4) {
 259                 __raw_writel(val, dma_block->sched_table_base +
 260                         DMA_SCHED_TABLE_WORD_REG(tbl_index));
 261         }
 262         return num_ch;
 263 }
 264 EXPORT_SYMBOL(cppi41_schedtbl_remove_dma_ch);
 265
 266 int cppi41_dma_block_init(u8 dma_num, u8 q_mgr, u8 num_order,
 267                                  u32 *sched_tbl, u8 tbl_size)
 268 {
 269         const struct cppi41_dma_block *dma_block;
 270         struct cppi41_teardown_desc *curr_td;
 271         dma_addr_t td_addr;
 272         unsigned num_desc, num_reg;
 273         void *ptr;
 274         int error, i;
 275         u16 q_num;
 276         u32 val;
 277
 278         if (dma_num >= cppi41_num_dma_block ||
 279             q_mgr >= cppi41_num_queue_mgr ||
 280             !tbl_size || sched_tbl == NULL)
 281                 return -EINVAL;
 282
 283         error = cppi41_queue_alloc(CPPI41_FREE_DESC_QUEUE |
 284                                    CPPI41_UNASSIGNED_QUEUE, q_mgr, &q_num);
 285         if (error) {
 286                 printk(KERN_ERR "ERROR: %s: Unable to allocate teardown "
 287                        "descriptor queue.\n", __func__);
 288                 return error;
 289         }
 290         DBG("Teardown descriptor queue %d in queue manager 0 "
 291             "allocated\n", q_num);
 292
 293         /*
 294          * Tell the hardware about the Teardown descriptor
 295          * queue manager and queue number.
 296          */
 297         dma_block = &cppi41_dma_block[dma_num];
 298         __raw_writel((q_mgr << DMA_TD_DESC_QMGR_SHIFT) |
 299                      (q_num << DMA_TD_DESC_QNUM_SHIFT),
 300                      dma_block->global_ctrl_base +
 301                      DMA_TEARDOWN_FREE_DESC_CTRL_REG);
 302         DBG("Teardown free descriptor control @ %p, value: %x\n",
 303             dma_block->global_ctrl_base + DMA_TEARDOWN_FREE_DESC_CTRL_REG,
 304             __raw_readl(dma_block->global_ctrl_base +
 305                         DMA_TEARDOWN_FREE_DESC_CTRL_REG));
 306
 307         num_desc = 1 << num_order;
 308         dma_teardown[dma_num].rgn_size = num_desc *
 309                                          sizeof(struct cppi41_teardown_desc);
 310
 311         /* Pre-allocate teardown descriptors. */
 312         ptr = dma_alloc_coherent(NULL, dma_teardown[dma_num].rgn_size,
 313                                  &dma_teardown[dma_num].phys_addr,
 314                                  GFP_KERNEL | GFP_DMA);
 315         if (ptr == NULL) {
 316                 printk(KERN_ERR "ERROR: %s: Unable to allocate teardown "
 317                        "descriptors.\n", __func__);
 318                 error = -ENOMEM;
 319                 goto free_queue;
 320         }
 321         dma_teardown[dma_num].virt_addr = ptr;
 322
 323         error = cppi41_mem_rgn_alloc(q_mgr, dma_teardown[dma_num].phys_addr, 5,
 324                                      num_order, &dma_teardown[dma_num].mem_rgn);
 325         if (error) {
 326                 printk(KERN_ERR "ERROR: %s: Unable to allocate queue manager "
 327                        "memory region for teardown descriptors.\n", __func__);
 328                 goto free_mem;
 329         }
 330
 331         error = cppi41_queue_init(&dma_teardown[dma_num].queue_obj, 0, q_num);
 332         if (error) {
 333                 printk(KERN_ERR "ERROR: %s: Unable to initialize teardown "
 334                        "free descriptor queue.\n", __func__);
 335                 goto free_rgn;
 336         }
 337
 338         dma_teardown[dma_num].q_num = q_num;
 339         dma_teardown[dma_num].q_mgr = q_mgr;
 340         /*
 341          * Push all teardown descriptors to the free teardown queue
 342          * for the CPPI 4.1 system.
 343          */
 344         curr_td = dma_teardown[dma_num].virt_addr;
 345         td_addr = dma_teardown[dma_num].phys_addr;
 346
 347         for (i = 0; i < num_desc; i++) {
 348                 cppi41_queue_push(&dma_teardown[dma_num].queue_obj, td_addr,
 349                                   sizeof(*curr_td), 0);
 350                 td_addr += sizeof(*curr_td);
 351         }
 352         dma_teardown[dma_num].num_desc = num_desc;
 353
 354         /* Initialize the DMA scheduler. */
 355         num_reg = (tbl_size + 3) / 4;
 356         for (i = 0; i < num_reg; i++) {
 357                 val = sched_tbl[i];
 358                 __raw_writel(val, dma_block->sched_table_base +
 359                              DMA_SCHED_TABLE_WORD_REG(i));
 360                 DBG("DMA scheduler table @ %p, value written: %x\n",
 361                     dma_block->sched_table_base + DMA_SCHED_TABLE_WORD_REG(i),
 362                     val);
 363         }
 364
 365         __raw_writel((tbl_size - 1) << DMA_SCHED_LAST_ENTRY_SHIFT |
 366                      DMA_SCHED_ENABLE_MASK,
 367                      dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG);
 368         DBG("DMA scheduler control @ %p, value: %x\n",
 369             dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG,
 370             __raw_readl(dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG));
 371
 372         return 0;
 373
 374 free_rgn:
 375         cppi41_mem_rgn_free(q_mgr, dma_teardown[dma_num].mem_rgn);
 376 free_mem:
 377         dma_free_coherent(NULL, dma_teardown[dma_num].rgn_size,
 378                           dma_teardown[dma_num].virt_addr,
 379                           dma_teardown[dma_num].phys_addr);
 380 free_queue:
 381         cppi41_queue_free(q_mgr, q_num);
 382         return error;
 383 }
 384 EXPORT_SYMBOL(cppi41_dma_block_init);
 385
 386 int cppi41_dma_block_uninit(u8 dma_num, u8 q_mgr, u8 num_order,
 387                                  u32 *sched_tbl, u8 tbl_size)
 388 {
 389         const struct cppi41_dma_block *dma_block;
 390         unsigned num_reg;
 391         int i;
 392
 393         /* popout all teardown descriptors */
 394         cppi41_free_teardown_queue(dma_num);
 395
 396         /* free queue mgr region */
 397         cppi41_mem_rgn_free(q_mgr, dma_teardown[dma_num].mem_rgn);
 398         /* free the allocated teardown descriptors */
 399         dma_free_coherent(NULL, dma_teardown[dma_num].rgn_size,
 400                         dma_teardown[dma_num].virt_addr,
 401                         dma_teardown[dma_num].phys_addr);
 402
 403         /* free the teardown queue*/
 404         cppi41_queue_free(dma_teardown[dma_num].q_mgr,
 405                         dma_teardown[dma_num].q_num);
 406
 407         dma_block = (struct cppi41_dma_block *)&cppi41_dma_block[dma_num];
 408         /* disable the dma schedular */
 409         num_reg = (tbl_size + 3) / 4;
 410         for (i = 0; i < num_reg; i++) {
 411                 __raw_writel(0, dma_block->sched_table_base +
 412                              DMA_SCHED_TABLE_WORD_REG(i));
 413                 DBG("DMA scheduler table @ %p, value written: %x\n",
 414                     dma_block->sched_table_base + DMA_SCHED_TABLE_WORD_REG(i),
 415                     0);
 416         }
 417
 418         __raw_writel(0, dma_block->sched_ctrl_base + DMA_SCHED_CTRL_REG);
 419
 420         return 0;
 421 }
 422 EXPORT_SYMBOL(cppi41_dma_block_uninit);
 423 /*
 424  * cppi41_mem_rgn_alloc - allocate a memory region within the queue manager
 425  */
 426 int cppi41_mem_rgn_alloc(u8 q_mgr, dma_addr_t rgn_addr, u8 size_order,
 427                          u8 num_order, u8 *mem_rgn)
 428 {
 429         void __iomem *desc_mem_regs;
 430         u32 num_desc = 1 << num_order, index, ctrl;
 431         int rgn;
 432
 433         DBG("%s called with rgn_addr = %08x, size_order = %d, num_order = %d\n",
 434             __func__, rgn_addr, size_order, num_order);
 435
 436         if (q_mgr >= cppi41_num_queue_mgr ||
 437             size_order < 5 || size_order > 13 ||
 438             num_order  < 5 || num_order  > 12 ||
 439             (rgn_addr & ((1 << size_order) - 1)))
 440                 return -EINVAL;
 441
 442         rgn = next_mem_rgn[q_mgr];
 443         index = next_desc_index[q_mgr];
 444         if (rgn >= CPPI41_MAX_MEM_RGN || index + num_desc > 0x4000)
 445                 return -ENOSPC;
 446
 447         next_mem_rgn[q_mgr] = rgn + 1;
 448         next_desc_index[q_mgr] = index + num_desc;
 449
 450         desc_mem_regs = cppi41_queue_mgr[q_mgr].desc_mem_rgn_base;
 451
 452         /* Write the base register */
 453         __raw_writel(rgn_addr, desc_mem_regs + QMGR_MEM_RGN_BASE_REG(rgn));
 454         DBG("Descriptor region base @ %p, value: %x\n",
 455             desc_mem_regs + QMGR_MEM_RGN_BASE_REG(rgn),
 456             __raw_readl(desc_mem_regs + QMGR_MEM_RGN_BASE_REG(rgn)));
 457
 458         /* Write the control register */
 459         ctrl = ((index << QMGR_MEM_RGN_INDEX_SHIFT) &
 460                 QMGR_MEM_RGN_INDEX_MASK) |
 461                (((size_order - 5) << QMGR_MEM_RGN_DESC_SIZE_SHIFT) &
 462                 QMGR_MEM_RGN_DESC_SIZE_MASK) |
 463                (((num_order - 5) << QMGR_MEM_RGN_SIZE_SHIFT) &
 464                 QMGR_MEM_RGN_SIZE_MASK);
 465         __raw_writel(ctrl, desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(rgn));
 466         DBG("Descriptor region control @ %p, value: %x\n",
 467             desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(rgn),
 468             __raw_readl(desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(rgn)));
 469
 470         *mem_rgn = rgn;
 471         return 0;
 472 }
 473 EXPORT_SYMBOL(cppi41_mem_rgn_alloc);
 474
 475 /*
 476  * cppi41_mem_rgn_free - free the memory region within the queue manager
 477  */
 478 int cppi41_mem_rgn_free(u8 q_mgr, u8 mem_rgn)
 479 {
 480         void __iomem *desc_mem_regs;
 481
 482         DBG("%s called.\n", __func__);
 483
 484         if (q_mgr >= cppi41_num_queue_mgr || mem_rgn >= next_mem_rgn[q_mgr])
 485                 return -EINVAL;
 486
 487         desc_mem_regs = cppi41_queue_mgr[q_mgr].desc_mem_rgn_base;
 488
 489         if (__raw_readl(desc_mem_regs + QMGR_MEM_RGN_BASE_REG(mem_rgn)) == 0)
 490                 return -ENOENT;
 491
 492         __raw_writel(0, desc_mem_regs + QMGR_MEM_RGN_BASE_REG(mem_rgn));
 493         __raw_writel(0, desc_mem_regs + QMGR_MEM_RGN_CTRL_REG(mem_rgn));
 494
 495         return 0;
 496 }
 497 EXPORT_SYMBOL(cppi41_mem_rgn_free);
 498
 499 /*
 500  * cppi41_tx_ch_init - initialize a CPPI 4.1 Tx channel object
 501  *
 502  * Verify the channel info (range checking, etc.) and store the channel
 503  * information within the object structure.
 504  */
 505 int cppi41_tx_ch_init(struct cppi41_dma_ch_obj *tx_ch_obj,
 506                       u8 dma_num, u8 ch_num)
 507 {
 508         if (dma_num >= cppi41_num_dma_block ||
 509             ch_num  >= cppi41_dma_block[dma_num].num_tx_ch)
 510                 return -EINVAL;
 511
 512         /* Populate the channel object structure */
 513         tx_ch_obj->base_addr  = cppi41_dma_block[dma_num].ch_ctrl_stat_base +
 514                                 DMA_CH_TX_GLOBAL_CFG_REG(ch_num);
 515         tx_ch_obj->global_cfg = __raw_readl(tx_ch_obj->base_addr);
 516         return 0;
 517 }
 518 EXPORT_SYMBOL(cppi41_tx_ch_init);
 519
 520 /*
 521  * cppi41_rx_ch_init - initialize a CPPI 4.1 Rx channel object
 522  *
 523  * Verify the channel info (range checking, etc.) and store the channel
 524  * information within the object structure.
 525  */
 526 int cppi41_rx_ch_init(struct cppi41_dma_ch_obj *rx_ch_obj,
 527                       u8 dma_num, u8 ch_num)
 528 {
 529         if (dma_num >= cppi41_num_dma_block ||
 530             ch_num  >= cppi41_dma_block[dma_num].num_rx_ch)
 531                 return -EINVAL;
 532
 533         /* Populate the channel object structure */
 534         rx_ch_obj->base_addr  = cppi41_dma_block[dma_num].ch_ctrl_stat_base +
 535                                 DMA_CH_RX_GLOBAL_CFG_REG(ch_num);
 536         rx_ch_obj->global_cfg = __raw_readl(rx_ch_obj->base_addr);
 537         return 0;
 538 }
 539 EXPORT_SYMBOL(cppi41_rx_ch_init);
 540
 541 /*
 542  * We have to cache the last written Rx/Tx channel global configration register
 543  * value due to its bits other than enable/teardown being write-only. Yet there
 544  * is a caveat related to caching the enable bit: this bit may be automatically
 545  * cleared as a result of teardown, so we can't trust its cached value!
 546  * When modifying the write only register fields, we're making use of the fact
 547  * that they read back as zeros, and not clearing them explicitly...
 548  */
 549
 550 /*
 551  * cppi41_dma_ch_default_queue - set CPPI 4.1 channel default completion queue
 552  */
 553 void cppi41_dma_ch_default_queue(struct cppi41_dma_ch_obj *dma_ch_obj,
 554                                  u8 q_mgr, u16 q_num)
 555 {
 556         u32 val = dma_ch_obj->global_cfg;
 557
 558         /* Clear the fields to be modified. */
 559         val &= ~(DMA_CH_TX_DEFAULT_QMGR_MASK | DMA_CH_TX_DEFAULT_QNUM_MASK |
 560                  DMA_CH_TX_ENABLE_MASK);
 561
 562         /* Set the default completion queue. */
 563         val |= ((q_mgr << DMA_CH_TX_DEFAULT_QMGR_SHIFT) &
 564                 DMA_CH_TX_DEFAULT_QMGR_MASK) |
 565                ((q_num << DMA_CH_TX_DEFAULT_QNUM_SHIFT) &
 566                 DMA_CH_TX_DEFAULT_QNUM_MASK);
 567
 568         /* Get the current state of the enable bit. */
 569         dma_ch_obj->global_cfg = val |= __raw_readl(dma_ch_obj->base_addr);
 570         __raw_writel(val, dma_ch_obj->base_addr);
 571         DBG("Channel global configuration @ %p, value written: %x, "
 572             "value read: %x\n", dma_ch_obj->base_addr, val,
 573             __raw_readl(dma_ch_obj->base_addr));
 574
 575 }
 576 EXPORT_SYMBOL(cppi41_dma_ch_default_queue);
 577
 578 /*
 579  * cppi41_rx_ch_configure - configure CPPI 4.1 Rx channel
 580  */
 581 void cppi41_rx_ch_configure(struct cppi41_dma_ch_obj *rx_ch_obj,
 582                             struct cppi41_rx_ch_cfg  *cfg)
 583 {
 584         void __iomem *base = rx_ch_obj->base_addr;
 585         u32 val = __raw_readl(rx_ch_obj->base_addr);
 586
 587         val |= ((cfg->sop_offset << DMA_CH_RX_SOP_OFFSET_SHIFT) &
 588                 DMA_CH_RX_SOP_OFFSET_MASK) |
 589                ((cfg->default_desc_type << DMA_CH_RX_DEFAULT_DESC_TYPE_SHIFT) &
 590                 DMA_CH_RX_DEFAULT_DESC_TYPE_MASK) |
 591                ((cfg->retry_starved << DMA_CH_RX_ERROR_HANDLING_SHIFT) &
 592                 DMA_CH_RX_ERROR_HANDLING_MASK) |
 593                ((cfg->rx_queue.q_mgr << DMA_CH_RX_DEFAULT_RQ_QMGR_SHIFT) &
 594                 DMA_CH_RX_DEFAULT_RQ_QMGR_MASK) |
 595                ((cfg->rx_queue.q_num << DMA_CH_RX_DEFAULT_RQ_QNUM_SHIFT) &
 596                 DMA_CH_RX_DEFAULT_RQ_QNUM_MASK);
 597
 598         val &= ~(0x7 << DMA_CH_RX_MAX_BUF_CNT_SHIFT);
 599         val |= (cfg->rx_max_buf_cnt << DMA_CH_RX_MAX_BUF_CNT_SHIFT);
 600
 601         rx_ch_obj->global_cfg = val;
 602         __raw_writel(val, base);
 603         DBG("Rx channel global configuration @ %p, value written: %x, "
 604             "value read: %x\n", base, val, __raw_readl(base));
 605
 606         base -= DMA_CH_RX_GLOBAL_CFG_REG(0);
 607
 608         /*
 609          * Set up the packet configuration register
 610          * based on the descriptor type...
 611          */
 612         switch (cfg->default_desc_type) {
 613         case DMA_CH_RX_DEFAULT_DESC_EMBED:
 614                 val = ((cfg->cfg.embed_pkt.fd_queue.q_mgr <<
 615                         DMA_CH_RX_EMBED_FDQ_QMGR_SHIFT) &
 616                        DMA_CH_RX_EMBED_FDQ_QMGR_MASK) |
 617                       ((cfg->cfg.embed_pkt.fd_queue.q_num <<
 618                         DMA_CH_RX_EMBED_FDQ_QNUM_SHIFT) &
 619                        DMA_CH_RX_EMBED_FDQ_QNUM_MASK) |
 620                       ((cfg->cfg.embed_pkt.num_buf_slot <<
 621                         DMA_CH_RX_EMBED_NUM_SLOT_SHIFT) &
 622                        DMA_CH_RX_EMBED_NUM_SLOT_MASK) |
 623                       ((cfg->cfg.embed_pkt.sop_slot_num <<
 624                         DMA_CH_RX_EMBED_SOP_SLOT_SHIFT) &
 625                        DMA_CH_RX_EMBED_SOP_SLOT_MASK);
 626
 627                 __raw_writel(val, base + DMA_CH_RX_EMBED_PKT_CFG_REG_B(0));
 628                 DBG("Rx channel embedded packet configuration B @ %p, "
 629                     "value written: %x\n",
 630                     base + DMA_CH_RX_EMBED_PKT_CFG_REG_B(0), val);
 631
 632                 val = ((cfg->cfg.embed_pkt.free_buf_pool[0].b_pool <<
 633                         DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(0)) &
 634                        DMA_CH_RX_EMBED_FBP_PNUM_MASK(0)) |
 635                       ((cfg->cfg.embed_pkt.free_buf_pool[0].b_mgr <<
 636                         DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(0)) &
 637                        DMA_CH_RX_EMBED_FBP_BMGR_MASK(0)) |
 638                       ((cfg->cfg.embed_pkt.free_buf_pool[1].b_pool <<
 639                         DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(1)) &
 640                        DMA_CH_RX_EMBED_FBP_PNUM_MASK(1)) |
 641                       ((cfg->cfg.embed_pkt.free_buf_pool[1].b_mgr <<
 642                         DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(1)) &
 643                        DMA_CH_RX_EMBED_FBP_BMGR_MASK(1)) |
 644                       ((cfg->cfg.embed_pkt.free_buf_pool[2].b_pool <<
 645                         DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(2)) &
 646                        DMA_CH_RX_EMBED_FBP_PNUM_MASK(2)) |
 647                       ((cfg->cfg.embed_pkt.free_buf_pool[2].b_mgr <<
 648                         DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(2)) &
 649                        DMA_CH_RX_EMBED_FBP_BMGR_MASK(2)) |
 650                       ((cfg->cfg.embed_pkt.free_buf_pool[3].b_pool <<
 651                         DMA_CH_RX_EMBED_FBP_PNUM_SHIFT(3)) &
 652                        DMA_CH_RX_EMBED_FBP_PNUM_MASK(3)) |
 653                       ((cfg->cfg.embed_pkt.free_buf_pool[3].b_mgr <<
 654                         DMA_CH_RX_EMBED_FBP_BMGR_SHIFT(3)) &
 655                        DMA_CH_RX_EMBED_FBP_BMGR_MASK(3));
 656
 657                 __raw_writel(val, base + DMA_CH_RX_EMBED_PKT_CFG_REG_A(0));
 658                 DBG("Rx channel embedded packet configuration A @ %p, "
 659                     "value written: %x\n",
 660                     base + DMA_CH_RX_EMBED_PKT_CFG_REG_A(0), val);
 661                 break;
 662         case DMA_CH_RX_DEFAULT_DESC_HOST:
 663                 val = ((cfg->cfg.host_pkt.fdb_queue[0].q_num <<
 664                         DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(0)) &
 665                        DMA_CH_RX_HOST_FDQ_QNUM_MASK(0)) |
 666                       ((cfg->cfg.host_pkt.fdb_queue[0].q_mgr <<
 667                         DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(0)) &
 668                        DMA_CH_RX_HOST_FDQ_QMGR_MASK(0)) |
 669                       ((cfg->cfg.host_pkt.fdb_queue[1].q_num <<
 670                         DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(1)) &
 671                        DMA_CH_RX_HOST_FDQ_QNUM_MASK(1)) |
 672                       ((cfg->cfg.host_pkt.fdb_queue[1].q_mgr <<
 673                         DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(1)) &
 674                        DMA_CH_RX_HOST_FDQ_QMGR_MASK(1));
 675
 676                 __raw_writel(val, base + DMA_CH_RX_HOST_PKT_CFG_REG_A(0));
 677                 DBG("Rx channel host packet configuration A @ %p, "
 678                     "value written: %x\n",
 679                     base + DMA_CH_RX_HOST_PKT_CFG_REG_A(0), val);
 680
 681                 val = ((cfg->cfg.host_pkt.fdb_queue[2].q_num <<
 682                         DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(2)) &
 683                        DMA_CH_RX_HOST_FDQ_QNUM_MASK(2)) |
 684                       ((cfg->cfg.host_pkt.fdb_queue[2].q_mgr <<
 685                         DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(2)) &
 686                        DMA_CH_RX_HOST_FDQ_QMGR_MASK(2)) |
 687                       ((cfg->cfg.host_pkt.fdb_queue[3].q_num <<
 688                        DMA_CH_RX_HOST_FDQ_QNUM_SHIFT(3)) &
 689                        DMA_CH_RX_HOST_FDQ_QNUM_MASK(3)) |
 690                       ((cfg->cfg.host_pkt.fdb_queue[3].q_mgr <<
 691                         DMA_CH_RX_HOST_FDQ_QMGR_SHIFT(3)) &
 692                        DMA_CH_RX_HOST_FDQ_QMGR_MASK(3));
 693
 694                 __raw_writel(val, base + DMA_CH_RX_HOST_PKT_CFG_REG_B(0));
 695                 DBG("Rx channel host packet configuration B @ %p, "
 696                     "value written: %x\n",
 697                     base + DMA_CH_RX_HOST_PKT_CFG_REG_B(0), val);
 698                 break;
 699         case DMA_CH_RX_DEFAULT_DESC_MONO:
 700                 val = ((cfg->cfg.mono_pkt.fd_queue.q_num <<
 701                         DMA_CH_RX_MONO_FDQ_QNUM_SHIFT) &
 702                        DMA_CH_RX_MONO_FDQ_QNUM_MASK) |
 703                       ((cfg->cfg.mono_pkt.fd_queue.q_mgr <<
 704                         DMA_CH_RX_MONO_FDQ_QMGR_SHIFT) &
 705                        DMA_CH_RX_MONO_FDQ_QMGR_MASK) |
 706                       ((cfg->cfg.mono_pkt.sop_offset <<
 707                         DMA_CH_RX_MONO_SOP_OFFSET_SHIFT) &
 708                        DMA_CH_RX_MONO_SOP_OFFSET_MASK);
 709
 710                 __raw_writel(val, base + DMA_CH_RX_MONO_PKT_CFG_REG(0));
 711                 DBG("Rx channel monolithic packet configuration @ %p, "
 712                     "value written: %x\n",
 713                     base + DMA_CH_RX_MONO_PKT_CFG_REG(0), val);
 714                 break;
 715         }
 716 }
 717 EXPORT_SYMBOL(cppi41_rx_ch_configure);
 718
 719 void cppi41_rx_ch_set_maxbufcnt(struct cppi41_dma_ch_obj *rx_ch_obj,
 720                             u8 rx_max_buf_cnt)
 721 {
 722         void __iomem *base = rx_ch_obj->base_addr;
 723         u32 val = __raw_readl(rx_ch_obj->base_addr);
 724
 725         val = rx_ch_obj->global_cfg;
 726         val &= ~(0x7 << DMA_CH_RX_MAX_BUF_CNT_SHIFT);
 727         val |= (rx_max_buf_cnt << DMA_CH_RX_MAX_BUF_CNT_SHIFT);
 728
 729         rx_ch_obj->global_cfg = val;
 730         __raw_writel(val, base);
 731
 732         DBG("%s: rx-global-cfg @ %p, value written: %x, "
 733             "value read: %x\n", __func__, base, val, __raw_readl(base));
 734
 735 }
 736 EXPORT_SYMBOL(cppi41_rx_ch_set_maxbufcnt);
 737 /*
 738  * cppi41_dma_ch_teardown - teardown a given Tx/Rx channel
 739  */
 740 void cppi41_dma_ch_teardown(struct cppi41_dma_ch_obj *dma_ch_obj)
 741 {
 742         u32 val = __raw_readl(dma_ch_obj->base_addr);
 743
 744         /* Initiate channel teardown. */
 745         val |= dma_ch_obj->global_cfg & ~DMA_CH_TX_ENABLE_MASK;
 746         dma_ch_obj->global_cfg = val |= DMA_CH_TX_TEARDOWN_MASK;
 747         __raw_writel(val, dma_ch_obj->base_addr);
 748         DBG("Tear down channel @ %p, value written: %x, value read: %x\n",
 749             dma_ch_obj->base_addr, val, __raw_readl(dma_ch_obj->base_addr));
 750 }
 751 EXPORT_SYMBOL(cppi41_dma_ch_teardown);
 752
 753 /*
 754  * cppi41_dma_ch_enable - enable Tx/Rx DMA channel in hardware
 755  *
 756  * Makes the channel ready for data transmission/reception.
 757  */
 758 void cppi41_dma_ch_enable(struct cppi41_dma_ch_obj *dma_ch_obj)
 759 {
 760         u32 val = dma_ch_obj->global_cfg | DMA_CH_TX_ENABLE_MASK;
 761
 762         /* Teardown bit remains set after completion, so clear it now... */
 763         dma_ch_obj->global_cfg = val &= ~DMA_CH_TX_TEARDOWN_MASK;
 764         __raw_writel(val, dma_ch_obj->base_addr);
 765         DBG("Enable channel @ %p, value written: %x, value read: %x\n",
 766             dma_ch_obj->base_addr, val, __raw_readl(dma_ch_obj->base_addr));
 767 }
 768 EXPORT_SYMBOL(cppi41_dma_ch_enable);
 769
 770 /*
 771  * cppi41_dma_ch_disable - disable Tx/Rx DMA channel in hardware
 772  */
 773 void cppi41_dma_ch_disable(struct cppi41_dma_ch_obj *dma_ch_obj)
 774 {
 775         dma_ch_obj->global_cfg &= ~DMA_CH_TX_ENABLE_MASK;
 776         __raw_writel(dma_ch_obj->global_cfg, dma_ch_obj->base_addr);
 777         DBG("Disable channel @ %p, value written: %x, value read: %x\n",
 778             dma_ch_obj->base_addr, dma_ch_obj->global_cfg,
 779             __raw_readl(dma_ch_obj->base_addr));
 780 }
 781 EXPORT_SYMBOL(cppi41_dma_ch_disable);
 782
 783 void cppi41_free_teardown_queue(int dma_num)
 784 {
 785         unsigned long td_addr;
 786         u32 num_desc = dma_teardown[dma_num].num_desc;
 787
 788         while (num_desc--) {
 789                 td_addr = cppi41_queue_pop(&dma_teardown[dma_num].queue_obj);
 790
 791                 if (td_addr == 0)
 792                         break;
 793         }
 794 }
 795 EXPORT_SYMBOL(cppi41_free_teardown_queue);
 796
 797 /**
 798  * alloc_queue - allocate a queue in the given range
 799  * @allocated:  pointer to the bitmap of the allocated queues
 800  * @excluded:   pointer to the bitmap of the queues excluded from allocation
 801  *              (optional)
 802  * @start:      starting queue number
 803  * @count:      number of queues available
 804  *
 805  * Returns queue number on success, -ENOSPC otherwise.
 806  */
 807 static int alloc_queue(u32 *allocated, const u32 *excluded, unsigned start,
 808                        unsigned count)
 809 {
 810         u32 bit, mask = 0;
 811         int index = -1;
 812
 813         /*
 814          * We're starting the loop as if we've just wrapped around 32 bits
 815          * in order to save on preloading the bitmasks.
 816          */
 817         for (bit = 0; count--; start++, bit <<= 1) {
 818                 /* Have we just wrapped around 32 bits? */
 819                 if (!bit) {
 820                         /* Start over with the next bitmask word */
 821                         bit = 1;
 822                         index++;
 823                         /* Have we just entered the loop? */
 824                         if (!index) {
 825                                 /* Calculate the starting values */
 826                                 bit <<= start & 0x1f;
 827                                 index = start >> 5;
 828                         }
 829                         /*
 830                          * Load the next word of the allocated bitmask OR'ing
 831                          * it with the excluded bitmask if it's been passed.
 832                          */
 833                         mask = allocated[index];
 834                         if (excluded != NULL)
 835                                 mask |= excluded[index];
 836                 }
 837                 /*
 838                  * If the bit in the combined bitmask is zero,
 839                  * we've just found a free queue.
 840                  */
 841                 if (!(mask & bit)) {
 842                         allocated[index] |= bit;
 843                         return start;
 844                 }
 845         }
 846         return -ENOSPC;
 847 }
 848
 849 /*
 850  * cppi41_queue_alloc - allocate a queue of a given type in the queue manager
 851  */
 852 int cppi41_queue_alloc(u8 type, u8 q_mgr, u16 *q_num)
 853 {
 854         int res = -ENOSPC;
 855
 856         if (q_mgr >= cppi41_num_queue_mgr)
 857                 return -EINVAL;
 858
 859         /* Mask out the unsupported queue types */
 860         type &= cppi41_queue_mgr[q_mgr].queue_types;
 861         /* First see if a free descriptor queue was requested... */
 862         if (type & CPPI41_FREE_DESC_QUEUE)
 863                 res = alloc_queue(allocated_queues[q_mgr], NULL,
 864                                   cppi41_queue_mgr[q_mgr].base_fdq_num,  16);
 865
 866         /* Then see if a free descriptor/buffer queue was requested... */
 867         if (res < 0 && (type & CPPI41_FREE_DESC_BUF_QUEUE))
 868                 res = alloc_queue(allocated_queues[q_mgr], NULL,
 869                                   cppi41_queue_mgr[q_mgr].base_fdbq_num, 16);
 870
 871         /* Last see if an unassigned queue was requested... */
 872         if (res < 0 && (type & CPPI41_UNASSIGNED_QUEUE))
 873                 res = alloc_queue(allocated_queues[q_mgr],
 874                                   cppi41_queue_mgr[q_mgr].assigned, 0,
 875                                   cppi41_queue_mgr[q_mgr].num_queue);
 876
 877         /* See if any queue was allocated... */
 878         if (res < 0)
 879                 return res;
 880
 881         /* Return the queue allocated */
 882         *q_num = res;
 883         return 0;
 884 }
 885 EXPORT_SYMBOL(cppi41_queue_alloc);
 886
 887 /*
 888  * cppi41_queue_free - free the given queue in the queue manager
 889  */
 890 int cppi41_queue_free(u8 q_mgr, u16 q_num)
 891 {
 892         int index = q_num >> 5, bit = 1 << (q_num & 0x1f);
 893
 894         if (allocated_queues[q_mgr] != NULL) {
 895                 if (q_mgr >= cppi41_num_queue_mgr ||
 896                     q_num >= cppi41_queue_mgr[q_mgr].num_queue ||
 897                     !(allocated_queues[q_mgr][index] & bit))
 898                         return -EINVAL;
 899                 allocated_queues[q_mgr][index] &= ~bit;
 900         }
 901         return 0;
 902 }
 903 EXPORT_SYMBOL(cppi41_queue_free);
 904
 905 /*
 906  * cppi41_queue_init - initialize a CPPI 4.1 queue object
 907  */
 908 int cppi41_queue_init(struct cppi41_queue_obj *queue_obj, u8 q_mgr, u16 q_num)
 909 {
 910         if (q_mgr >= cppi41_num_queue_mgr ||
 911             q_num >= cppi41_queue_mgr[q_mgr].num_queue)
 912                 return -EINVAL;
 913
 914         queue_obj->base_addr = cppi41_queue_mgr[q_mgr].q_mgmt_rgn_base +
 915                                QMGR_QUEUE_STATUS_REG_A(q_num);
 916
 917         return 0;
 918 }
 919 EXPORT_SYMBOL(cppi41_queue_init);
 920
 921 /*
 922  * cppi41_queue_push - push a descriptor into the given queue
 923  */
 924 void cppi41_queue_push(const struct cppi41_queue_obj *queue_obj, u32 desc_addr,
 925                        u32 desc_size, u32 pkt_size)
 926 {
 927         u32 val;
 928
 929         /*
 930          * Write to the tail of the queue.
 931          * TODO: Can't think of a reason why a queue to head may be required.
 932          * If it is, the API may have to be extended.
 933          */
 934 #if 0
 935         /*
 936          * Also, can't understand why packet size is required to queue up a
 937          * descriptor. The spec says packet size *must* be written prior to
 938          * the packet write operation.
 939          */
 940         if (pkt_size)
 941                 val = (pkt_size << QMGR_QUEUE_PKT_SIZE_SHIFT) &
 942                       QMGR_QUEUE_PKT_SIZE_MASK;
 943         __raw_writel(val, queue_obj->base_addr + QMGR_QUEUE_REG_C(0));
 944 #endif
 945
 946         val = (((desc_size - 24) >> (2 - QMGR_QUEUE_DESC_SIZE_SHIFT)) &
 947                QMGR_QUEUE_DESC_SIZE_MASK) |
 948               (desc_addr & QMGR_QUEUE_DESC_PTR_MASK);
 949
 950         DBG("Pushing value %x to queue @ %p\n", val, queue_obj->base_addr);
 951
 952         __raw_writel(val, queue_obj->base_addr + QMGR_QUEUE_REG_D(0));
 953 }
 954 EXPORT_SYMBOL(cppi41_queue_push);
 955
 956 /*
 957  * cppi41_queue_pop - pop a descriptor from a given queue
 958  */
 959 unsigned long cppi41_queue_pop(const struct cppi41_queue_obj *queue_obj)
 960 {
 961         u32 val = __raw_readl(queue_obj->base_addr + QMGR_QUEUE_REG_D(0));
 962
 963         DBG("Popping value %x from queue @ %p\n", val, queue_obj->base_addr);
 964
 965         return val & QMGR_QUEUE_DESC_PTR_MASK;
 966 }
 967 EXPORT_SYMBOL(cppi41_queue_pop);
 968
 969 /*
 970  * cppi41_get_teardown_info - extract information from a teardown descriptor
 971  */
 972 int cppi41_get_teardown_info(unsigned long addr, u32 *info)
 973 {
 974         struct cppi41_teardown_desc *desc;
 975         int dma_num;
 976
 977         for (dma_num = 0; dma_num < cppi41_num_dma_block; dma_num++)
 978                 if (addr >= dma_teardown[dma_num].phys_addr &&
 979                     addr <  dma_teardown[dma_num].phys_addr +
 980                             dma_teardown[dma_num].rgn_size)
 981                         break;
 982
 983         if (dma_num == cppi41_num_dma_block)
 984                 return -EINVAL;
 985
 986         desc = addr - dma_teardown[dma_num].phys_addr +
 987                dma_teardown[dma_num].virt_addr;
 988
 989         if ((desc->teardown_info & CPPI41_DESC_TYPE_MASK) !=
 990             (CPPI41_DESC_TYPE_TEARDOWN << CPPI41_DESC_TYPE_SHIFT))
 991                 return -EINVAL;
 992
 993         *info = desc->teardown_info;
 994 #if 1
 995         /* Hardware is not giving the current DMA number as of now. :-/ */
 996         *info |= (dma_num << CPPI41_TEARDOWN_DMA_NUM_SHIFT) &
 997                  CPPI41_TEARDOWN_DMA_NUM_MASK;
 998 #else
 999         dma_num = (desc->teardown_info & CPPI41_TEARDOWN_DMA_NUM_MASK) >>
1000                  CPPI41_TEARDOWN_DMA_NUM_SHIFT;
1001 #endif
1002
1003         cppi41_queue_push(&dma_teardown[dma_num].queue_obj, addr,
1004                           sizeof(struct cppi41_teardown_desc), 0);
1005
1006         return 0;
1007 }
1008 EXPORT_SYMBOL(cppi41_get_teardown_info);
1009
1010 MODULE_DESCRIPTION("TI CPPI 4.1 support");
1011 MODULE_AUTHOR("MontaVista Software");
1012 MODULE_LICENSE("GPL");