1 /*
2 * Copyright (C) 2005-2006 by Texas Instruments
3 * Copyright (c) 2008, MontaVista Software, Inc. <source@mvista.com>
4 *
5 * This file implements a DMA interface using TI's CPPI 4.1 DMA.
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 */
22 #include <linux/errno.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/module.h>
26 #include "cppi41.h"
28 #include "musb_core.h"
29 #include "musb_dma.h"
30 #include "cppi41_dma.h"
32 /* Configuration */
33 #define USB_CPPI41_DESC_SIZE_SHIFT 6
34 #define USB_CPPI41_DESC_ALIGN (1 << USB_CPPI41_DESC_SIZE_SHIFT)
35 #define USB_CPPI41_CH_NUM_PD 64 /* 4K bulk data at full speed */
36 #define USB_CPPI41_MAX_PD (USB_CPPI41_CH_NUM_PD * USB_CPPI41_NUM_CH)
38 #undef DEBUG_CPPI_TD
39 #undef USBDRV_DEBUG
41 #ifdef USBDRV_DEBUG
42 #define dprintk(x, ...) printk(x, ## __VA_ARGS__)
43 #else
44 #define dprintk(x, ...)
45 #endif
47 /*
48 * Data structure definitions
49 */
51 /*
52 * USB Packet Descriptor
53 */
54 struct usb_pkt_desc;
56 struct usb_pkt_desc {
57 /* Hardware descriptor fields from this point */
58 struct cppi41_host_pkt_desc hw_desc;
59 /* Protocol specific data */
60 dma_addr_t dma_addr;
61 struct usb_pkt_desc *next_pd_ptr;
62 u8 ch_num;
63 u8 ep_num;
64 };
66 /**
67 * struct cppi41_channel - DMA Channel Control Structure
68 *
69 * Using the same for Tx/Rx.
70 */
71 struct cppi41_channel {
72 struct dma_channel channel;
74 struct cppi41_dma_ch_obj dma_ch_obj; /* DMA channel object */
75 struct cppi41_queue src_queue; /* Tx queue or Rx free descriptor/ */
76 /* buffer queue */
77 struct cppi41_queue_obj queue_obj; /* Tx queue object or Rx free */
78 /* descriptor/buffer queue object */
80 u32 tag_info; /* Tx PD Tag Information field */
82 /* Which direction of which endpoint? */
83 struct musb_hw_ep *end_pt;
84 u8 transmit;
85 u8 ch_num; /* Channel number of Tx/Rx 0..3 */
87 /* DMA mode: "transparent", RNDIS, CDC, or Generic RNDIS */
88 u8 dma_mode;
89 u8 autoreq;
91 /* Book keeping for the current transfer request */
92 dma_addr_t start_addr;
93 u32 length;
94 u32 curr_offset;
95 u16 pkt_size;
96 u8 transfer_mode;
97 u8 zlp_queued;
98 };
100 /**
101 * struct cppi41 - CPPI 4.1 DMA Controller Object
102 *
103 * Encapsulates all book keeping and data structures pertaining to
104 * the CPPI 1.4 DMA controller.
105 */
106 struct cppi41 {
107 struct dma_controller controller;
108 struct musb *musb;
110 struct cppi41_channel tx_cppi_ch[USB_CPPI41_NUM_CH];
111 struct cppi41_channel rx_cppi_ch[USB_CPPI41_NUM_CH];
113 struct usb_pkt_desc *pd_pool_head; /* Free PD pool head */
114 dma_addr_t pd_mem_phys; /* PD memory physical address */
115 void *pd_mem; /* PD memory pointer */
116 u8 pd_mem_rgn; /* PD memory region number */
118 u16 teardownQNum; /* Teardown completion queue number */
119 struct cppi41_queue_obj queue_obj; /* Teardown completion queue */
120 /* object */
121 u32 pkt_info; /* Tx PD Packet Information field */
122 };
124 #ifdef DEBUG_CPPI_TD
125 static void print_pd_list(struct usb_pkt_desc *pd_pool_head)
126 {
127 struct usb_pkt_desc *curr_pd = pd_pool_head;
128 int cnt = 0;
130 while (curr_pd != NULL) {
131 if (cnt % 8 == 0)
132 dprintk("\n%02x ", cnt);
133 cnt++;
134 dprintk(" %p", curr_pd);
135 curr_pd = curr_pd->next_pd_ptr;
136 }
137 dprintk("\n");
138 }
139 #endif
141 static struct usb_pkt_desc *usb_get_free_pd(struct cppi41 *cppi)
142 {
143 struct usb_pkt_desc *free_pd = cppi->pd_pool_head;
145 if (free_pd != NULL) {
146 cppi->pd_pool_head = free_pd->next_pd_ptr;
147 free_pd->next_pd_ptr = NULL;
148 }
149 return free_pd;
150 }
152 static void usb_put_free_pd(struct cppi41 *cppi, struct usb_pkt_desc *free_pd)
153 {
154 free_pd->next_pd_ptr = cppi->pd_pool_head;
155 cppi->pd_pool_head = free_pd;
156 }
158 /**
159 * cppi41_controller_start - start DMA controller
160 * @controller: the controller
161 *
162 * This function initializes the CPPI 4.1 Tx/Rx channels.
163 */
164 static int __devinit cppi41_controller_start(struct dma_controller *controller)
165 {
166 struct cppi41 *cppi;
167 struct cppi41_channel *cppi_ch;
168 void __iomem *reg_base;
169 struct usb_pkt_desc *curr_pd;
170 unsigned long pd_addr;
171 int i;
173 cppi = container_of(controller, struct cppi41, controller);
175 /*
176 * TODO: We may need to check USB_CPPI41_MAX_PD here since CPPI 4.1
177 * requires the descriptor count to be a multiple of 2 ^ 5 (i.e. 32).
178 * Similarly, the descriptor size should also be a multiple of 32.
179 */
181 /*
182 * Allocate free packet descriptor pool for all Tx/Rx endpoints --
183 * dma_alloc_coherent() will return a page aligned address, so our
184 * alignment requirement will be honored.
185 */
186 cppi->pd_mem = dma_alloc_coherent(cppi->musb->controller,
187 USB_CPPI41_MAX_PD *
188 USB_CPPI41_DESC_ALIGN,
189 &cppi->pd_mem_phys,
190 GFP_KERNEL | GFP_DMA);
191 if (cppi->pd_mem == NULL) {
192 DBG(1, "ERROR: packet descriptor memory allocation failed\n");
193 return 0;
194 }
195 if (cppi41_mem_rgn_alloc(usb_cppi41_info.q_mgr, cppi->pd_mem_phys,
196 USB_CPPI41_DESC_SIZE_SHIFT,
197 get_count_order(USB_CPPI41_MAX_PD),
198 &cppi->pd_mem_rgn)) {
199 DBG(1, "ERROR: queue manager memory region allocation "
200 "failed\n");
201 goto free_pds;
202 }
204 /* Allocate the teardown completion queue */
205 if (cppi41_queue_alloc(CPPI41_UNASSIGNED_QUEUE,
206 0, &cppi->teardownQNum)) {
207 DBG(1, "ERROR: teardown completion queue allocation failed\n");
208 goto free_mem_rgn;
209 }
210 DBG(4, "Allocated teardown completion queue %d in queue manager 0\n",
211 cppi->teardownQNum);
213 if (cppi41_queue_init(&cppi->queue_obj, 0, cppi->teardownQNum)) {
214 DBG(1, "ERROR: teardown completion queue initialization "
215 "failed\n");
216 goto free_queue;
217 }
219 /*
220 * "Slice" PDs one-by-one from the big chunk and
221 * add them to the free pool.
222 */
223 curr_pd = (struct usb_pkt_desc *)cppi->pd_mem;
224 pd_addr = cppi->pd_mem_phys;
225 for (i = 0; i < USB_CPPI41_MAX_PD; i++) {
226 curr_pd->dma_addr = pd_addr;
228 usb_put_free_pd(cppi, curr_pd);
229 curr_pd = (struct usb_pkt_desc *)((char *)curr_pd +
230 USB_CPPI41_DESC_ALIGN);
231 pd_addr += USB_CPPI41_DESC_ALIGN;
232 }
234 /* Configure the Tx channels */
235 for (i = 0, cppi_ch = cppi->tx_cppi_ch;
236 i < ARRAY_SIZE(cppi->tx_cppi_ch); ++i, ++cppi_ch) {
237 const struct cppi41_tx_ch *tx_info;
239 memset(cppi_ch, 0, sizeof(struct cppi41_channel));
240 cppi_ch->transmit = 1;
241 cppi_ch->ch_num = i;
242 cppi_ch->channel.private_data = cppi;
244 /*
245 * Extract the CPPI 4.1 DMA Tx channel configuration and
246 * construct/store the Tx PD tag info field for later use...
247 */
248 tx_info = cppi41_dma_block[usb_cppi41_info.dma_block].tx_ch_info
249 + usb_cppi41_info.ep_dma_ch[i];
250 cppi_ch->src_queue = tx_info->tx_queue[0];
251 cppi_ch->tag_info = (tx_info->port_num <<
252 CPPI41_SRC_TAG_PORT_NUM_SHIFT) |
253 (tx_info->ch_num <<
254 CPPI41_SRC_TAG_CH_NUM_SHIFT) |
255 (tx_info->sub_ch_num <<
256 CPPI41_SRC_TAG_SUB_CH_NUM_SHIFT);
257 }
259 /* Configure the Rx channels */
260 for (i = 0, cppi_ch = cppi->rx_cppi_ch;
261 i < ARRAY_SIZE(cppi->rx_cppi_ch); ++i, ++cppi_ch) {
262 memset(cppi_ch, 0, sizeof(struct cppi41_channel));
263 cppi_ch->ch_num = i;
264 cppi_ch->channel.private_data = cppi;
265 }
267 /* Construct/store Tx PD packet info field for later use */
268 cppi->pkt_info = (CPPI41_PKT_TYPE_USB << CPPI41_PKT_TYPE_SHIFT) |
269 (CPPI41_RETURN_LINKED << CPPI41_RETURN_POLICY_SHIFT) |
270 (usb_cppi41_info.q_mgr << CPPI41_RETURN_QMGR_SHIFT) |
271 (usb_cppi41_info.tx_comp_q[0] <<
272 CPPI41_RETURN_QNUM_SHIFT);
274 /* Do necessary configuartion in hardware to get started */
275 reg_base = cppi->musb->ctrl_base;
277 /* Disable auto request mode */
278 musb_writel(reg_base, USB_AUTOREQ_REG, 0);
280 /* Disable the CDC/RNDIS modes */
281 musb_writel(reg_base, USB_MODE_REG, 0);
283 return 1;
285 free_queue:
286 if (cppi41_queue_free(0, cppi->teardownQNum))
287 DBG(1, "ERROR: failed to free teardown completion queue\n");
289 free_mem_rgn:
290 if (cppi41_mem_rgn_free(usb_cppi41_info.q_mgr, cppi->pd_mem_rgn))
291 DBG(1, "ERROR: failed to free queue manager memory region\n");
293 free_pds:
294 dma_free_coherent(cppi->musb->controller,
295 USB_CPPI41_MAX_PD * USB_CPPI41_DESC_ALIGN,
296 cppi->pd_mem, cppi->pd_mem_phys);
298 return 0;
299 }
301 /**
302 * cppi41_controller_stop - stop DMA controller
303 * @controller: the controller
304 *
305 * De-initialize the DMA Controller as necessary.
306 */
307 static int cppi41_controller_stop(struct dma_controller *controller)
308 {
309 struct cppi41 *cppi;
310 void __iomem *reg_base;
312 cppi = container_of(controller, struct cppi41, controller);
314 /* Free the teardown completion queue */
315 if (cppi41_queue_free(usb_cppi41_info.q_mgr, cppi->teardownQNum))
316 DBG(1, "ERROR: failed to free teardown completion queue\n");
318 /*
319 * Free the packet descriptor region allocated
320 * for all Tx/Rx channels.
321 */
322 if (cppi41_mem_rgn_free(usb_cppi41_info.q_mgr, cppi->pd_mem_rgn))
323 DBG(1, "ERROR: failed to free queue manager memory region\n");
325 dma_free_coherent(cppi->musb->controller,
326 USB_CPPI41_MAX_PD * USB_CPPI41_DESC_ALIGN,
327 cppi->pd_mem, cppi->pd_mem_phys);
329 reg_base = cppi->musb->ctrl_base;
331 /* Disable auto request mode */
332 musb_writel(reg_base, USB_AUTOREQ_REG, 0);
334 /* Disable the CDC/RNDIS modes */
335 musb_writel(reg_base, USB_MODE_REG, 0);
337 return 1;
338 }
340 /**
341 * cppi41_channel_alloc - allocate a CPPI channel for DMA.
342 * @controller: the controller
343 * @ep: the endpoint
344 * @is_tx: 1 for Tx channel, 0 for Rx channel
345 *
346 * With CPPI, channels are bound to each transfer direction of a non-control
347 * endpoint, so allocating (and deallocating) is mostly a way to notice bad
348 * housekeeping on the software side. We assume the IRQs are always active.
349 */
350 static struct dma_channel *cppi41_channel_alloc(struct dma_controller
351 *controller,
352 struct musb_hw_ep *ep, u8 is_tx)
353 {
354 struct cppi41 *cppi;
355 struct cppi41_channel *cppi_ch;
356 u32 ch_num, ep_num = ep->epnum;
358 cppi = container_of(controller, struct cppi41, controller);
360 /* Remember, ep_num: 1 .. Max_EP, and CPPI ch_num: 0 .. Max_EP - 1 */
361 ch_num = ep_num - 1;
363 if (ep_num > USB_CPPI41_NUM_CH) {
364 DBG(1, "No %cx DMA channel for EP%d\n",
365 is_tx ? 'T' : 'R', ep_num);
366 return NULL;
367 }
369 cppi_ch = (is_tx ? cppi->tx_cppi_ch : cppi->rx_cppi_ch) + ch_num;
371 /* As of now, just return the corresponding CPPI 4.1 channel handle */
372 if (is_tx) {
373 /* Initialize the CPPI 4.1 Tx DMA channel */
374 if (cppi41_tx_ch_init(&cppi_ch->dma_ch_obj,
375 usb_cppi41_info.dma_block,
376 usb_cppi41_info.ep_dma_ch[ch_num])) {
377 DBG(1, "ERROR: cppi41_tx_ch_init failed for "
378 "channel %d\n", ch_num);
379 return NULL;
380 }
381 /*
382 * Teardown descriptors will be pushed to the dedicated
383 * completion queue.
384 */
385 cppi41_dma_ch_default_queue(&cppi_ch->dma_ch_obj,
386 0, cppi->teardownQNum);
387 } else {
388 struct cppi41_rx_ch_cfg rx_cfg;
389 u8 q_mgr = usb_cppi41_info.q_mgr;
390 int i;
392 /* Initialize the CPPI 4.1 Rx DMA channel */
393 if (cppi41_rx_ch_init(&cppi_ch->dma_ch_obj,
394 usb_cppi41_info.dma_block,
395 usb_cppi41_info.ep_dma_ch[ch_num])) {
396 DBG(1, "ERROR: cppi41_rx_ch_init failed\n");
397 return NULL;
398 }
400 if (cppi41_queue_alloc(CPPI41_FREE_DESC_BUF_QUEUE |
401 CPPI41_UNASSIGNED_QUEUE,
402 q_mgr, &cppi_ch->src_queue.q_num)) {
403 DBG(1, "ERROR: cppi41_queue_alloc failed for "
404 "free descriptor/buffer queue\n");
405 return NULL;
406 }
407 DBG(4, "Allocated free descriptor/buffer queue %d in "
408 "queue manager %d\n", cppi_ch->src_queue.q_num, q_mgr);
410 rx_cfg.default_desc_type = cppi41_rx_host_desc;
411 rx_cfg.sop_offset = 0;
412 rx_cfg.retry_starved = 1;
413 rx_cfg.rx_queue.q_mgr = cppi_ch->src_queue.q_mgr = q_mgr;
414 rx_cfg.rx_queue.q_num = usb_cppi41_info.rx_comp_q[0];
415 for (i = 0; i < 4; i++)
416 rx_cfg.cfg.host_pkt.fdb_queue[i] = cppi_ch->src_queue;
417 cppi41_rx_ch_configure(&cppi_ch->dma_ch_obj, &rx_cfg);
418 }
420 /* Initialize the CPPI 4.1 DMA source queue */
421 if (cppi41_queue_init(&cppi_ch->queue_obj, cppi_ch->src_queue.q_mgr,
422 cppi_ch->src_queue.q_num)) {
423 DBG(1, "ERROR: cppi41_queue_init failed for %s queue",
424 is_tx ? "Tx" : "Rx free descriptor/buffer");
425 if (is_tx == 0 &&
426 cppi41_queue_free(cppi_ch->src_queue.q_mgr,
427 cppi_ch->src_queue.q_num))
428 DBG(1, "ERROR: failed to free Rx descriptor/buffer "
429 "queue\n");
430 return NULL;
431 }
433 /* Enable the DMA channel */
434 cppi41_dma_ch_enable(&cppi_ch->dma_ch_obj);
436 if (cppi_ch->end_pt)
437 DBG(1, "Re-allocating DMA %cx channel %d (%p)\n",
438 is_tx ? 'T' : 'R', ch_num, cppi_ch);
440 cppi_ch->end_pt = ep;
441 cppi_ch->ch_num = ch_num;
442 cppi_ch->channel.status = MUSB_DMA_STATUS_FREE;
443 cppi_ch->channel.max_len = is_tx ?
444 CPPI41_TXDMA_MAXLEN : CPPI41_RXDMA_MAXLEN;
446 DBG(4, "Allocated DMA %cx channel %d for EP%d\n", is_tx ? 'T' : 'R',
447 ch_num, ep_num);
449 return &cppi_ch->channel;
450 }
452 /**
453 * cppi41_channel_release - release a CPPI DMA channel
454 * @channel: the channel
455 */
456 static void cppi41_channel_release(struct dma_channel *channel)
457 {
458 struct cppi41_channel *cppi_ch;
460 /* REVISIT: for paranoia, check state and abort if needed... */
461 cppi_ch = container_of(channel, struct cppi41_channel, channel);
462 if (cppi_ch->end_pt == NULL)
463 DBG(1, "Releasing idle DMA channel %p\n", cppi_ch);
465 /* But for now, not its IRQ */
466 cppi_ch->end_pt = NULL;
467 channel->status = MUSB_DMA_STATUS_UNKNOWN;
469 cppi41_dma_ch_disable(&cppi_ch->dma_ch_obj);
471 /* De-allocate Rx free descriptior/buffer queue */
472 if (cppi_ch->transmit == 0 &&
473 cppi41_queue_free(cppi_ch->src_queue.q_mgr,
474 cppi_ch->src_queue.q_num))
475 DBG(1, "ERROR: failed to free Rx descriptor/buffer queue\n");
476 }
478 static void cppi41_mode_update(struct cppi41_channel *cppi_ch, u8 mode)
479 {
480 if (mode != cppi_ch->dma_mode) {
481 struct cppi41 *cppi = cppi_ch->channel.private_data;
482 void *__iomem reg_base = cppi->musb->ctrl_base;
483 u32 reg_val = musb_readl(reg_base, USB_MODE_REG);
484 u8 ep_num = cppi_ch->ch_num + 1;
486 if (cppi_ch->transmit) {
487 reg_val &= ~USB_TX_MODE_MASK(ep_num);
488 reg_val |= mode << USB_TX_MODE_SHIFT(ep_num);
489 } else {
490 reg_val &= ~USB_RX_MODE_MASK(ep_num);
491 reg_val |= mode << USB_RX_MODE_SHIFT(ep_num);
492 }
493 musb_writel(reg_base, USB_MODE_REG, reg_val);
494 cppi_ch->dma_mode = mode;
495 }
496 }
498 /*
499 * CPPI 4.1 Tx:
500 * ============
501 * Tx is a lot more reasonable than Rx: RNDIS mode seems to behave well except
502 * how it handles the exactly-N-packets case. It appears that there's a hiccup
503 * in that case (maybe the DMA completes before a ZLP gets written?) boiling
504 * down to not being able to rely on the XFER DMA writing any terminating zero
505 * length packet before the next transfer is started...
506 *
507 * The generic RNDIS mode does not have this misfeature, so we prefer using it
508 * instead. We then send the terminating ZLP *explictly* using DMA instead of
509 * doing it by PIO after an IRQ.
510 *
511 */
513 /**
514 * cppi41_next_tx_segment - DMA write for the next chunk of a buffer
515 * @tx_ch: Tx channel
516 *
517 * Context: controller IRQ-locked
518 */
519 static unsigned cppi41_next_tx_segment(struct cppi41_channel *tx_ch)
520 {
521 struct cppi41 *cppi = tx_ch->channel.private_data;
522 struct usb_pkt_desc *curr_pd;
523 u32 length = tx_ch->length - tx_ch->curr_offset;
524 u32 pkt_size = tx_ch->pkt_size;
525 unsigned num_pds, n;
527 /*
528 * Tx can use the generic RNDIS mode where we can probably fit this
529 * transfer in one PD and one IRQ. The only time we would NOT want
530 * to use it is when the hardware constraints prevent it...
531 */
532 if ((pkt_size & 0x3f) == 0 && length > pkt_size) {
533 num_pds = 1;
534 pkt_size = length;
535 cppi41_mode_update(tx_ch, USB_GENERIC_RNDIS_MODE);
536 } else {
537 num_pds = (length + pkt_size - 1) / pkt_size;
538 cppi41_mode_update(tx_ch, USB_TRANSPARENT_MODE);
539 }
541 /*
542 * If length of transmit buffer is 0 or a multiple of the endpoint size,
543 * then send the zero length packet.
544 */
545 if (!length || (tx_ch->transfer_mode && length % pkt_size == 0))
546 num_pds++;
548 DBG(4, "TX DMA%u, %s, maxpkt %u, %u PDs, addr %#x, len %u\n",
549 tx_ch->ch_num, tx_ch->dma_mode ? "accelerated" : "transparent",
550 pkt_size, num_pds, tx_ch->start_addr + tx_ch->curr_offset, length);
552 for (n = 0; n < num_pds; n++) {
553 struct cppi41_host_pkt_desc *hw_desc;
555 /* Get Tx host packet descriptor from the free pool */
556 curr_pd = usb_get_free_pd(cppi);
557 if (curr_pd == NULL) {
558 DBG(1, "No Tx PDs\n");
559 break;
560 }
562 if (length < pkt_size)
563 pkt_size = length;
565 hw_desc = &curr_pd->hw_desc;
566 hw_desc->desc_info = (CPPI41_DESC_TYPE_HOST <<
567 CPPI41_DESC_TYPE_SHIFT) | pkt_size;
568 hw_desc->tag_info = tx_ch->tag_info;
569 hw_desc->pkt_info = cppi->pkt_info;
571 hw_desc->buf_ptr = tx_ch->start_addr + tx_ch->curr_offset;
572 hw_desc->buf_len = pkt_size;
573 hw_desc->next_desc_ptr = 0;
575 curr_pd->ch_num = tx_ch->ch_num;
576 curr_pd->ep_num = tx_ch->end_pt->epnum;
578 tx_ch->curr_offset += pkt_size;
579 length -= pkt_size;
581 if (pkt_size == 0)
582 tx_ch->zlp_queued = 1;
584 DBG(5, "TX PD %p: buf %08x, len %08x, pkt info %08x\n", curr_pd,
585 hw_desc->buf_ptr, hw_desc->buf_len, hw_desc->pkt_info);
587 cppi41_queue_push(&tx_ch->queue_obj, curr_pd->dma_addr,
588 USB_CPPI41_DESC_ALIGN, pkt_size);
589 }
591 return n;
592 }
594 static void cppi41_autoreq_update(struct cppi41_channel *rx_ch, u8 autoreq)
595 {
596 struct cppi41 *cppi = rx_ch->channel.private_data;
598 if (is_host_active(cppi->musb) &&
599 autoreq != rx_ch->autoreq) {
600 void *__iomem reg_base = cppi->musb->ctrl_base;
601 u32 reg_val = musb_readl(reg_base, USB_AUTOREQ_REG);
602 u8 ep_num = rx_ch->ch_num + 1;
604 reg_val &= ~USB_RX_AUTOREQ_MASK(ep_num);
605 reg_val |= autoreq << USB_RX_AUTOREQ_SHIFT(ep_num);
607 musb_writel(reg_base, USB_AUTOREQ_REG, reg_val);
608 rx_ch->autoreq = autoreq;
609 }
610 }
612 static void cppi41_set_ep_size(struct cppi41_channel *rx_ch, u32 pkt_size)
613 {
614 struct cppi41 *cppi = rx_ch->channel.private_data;
615 void *__iomem reg_base = cppi->musb->ctrl_base;
616 u8 ep_num = rx_ch->ch_num + 1;
618 musb_writel(reg_base, USB_GENERIC_RNDIS_EP_SIZE_REG(ep_num), pkt_size);
619 }
621 /*
622 * CPPI 4.1 Rx:
623 * ============
624 * Consider a 1KB bulk Rx buffer in two scenarios: (a) it's fed two 300 byte
625 * packets back-to-back, and (b) it's fed two 512 byte packets back-to-back.
626 * (Full speed transfers have similar scenarios.)
627 *
628 * The correct behavior for Linux is that (a) fills the buffer with 300 bytes,
629 * and the next packet goes into a buffer that's queued later; while (b) fills
630 * the buffer with 1024 bytes. How to do that with accelerated DMA modes?
631 *
632 * Rx queues in RNDIS mode (one single BD) handle (a) correctly but (b) loses
633 * BADLY because nothing (!) happens when that second packet fills the buffer,
634 * much less when a third one arrives -- which makes it not a "true" RNDIS mode.
635 * In the RNDIS protocol short-packet termination is optional, and it's fine if
636 * the peripherals (not hosts!) pad the messages out to end of buffer. Standard
637 * PCI host controller DMA descriptors implement that mode by default... which
638 * is no accident.
639 *
640 * Generic RNDIS mode is the only way to reliably make both cases work. This
641 * mode is identical to the "normal" RNDIS mode except for the case where the
642 * last packet of the segment matches the max USB packet size -- in this case,
643 * the packet will be closed when a value (0x10000 max) in the Generic RNDIS
644 * EP Size register is reached. This mode will work for the network drivers
645 * (CDC/RNDIS) as well as for the mass storage drivers where there is no short
646 * packet.
647 *
648 * BUT we can only use non-transparent modes when USB packet size is a multiple
649 * of 64 bytes. Let's see what happens when this is not the case...
650 *
651 * Rx queues (2 BDs with 512 bytes each) have converse problems to RNDIS mode:
652 * (b) is handled right but (a) loses badly. DMA doesn't stop after receiving
653 * a short packet and processes both of those PDs; so both packets are loaded
654 * into the buffer (with 212 byte gap between them), and the next buffer queued
655 * will NOT get its 300 bytes of data. Even in the case when there should be
656 * no short packets (URB_SHORT_NOT_OK is set), queueing several packets in the
657 * host mode doesn't win us anything since we have to manually "prod" the Rx
658 * process after each packet is received by setting ReqPkt bit in endpoint's
659 * RXCSR; in the peripheral mode without short packets, queueing could be used
660 * BUT we'll have to *teardown* the channel if a short packet still arrives in
661 * the peripheral mode, and to "collect" the left-over packet descriptors from
662 * the free descriptor/buffer queue in both cases...
663 *
664 * One BD at a time is the only way to make make both cases work reliably, with
665 * software handling both cases correctly, at the significant penalty of needing
666 * an IRQ per packet. (The lack of I/O overlap can be slightly ameliorated by
667 * enabling double buffering.)
668 *
669 * There seems to be no way to identify for sure the cases where the CDC mode
670 * is appropriate...
671 *
672 */
674 /**
675 * cppi41_next_rx_segment - DMA read for the next chunk of a buffer
676 * @rx_ch: Rx channel
677 *
678 * Context: controller IRQ-locked
679 *
680 * NOTE: In the transparent mode, we have to queue one packet at a time since:
681 * - we must avoid starting reception of another packet after receiving
682 * a short packet;
683 * - in host mode we have to set ReqPkt bit in the endpoint's RXCSR after
684 * receiving each packet but the last one... ugly!
685 */
686 static unsigned cppi41_next_rx_segment(struct cppi41_channel *rx_ch)
687 {
688 struct cppi41 *cppi = rx_ch->channel.private_data;
689 struct usb_pkt_desc *curr_pd;
690 struct cppi41_host_pkt_desc *hw_desc;
691 u32 length = rx_ch->length - rx_ch->curr_offset;
692 u32 pkt_size = rx_ch->pkt_size;
694 /*
695 * Rx can use the generic RNDIS mode where we can probably fit this
696 * transfer in one PD and one IRQ (or two with a short packet).
697 */
698 if ((pkt_size & 0x3f) == 0 && length >= 2 * pkt_size) {
699 cppi41_mode_update(rx_ch, USB_GENERIC_RNDIS_MODE);
700 cppi41_autoreq_update(rx_ch, USB_AUTOREQ_ALL_BUT_EOP);
702 if (likely(length < 0x10000))
703 pkt_size = length - length % pkt_size;
704 else
705 pkt_size = 0x10000;
706 cppi41_set_ep_size(rx_ch, pkt_size);
707 } else {
708 cppi41_mode_update(rx_ch, USB_TRANSPARENT_MODE);
709 cppi41_autoreq_update(rx_ch, USB_NO_AUTOREQ);
710 }
712 DBG(4, "RX DMA%u, %s, maxpkt %u, addr %#x, rec'd %u/%u\n",
713 rx_ch->ch_num, rx_ch->dma_mode ? "accelerated" : "transparent",
714 pkt_size, rx_ch->start_addr + rx_ch->curr_offset,
715 rx_ch->curr_offset, rx_ch->length);
717 /* Get Rx packet descriptor from the free pool */
718 curr_pd = usb_get_free_pd(cppi);
719 if (curr_pd == NULL) {
720 /* Shouldn't ever happen! */
721 DBG(4, "No Rx PDs\n");
722 return 0;
723 }
725 /*
726 * HCD arranged ReqPkt for the first packet.
727 * We arrange it for all but the last one.
728 */
729 if (is_host_active(cppi->musb) && rx_ch->channel.actual_len) {
730 void __iomem *epio = rx_ch->end_pt->regs;
731 u16 csr = musb_readw(epio, MUSB_RXCSR);
733 csr |= MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_H_WZC_BITS;
734 musb_writew(epio, MUSB_RXCSR, csr);
735 }
737 if (length < pkt_size)
738 pkt_size = length;
740 hw_desc = &curr_pd->hw_desc;
741 hw_desc->orig_buf_ptr = rx_ch->start_addr + rx_ch->curr_offset;
742 hw_desc->orig_buf_len = pkt_size;
744 curr_pd->ch_num = rx_ch->ch_num;
745 curr_pd->ep_num = rx_ch->end_pt->epnum;
747 rx_ch->curr_offset += pkt_size;
749 /*
750 * Push the free Rx packet descriptor
751 * to the free descriptor/buffer queue.
752 */
753 cppi41_queue_push(&rx_ch->queue_obj, curr_pd->dma_addr,
754 USB_CPPI41_DESC_ALIGN, 0);
756 return 1;
757 }
759 /**
760 * cppi41_channel_program - program channel for data transfer
761 * @channel: the channel
762 * @maxpacket: max packet size
763 * @mode: for Rx, 1 unless the USB protocol driver promised to treat
764 * all short reads as errors and kick in high level fault recovery;
765 * for Tx, 0 unless the protocol driver _requires_ short-packet
766 * termination mode
767 * @dma_addr: DMA address of buffer
768 * @length: length of buffer
769 *
770 * Context: controller IRQ-locked
771 */
772 static int cppi41_channel_program(struct dma_channel *channel, u16 maxpacket,
773 u8 mode, dma_addr_t dma_addr, u32 length)
774 {
775 struct cppi41_channel *cppi_ch;
776 unsigned queued;
778 cppi_ch = container_of(channel, struct cppi41_channel, channel);
780 switch (channel->status) {
781 case MUSB_DMA_STATUS_BUS_ABORT:
782 case MUSB_DMA_STATUS_CORE_ABORT:
783 /* Fault IRQ handler should have handled cleanup */
784 WARNING("%cx DMA%d not cleaned up after abort!\n",
785 cppi_ch->transmit ? 'T' : 'R', cppi_ch->ch_num);
786 break;
787 case MUSB_DMA_STATUS_BUSY:
788 WARNING("Program active channel? %cx DMA%d\n",
789 cppi_ch->transmit ? 'T' : 'R', cppi_ch->ch_num);
790 break;
791 case MUSB_DMA_STATUS_UNKNOWN:
792 DBG(1, "%cx DMA%d not allocated!\n",
793 cppi_ch->transmit ? 'T' : 'R', cppi_ch->ch_num);
794 return 0;
795 case MUSB_DMA_STATUS_FREE:
796 break;
797 }
799 channel->status = MUSB_DMA_STATUS_BUSY;
801 /* Set the transfer parameters, then queue up the first segment */
802 cppi_ch->start_addr = dma_addr;
803 cppi_ch->curr_offset = 0;
804 cppi_ch->pkt_size = maxpacket;
805 cppi_ch->length = length;
806 cppi_ch->transfer_mode = mode;
807 cppi_ch->zlp_queued = 0;
809 /* Tx or Rx channel? */
810 if (cppi_ch->transmit)
811 queued = cppi41_next_tx_segment(cppi_ch);
812 else
813 queued = cppi41_next_rx_segment(cppi_ch);
815 return queued > 0;
816 }
818 static struct usb_pkt_desc *usb_get_pd_ptr(struct cppi41 *cppi,
819 unsigned long pd_addr)
820 {
821 if (pd_addr >= cppi->pd_mem_phys && pd_addr < cppi->pd_mem_phys +
822 USB_CPPI41_MAX_PD * USB_CPPI41_DESC_ALIGN)
823 return pd_addr - cppi->pd_mem_phys + cppi->pd_mem;
824 else
825 return NULL;
826 }
828 static int usb_check_teardown(struct cppi41_channel *cppi_ch,
829 unsigned long pd_addr)
830 {
831 u32 info;
833 if (cppi41_get_teardown_info(pd_addr, &info)) {
834 DBG(1, "ERROR: not a teardown descriptor\n");
835 return 0;
836 }
838 if ((info & CPPI41_TEARDOWN_TX_RX_MASK) ==
839 (!cppi_ch->transmit << CPPI41_TEARDOWN_TX_RX_SHIFT) &&
840 (info & CPPI41_TEARDOWN_DMA_NUM_MASK) ==
841 (usb_cppi41_info.dma_block << CPPI41_TEARDOWN_DMA_NUM_SHIFT) &&
842 (info & CPPI41_TEARDOWN_CHAN_NUM_MASK) ==
843 (usb_cppi41_info.ep_dma_ch[cppi_ch->ch_num] <<
844 CPPI41_TEARDOWN_CHAN_NUM_SHIFT))
845 return 1;
847 DBG(1, "ERROR: unexpected values in teardown descriptor\n");
848 return 0;
849 }
851 /*
852 * We can't handle the channel teardown via the default completion queue in
853 * context of the controller IRQ-locked, so we use the dedicated teardown
854 * completion queue which we can just poll for a teardown descriptor, not
855 * interfering with the Tx completion queue processing.
856 */
857 static void usb_tx_ch_teardown(struct cppi41_channel *tx_ch)
858 {
859 struct cppi41 *cppi = tx_ch->channel.private_data;
860 unsigned long pd_addr;
862 /* Initiate teardown for Tx DMA channel */
863 cppi41_dma_ch_teardown(&tx_ch->dma_ch_obj);
865 do {
866 /* Wait for a descriptor to be queued and pop it... */
867 do {
868 pd_addr = cppi41_queue_pop(&cppi->queue_obj);
869 } while (!pd_addr);
871 dprintk("Descriptor (%08lx) popped from teardown completion "
872 "queue\n", pd_addr);
873 } while (!usb_check_teardown(tx_ch, pd_addr));
874 }
876 /*
877 * For Rx DMA channels, the situation is more complex: there's only a single
878 * completion queue for all our needs, so we have to temporarily redirect the
879 * completed descriptors to our teardown completion queue, with a possibility
880 * of a completed packet landing there as well...
881 */
882 static void usb_rx_ch_teardown(struct cppi41_channel *rx_ch)
883 {
884 struct cppi41 *cppi = rx_ch->channel.private_data;
886 cppi41_dma_ch_default_queue(&rx_ch->dma_ch_obj, 0, cppi->teardownQNum);
888 /* Initiate teardown for Rx DMA channel */
889 cppi41_dma_ch_teardown(&rx_ch->dma_ch_obj);
891 while (1) {
892 struct usb_pkt_desc *curr_pd;
893 unsigned long pd_addr;
895 /* Wait for a descriptor to be queued and pop it... */
896 do {
897 pd_addr = cppi41_queue_pop(&cppi->queue_obj);
898 } while (!pd_addr);
900 dprintk("Descriptor (%08lx) popped from teardown completion "
901 "queue\n", pd_addr);
903 /*
904 * We might have popped a completed Rx PD, so check if the
905 * physical address is within the PD region first. If it's
906 * not the case, it must be a teardown descriptor...
907 * */
908 curr_pd = usb_get_pd_ptr(cppi, pd_addr);
909 if (curr_pd == NULL) {
910 if (usb_check_teardown(rx_ch, pd_addr))
911 break;
912 continue;
913 }
915 /* Paranoia: check if PD is from the right channel... */
916 if (curr_pd->ch_num != rx_ch->ch_num) {
917 ERR("Unexpected channel %d in Rx PD\n",
918 curr_pd->ch_num);
919 continue;
920 }
922 /* Extract the buffer length from the completed PD */
923 rx_ch->channel.actual_len += curr_pd->hw_desc.buf_len;
925 /*
926 * Return Rx PDs to the software list --
927 * this is protected by critical section.
928 */
929 usb_put_free_pd(cppi, curr_pd);
930 }
932 /* Now restore the default Rx completion queue... */
933 cppi41_dma_ch_default_queue(&rx_ch->dma_ch_obj, usb_cppi41_info.q_mgr,
934 usb_cppi41_info.rx_comp_q[0]);
935 }
937 /*
938 * cppi41_channel_abort
939 *
940 * Context: controller IRQ-locked, endpoint selected.
941 */
942 static int cppi41_channel_abort(struct dma_channel *channel)
943 {
944 struct cppi41 *cppi;
945 struct cppi41_channel *cppi_ch;
946 struct musb *musb;
947 void __iomem *reg_base, *epio;
948 unsigned long pd_addr;
949 u32 csr, td_reg;
950 u8 ch_num, ep_num;
952 cppi_ch = container_of(channel, struct cppi41_channel, channel);
953 ch_num = cppi_ch->ch_num;
955 switch (channel->status) {
956 case MUSB_DMA_STATUS_BUS_ABORT:
957 case MUSB_DMA_STATUS_CORE_ABORT:
958 /* From Rx or Tx fault IRQ handler */
959 case MUSB_DMA_STATUS_BUSY:
960 /* The hardware needs shutting down... */
961 dprintk("%s: DMA busy, status = %x\n",
962 __func__, channel->status);
963 break;
964 case MUSB_DMA_STATUS_UNKNOWN:
965 DBG(1, "%cx DMA%d not allocated\n",
966 cppi_ch->transmit ? 'T' : 'R', ch_num);
967 /* FALLTHROUGH */
968 case MUSB_DMA_STATUS_FREE:
969 return 0;
970 }
972 cppi = cppi_ch->channel.private_data;
973 musb = cppi->musb;
974 reg_base = musb->ctrl_base;
975 epio = cppi_ch->end_pt->regs;
976 ep_num = ch_num + 1;
978 #ifdef DEBUG_CPPI_TD
979 printk("Before teardown:");
980 print_pd_list(cppi->pd_pool_head);
981 #endif
983 if (cppi_ch->transmit) {
984 dprintk("Tx channel teardown, cppi_ch = %p\n", cppi_ch);
986 /* Tear down Tx DMA channel */
987 usb_tx_ch_teardown(cppi_ch);
989 /* Issue CPPI FIFO teardown for Tx channel */
990 td_reg = musb_readl(reg_base, USB_TEARDOWN_REG);
991 td_reg |= USB_TX_TDOWN_MASK(ep_num);
992 musb_writel(reg_base, USB_TEARDOWN_REG, td_reg);
994 /* Flush FIFO of the endpoint */
995 csr = musb_readw(epio, MUSB_TXCSR);
996 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_H_WZC_BITS;
997 musb_writew(epio, MUSB_TXCSR, csr);
998 } else { /* Rx */
999 dprintk("Rx channel teardown, cppi_ch = %p\n", cppi_ch);
1001 /* Flush FIFO of the endpoint */
1002 csr = musb_readw(epio, MUSB_RXCSR);
1003 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_H_WZC_BITS;
1004 musb_writew(epio, MUSB_RXCSR, csr);
1006 /* Issue CPPI FIFO teardown for Rx channel */
1007 td_reg = musb_readl(reg_base, USB_TEARDOWN_REG);
1008 td_reg |= USB_RX_TDOWN_MASK(ep_num);
1009 musb_writel(reg_base, USB_TEARDOWN_REG, td_reg);
1011 /* Tear down Rx DMA channel */
1012 usb_rx_ch_teardown(cppi_ch);
1014 /*
1015 * NOTE: docs don't guarantee any of this works... we expect
1016 * that if the USB core stops telling the CPPI core to pull
1017 * more data from it, then it'll be safe to flush current Rx
1018 * DMA state iff any pending FIFO transfer is done.
1019 */
1021 /* For host, ensure ReqPkt is never set again */
1022 cppi41_autoreq_update(cppi_ch, USB_NO_AUTOREQ);
1024 /* For host, clear (just) ReqPkt at end of current packet(s) */
1025 if (is_host_active(cppi->musb))
1026 csr &= ~MUSB_RXCSR_H_REQPKT;
1027 csr |= MUSB_RXCSR_H_WZC_BITS;
1029 /* Clear DMA enable */
1030 csr &= ~MUSB_RXCSR_DMAENAB;
1031 musb_writew(epio, MUSB_RXCSR, csr);
1033 /* Flush the FIFO of endpoint once again */
1034 csr = musb_readw(epio, MUSB_RXCSR);
1035 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_H_WZC_BITS;
1036 musb_writew(epio, MUSB_RXCSR, csr);
1038 udelay(50);
1039 }
1041 /*
1042 * There might be PDs in the Rx/Tx source queue that were not consumed
1043 * by the DMA controller -- they need to be recycled properly.
1044 */
1045 while ((pd_addr = cppi41_queue_pop(&cppi_ch->queue_obj)) != 0) {
1046 struct usb_pkt_desc *curr_pd;
1048 curr_pd = usb_get_pd_ptr(cppi, pd_addr);
1049 if (curr_pd == NULL) {
1050 ERR("Invalid PD popped from source queue\n");
1051 continue;
1052 }
1054 /*
1055 * Return Rx/Tx PDs to the software list --
1056 * this is protected by critical section.
1057 */
1058 dprintk("Returning PD %p to the free PD list\n", curr_pd);
1059 usb_put_free_pd(cppi, curr_pd);
1060 }
1062 #ifdef DEBUG_CPPI_TD
1063 printk("After teardown:");
1064 print_pd_list(cppi->pd_pool_head);
1065 #endif
1067 /* Re-enable the DMA channel */
1068 cppi41_dma_ch_enable(&cppi_ch->dma_ch_obj);
1070 channel->status = MUSB_DMA_STATUS_FREE;
1072 return 0;
1073 }
1075 /**
1076 * cppi41_dma_controller_create -
1077 * instantiate an object representing DMA controller.
1078 */
1079 struct dma_controller * __devinit
1080 cppi41_dma_controller_create(struct musb *musb, void __iomem *mregs)
1081 {
1082 struct cppi41 *cppi;
1084 cppi = kzalloc(sizeof *cppi, GFP_KERNEL);
1085 if (!cppi)
1086 return NULL;
1088 /* Initialize the CPPI 4.1 DMA controller structure */
1089 cppi->musb = musb;
1090 cppi->controller.start = cppi41_controller_start;
1091 cppi->controller.stop = cppi41_controller_stop;
1092 cppi->controller.channel_alloc = cppi41_channel_alloc;
1093 cppi->controller.channel_release = cppi41_channel_release;
1094 cppi->controller.channel_program = cppi41_channel_program;
1095 cppi->controller.channel_abort = cppi41_channel_abort;
1097 return &cppi->controller;
1098 }
1099 EXPORT_SYMBOL(cppi41_dma_controller_create);
1101 /**
1102 * cppi41_dma_controller_destroy -
1103 * destroy a previously instantiated DMA controller
1104 * @controller: the controller
1105 */
1106 void cppi41_dma_controller_destroy(struct dma_controller *controller)
1107 {
1108 struct cppi41 *cppi;
1110 cppi = container_of(controller, struct cppi41, controller);
1112 /* Free the CPPI object */
1113 kfree(cppi);
1114 }
1115 EXPORT_SYMBOL(cppi41_dma_controller_destroy);
1117 static void usb_process_tx_queue(struct cppi41 *cppi, unsigned index)
1118 {
1119 struct cppi41_queue_obj tx_queue_obj;
1120 unsigned long pd_addr;
1122 if (cppi41_queue_init(&tx_queue_obj, usb_cppi41_info.q_mgr,
1123 usb_cppi41_info.tx_comp_q[index])) {
1124 DBG(1, "ERROR: cppi41_queue_init failed for "
1125 "Tx completion queue");
1126 return;
1127 }
1129 while ((pd_addr = cppi41_queue_pop(&tx_queue_obj)) != 0) {
1130 struct usb_pkt_desc *curr_pd;
1131 struct cppi41_channel *tx_ch;
1132 u8 ch_num, ep_num;
1133 u32 length;
1135 curr_pd = usb_get_pd_ptr(cppi, pd_addr);
1136 if (curr_pd == NULL) {
1137 ERR("Invalid PD popped from Tx completion queue\n");
1138 continue;
1139 }
1141 /* Extract the data from received packet descriptor */
1142 ch_num = curr_pd->ch_num;
1143 ep_num = curr_pd->ep_num;
1144 length = curr_pd->hw_desc.buf_len;
1146 tx_ch = &cppi->tx_cppi_ch[ch_num];
1147 tx_ch->channel.actual_len += length;
1149 /*
1150 * Return Tx PD to the software list --
1151 * this is protected by critical section
1152 */
1153 usb_put_free_pd(cppi, curr_pd);
1155 if ((tx_ch->curr_offset < tx_ch->length) ||
1156 (tx_ch->transfer_mode && !tx_ch->zlp_queued))
1157 cppi41_next_tx_segment(tx_ch);
1158 else if (tx_ch->channel.actual_len >= tx_ch->length) {
1159 tx_ch->channel.status = MUSB_DMA_STATUS_FREE;
1161 /* Tx completion routine callback */
1162 musb_dma_completion(cppi->musb, ep_num, 1);
1163 }
1164 }
1165 }
1167 static void usb_process_rx_queue(struct cppi41 *cppi, unsigned index)
1168 {
1169 struct cppi41_queue_obj rx_queue_obj;
1170 unsigned long pd_addr;
1172 if (cppi41_queue_init(&rx_queue_obj, usb_cppi41_info.q_mgr,
1173 usb_cppi41_info.rx_comp_q[index])) {
1174 DBG(1, "ERROR: cppi41_queue_init failed for Rx queue\n");
1175 return;
1176 }
1178 while ((pd_addr = cppi41_queue_pop(&rx_queue_obj)) != 0) {
1179 struct usb_pkt_desc *curr_pd;
1180 struct cppi41_channel *rx_ch;
1181 u8 ch_num, ep_num;
1182 u32 length;
1184 curr_pd = usb_get_pd_ptr(cppi, pd_addr);
1185 if (curr_pd == NULL) {
1186 ERR("Invalid PD popped from Rx completion queue\n");
1187 continue;
1188 }
1190 /* Extract the data from received packet descriptor */
1191 ch_num = curr_pd->ch_num;
1192 ep_num = curr_pd->ep_num;
1193 length = curr_pd->hw_desc.buf_len;
1195 rx_ch = &cppi->rx_cppi_ch[ch_num];
1196 rx_ch->channel.actual_len += length;
1198 /*
1199 * Return Rx PD to the software list --
1200 * this is protected by critical section
1201 */
1202 usb_put_free_pd(cppi, curr_pd);
1204 if (unlikely(rx_ch->channel.actual_len >= rx_ch->length ||
1205 length < curr_pd->hw_desc.orig_buf_len)) {
1206 rx_ch->channel.status = MUSB_DMA_STATUS_FREE;
1208 /* Rx completion routine callback */
1209 musb_dma_completion(cppi->musb, ep_num, 0);
1210 } else
1211 cppi41_next_rx_segment(rx_ch);
1212 }
1213 }
1215 /*
1216 * cppi41_completion - handle interrupts from the Tx/Rx completion queues
1217 *
1218 * NOTE: since we have to manually prod the Rx process in the transparent mode,
1219 * we certainly want to handle the Rx queues first.
1220 */
1221 void cppi41_completion(struct musb *musb, u32 rx, u32 tx)
1222 {
1223 struct cppi41 *cppi;
1224 unsigned index;
1226 cppi = container_of(musb->dma_controller, struct cppi41, controller);
1228 /* Process packet descriptors from the Rx queues */
1229 for (index = 0; rx != 0; rx >>= 1, index++)
1230 if (rx & 1)
1231 usb_process_rx_queue(cppi, index);
1233 /* Process packet descriptors from the Tx completion queues */
1234 for (index = 0; tx != 0; tx >>= 1, index++)
1235 if (tx & 1)
1236 usb_process_tx_queue(cppi, index);
1237 }
1239 MODULE_DESCRIPTION("CPPI4.1 dma controller driver for musb");
1240 MODULE_LICENSE("GPL v2");
1242 static int __init cppi41_dma_init(void)
1243 {
1244 return 0;
1245 }
1246 module_init(cppi41_dma_init);
1248 static void __exit cppi41_dma__exit(void)
1249 {
1250 }
1251 module_exit(cppi41_dma__exit);